1 /*
2 * Copyright 2021-2024 NXP
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 /**
8 * @file File with source code used to implement ICU driver functionality on EMIOS module.
9 * @details This file contains the source code for all functions which are using EMIOS module.
10 * @addtogroup emios_icu_ip EMIOS IPL
11 * @{
12 */
13 #ifdef __cplusplus
14 extern "C"{
15 #endif
16
17 /*==================================================================================================
18 * INCLUDE FILES
19 * 1) system and project includes
20 * 2) needed interfaces from external units
21 * 3) internal and external interfaces from this unit
22 ==================================================================================================*/
23 #include "Emios_Icu_Ip.h"
24 #include "SchM_Icu.h"
25
26 #if (STD_ON == EMIOS_ICU_IP_USED)
27 #if (STD_ON == EMIOS_ICU_IP_DEV_ERROR_DETECT)
28 #include "Devassert.h"
29 #endif
30
31 #if (defined (EMIOS_ICU_IP_ENABLE_USER_MODE_SUPPORT))
32 #if (STD_ON == EMIOS_ICU_IP_ENABLE_USER_MODE_SUPPORT)
33 #define USER_MODE_REG_PROT_ENABLED (EMIOS_ICU_IP_ENABLE_USER_MODE_SUPPORT)
34 #include "RegLockMacros.h"
35 #endif
36 #endif /* defined (EMIOS_ICU_IP_ENABLE_USER_MODE_SUPPORT) */
37
38 #if ((STD_ON == EMIOS_ICU_IP_SIGNALMEASUREMENT_USES_DMA_IPL) || (STD_ON == EMIOS_ICU_IP_TIMESTAMP_USES_DMA_IPL))
39 #include "Dma_Ip.h"
40 #endif
41
42 #endif /* EMIOS_ICU_IP_USED */
43 /*==================================================================================================
44 * SOURCE FILE VERSION INFORMATION
45 ==================================================================================================*/
46 #define EMIOS_ICU_IP_VENDOR_ID_C 43
47 #define EMIOS_ICU_IP_AR_RELEASE_MAJOR_VERSION_C 4
48 #define EMIOS_ICU_IP_AR_RELEASE_MINOR_VERSION_C 7
49 #define EMIOS_ICU_IP_AR_RELEASE_REVISION_VERSION_C 0
50 #define EMIOS_ICU_IP_SW_MAJOR_VERSION_C 2
51 #define EMIOS_ICU_IP_SW_MINOR_VERSION_C 0
52 #define EMIOS_ICU_IP_SW_PATCH_VERSION_C 0
53
54 /*==================================================================================================
55 * FILE VERSION CHECKS
56 ==================================================================================================*/
57 #ifndef DISABLE_MCAL_INTERMODULE_ASR_CHECK
58 #if (STD_ON == EMIOS_ICU_IP_USED)
59 #if (defined (EMIOS_ICU_IP_ENABLE_USER_MODE_SUPPORT))
60 #if (STD_ON == EMIOS_ICU_IP_ENABLE_USER_MODE_SUPPORT)
61 /* Check if the files Emios_Icu_Ip.c and RegLockMacros.h are of the same version */
62 #if ((EMIOS_ICU_IP_AR_RELEASE_MAJOR_VERSION_C != REGLOCKMACROS_AR_RELEASE_MAJOR_VERSION) || \
63 (EMIOS_ICU_IP_AR_RELEASE_MINOR_VERSION_C != REGLOCKMACROS_AR_RELEASE_MINOR_VERSION))
64 #error "AutoSar Version Numbers of Emios_Icu_Ip.c and RegLockMacros.h are different"
65 #endif
66 #endif
67 #endif /* defined (EMIOS_ICU_IP_ENABLE_USER_MODE_SUPPORT) */
68
69 #if ((STD_ON == EMIOS_ICU_IP_SIGNALMEASUREMENT_USES_DMA_IPL) || (STD_ON == EMIOS_ICU_IP_TIMESTAMP_USES_DMA_IPL))
70 /* Check if header file and Dma_Ip.h file are of the same Autosar version */
71 #if ((EMIOS_ICU_IP_AR_RELEASE_MAJOR_VERSION_C != DMA_IP_AR_RELEASE_MAJOR_VERSION) || \
72 (EMIOS_ICU_IP_AR_RELEASE_MINOR_VERSION_C != DMA_IP_AR_RELEASE_MINOR_VERSION))
73 #error "AutoSar Version Numbers of Emios_Icu_Ip.c and Dma_Ip.h are different"
74 #endif
75 #endif
76 #endif /* EMIOS_ICU_IP_USED */
77
78 /* Check if this header file and SchM_Icu.h file are of the same Autosar version */
79 #if ((EMIOS_ICU_IP_AR_RELEASE_MAJOR_VERSION != SCHM_ICU_AR_RELEASE_MAJOR_VERSION) || \
80 (EMIOS_ICU_IP_AR_RELEASE_MINOR_VERSION != SCHM_ICU_AR_RELEASE_MINOR_VERSION))
81 #error "AutoSar Version Numbers of Emios_Icu_Ip.c and SchM_Icu.h are different"
82 #endif
83 #endif
84
85 /* Check if source file and ICU header file are of the same vendor */
86 #if (EMIOS_ICU_IP_VENDOR_ID_C != EMIOS_ICU_IP_VENDOR_ID)
87 #error "Emios_Icu_Ip.c and Emios_Icu_Ip.h have different vendor IDs"
88 #endif
89 /* Check if source file and Emios_Icu_Ip header file are of the same Autosar version */
90 #if ( (EMIOS_ICU_IP_AR_RELEASE_MAJOR_VERSION_C != EMIOS_ICU_IP_AR_RELEASE_MAJOR_VERSION) || \
91 (EMIOS_ICU_IP_AR_RELEASE_MINOR_VERSION_C != EMIOS_ICU_IP_AR_RELEASE_MINOR_VERSION) || \
92 (EMIOS_ICU_IP_AR_RELEASE_REVISION_VERSION_C != EMIOS_ICU_IP_AR_RELEASE_REVISION_VERSION))
93 #error "AutoSar Version Numbers of Emios_Icu_Ip.c and Emios_Icu_Ip.h are different"
94 #endif
95 /* Check if source file and Icu_eMIOS header file are of the same Software version */
96 #if ((EMIOS_ICU_IP_SW_MAJOR_VERSION_C != EMIOS_ICU_IP_SW_MAJOR_VERSION) || \
97 (EMIOS_ICU_IP_SW_MINOR_VERSION_C != EMIOS_ICU_IP_SW_MINOR_VERSION) || \
98 (EMIOS_ICU_IP_SW_PATCH_VERSION_C != EMIOS_ICU_IP_SW_PATCH_VERSION))
99 #error "Software Version Numbers of Emios_Icu_Ip.c and Emios_Icu_Ip.h are different"
100 #endif
101
102 #ifndef DISABLE_MCAL_INTERMODULE_ASR_CHECK
103 #if (STD_ON == EMIOS_ICU_IP_USED)
104 #if(EMIOS_ICU_IP_DEV_ERROR_DETECT == STD_ON)
105 /* Check if this header file and Devassert.h file are of the same Autosar version */
106 #if ((EMIOS_ICU_IP_AR_RELEASE_MAJOR_VERSION_C != DEVASSERT_AR_RELEASE_MAJOR_VERSION) || \
107 (EMIOS_ICU_IP_AR_RELEASE_MINOR_VERSION_C != DEVASSERT_AR_RELEASE_MINOR_VERSION))
108 #error "AutoSar Version Numbers of Emios_Icu_Ip.c and Devassert.h are different"
109 #endif
110 #endif
111 #endif /* EMIOS_ICU_IP_USED */
112 #endif
113 /*==================================================================================================
114 * LOCAL MACROS
115 ==================================================================================================*/
116 #if (STD_ON == EMIOS_ICU_IP_USED)
117 #if ((defined (MCAL_EMIOS_REG_PROT_AVAILABLE)) && (defined (EMIOS_ICU_IP_ENABLE_USER_MODE_SUPPORT)))
118 #if ((STD_ON == MCAL_EMIOS_REG_PROT_AVAILABLE) && (STD_ON == EMIOS_ICU_IP_ENABLE_USER_MODE_SUPPORT))
119 #define Call_Emios_Icu_Ip_SetUserAccessAllowed(BaseAddr) OsIf_Trusted_Call1param(Emios_Icu_Ip_SetUserAccessAllowed,(BaseAddr))
120 #else
121 #define Call_Emios_Icu_Ip_SetUserAccessAllowed(BaseAddr)
122 #endif
123 #else
124 #define Call_Emios_Icu_Ip_SetUserAccessAllowed(BaseAddr)
125 #endif
126 #endif /* EMIOS_ICU_IP_USED */
127 /*==================================================================================================
128 * LOCAL CONSTANTS
129 ==================================================================================================*/
130
131
132 /*==================================================================================================
133 * LOCAL VARIABLES
134 ==================================================================================================*/
135 #if (STD_ON == EMIOS_ICU_IP_USED)
136
137 #if (EMIOS_ICU_IP_NO_CACHE_USED == STD_ON)
138 #define ICU_START_SEC_VAR_CLEARED_BOOLEAN_NO_CACHEABLE
139 #else
140 #define ICU_START_SEC_VAR_CLEARED_BOOLEAN
141 #endif
142 #include "Icu_MemMap.h"
143
144 /* State of initialized EMIOS modules. */
145 static boolean eMios_Icu_Ip_bInstanceState[EMIOS_ICU_IP_INSTANCE_COUNT];
146
147 #if (EMIOS_ICU_IP_NO_CACHE_USED == STD_ON)
148 #define ICU_STOP_SEC_VAR_CLEARED_BOOLEAN_NO_CACHEABLE
149 #else
150 #define ICU_STOP_SEC_VAR_CLEARED_BOOLEAN
151 #endif
152 #include "Icu_MemMap.h"
153
154 #if (EMIOS_ICU_IP_NO_CACHE_USED == STD_ON)
155 #define ICU_START_SEC_VAR_CLEARED_8_NO_CACHEABLE
156 #else
157 #define ICU_START_SEC_VAR_CLEARED_8
158 #endif
159 #include "Icu_MemMap.h"
160 #if ((EMIOS_ICU_IP_TIMESTAMP_API == STD_ON)||(EMIOS_ICU_IP_SIGNAL_MEASUREMENT_API == STD_ON)||(EMIOS_ICU_IP_EDGE_DETECT_API == STD_ON))
161 #if (EMIOS_ICU_IP_OVERFLOW_NOTIFICATION_API == STD_ON)
162 /**
163 * @brief eMios_Icu_Ip_u8NumOvflByCounterBus
164 * @details The number of active channels has the overflow notification function using masterbus.
165 */
166 static uint8 eMios_Icu_Ip_u8NumOvflByCounterBus[EMIOS_ICU_IP_INSTANCE_COUNT][EMIOS_ICU_IP_NUM_OF_CHANNELS];
167 #endif /* EMIOS_ICU_IP_OVERFLOW_NOTIFICATION_API == STD_ON */
168 #endif /* ((EMIOS_ICU_IP_TIMESTAMP_API == STD_ON)||(EMIOS_ICU_IP_SIGNAL_MEASUREMENT_API == STD_ON)||(EMIOS_ICU_IP_EDGE_DETECT_API == STD_ON)) */
169 #if (EMIOS_ICU_IP_NO_CACHE_USED == STD_ON)
170 #define ICU_STOP_SEC_VAR_CLEARED_8_NO_CACHEABLE
171 #else
172 #define ICU_STOP_SEC_VAR_CLEARED_8
173 #endif
174 #include "Icu_MemMap.h"
175
176 #define ICU_START_SEC_VAR_CLEARED_32_NO_CACHEABLE
177 #include "Icu_MemMap.h"
178
179 #if (EMIOS_ICU_IP_EDGE_COUNT_API == STD_ON)
180 static uint32 eMios_Icu_Ip_u32aEdgeCurrent_Value[EMIOS_ICU_IP_NUM_OF_CHANNELS_USED];
181 #endif /* EMIOS_ICU_IP_EDGE_COUNT_API == STD_ON */
182
183 #if (STD_ON == EMIOS_ICU_IP_SIGNALMEASUREMENT_USES_DMA_IPL)
184 /** @brief Array for saving value of DMA **/
185 volatile uint32 Emios_Icu_Ip_aDmaBuffer[EMIOS_ICU_IP_NUM_OF_CHANNELS_USED][EMIOS_ICU_IP_DMA_MAJORLOOP_COUNT];
186
187 /** @brief Array for saving the period */
188 volatile uint32 Emios_Icu_Ip_aIsSecondInterrupt[EMIOS_ICU_IP_NUM_OF_CHANNELS_USED];
189
190 /** @brief Array for saving the period */
191 volatile uint32 Emios_Icu_Ip_aFirstEdgeTimeStamp[EMIOS_ICU_IP_NUM_OF_CHANNELS_USED];
192
193 #endif /* EMIOS_ICU_IP_SIGNALMEASUREMENT_USES_DMA_IPL */
194
195 #define ICU_STOP_SEC_VAR_CLEARED_32_NO_CACHEABLE
196 #include "Icu_MemMap.h"
197 /*==================================================================================================
198 GLOBAL CONSTANTS
199 ==================================================================================================*/
200 #define ICU_START_SEC_CONST_UNSPECIFIED
201 #include "Icu_MemMap.h"
202 /* Table of base addresses for EMIOS instances. */
203 eMIOS_Type * const s_emiosBase[] = IP_eMIOS_BASE_PTRS;
204 #define ICU_STOP_SEC_CONST_UNSPECIFIED
205 #include "Icu_MemMap.h"
206 /*==================================================================================================
207 * GLOBAL VARIABLES
208 ==================================================================================================*/
209 #if (EMIOS_ICU_IP_NO_CACHE_USED == STD_ON)
210 #define ICU_START_SEC_VAR_CLEARED_UNSPECIFIED_NO_CACHEABLE
211 #else
212 #define ICU_START_SEC_VAR_CLEARED_UNSPECIFIED
213 #endif
214 #include "Icu_MemMap.h"
215
216 #if (EMIOS_ICU_IP_SIGNAL_MEASUREMENT_API == STD_ON)
217 eMios_Icu_Ip_MeasStatusType eMios_Icu_Ip_aeInt_Counter[EMIOS_ICU_IP_NUM_OF_CHANNELS_USED];
218 eMios_Icu_ValueType eMios_Icu_Ip_CapturedActivePulseWidth[EMIOS_ICU_IP_NUM_OF_CHANNELS_USED];
219 eMios_Icu_ValueType eMios_Icu_Ip_TimeStart[EMIOS_ICU_IP_NUM_OF_CHANNELS_USED];
220 #endif /* EMIOS_ICU_IP_SIGNAL_MEASUREMENT_API == STD_ON */
221
222 #if (EMIOS_ICU_IP_TIMESTAMP_API == STD_ON)
223 eMios_Icu_ValueType eMios_Icu_Ip_BufferPtr[EMIOS_ICU_IP_NUM_OF_CHANNELS_USED];
224 #endif /* EMIOS_ICU_IP_TIMESTAMP_API == STD_ON */
225
226 eMios_Icu_Ip_ChStateType eMios_Icu_Ip_ChState[EMIOS_ICU_IP_NUM_OF_CHANNELS_USED];
227
228 #if (defined EMIOS_ICU_IP_WSC_SUPPORT)
229 #if (EMIOS_ICU_IP_WSC_SUPPORT == STD_ON)
230 eMios_Icu_Ip_WsChStateType eMios_Icu_Ip_WsChState[EMIOS_ICU_IP_INSTANCE_COUNT][EMIOS_ICU_IP_WSC_NUM_OF_CHANNELS];
231 #endif
232 #endif
233 #if (EMIOS_ICU_IP_NO_CACHE_USED == STD_ON)
234 #define ICU_STOP_SEC_VAR_CLEARED_UNSPECIFIED_NO_CACHEABLE
235 #else
236 #define ICU_STOP_SEC_VAR_CLEARED_UNSPECIFIED
237 #endif
238 #include "Icu_MemMap.h"
239
240 #if (EMIOS_ICU_IP_NO_CACHE_USED == STD_ON)
241 #define ICU_START_SEC_VAR_INIT_8_NO_CACHEABLE
242 #else
243 #define ICU_START_SEC_VAR_INIT_8
244 #endif
245 #include "Icu_MemMap.h"
246 /* This array stores the positions in the eMios_Icu_Ip_ChState array of the configured eMios channels. */
247 uint8 eMios_Icu_Ip_IndexInChState[EMIOS_ICU_IP_INSTANCE_COUNT][EMIOS_ICU_IP_NUM_OF_CHANNELS] = EMIOS_ICU_IP_INITIAL_INDEX_OF_CHANNELS;
248 #if (EMIOS_ICU_IP_NO_CACHE_USED == STD_ON)
249 #define ICU_STOP_SEC_VAR_INIT_8_NO_CACHEABLE
250 #else
251 #define ICU_STOP_SEC_VAR_INIT_8
252 #endif
253 #include "Icu_MemMap.h"
254
255 /*==================================================================================================
256 * LOCAL FUNCTION PROTOTYPES
257 ==================================================================================================*/
258 #define ICU_START_SEC_CODE
259 #include "Icu_MemMap.h"
260
261 #if (EMIOS_ICU_IP_SIGNAL_MEASUREMENT_API == STD_ON)
262 extern void Emios_Icu_Ip_SignalMeasurementHandler(const uint8 instance, const uint8 hwChannel, boolean bOverflow);
263 #endif
264
265 #if (EMIOS_ICU_IP_DUAL_CLOCK_MODE_API == STD_ON)
266 /**
267 * @brief Icu driver function that sets the channel prescaler.
268 * @details This function:
269 * - Writes prescaling rate at UCPRE[0:1] bits in EMIOSC[n] register
270 * - Enables channel prescaler by setting UCPREN bit in EMIOSC[n] register
271 *
272 * @param[in] instance - eMIOS module index
273 * @param[in] hwChannel - eMIOS encoded hardware channel
274 * @param[in] u32ChannelPrescaler - prescaler for the hardware channel
275 */
276 static inline void Emios_Icu_Ip_SetPrescaler
277 (
278 const uint8 instance,
279 const uint8 hwChannel,
280 const uint32 u32ChannelPrescaler
281 );
282 #endif /* EMIOS_ICU_IP_DUAL_CLOCK_MODE_API == STD_ON */
283
284 #if ((EMIOS_ICU_IP_TIMESTAMP_API == STD_ON)||(EMIOS_ICU_IP_SIGNAL_MEASUREMENT_API == STD_ON)||(EMIOS_ICU_IP_EDGE_DETECT_API == STD_ON))
285 #if (EMIOS_ICU_IP_OVERFLOW_NOTIFICATION_API == STD_ON)
286 /**
287 * @brief Icu driver function that enable the master buses Interrupt.
288 * @details This function:
289 * - Only using for the following functions:
290 * - Emios_Icu_Ip_StartSignalMeasurement: Used for enable master buses interrupt that hwChannel uses as an overflow notification.
291 * - Emios_Icu_Ip_StartTimestamp: Used for enable master buses interrupt that hwChannel uses as an overflow notification.
292 *
293 * @param[in] instance - eMIOS module index
294 * @param[in] hwChannel - eMIOS encoded hardware channel using master bus
295 * @api
296 */
297 static inline void Emios_Icu_Ip_EnableMasterBusInterrupt
298 (
299 const uint8 instance,
300 const uint8 hwChannel
301 );
302
303 /**
304 * @brief Icu driver function that disable the master buses Interrupt.
305 * @details This function:
306 * - Only using for the following functions:
307 * - Emios_Icu_Ip_StartSignalMeasurement: Used for disable master buses interrupt that hwChannel uses as an overflow notification.
308 * - Emios_Icu_Ip_StartTimestamp: Used for disable master buses interrupt that hwChannel uses as an overflow notification.
309 *
310 * @param[in] instance - eMIOS module index
311 * @param[in] hwChannel - eMIOS encoded hardware channel using master bus
312 * @api
313 */
314 static inline void Emios_Icu_Ip_DisableMasterBusInterrupt
315 (
316 const uint8 instance,
317 const uint8 hwChannel
318 );
319 #endif /* EMIOS_ICU_IP_OVERFLOW_NOTIFICATION_API == STD_ON */
320 #endif
321
322 /**
323 * @brief Emios_Icu_Ip_UCSetMode
324 * @details This function sets CCR_MODE bitfield, the mode of operation of the Unified Channel
325 *
326 * @param[in] instance - eMIOS module index
327 * @param[in] hwChannel - eMIOS Channel index
328 * @param[in] u32Mode - CCR_MODE bitfield value to be set
329 * @api
330 */
331 static inline void Emios_Icu_Ip_UCSetMode
332 (
333 const uint8 instance,
334 const uint8 hwChannel,
335 const uint32 u32Mode
336 );
337
338 /**
339 * @brief Function to return the channel id of master bus of current channel
340 * @details Function to return the channel id of master bus of current channel
341 * @param[in] hwChannel - eMIOS Channel index
342 * @param[in] u32Bus - the used bus for current channels
343 * @param[out] - The id of master bus
344 */
345 static inline uint8 Emios_Icu_Ip_GetMasterBus
346 (
347 uint8 hwChannel,
348 eMios_Icu_Ip_BusType u32Bus
349 );
350
351 #if (defined (EMIOS_ICU_IP_ENABLE_USER_MODE_SUPPORT))
352 #if (STD_ON == EMIOS_ICU_IP_ENABLE_USER_MODE_SUPPORT)
353
354 #if (defined(MCAL_EMIOS_REG_PROT_AVAILABLE))
355 #if (STD_ON == MCAL_EMIOS_REG_PROT_AVAILABLE)
356 /**
357 * @brief Enables EMIOS registers writing in User Mode by configuring REG_PROT
358 * @details Sets the UAA (User Access Allowed) bit of the EMIOS IP allowing EMIOS registers writing in User Mode
359 *
360 * @param[in] EmiosBaseAddr
361 *
362 * @return none
363 *
364 * @pre Should be executed in supervisor mode
365 * @post none
366 *
367 */
368 void Emios_Icu_Ip_SetUserAccessAllowed(uint32 EmiosBaseAddr);
369 #endif /* (STD_ON == MCAL_EMIOS_REG_PROT_AVAILABLE) */
370 #endif /* (defined(MCAL_EMIOS_REG_PROT_AVAILABLE)) */
371
372 #endif /* (STD_ON == EMIOS_ICU_IP_ENABLE_USER_MODE_SUPPORT) */
373 #endif /* defined (EMIOS_ICU_IP_ENABLE_USER_MODE_SUPPORT) */
374
375 /*==================================================================================================
376 * LOCAL FUNCTIONS
377 ==================================================================================================*/
Emios_Icu_Ip_UCSetMode(const uint8 instance,const uint8 hwChannel,const uint32 u32Mode)378 static inline void Emios_Icu_Ip_UCSetMode
379 (
380 const uint8 instance,
381 const uint8 hwChannel,
382 const uint32 u32Mode
383 )
384 {
385 SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_48();
386 /* Clear MODE bitfield - GPIO mode */
387 s_emiosBase[instance]->CH.UC[hwChannel].C &= ~eMIOS_C_MODE_MASK;
388 /* Set desired mode */
389 s_emiosBase[instance]->CH.UC[hwChannel].C |= (u32Mode & eMIOS_C_MODE_MASK);
390 SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_48();
391 }
392
Emios_Icu_Ip_GetMasterBus(uint8 hwChannel,eMios_Icu_Ip_BusType u32Bus)393 static inline uint8 Emios_Icu_Ip_GetMasterBus
394 (
395 uint8 hwChannel,
396 eMios_Icu_Ip_BusType u32Bus
397 )
398 {
399 uint8 u8MasterBusChannelIdx = (uint8)0U;
400
401 if (EMIOS_ICU_BUS_DIVERSE == u32Bus)
402 {
403 if (EMIOS_ICU_IP_CHANNEL_7 >= hwChannel) /* bus B */
404 {
405 u8MasterBusChannelIdx = EMIOS_ICU_IP_CHANNEL_0;
406 }
407 else if (EMIOS_ICU_IP_CHANNEL_15 >= hwChannel) /* Bus C */
408 {
409 u8MasterBusChannelIdx = EMIOS_ICU_IP_CHANNEL_8;
410 }
411 else if (EMIOS_ICU_IP_CHANNEL_23 >= hwChannel) /* bus D */
412 {
413 u8MasterBusChannelIdx = EMIOS_ICU_IP_CHANNEL_16;
414 }
415 else /* Bus E remaining */
416 {
417 u8MasterBusChannelIdx = EMIOS_ICU_IP_CHANNEL_24;
418 }
419 }
420 else if (EMIOS_ICU_BUS_A == u32Bus) /* bus A */
421 {
422 u8MasterBusChannelIdx = EMIOS_ICU_IP_CHANNEL_23;
423 }
424 else if (EMIOS_ICU_BUS_F == u32Bus) /* bus F remaining */
425 {
426 u8MasterBusChannelIdx = EMIOS_ICU_IP_CHANNEL_22;
427 }
428 else
429 {
430 /*Empty else to fix misra*/
431 }
432 return u8MasterBusChannelIdx;
433 }
434
435 #if (EMIOS_ICU_IP_DUAL_CLOCK_MODE_API == STD_ON)
Emios_Icu_Ip_SetPrescaler(const uint8 instance,const uint8 hwChannel,const uint32 u32ChannelPrescaler)436 static inline void Emios_Icu_Ip_SetPrescaler
437 (
438 const uint8 instance,
439 const uint8 hwChannel,
440 const uint32 u32ChannelPrescaler
441 )
442 {
443 SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_53();
444
445 /* Clear UCPREN bit */
446 s_emiosBase[instance]->CH.UC[hwChannel].C &= ~eMIOS_C_UCPREN_MASK;
447 /* Write prescaling rate at UCEXTPRE[0:3] bits in EMIOSC2[n] */
448 s_emiosBase[instance]->CH.UC[hwChannel].C2 &= ~eMIOS_C2_UCEXTPRE_MASK;
449
450 s_emiosBase[instance]->CH.UC[hwChannel].C2 |= eMIOS_C2_UCEXTPRE(u32ChannelPrescaler);
451 /* Enable channel prescaler */
452 s_emiosBase[instance]->CH.UC[hwChannel].C |= eMIOS_C_UCPREN_MASK;
453
454 SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_53();
455 }
456 #endif /* EMIOS_ICU_IP_DUAL_CLOCK_MODE_API == STD_ON */
457
458 #if ((EMIOS_ICU_IP_TIMESTAMP_API == STD_ON)||(EMIOS_ICU_IP_SIGNAL_MEASUREMENT_API == STD_ON)||(EMIOS_ICU_IP_EDGE_DETECT_API == STD_ON))
459 #if (EMIOS_ICU_IP_OVERFLOW_NOTIFICATION_API == STD_ON)
Emios_Icu_Ip_EnableMasterBusInterrupt(const uint8 instance,const uint8 hwChannel)460 static inline void Emios_Icu_Ip_EnableMasterBusInterrupt
461 (
462 const uint8 instance,
463 const uint8 hwChannel
464 )
465 {
466 uint8 nMasterBusHwChannel;
467
468 if (EMIOS_ICU_BUS_INTERNAL_COUNTER != eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].BusSelected)
469 {
470 nMasterBusHwChannel = Emios_Icu_Ip_GetMasterBus(hwChannel, eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].BusSelected);
471 if (nMasterBusHwChannel < EMIOS_ICU_IP_NUM_OF_CHANNELS)
472 {
473 if((uint8)0U == eMios_Icu_Ip_u8NumOvflByCounterBus[instance][nMasterBusHwChannel])
474 {
475 /* Clear pending interrupts */
476 s_emiosBase[instance]->CH.UC[hwChannel].S |= (eMIOS_S_OVR_MASK | eMIOS_S_OVFL_MASK | eMIOS_S_FLAG_MASK);
477 /* Enable Interrupt for master bus*/
478 Emios_Icu_Ip_EnableInterrupt(instance, nMasterBusHwChannel);
479 }
480 eMios_Icu_Ip_u8NumOvflByCounterBus[instance][nMasterBusHwChannel]++;
481 }
482 }
483 }
484
Emios_Icu_Ip_DisableMasterBusInterrupt(const uint8 instance,const uint8 hwChannel)485 static inline void Emios_Icu_Ip_DisableMasterBusInterrupt
486 (
487 const uint8 instance,
488 const uint8 hwChannel
489 )
490 {
491 uint8 nMasterBusHwChannel;
492
493 if (EMIOS_ICU_BUS_INTERNAL_COUNTER != eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].BusSelected)
494 {
495 nMasterBusHwChannel = Emios_Icu_Ip_GetMasterBus(hwChannel, eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].BusSelected);
496 if (nMasterBusHwChannel < EMIOS_ICU_IP_NUM_OF_CHANNELS)
497 {
498 eMios_Icu_Ip_u8NumOvflByCounterBus[instance][nMasterBusHwChannel]--;
499 if((uint8)0U == eMios_Icu_Ip_u8NumOvflByCounterBus[instance][nMasterBusHwChannel])
500 {
501 /* Disable Interrupt for master bus*/
502 Emios_Icu_Ip_DisableInterrupt(instance, nMasterBusHwChannel);
503 }
504 }
505 }
506 }
507 #endif /* EMIOS_ICU_IP_OVERFLOW_NOTIFICATION_API == STD_ON */
508 #endif /* (EMIOS_ICU_IP_TIMESTAMP_API == STD_ON)||(EMIOS_ICU_IP_SIGNAL_MEASUREMENT_API == STD_ON)||(EMIOS_ICU_IP_EDGE_DETECT_API == STD_ON) */
509
510 /*==================================================================================================
511 * GLOBAL FUNCTIONS
512 ==================================================================================================*/
513 #if (defined (EMIOS_ICU_IP_ENABLE_USER_MODE_SUPPORT))
514 #if (STD_ON == EMIOS_ICU_IP_ENABLE_USER_MODE_SUPPORT)
515
516 #if (defined(MCAL_EMIOS_REG_PROT_AVAILABLE))
517 #if (STD_ON == MCAL_EMIOS_REG_PROT_AVAILABLE)
Emios_Icu_Ip_SetUserAccessAllowed(uint32 EmiosBaseAddr)518 void Emios_Icu_Ip_SetUserAccessAllowed(uint32 EmiosBaseAddr)
519 {
520 SET_USER_ACCESS_ALLOWED(EmiosBaseAddr, EMIOS_PROT_MEM_U32);
521 }
522 #endif /* (STD_ON == MCAL_EMIOS_REG_PROT_AVAILABLE) */
523 #endif /* (defined(MCAL_EMIOS_REG_PROT_AVAILABLE)) */
524
525 #endif /* (STD_ON == EMIOS_ICU_IP_ENABLE_USER_MODE_SUPPORT) */
526 #endif /* defined (EMIOS_ICU_IP_ENABLE_USER_MODE_SUPPORT) */
527
528 /** @implements Emios_Icu_Ip_EnableInterrupt_Activity */
Emios_Icu_Ip_EnableInterrupt(uint8 instance,uint8 hwChannel)529 void Emios_Icu_Ip_EnableInterrupt(uint8 instance, uint8 hwChannel)
530 {
531 /* Clear pending flag */
532 s_emiosBase[instance]->CH.UC[hwChannel].S |= eMIOS_S_FLAG_MASK;
533
534 SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_46();
535 /* Enable interrupt */
536 s_emiosBase[instance]->CH.UC[hwChannel].C |= eMIOS_C_FEN_MASK;
537 SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_46();
538 }
539
540 /** @implements Emios_Icu_Ip_DisableInterrupt_Activity */
Emios_Icu_Ip_DisableInterrupt(uint8 instance,uint8 hwChannel)541 void Emios_Icu_Ip_DisableInterrupt(uint8 instance, uint8 hwChannel)
542 {
543 SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_47();
544 /* Disable interrupt */
545 s_emiosBase[instance]->CH.UC[hwChannel].C &= ~eMIOS_C_FEN_MASK;
546 SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_47();
547 }
548
549 /* @implements Emios_Icu_Ip_Init_Activity */
Emios_Icu_Ip_Init(uint8 instance,const eMios_Icu_Ip_ConfigType * userConfig)550 eMios_Icu_Ip_StatusType Emios_Icu_Ip_Init(uint8 instance, const eMios_Icu_Ip_ConfigType *userConfig)
551 {
552 uint8 hwChannel;
553 uint32 u32RegCCR;
554 uint8 u8MasterBusMode[EMIOS_ICU_IP_NUM_OF_CHANNELS];
555 uint8 index;
556 uint8 u8MasterBusChannelIdx;
557 eMios_Icu_Ip_StatusType retStatus = EMIOS_IP_STATUS_SUCCESS;
558 #if (defined EMIOS_ICU_IP_WSC_SUPPORT)
559 #if (EMIOS_ICU_IP_WSC_SUPPORT == STD_ON)
560 uint32 wsRegisterValue;
561 uint32 wsInputFilter;
562 #endif /* EMIOS_ICU_IP_WSC_SUPPORT */
563 #endif /* defined EMIOS_ICU_IP_WSC_SUPPORT */
564
565 #if (STD_ON == EMIOS_ICU_IP_DEV_ERROR_DETECT)
566 DevAssert(instance < EMIOS_ICU_IP_INSTANCE_COUNT);
567 DevAssert(userConfig != NULL_PTR);
568 #endif
569 if (FALSE == eMios_Icu_Ip_bInstanceState[instance])
570 {
571 eMios_Icu_Ip_bInstanceState[instance] = TRUE;
572
573 if (userConfig->nNumChannels > 0U)
574 {
575 for (index=0U; index < EMIOS_ICU_IP_NUM_OF_CHANNELS; index++)
576 {
577 if (eMios_Icu_Ip_IndexInChState[instance][index] < EMIOS_ICU_IP_NUM_OF_CHANNELS_USED)
578 {
579 eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][index]].channelsInitState = FALSE;
580 }
581 u8MasterBusMode[index] = EMIOS_ICU_IP_CB_NONE;
582 }
583 /* Register Protection - Set UAA bit in GCR - allow USER MODE access */
584 Call_Emios_Icu_Ip_SetUserAccessAllowed((uint32)s_emiosBase[instance]);
585
586 for (index=0U; index < userConfig->nNumChannels; index++)
587 {
588 hwChannel = (*userConfig->pChannelsConfig)[index].hwChannel;
589 eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].channelsInitState = TRUE;
590
591 /* Initialize the state for calling user notification - can be HLD or IPL direct user notification */
592 eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].eMiosChannelNotification = (*userConfig->pChannelsConfig)[index].eMiosChannelNotification;
593
594 /* Take HLD callback pointer and logic channel and store them in state configuration. */
595 eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].eMiosOverflowNotification = (*userConfig->pChannelsConfig)[index].eMiosOverflowNotification;
596 eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].callback = (*userConfig->pChannelsConfig)[index].callback;
597 eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].logicChStateCallback = (*userConfig->pChannelsConfig)[index].logicChStateCallback;
598 eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].callbackParam = (*userConfig->pChannelsConfig)[index].callbackParams;
599
600 /* Set the event which will generate the interrupt */
601 eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].edgeTrigger = (*userConfig->pChannelsConfig)[index].edgeAlignement;
602
603 /* Clear channel config for hwChannel */
604 eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].channelMode = EMIOS_ICU_MODE_NO_MEASUREMENT;
605 #if (defined(EMIOS_ICU_IP_EDGE_COUNT_API) && (STD_ON == EMIOS_ICU_IP_EDGE_COUNT_API))
606 #if (STD_ON == EMIOS_ICU_IP_SET_MAX_COUNTER)
607 eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].maxCounterValue = EMIOS_ICU_IP_INIT_CADR_U32;
608 #endif /* STD_ON == EMIOS_ICU_IP_SET_MAX_COUNTER */
609 #endif /* (defined(EMIOS_ICU_IP_EDGE_COUNT_API) && (STD_ON == EMIOS_ICU_IP_EDGE_COUNT_API)) */
610
611 #if (STD_ON == EMIOS_ICU_IP_SIGNAL_MEASUREMENT_API)
612 eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].measurement = EMIOS_ICU_NO_MEASUREMENT;
613 eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].eMios_Icu_Ip_aPeriod = (uint16)0U;
614 eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].eMios_Icu_Ip_aActivePulseWidth = (uint16)0U;
615 #endif
616 #if (STD_ON == EMIOS_ICU_IP_TIMESTAMP_API)
617 #if (STD_ON == EMIOS_ICU_IP_TIMESTAMP_USES_DMA_IPL)
618 /* Reset aBufferPtr */
619 eMios_Icu_Ip_BufferPtr[eMios_Icu_Ip_IndexInChState[instance][hwChannel]] = 0U;
620 #endif /* (STD_ON == EMIOS_ICU_IP_TIMESTAMP_USES_DMA_IPL) */
621 eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].eMios_Icu_Ip_aBuffer = NULL_PTR;
622 eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].eMios_Icu_Ip_aBufferSize = (uint16)0U;
623 eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].eMios_Icu_Ip_aBufferNotify = (uint16)0U;
624 eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].eMios_Icu_Ip_aNotifyCount = (uint16)0U;
625 eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].eMios_Icu_Ip_aBufferIndex = (uint16)0U;
626 eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].timestampBufferType = (*userConfig->pChannelsConfig)[index].timestampBufferType;
627 #endif /* (STD_ON == EMIOS_ICU_IP_TIMESTAMP_API) */
628 #if ((STD_ON == EMIOS_ICU_IP_SIGNALMEASUREMENT_USES_DMA_IPL) || (STD_ON == EMIOS_ICU_IP_TIMESTAMP_USES_DMA_IPL))
629 eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].dmaChannel = (*userConfig->pChannelsConfig)[index].dmaChannel;
630 #endif
631
632 #if (STD_ON == EMIOS_ICU_USES_MCL_DRIVER)
633 /* Enable EMIOS Channel. */
634 Emios_Mcl_Ip_EnableChannel(instance, hwChannel);
635 #endif
636
637 /* Enter GPIO Mode to Configure Channel */
638 /* Reset mode for selected channel */
639 s_emiosBase[instance]->CH.UC[hwChannel].C = EMIOS_ICU_IP_CCR_CLEAR_U32;
640
641 /* Initialize channel filter, freeze enable, and bus select and disable the
642 * Set Default Edge (included)
643 */
644 u32RegCCR = eMIOS_C_UCPREN_MASK | eMIOS_C_FCK_MASK;
645 u32RegCCR |= eMIOS_C_FREN(((*userConfig->pChannelsConfig)[index].FreezeEn)?1U:0U);
646 u32RegCCR |= eMIOS_C_IF((*userConfig->pChannelsConfig)[index].Filter);
647 u32RegCCR |= eMIOS_C_BSL((*userConfig->pChannelsConfig)[index].CntBus);
648
649 s_emiosBase[instance]->CH.UC[hwChannel].C |= u32RegCCR;
650
651 /* Initialize prescaler value */
652 s_emiosBase[instance]->CH.UC[hwChannel].C2 &= ~eMIOS_C2_UCEXTPRE_MASK;
653 s_emiosBase[instance]->CH.UC[hwChannel].C2 |= eMIOS_C2_UCEXTPRE((*userConfig->pChannelsConfig)[index].Prescaler);
654
655 /* Disable interrupt */
656 Emios_Icu_Ip_DisableInterrupt(instance, hwChannel);
657
658 /* Clear pending interrupt flag (and other flags) for the channel */
659 s_emiosBase[instance]->CH.UC[hwChannel].S |= (eMIOS_S_OVR_MASK | eMIOS_S_OVFL_MASK | eMIOS_S_FLAG_MASK);
660
661 Emios_Icu_Ip_SetActivation( instance, hwChannel, eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].edgeTrigger);
662
663 /* Set Configuration for hwChannel */
664 eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].dmaMode = (*userConfig->pChannelsConfig)[index].chSubMode;
665 eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].operationMode = (*userConfig->pChannelsConfig)[index].ucMode;
666 eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].msWithoutInterrupt = (*userConfig->pChannelsConfig)[index].bWithoutInterrupt;
667 #if (STD_ON == EMIOS_ICU_IP_SIGNAL_MEASUREMENT_API)
668 eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].measurement = (*userConfig->pChannelsConfig)[index].measurementMode;
669 #endif
670 /* Store bus select of hwChannel */
671 eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].BusSelected = (*userConfig->pChannelsConfig)[index].CntBus;
672
673 if (EMIOS_ICU_BUS_INTERNAL_COUNTER != eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].BusSelected)
674 {
675 u8MasterBusChannelIdx = (uint8)Emios_Icu_Ip_GetMasterBus(hwChannel, eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].BusSelected);
676 if(EMIOS_ICU_IP_CB_NONE == u8MasterBusMode[u8MasterBusChannelIdx]) /* This master bus have not been configured*/
677 {
678 /* store master bus mode and master bus pre-scaler*/
679 u8MasterBusMode[u8MasterBusChannelIdx] = (uint8)EMIOS_ICU_IP_MCB_INT_CLOCK_U32;
680 eMios_Icu_Ip_IndexInChState[instance][u8MasterBusChannelIdx] = EMIOS_ICU_IP_MASTERBUS_CHANNEL_USED;
681 #if (STD_ON == EMIOS_ICU_USES_MCL_DRIVER)
682 /* Enable EMIOS Channel to make registers write-able. */
683 Emios_Mcl_Ip_EnableChannel(instance, hwChannel);
684 #endif
685 }
686 }
687 }
688
689 /* configuration for master bus */
690 for (index=0U; index < EMIOS_ICU_IP_NUM_OF_CHANNELS; index++)
691 {
692 if(EMIOS_ICU_IP_CB_NONE != u8MasterBusMode[index]) /* Master bus is used */
693 {
694 #if ((EMIOS_ICU_IP_TIMESTAMP_API == STD_ON)||(EMIOS_ICU_IP_SIGNAL_MEASUREMENT_API == STD_ON)||(EMIOS_ICU_IP_EDGE_DETECT_API == STD_ON))
695 #if (EMIOS_ICU_IP_OVERFLOW_NOTIFICATION_API == STD_ON)
696 /* Reset the number of active channels has the overflow notification function using masterbus. */
697 eMios_Icu_Ip_u8NumOvflByCounterBus[instance][index] = 0;
698 #endif
699 #endif
700 }
701 }
702 }
703 #if (defined EMIOS_ICU_IP_WSC_SUPPORT)
704 #if (EMIOS_ICU_IP_WSC_SUPPORT == STD_ON)
705 if (userConfig->nNumWsChannels > 0U)
706 {
707 for (index=0U; index < userConfig->nNumWsChannels; index++)
708 {
709 hwChannel = (*userConfig->pWSChannelsConfig)[index].HwWsChannel;
710
711 /* Disable mode */
712 s_emiosBase[instance]->CH.WSC[hwChannel + EMIOS_ICU_IP_WSC_CHANNEL_OFFSET].WSC1 &= ~eMIOS_WSC1_MODE_MASK;
713
714 wsRegisterValue = 0U;
715 wsInputFilter = (uint32)(*userConfig->pWSChannelsConfig)[index].WscInputFilter;
716 wsRegisterValue |= eMIOS_WSC1_FREN((*userConfig->pWSChannelsConfig)[index].FreezeEn ? 1U : 0U);
717 wsRegisterValue |= eMIOS_WSC1_FCK((*userConfig->pWSChannelsConfig)[index].FilterClockScr ? 1U : 0U);
718 wsRegisterValue |= eMIOS_WSC1_IF4_7((wsInputFilter & 0xF0U) >> 4U);
719 wsRegisterValue |= eMIOS_WSC1_IF0_3(wsInputFilter & 0x0FU);
720 wsRegisterValue |= eMIOS_WSC1_BSL((*userConfig->pWSChannelsConfig)[index].WscBusSelect);
721 wsRegisterValue |= (uint32)((*userConfig->pWSChannelsConfig)[index].CapEdgeDetect) << eMIOS_WSC1_EDPOLCAP_SHIFT;
722 wsRegisterValue |= eMIOS_WSC1_CPREN(1U);
723 s_emiosBase[instance]->CH.WSC[hwChannel + EMIOS_ICU_IP_WSC_CHANNEL_OFFSET].WSC1 = wsRegisterValue;
724
725 wsRegisterValue = 0U;
726 wsRegisterValue |= (uint32)((*userConfig->pWSChannelsConfig)[index].PwEdgeDetect) << eMIOS_WSC2_EDPOLPW_SHIFT;
727 wsRegisterValue |= eMIOS_WSC2_WSPREMODE((*userConfig->pWSChannelsConfig)[index].IntPrescalerMode ? 1U : 0U);
728 wsRegisterValue |= eMIOS_WSC2_WSPRE((*userConfig->pWSChannelsConfig)[index].IntPrescaler);
729 wsRegisterValue |= eMIOS_WSC2_PWREN((*userConfig->pWSChannelsConfig)[index].ResetCnt ? 1U : 0U);
730 wsRegisterValue |= eMIOS_WSC2_PWSWR(1U);
731 s_emiosBase[instance]->CH.WSC[hwChannel + EMIOS_ICU_IP_WSC_CHANNEL_OFFSET].WSC2 = wsRegisterValue;
732
733 s_emiosBase[instance]->CH.WSC[hwChannel + EMIOS_ICU_IP_WSC_CHANNEL_OFFSET].WSEV |= eMIOS_WSEV_EVENT((*userConfig->pWSChannelsConfig)[index].WscNumEvent);
734
735 s_emiosBase[instance]->CH.WSC[hwChannel + EMIOS_ICU_IP_WSC_CHANNEL_OFFSET].WSFC |= eMIOS_WSFC_FOOE((*userConfig->pWSChannelsConfig)[index].FiFoOverwrite ? 1U : 0U);
736
737 /* Set mode */
738 s_emiosBase[instance]->CH.WSC[hwChannel + EMIOS_ICU_IP_WSC_CHANNEL_OFFSET].WSC1 |= eMIOS_WSC1_MODE((*userConfig->pWSChannelsConfig)[index].WsChannelMode);
739
740 eMios_Icu_Ip_WsChState[instance][hwChannel].WsCAPNotification = (*userConfig->pWSChannelsConfig)[index].WsCAPNotification;
741 eMios_Icu_Ip_WsChState[instance][hwChannel].WsCENotification = (*userConfig->pWSChannelsConfig)[index].WsCENotification;
742 eMios_Icu_Ip_WsChState[instance][hwChannel].WsCEONotification = (*userConfig->pWSChannelsConfig)[index].WsCEONotification;
743 eMios_Icu_Ip_WsChState[instance][hwChannel].WsPWONotification = (*userConfig->pWSChannelsConfig)[index].WsPWONotification;
744 eMios_Icu_Ip_WsChState[instance][hwChannel].WsPWNotification = (*userConfig->pWSChannelsConfig)[index].WsPWNotification;
745 eMios_Icu_Ip_WsChState[instance][hwChannel].EnableInterruptStatus = 0U;
746 }
747 }
748 #endif /* EMIOS_ICU_IP_WSC_SUPPORT */
749 #endif /* defined EMIOS_ICU_IP_WSC_SUPPORT */
750 }
751 else
752 {
753 /* Module already initialized - use de-initialize first */
754 retStatus = EMIOS_IP_STATUS_ERROR;
755 }
756 return retStatus;
757 }
758
759 #if (EMIOS_ICU_IP_DEINIT_API == STD_ON)
760 /* @implements Emios_Icu_Ip_Deinit_Activity */
Emios_Icu_Ip_Deinit(uint8 instance)761 eMios_Icu_Ip_StatusType Emios_Icu_Ip_Deinit(uint8 instance)
762 {
763 eMios_Icu_Ip_ModeType nMeasMode;
764 uint8 hwChannel;
765
766 eMios_Icu_Ip_StatusType retStatus = EMIOS_IP_STATUS_SUCCESS;
767
768 #if (STD_ON == EMIOS_ICU_IP_DEV_ERROR_DETECT)
769 DevAssert(instance < EMIOS_ICU_IP_INSTANCE_COUNT);
770 #endif
771
772 if (TRUE == eMios_Icu_Ip_bInstanceState[instance])
773 {
774 eMios_Icu_Ip_bInstanceState[instance] = FALSE;
775
776 for (hwChannel = 0U; hwChannel < EMIOS_ICU_IP_NUM_OF_CHANNELS; hwChannel++)
777 {
778 if (eMios_Icu_Ip_IndexInChState[instance][hwChannel] < EMIOS_ICU_IP_NUM_OF_CHANNELS_USED)
779 {
780 if (TRUE == eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].channelsInitState)
781 {
782 eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].channelsInitState = FALSE;
783
784 nMeasMode = eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].channelMode;
785
786 /* Set all channel registers as after reset */
787 s_emiosBase[instance]->CH.UC[hwChannel].C = EMIOS_ICU_IP_CCR_CLEAR_U32;
788 s_emiosBase[instance]->CH.UC[hwChannel].A = EMIOS_ICU_IP_CCR_CLEAR_U32;
789
790 switch (nMeasMode)
791 {
792 case EMIOS_ICU_MODE_SIGNAL_MEASUREMENT:
793 {
794 s_emiosBase[instance]->CH.UC[hwChannel].B = EMIOS_ICU_IP_CCR_CLEAR_U32;
795 }
796 break;
797
798 case EMIOS_ICU_MODE_EDGE_COUNTER:
799 {
800 s_emiosBase[instance]->CH.UC[hwChannel].CNT = EMIOS_ICU_IP_CCR_CLEAR_U32;
801 }
802 break;
803
804 default:
805 {
806 /*For Misra Compliance*/
807 }
808 break;
809 }
810 /* Clear CSR register */
811 s_emiosBase[instance]->CH.UC[hwChannel].S = EMIOS_ICU_IP_CSR_CLEAR_U32;
812
813 #if (EMIOS_ICU_IP_EDGE_COUNT_API == STD_ON)
814 /* Clear all aEdgeCurrent_Value */
815 eMios_Icu_Ip_u32aEdgeCurrent_Value[eMios_Icu_Ip_IndexInChState[instance][hwChannel]] = (uint32)(0x0U);
816 #endif /* EMIOS_ICU_IP_EDGE_COUNT_API == STD_ON */
817
818 /* if channel using master bus, so de-init for master bus */
819 if (EMIOS_ICU_BUS_INTERNAL_COUNTER != eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].BusSelected)
820 {
821 #if (STD_ON == EMIOS_ICU_USES_MCL_DRIVER)
822 /* Disable eMIOS Channel */
823 Emios_Mcl_Ip_DisableChannel(instance, hwChannel);
824 #endif
825 }
826 /* Clear config for hardware channel */
827 eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].operationMode = EMIOS_ICU_UNINIT;
828 eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].BusSelected = EMIOS_ICU_BUS_INTERNAL_COUNTER;
829 eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].channelMode = EMIOS_ICU_MODE_NO_MEASUREMENT;
830 #if (STD_ON == EMIOS_ICU_IP_SIGNAL_MEASUREMENT_API)
831 eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].measurement = EMIOS_ICU_NO_MEASUREMENT;
832 #endif
833 #if (STD_ON == EMIOS_ICU_IP_TIMESTAMP_API)
834 eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].timestampBufferType = EMIOS_ICU_NO_TIMESTAMP;
835 #endif
836 }
837 }
838 if (EMIOS_ICU_IP_MASTERBUS_CHANNEL_USED == eMios_Icu_Ip_IndexInChState[instance][hwChannel])
839 {
840 eMios_Icu_Ip_IndexInChState[instance][hwChannel] = EMIOS_ICU_IP_CHANNEL_NOT_USED;
841 }
842 }
843 #if (defined EMIOS_ICU_IP_WSC_SUPPORT)
844 #if (EMIOS_ICU_IP_WSC_SUPPORT == STD_ON)
845 for (hwChannel = 0U; hwChannel < EMIOS_ICU_IP_WSC_NUM_OF_CHANNELS; hwChannel ++)
846 {
847 /* Disable mode */
848 s_emiosBase[instance]->CH.WSC[hwChannel + EMIOS_ICU_IP_WSC_CHANNEL_OFFSET].WSC1 &= ~eMIOS_WSC1_MODE_MASK;
849 /* Clear event counter */
850 s_emiosBase[instance]->CH.WSC[hwChannel + EMIOS_ICU_IP_WSC_CHANNEL_OFFSET].WSCAEC &= ~eMIOS_WSCAEC_EVCNT_MASK;
851 s_emiosBase[instance]->CH.WSC[hwChannel + EMIOS_ICU_IP_WSC_CHANNEL_OFFSET].WSEV = 0U;
852 /* Disable channel pre-scaler and Pulse Width Detection Edge */
853 s_emiosBase[instance]->CH.WSC[hwChannel + EMIOS_ICU_IP_WSC_CHANNEL_OFFSET].WSC2 = 0U;
854 /* Clear FIFO Overflow Overwrite */
855 s_emiosBase[instance]->CH.WSC[hwChannel + EMIOS_ICU_IP_WSC_CHANNEL_OFFSET].WSFC &= ~eMIOS_WSFC_FOOE_MASK;
856 /* Reset WSC Control 1 */
857 s_emiosBase[instance]->CH.WSC[hwChannel + EMIOS_ICU_IP_WSC_CHANNEL_OFFSET].WSC1 = 0U;
858 /* Clears all data stored in the FIFO */
859 s_emiosBase[instance]->CH.WSC[hwChannel + EMIOS_ICU_IP_WSC_CHANNEL_OFFSET].WSFC |= eMIOS_WSFC_CLRF(1U);
860 /* Clear pulse width count.*/
861 s_emiosBase[instance]->CH.WSC[hwChannel + EMIOS_ICU_IP_WSC_CHANNEL_OFFSET].WSPWCNT &= ~eMIOS_WSPWCNT_T16PWCNT_MASK;
862 /* Clear all flags.*/
863 s_emiosBase[instance]->CH.WSC[hwChannel + EMIOS_ICU_IP_WSC_CHANNEL_OFFSET].WSS |= (eMIOS_WSS_FLAGCEC(1U) | eMIOS_WSS_FLAGECOC(1U) | eMIOS_WSS_FLAGPWC(1U) | eMIOS_WSS_FLAGCAPC(1U) | eMIOS_WSS_FLAGPWOC(1U) | eMIOS_WSS_FLAGFFC(1U));
864 /* Clear all Overrun flags.*/
865 s_emiosBase[instance]->CH.WSC[hwChannel + EMIOS_ICU_IP_WSC_CHANNEL_OFFSET].WSS |= (eMIOS_WSS_OVRCEC(1U) | eMIOS_WSS_OVRECOC(1U) | eMIOS_WSS_OVRPWC(1U) | eMIOS_WSS_OVRCAPC(1U) | eMIOS_WSS_OVRPWOC(1U));
866
867 eMios_Icu_Ip_WsChState[instance][hwChannel].EnableInterruptStatus = 0U;
868 }
869 #endif /* EMIOS_ICU_IP_WSC_SUPPORT */
870 #endif /* defined EMIOS_ICU_IP_WSC_SUPPORT */
871 }
872 else
873 {
874 /* Module already de-init - use init first */
875 retStatus = EMIOS_IP_STATUS_ERROR;
876 }
877 return retStatus;
878 }
879 #endif
880
881 #if (EMIOS_ICU_IP_SET_MODE_API == STD_ON)
Emios_Icu_Ip_SetSleepMode(uint8 instance,uint8 hwChannel)882 void Emios_Icu_Ip_SetSleepMode(uint8 instance, uint8 hwChannel)
883 {
884 #if (STD_ON == EMIOS_ICU_IP_DEV_ERROR_DETECT)
885 DevAssert(instance < EMIOS_ICU_IP_INSTANCE_COUNT);
886 DevAssert(hwChannel < EMIOS_ICU_IP_NUM_OF_CHANNELS);
887 DevAssert(eMios_Icu_Ip_IndexInChState[instance][hwChannel] < EMIOS_ICU_IP_NUM_OF_CHANNELS_USED);
888 #endif
889 /* Stop eMIOS channel */
890 Emios_Icu_Ip_DisableInterrupt(instance, hwChannel);
891 }
892
Emios_Icu_Ip_SetNormalMode(uint8 instance,uint8 hwChannel)893 void Emios_Icu_Ip_SetNormalMode(uint8 instance, uint8 hwChannel)
894 {
895 #if (STD_ON == EMIOS_ICU_IP_DEV_ERROR_DETECT)
896 DevAssert(instance < EMIOS_ICU_IP_INSTANCE_COUNT);
897 DevAssert(hwChannel < EMIOS_ICU_IP_NUM_OF_CHANNELS);
898 #endif
899
900 /* Enable interrupt */
901 Emios_Icu_Ip_EnableInterrupt(instance, hwChannel);
902 }
903 #endif /* EMIOS_ICU_IP_SET_MODE_API */
904
905 /* @implements Emios_Icu_Ip_SetActivation_Activity */
Emios_Icu_Ip_SetActivation(uint8 instance,uint8 hwChannel,eMios_Icu_Ip_EdgeType edge)906 void Emios_Icu_Ip_SetActivation(uint8 instance, uint8 hwChannel, eMios_Icu_Ip_EdgeType edge)
907 {
908 #if (STD_ON == EMIOS_ICU_IP_SIGNAL_MEASUREMENT_USES_SAIC_MODE)
909 uint32 u32RegEmiosCCR;
910 #endif /* STD_ON == EMIOS_ICU_IP_SIGNAL_MEASUREMENT_USES_SAIC_MODE */
911
912 #if (STD_ON == EMIOS_ICU_IP_DEV_ERROR_DETECT)
913 DevAssert(instance < EMIOS_ICU_IP_INSTANCE_COUNT);
914 DevAssert(hwChannel < EMIOS_ICU_IP_NUM_OF_CHANNELS);
915 #endif
916 SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_50();
917 switch (edge)
918 {
919 #if (STD_ON == EMIOS_ICU_IP_SIGNAL_MEASUREMENT_USES_SAIC_MODE)
920 case EMIOS_OPPOSITE_EDGES:
921 {
922 u32RegEmiosCCR = s_emiosBase[instance]->CH.UC[hwChannel].C;
923 s_emiosBase[instance]->CH.UC[hwChannel].C = (u32RegEmiosCCR ^ eMIOS_C_EDPOL_MASK);
924 }
925 break;
926 #endif /* STD_ON == EMIOS_ICU_IP_SIGNAL_MEASUREMENT_USES_SAIC_MODE */
927
928 case EMIOS_ICU_BOTH_EDGES:
929 {
930 s_emiosBase[instance]->CH.UC[hwChannel].C |= eMIOS_C_EDSEL_MASK;
931 }
932 break;
933
934 case EMIOS_ICU_RISING_EDGE:
935 {
936 s_emiosBase[instance]->CH.UC[hwChannel].C &= ~eMIOS_C_EDSEL_MASK;
937 s_emiosBase[instance]->CH.UC[hwChannel].C |= eMIOS_C_EDPOL_MASK;
938 }
939 break;
940
941 default:
942 {
943 /* EMIOS_ICU_FALLING_EDGE */
944 s_emiosBase[instance]->CH.UC[hwChannel].C &= ~(eMIOS_C_EDSEL_MASK|eMIOS_C_EDPOL_MASK);
945 }
946 break;
947 }
948 SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_50();
949 }
950
951 #if (EMIOS_ICU_IP_EDGE_DETECT_API == STD_ON)
952 /* @implements Emios_Icu_Ip_EnableEdgeDetection_Activity */
Emios_Icu_Ip_EnableEdgeDetection(uint8 instance,uint8 hwChannel)953 void Emios_Icu_Ip_EnableEdgeDetection(uint8 instance, uint8 hwChannel)
954 {
955
956 #if (STD_ON == EMIOS_ICU_IP_DEV_ERROR_DETECT)
957 DevAssert(instance < EMIOS_ICU_IP_INSTANCE_COUNT);
958 DevAssert(hwChannel < EMIOS_ICU_IP_NUM_OF_CHANNELS);
959 DevAssert(eMios_Icu_Ip_IndexInChState[instance][hwChannel] < EMIOS_ICU_IP_NUM_OF_CHANNELS_USED);
960 #endif
961 /* Enter GPIO Mode */
962 Emios_Icu_Ip_UCSetMode(instance, hwChannel, EMIOS_ICU_IP_CCR_MODE_GPI_U32);
963
964 /* Enable SAIC mode */
965 Emios_Icu_Ip_UCSetMode(instance, hwChannel, EMIOS_ICU_IP_CCR_MODE_SAIC_U32);
966
967 /* Enable Interrupt */
968 Emios_Icu_Ip_EnableInterrupt(instance, hwChannel);
969
970 /* Set Channel Config */
971 eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].channelMode = EMIOS_ICU_MODE_SIGNAL_EDGE_DETECT;
972
973 #if (EMIOS_ICU_IP_OVERFLOW_NOTIFICATION_API == STD_ON)
974 /* Enable Interrupt for masterbus*/
975 Emios_Icu_Ip_EnableMasterBusInterrupt(instance, hwChannel);
976 #endif
977 }
978
979 /* @implements Emios_Icu_Ip_DisableEdgeDetection_Activity */
Emios_Icu_Ip_DisableEdgeDetection(uint8 instance,uint8 hwChannel)980 void Emios_Icu_Ip_DisableEdgeDetection(uint8 instance, uint8 hwChannel)
981 {
982
983 #if (STD_ON == EMIOS_ICU_IP_DEV_ERROR_DETECT)
984 DevAssert(instance < EMIOS_ICU_IP_INSTANCE_COUNT);
985 DevAssert(hwChannel < EMIOS_ICU_IP_NUM_OF_CHANNELS);
986 DevAssert(eMios_Icu_Ip_IndexInChState[instance][hwChannel] < EMIOS_ICU_IP_NUM_OF_CHANNELS_USED);
987 #endif
988 /* Disable interrupt */
989 Emios_Icu_Ip_DisableInterrupt(instance, hwChannel);
990
991 /* Enter GPIO Mode */
992 Emios_Icu_Ip_UCSetMode(instance, hwChannel, EMIOS_ICU_IP_CCR_MODE_GPI_U32);
993
994 /* Clear Channel Config */
995 eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].channelMode = EMIOS_ICU_MODE_NO_MEASUREMENT;
996
997 #if (EMIOS_ICU_IP_OVERFLOW_NOTIFICATION_API == STD_ON)
998 /* Disable Interrupt for masterbus*/
999 Emios_Icu_Ip_DisableMasterBusInterrupt(instance, hwChannel);
1000 #endif
1001 }
1002 #endif /* EMIOS_ICU_IP_EDGE_DETECT_API */
1003
1004 /* @implements Emios_Icu_Ip_EnableNotification_Activity */
Emios_Icu_Ip_EnableNotification(uint8 instance,uint8 hwChannel)1005 void Emios_Icu_Ip_EnableNotification(uint8 instance, uint8 hwChannel)
1006 {
1007 #if (STD_ON == EMIOS_ICU_IP_DEV_ERROR_DETECT)
1008 DevAssert(instance < EMIOS_ICU_IP_INSTANCE_COUNT);
1009 DevAssert(hwChannel < EMIOS_ICU_IP_NUM_OF_CHANNELS);
1010 DevAssert(eMios_Icu_Ip_IndexInChState[instance][hwChannel] < EMIOS_ICU_IP_NUM_OF_CHANNELS_USED);
1011 #endif
1012
1013 eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].notificationEnable = TRUE;
1014 }
1015
1016 /* @implements Emios_Icu_Ip_DisableNotification_Activity */
Emios_Icu_Ip_DisableNotification(uint8 instance,uint8 hwChannel)1017 void Emios_Icu_Ip_DisableNotification(uint8 instance, uint8 hwChannel)
1018 {
1019 #if (STD_ON == EMIOS_ICU_IP_DEV_ERROR_DETECT)
1020 DevAssert(instance < EMIOS_ICU_IP_INSTANCE_COUNT);
1021 DevAssert(hwChannel < EMIOS_ICU_IP_NUM_OF_CHANNELS);
1022 DevAssert(eMios_Icu_Ip_IndexInChState[instance][hwChannel] < EMIOS_ICU_IP_NUM_OF_CHANNELS_USED);
1023 #endif
1024
1025 eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].notificationEnable = FALSE;
1026 }
1027
1028 #if (EMIOS_ICU_IP_TIMESTAMP_API == STD_ON)
1029 /* @implements Emios_Icu_Ip_StartTimestamp_Activity */
Emios_Icu_Ip_StartTimestamp(uint8 instance,uint8 hwChannel,eMios_Icu_ValueType * bufferPtr,uint16 bufferSize,uint16 notifyInterval)1030 void Emios_Icu_Ip_StartTimestamp
1031 (
1032 uint8 instance,
1033 uint8 hwChannel,
1034 eMios_Icu_ValueType * bufferPtr,
1035 uint16 bufferSize,
1036 uint16 notifyInterval
1037 )
1038 {
1039 #if (STD_ON == EMIOS_ICU_IP_TIMESTAMP_USES_DMA_IPL)
1040 Dma_Ip_LogicChannelTransferListType global_DmaChannelTransferList[11U];
1041 #endif /* (EMIOS_ICU_IP_TIMESTAMP_USES_DMA_IPL == STD_ON) */
1042
1043 #if (STD_ON == EMIOS_ICU_IP_DEV_ERROR_DETECT)
1044 DevAssert(instance < EMIOS_ICU_IP_INSTANCE_COUNT);
1045 DevAssert(hwChannel < EMIOS_ICU_IP_NUM_OF_CHANNELS);
1046 DevAssert(eMios_Icu_Ip_IndexInChState[instance][hwChannel] < EMIOS_ICU_IP_NUM_OF_CHANNELS_USED);
1047 #endif
1048 SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_51();
1049 eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].eMios_Icu_Ip_aBuffer = bufferPtr;
1050 eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].eMios_Icu_Ip_aBufferSize = bufferSize;
1051 eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].eMios_Icu_Ip_aBufferNotify = notifyInterval;
1052 eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].eMios_Icu_Ip_aNotifyCount = (uint16)0U;
1053 eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].eMios_Icu_Ip_aBufferIndex = (uint16)0U;
1054 SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_51();
1055
1056 /* Reset aBufferPtr */
1057 eMios_Icu_Ip_BufferPtr[eMios_Icu_Ip_IndexInChState[instance][hwChannel]] = 0U;
1058
1059 #if (STD_ON == EMIOS_ICU_IP_TIMESTAMP_USES_DMA_IPL)
1060 /* Setup DMA in Dma_Ip*/
1061 if (0xFFU != eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].dmaChannel)
1062 {
1063 /* Create the desired configuration list. */
1064 global_DmaChannelTransferList[0U].Param = DMA_IP_CH_SET_SOURCE_ADDRESS;
1065 global_DmaChannelTransferList[0U].Value = Emios_Icu_Ip_GetStartAddress(instance, hwChannel);
1066 /* Compiler_Warning: DMA TCD addresses are restricted to 32 bits, so casting from pointer type to uint32 is safe.
1067 * The application should ensure that only addresses that fit in uint32 are used for configuring DMA. */
1068 global_DmaChannelTransferList[1U].Param = DMA_IP_CH_SET_DESTINATION_ADDRESS;
1069 global_DmaChannelTransferList[1U].Value = (uint32)bufferPtr;
1070 global_DmaChannelTransferList[2U].Param = DMA_IP_CH_SET_DESTINATION_TRANSFER_SIZE;
1071 global_DmaChannelTransferList[2U].Value = (uint32)DMA_IP_TRANSFER_SIZE_4_BYTE;
1072 global_DmaChannelTransferList[3U].Param = DMA_IP_CH_SET_SOURCE_TRANSFER_SIZE;
1073 global_DmaChannelTransferList[3U].Value = (uint32)DMA_IP_TRANSFER_SIZE_4_BYTE;
1074 global_DmaChannelTransferList[4U].Param = DMA_IP_CH_SET_SOURCE_SIGNED_OFFSET;
1075 global_DmaChannelTransferList[4U].Value = (uint32)0U;
1076 global_DmaChannelTransferList[5U].Param = DMA_IP_CH_SET_DESTINATION_SIGNED_OFFSET;
1077 global_DmaChannelTransferList[5U].Value = (uint32)4U;
1078 global_DmaChannelTransferList[6U].Param = DMA_IP_CH_SET_SOURCE_MODULO;
1079 global_DmaChannelTransferList[6U].Value = (uint32)0U;
1080 global_DmaChannelTransferList[7U].Param = DMA_IP_CH_SET_DESTINATION_MODULO;
1081 global_DmaChannelTransferList[7U].Value = (uint32)0U;
1082
1083 if ((notifyInterval >= bufferSize) || (notifyInterval == (uint16)0))
1084 {
1085 global_DmaChannelTransferList[8U].Param = DMA_IP_CH_SET_MINORLOOP_SIZE;
1086 global_DmaChannelTransferList[8U].Value = 4U;
1087 global_DmaChannelTransferList[9U].Param = DMA_IP_CH_SET_MAJORLOOP_COUNT;
1088 global_DmaChannelTransferList[9U].Value = bufferSize;
1089 if ((uint8) EMIOS_ICU_CIRCULAR_BUFFER == eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].timestampBufferType)
1090 {
1091 global_DmaChannelTransferList[10U].Param = DMA_IP_CH_SET_DESTINATION_SIGNED_LAST_ADDR_ADJ;
1092 global_DmaChannelTransferList[10U].Value = (uint32) (~(bufferSize * 4U)) + 1U;
1093 }
1094 else
1095 {
1096 global_DmaChannelTransferList[10U].Param = DMA_IP_CH_SET_CONTROL_DIS_AUTO_REQUEST;
1097 global_DmaChannelTransferList[10U].Value = (uint32)1U;
1098 }
1099 }
1100 else if (notifyInterval < bufferSize)
1101 {
1102 global_DmaChannelTransferList[8U].Param = DMA_IP_CH_SET_MINORLOOP_SIZE;
1103 global_DmaChannelTransferList[8U].Value = 4U;
1104 global_DmaChannelTransferList[9U].Param = DMA_IP_CH_SET_MAJORLOOP_COUNT;
1105 global_DmaChannelTransferList[9U].Value = notifyInterval;
1106 if ((uint8) EMIOS_ICU_CIRCULAR_BUFFER == eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].timestampBufferType)
1107 {
1108
1109 global_DmaChannelTransferList[10U].Param = DMA_IP_CH_SET_DESTINATION_SIGNED_LAST_ADDR_ADJ;
1110 global_DmaChannelTransferList[10U].Value = (uint32)0U;
1111 }
1112 else
1113 {
1114 global_DmaChannelTransferList[10U].Param = DMA_IP_CH_SET_CONTROL_DIS_AUTO_REQUEST;
1115 global_DmaChannelTransferList[10U].Value = (uint32)0U;
1116 }
1117 }
1118 else
1119 {
1120 /* Nothing to be done */
1121 }
1122
1123 Dma_Ip_SetLogicChannelTransferList(eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].dmaChannel, global_DmaChannelTransferList, (uint32)11U);
1124 Dma_Ip_SetLogicChannelCommand(eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].dmaChannel, DMA_IP_CH_SET_HARDWARE_REQUEST);
1125 }
1126 #endif /* (STD_ON == EMIOS_ICU_IP_TIMESTAMP_USES_DMA_IPL) */
1127
1128 /* Make sure channel is in GPIO mode before switching modes */
1129 Emios_Icu_Ip_UCSetMode(instance, hwChannel, EMIOS_ICU_IP_CCR_MODE_GPI_U32);
1130
1131 /* Clear pending interrupts */
1132 s_emiosBase[instance]->CH.UC[hwChannel].S |= (eMIOS_S_OVR_MASK | eMIOS_S_OVFL_MASK | eMIOS_S_FLAG_MASK);
1133
1134 /* Enable SAIC mode */
1135 Emios_Icu_Ip_UCSetMode(instance, hwChannel, EMIOS_ICU_IP_CCR_MODE_SAIC_U32);
1136
1137 if(EMIOS_ICU_MODE_WITH_DMA == eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].dmaMode)
1138 {
1139 SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_51();
1140 s_emiosBase[instance]->CH.UC[hwChannel].C |= (eMIOS_C_DMA_MASK);
1141 SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_51();
1142 }
1143
1144 if (EMIOS_ICU_BUS_INTERNAL_COUNTER == eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].BusSelected)
1145 {
1146 /* Set Max. A value */
1147 s_emiosBase[instance]->CH.UC[hwChannel].A = EMIOS_ICU_IP_INIT_CADR_U32;
1148 }
1149
1150 /* Set channel Config*/
1151 eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].channelMode = EMIOS_ICU_MODE_TIMESTAMP;
1152 /* Enable Interrupt */
1153 Emios_Icu_Ip_EnableInterrupt(instance, hwChannel);
1154
1155 #if (EMIOS_ICU_IP_OVERFLOW_NOTIFICATION_API == STD_ON)
1156 /* Enable Interrupt for masterbus*/
1157 Emios_Icu_Ip_EnableMasterBusInterrupt(instance ,hwChannel);
1158 #endif
1159 }
1160
1161 /* @implements Emios_Icu_Ip_GetTimestampIndex_Activity */
Emios_Icu_Ip_GetTimestampIndex(uint8 instance,uint8 hwChannel)1162 uint16 Emios_Icu_Ip_GetTimestampIndex
1163 (
1164 uint8 instance,
1165 uint8 hwChannel
1166 )
1167 {
1168 uint16 timestampIndex = 0U;
1169
1170 #if (EMIOS_ICU_IP_TIMESTAMP_USES_DMA_IPL == STD_ON)
1171 uint32 startIter;
1172 uint32 crtIter;
1173 uint32* const pStartIter = &startIter;
1174 uint32* const pCrtIter = &crtIter;
1175 #endif
1176
1177 #if (STD_ON == EMIOS_ICU_IP_DEV_ERROR_DETECT)
1178 DevAssert(instance < EMIOS_ICU_IP_INSTANCE_COUNT);
1179 DevAssert(hwChannel < EMIOS_ICU_IP_NUM_OF_CHANNELS);
1180 #endif
1181
1182 #if (STD_ON == EMIOS_ICU_IP_TIMESTAMP_USES_DMA_IPL)
1183 if (0xFFU != eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].dmaChannel)
1184 {
1185 if (NULL_PTR == eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].eMios_Icu_Ip_aBuffer)
1186 {
1187 timestampIndex = 0U;
1188 }
1189 else
1190 {
1191 Dma_Ip_GetLogicChannelParam(eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].dmaChannel, DMA_IP_CH_GET_BEGIN_ITER_COUNT, pStartIter);
1192 Dma_Ip_GetLogicChannelParam(eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].dmaChannel, DMA_IP_CH_GET_CURRENT_ITER_COUNT, pCrtIter);
1193 crtIter = startIter - crtIter;
1194 timestampIndex = eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].eMios_Icu_Ip_aBufferIndex + (uint16)crtIter;
1195 }
1196 }
1197 else
1198 {
1199 #endif /* (STD_ON == EMIOS_ICU_IP_TIMESTAMP_USES_DMA_IPL) */
1200 if (NULL_PTR == eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].eMios_Icu_Ip_aBuffer)
1201 {
1202 timestampIndex = 0U;
1203 }
1204 else
1205 {
1206 timestampIndex = eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].eMios_Icu_Ip_aBufferIndex;
1207 }
1208 #if (STD_ON == EMIOS_ICU_IP_TIMESTAMP_USES_DMA_IPL)
1209 }
1210 #endif /* (STD_ON == EMIOS_ICU_IP_TIMESTAMP_USES_DMA_IPL) */
1211
1212 return timestampIndex;
1213 }
1214
1215 /* @implements Emios_Icu_Ip_StopTimestamp_Activity */
Emios_Icu_Ip_StopTimestamp(uint8 instance,uint8 hwChannel)1216 void Emios_Icu_Ip_StopTimestamp(uint8 instance, uint8 hwChannel)
1217 {
1218 #if (STD_ON == EMIOS_ICU_IP_DEV_ERROR_DETECT)
1219 DevAssert(instance < EMIOS_ICU_IP_INSTANCE_COUNT);
1220 DevAssert(hwChannel < EMIOS_ICU_IP_NUM_OF_CHANNELS);
1221 DevAssert(eMios_Icu_Ip_IndexInChState[instance][hwChannel] < EMIOS_ICU_IP_NUM_OF_CHANNELS_USED);
1222 #endif
1223
1224 #if (STD_ON == EMIOS_ICU_IP_TIMESTAMP_USES_DMA_IPL)
1225 /* Disable Dma for Timestamp */
1226 if (0xFFU != eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].dmaChannel)
1227 {
1228 Dma_Ip_SetLogicChannelCommand(eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].dmaChannel, DMA_IP_CH_CLEAR_HARDWARE_REQUEST);
1229 }
1230 #endif /* (STD_ON == EMIOS_ICU_IP_TIMESTAMP_USES_DMA_IPL) */
1231
1232 /* Disable interrupt */
1233 Emios_Icu_Ip_DisableInterrupt(instance, hwChannel);
1234
1235 /* Enter GPIO Mode */
1236 Emios_Icu_Ip_UCSetMode(instance, hwChannel, EMIOS_ICU_IP_CCR_MODE_GPI_U32);
1237
1238 /* Clear channel Config */
1239 eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].channelMode = EMIOS_ICU_MODE_NO_MEASUREMENT;
1240
1241 if (EMIOS_ICU_BUS_INTERNAL_COUNTER == eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].BusSelected)
1242 {
1243 /* Set Max. A value */
1244 s_emiosBase[instance]->CH.UC[hwChannel].A = EMIOS_ICU_IP_CCR_CLEAR_U32;;
1245 }
1246
1247 #if (EMIOS_ICU_IP_OVERFLOW_NOTIFICATION_API == STD_ON)
1248 /* Disable Interrupt for masterbus*/
1249 Emios_Icu_Ip_DisableMasterBusInterrupt(instance, hwChannel);
1250 #endif
1251 }
1252 #endif /* EMIOS_ICU_IP_TIMESTAMP_API */
1253
1254 #if ((EMIOS_ICU_IP_SIGNALMEASUREMENT_USES_DMA == STD_ON) || (EMIOS_ICU_IP_TIMESTAMP_USES_DMA == STD_ON))
Emios_Icu_Ip_GetStartAddress(uint8 instance,uint8 hwChannel)1255 uint32 Emios_Icu_Ip_GetStartAddress
1256 (
1257 uint8 instance,
1258 uint8 hwChannel
1259 )
1260 {
1261 #if (STD_ON == EMIOS_ICU_IP_DEV_ERROR_DETECT)
1262 DevAssert(instance < EMIOS_ICU_IP_INSTANCE_COUNT);
1263 DevAssert(hwChannel < EMIOS_ICU_IP_NUM_OF_CHANNELS);
1264 #endif
1265 /*return the value of A register*/
1266 return (uint32)(&s_emiosBase[instance]->CH.UC[hwChannel].A);
1267 }
1268 #endif
1269
1270
1271 #if (EMIOS_ICU_IP_EDGE_COUNT_API == STD_ON)
1272
1273 /* @implements Emios_Icu_Ip_ResetEdgeCount_Activity */
Emios_Icu_Ip_ResetEdgeCount(uint8 instance,uint8 hwChannel)1274 void Emios_Icu_Ip_ResetEdgeCount
1275 (
1276 uint8 instance,
1277 uint8 hwChannel
1278 )
1279 {
1280 uint32 u32PrevMode;
1281
1282 #if (STD_ON == EMIOS_ICU_IP_DEV_ERROR_DETECT)
1283 DevAssert(instance < EMIOS_ICU_IP_INSTANCE_COUNT);
1284 DevAssert(hwChannel < EMIOS_ICU_IP_NUM_OF_CHANNELS);
1285 #endif
1286 u32PrevMode = (s_emiosBase[instance]->CH.UC[hwChannel].C & eMIOS_C_MODE_MASK);
1287
1288 /* Disable timer interrupts */
1289 Emios_Icu_Ip_DisableInterrupt(instance, hwChannel);
1290
1291 /* Enter GPIO Mode */
1292 Emios_Icu_Ip_UCSetMode(instance, hwChannel, EMIOS_ICU_IP_CCR_MODE_GPI_U32);
1293
1294 /* Reset counter */
1295 s_emiosBase[instance]->CH.UC[hwChannel].CNT = EMIOS_ICU_IP_INIT_CCNTR_U32;
1296
1297 /* Max. value for register A. If reached, overflow interrupt */
1298 s_emiosBase[instance]->CH.UC[hwChannel].A = EMIOS_ICU_IP_INIT_CADR_U32;
1299
1300 /* Clear pending interrupts */
1301 s_emiosBase[instance]->CH.UC[hwChannel].S |= (eMIOS_S_OVR_MASK | eMIOS_S_OVFL_MASK | eMIOS_S_FLAG_MASK);
1302
1303 /* Restore previous mode */
1304 Emios_Icu_Ip_UCSetMode(instance, hwChannel, u32PrevMode);
1305
1306 /* Cleare Current Value*/
1307 eMios_Icu_Ip_u32aEdgeCurrent_Value[eMios_Icu_Ip_IndexInChState[instance][hwChannel]] = (uint32)0U;
1308 /* Enable timer interrupts */
1309 Emios_Icu_Ip_EnableInterrupt(instance, hwChannel);
1310 }
1311
1312 /* @implements Emios_Icu_Ip_EnableEdgeCount_Activity */
Emios_Icu_Ip_EnableEdgeCount(uint8 instance,uint8 hwChannel)1313 void Emios_Icu_Ip_EnableEdgeCount(uint8 instance, uint8 hwChannel)
1314 {
1315 #if (STD_ON == EMIOS_ICU_IP_DEV_ERROR_DETECT)
1316 DevAssert(instance < EMIOS_ICU_IP_INSTANCE_COUNT);
1317 DevAssert(hwChannel < EMIOS_ICU_IP_NUM_OF_CHANNELS);
1318 DevAssert(eMios_Icu_Ip_IndexInChState[instance][hwChannel] < EMIOS_ICU_IP_NUM_OF_CHANNELS_USED);
1319 #endif
1320 /* Disable interrupt */
1321 Emios_Icu_Ip_DisableInterrupt(instance, hwChannel);
1322 /* Make sure channel is in GPIO mode before switching modes */
1323 Emios_Icu_Ip_UCSetMode(instance, hwChannel, EMIOS_ICU_IP_CCR_MODE_GPI_U32);
1324
1325 /* Set Max. A value */
1326 #if (STD_ON == EMIOS_ICU_IP_SET_MAX_COUNTER)
1327 s_emiosBase[instance]->CH.UC[hwChannel].A = eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].maxCounterValue;
1328 #else
1329 s_emiosBase[instance]->CH.UC[hwChannel].A = EMIOS_ICU_IP_INIT_CADR_U32;
1330 #endif /* STD_ON == EMIOS_ICU_IP_SET_MAX_COUNTER */
1331
1332
1333 /* Sync. eMIOS counter value. (Needed in case of stopping and re-enabling counting)
1334 * Note: Setting GPIO mode, the internal counter was cleared and must be restored
1335 */
1336
1337 /* When call again affter call Emios_Icu_Ip_DisableEdgeCount*/
1338 s_emiosBase[instance]->CH.UC[hwChannel].CNT = eMios_Icu_Ip_u32aEdgeCurrent_Value[eMios_Icu_Ip_IndexInChState[instance][hwChannel]];
1339
1340 /* Modulus counter mode */
1341 Emios_Icu_Ip_UCSetMode(instance, hwChannel, EMIOS_ICU_IP_MCB_EXT_CLOCK_U32);
1342
1343 /* Clear pending interrupts */
1344 s_emiosBase[instance]->CH.UC[hwChannel].S |= (eMIOS_S_OVR_MASK | eMIOS_S_OVFL_MASK | eMIOS_S_FLAG_MASK);
1345
1346 /* Enable interrupt */
1347 Emios_Icu_Ip_EnableInterrupt(instance, hwChannel);
1348
1349 /* Set Channel config */
1350 eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].channelMode = EMIOS_ICU_MODE_EDGE_COUNTER;
1351
1352
1353 }
1354
1355 /* @implements Emios_Icu_Ip_DisableEdgeCount_Activity */
Emios_Icu_Ip_DisableEdgeCount(uint8 instance,uint8 hwChannel)1356 void Emios_Icu_Ip_DisableEdgeCount
1357 (
1358 uint8 instance,
1359 uint8 hwChannel
1360 )
1361 {
1362 #if (STD_ON == EMIOS_ICU_IP_DEV_ERROR_DETECT)
1363 DevAssert(instance < EMIOS_ICU_IP_INSTANCE_COUNT);
1364 DevAssert(hwChannel < EMIOS_ICU_IP_NUM_OF_CHANNELS);
1365 DevAssert(eMios_Icu_Ip_IndexInChState[instance][hwChannel] < EMIOS_ICU_IP_NUM_OF_CHANNELS_USED);
1366 #endif
1367 /* Disable interrupt */
1368 Emios_Icu_Ip_DisableInterrupt(instance, hwChannel);
1369
1370 /* Clear pending interrupts */
1371 s_emiosBase[instance]->CH.UC[hwChannel].S |= (eMIOS_S_OVR_MASK | eMIOS_S_OVFL_MASK | eMIOS_S_FLAG_MASK);
1372
1373 /* Save count, before going to GPIO mode (because counter is reset to 0x0000) */
1374 eMios_Icu_Ip_u32aEdgeCurrent_Value[eMios_Icu_Ip_IndexInChState[instance][hwChannel]] = s_emiosBase[instance]->CH.UC[hwChannel].CNT;
1375
1376 /* Disable MCB mode */
1377 Emios_Icu_Ip_UCSetMode(instance, hwChannel, EMIOS_ICU_IP_CCR_MODE_GPI_U32);
1378
1379 eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].channelMode = EMIOS_ICU_MODE_NO_MEASUREMENT;
1380
1381 #if (STD_ON == EMIOS_ICU_IP_SET_MAX_COUNTER)
1382 eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].maxCounterValue = EMIOS_ICU_IP_INIT_CADR_U32;
1383 #endif /* STD_ON == EMIOS_ICU_IP_SET_MAX_COUNTER */
1384 }
1385
1386
1387 /* @implements Emios_Icu_Ip_GetEdgeNumbers_Activity */
Emios_Icu_Ip_GetEdgeNumbers(uint8 instance,uint8 hwChannel)1388 eMios_Icu_ValueType Emios_Icu_Ip_GetEdgeNumbers
1389 (
1390 uint8 instance,
1391 uint8 hwChannel
1392 )
1393 {
1394 uint32 u32Mode;
1395 eMios_Icu_ValueType u16Result = (eMios_Icu_ValueType)0U;
1396 u32Mode = (s_emiosBase[instance]->CH.UC[hwChannel].C & eMIOS_C_MODE_MASK);
1397
1398 #if (STD_ON == EMIOS_ICU_IP_DEV_ERROR_DETECT)
1399 DevAssert(instance < EMIOS_ICU_IP_INSTANCE_COUNT);
1400 DevAssert(hwChannel < EMIOS_ICU_IP_NUM_OF_CHANNELS);
1401 #endif
1402 /* Check mode after call Emios_Icu_Ip_DisableEdgeCount */
1403 if(EMIOS_ICU_IP_CCR_MODE_GPI_U32 == u32Mode)
1404 {
1405 u16Result = (eMios_Icu_ValueType)eMios_Icu_Ip_u32aEdgeCurrent_Value[eMios_Icu_Ip_IndexInChState[instance][hwChannel]];
1406 }
1407 else
1408 {
1409 u16Result = (eMios_Icu_ValueType)s_emiosBase[instance]->CH.UC[hwChannel].CNT;
1410 }
1411 return u16Result;
1412
1413 }
1414
1415 #if (STD_ON == EMIOS_ICU_IP_SET_INITIAL_COUNTER)
1416 /* @implements Emios_Icu_Ip_SetInitialCounterValue_Activity */
Emios_Icu_Ip_SetInitialCounterValue(uint8 instance,uint8 hwChannel,uint32 initialCounter)1417 void Emios_Icu_Ip_SetInitialCounterValue
1418 (
1419 uint8 instance,
1420 uint8 hwChannel,
1421 uint32 initialCounter
1422 )
1423 {
1424 #if (STD_ON == EMIOS_ICU_IP_DEV_ERROR_DETECT)
1425 DevAssert(instance < EMIOS_ICU_IP_INSTANCE_COUNT);
1426 DevAssert(hwChannel < EMIOS_ICU_IP_NUM_OF_CHANNELS);
1427 #endif
1428
1429 /* Save initial counter for channel */
1430 eMios_Icu_Ip_u32aEdgeCurrent_Value[eMios_Icu_Ip_IndexInChState[instance][hwChannel]]= initialCounter;
1431 }
1432 #endif /* STD_ON == EMIOS_ICU_IP_SET_INITIAL_COUNTER */
1433
1434 #if (STD_ON == EMIOS_ICU_IP_SET_MAX_COUNTER)
1435 /* @implements Emios_Icu_Ip_SetMaxCounterValue_Activity */
Emios_Icu_Ip_SetMaxCounterValue(uint8 instance,uint8 hwChannel,uint32 maxCounter)1436 void Emios_Icu_Ip_SetMaxCounterValue
1437 (
1438 uint8 instance,
1439 uint8 hwChannel,
1440 uint32 maxCounter
1441 )
1442 {
1443 #if (STD_ON == EMIOS_ICU_IP_DEV_ERROR_DETECT)
1444 DevAssert(instance < EMIOS_ICU_IP_INSTANCE_COUNT);
1445 DevAssert(hwChannel < EMIOS_ICU_IP_NUM_OF_CHANNELS);
1446 DevAssert(maxCounter < EMIOS_ICU_IP_COUNTER_MASK);
1447 #endif
1448
1449 /* Save max counter for channel */
1450 eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].maxCounterValue = maxCounter;
1451 }
1452 #endif /* STD_ON == EMIOS_ICU_IP_SET_MAX_COUNTER */
1453 #endif /* EMIOS_ICU_IP_EDGE_COUNT_API */
1454
1455 #if (EMIOS_ICU_IP_SIGNAL_MEASUREMENT_API == STD_ON)
1456 /* @implements Emios_Icu_Ip_StartSignalMeasurement_Activity */
Emios_Icu_Ip_StartSignalMeasurement(uint8 instance,uint8 hwChannel)1457 void Emios_Icu_Ip_StartSignalMeasurement
1458 (
1459 uint8 instance,
1460 uint8 hwChannel
1461 )
1462 {
1463 eMios_Icu_Ip_UCModeType eMiosOperationMode;
1464 #if (STD_ON == EMIOS_ICU_IP_SIGNALMEASUREMENT_USES_DMA_IPL)
1465 /* Setup DMA for this channel */
1466 uint8 u8index = 0U;
1467 Dma_Ip_LogicChannelTransferListType global_DmaChannelTransferList[10U];
1468 #endif
1469
1470 #if (STD_ON == EMIOS_ICU_IP_DEV_ERROR_DETECT)
1471 DevAssert(instance < EMIOS_ICU_IP_INSTANCE_COUNT);
1472 DevAssert(hwChannel < EMIOS_ICU_IP_NUM_OF_CHANNELS);
1473 DevAssert(eMios_Icu_Ip_IndexInChState[instance][hwChannel] < EMIOS_ICU_IP_NUM_OF_CHANNELS_USED);
1474 #endif
1475
1476 #if (STD_ON == EMIOS_ICU_IP_SIGNALMEASUREMENT_USES_DMA_IPL)
1477 /* Setup DMA for this channel */
1478 if (0xFFU != eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].dmaChannel)
1479 {
1480 Emios_Icu_Ip_aIsSecondInterrupt[eMios_Icu_Ip_IndexInChState[instance][hwChannel]] = 0U;
1481 /* initialize the members of the structure */
1482 global_DmaChannelTransferList[0U].Param = DMA_IP_CH_SET_SOURCE_ADDRESS;
1483 global_DmaChannelTransferList[0U].Value = Emios_Icu_Ip_GetStartAddress(instance, hwChannel);
1484 global_DmaChannelTransferList[1U].Param = DMA_IP_CH_SET_DESTINATION_ADDRESS;
1485 global_DmaChannelTransferList[1U].Value = (uint32)&Emios_Icu_Ip_aDmaBuffer[eMios_Icu_Ip_IndexInChState[instance][hwChannel]][0];
1486 global_DmaChannelTransferList[2U].Param = DMA_IP_CH_SET_DESTINATION_TRANSFER_SIZE;
1487 global_DmaChannelTransferList[2U].Value = (uint32)DMA_IP_TRANSFER_SIZE_4_BYTE;
1488 global_DmaChannelTransferList[3U].Param = DMA_IP_CH_SET_SOURCE_TRANSFER_SIZE;
1489 global_DmaChannelTransferList[3U].Value = (uint32)DMA_IP_TRANSFER_SIZE_4_BYTE;
1490 global_DmaChannelTransferList[4U].Param = DMA_IP_CH_SET_SOURCE_SIGNED_OFFSET;
1491 global_DmaChannelTransferList[4U].Value = (uint32)0U;
1492 global_DmaChannelTransferList[5U].Param = DMA_IP_CH_SET_DESTINATION_SIGNED_OFFSET;
1493 global_DmaChannelTransferList[5U].Value = (uint32)4U;
1494 global_DmaChannelTransferList[6U].Param = DMA_IP_CH_SET_SOURCE_MODULO;
1495 global_DmaChannelTransferList[6U].Value = (uint32)0U;
1496 global_DmaChannelTransferList[7U].Param = DMA_IP_CH_SET_DESTINATION_MODULO;
1497 global_DmaChannelTransferList[7U].Value = (uint32)0U;
1498 global_DmaChannelTransferList[8U].Param = DMA_IP_CH_SET_MINORLOOP_SIZE;
1499 global_DmaChannelTransferList[8U].Value = (uint32)4U;
1500 global_DmaChannelTransferList[9U].Param = DMA_IP_CH_SET_MAJORLOOP_COUNT;
1501 global_DmaChannelTransferList[9U].Value = (uint32)1U;
1502
1503 Dma_Ip_SetLogicChannelTransferList(eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].dmaChannel, global_DmaChannelTransferList, (uint32)10U);
1504 Dma_Ip_SetLogicChannelCommand(eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].dmaChannel, DMA_IP_CH_SET_HARDWARE_REQUEST);
1505
1506 /*Clear the DMA result buffer for configured DMA channel*/
1507 for(u8index = 0U; u8index < EMIOS_ICU_IP_DMA_MAJORLOOP_COUNT; u8index++)
1508 {
1509 Emios_Icu_Ip_aDmaBuffer[eMios_Icu_Ip_IndexInChState[instance][hwChannel]][u8index] = (uint16)0;
1510 }
1511 }
1512 #endif
1513
1514 eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].eMios_Icu_Ip_aPeriod = (eMios_Icu_ValueType)0U;
1515 eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].eMios_Icu_Ip_aActivePulseWidth = (eMios_Icu_ValueType)0U;
1516
1517 /* Reset capture and timestart of hwChannel */
1518 eMios_Icu_Ip_CapturedActivePulseWidth[eMios_Icu_Ip_IndexInChState[instance][hwChannel]] = 0U;
1519 eMios_Icu_Ip_TimeStart[eMios_Icu_Ip_IndexInChState[instance][hwChannel]] = 0U;
1520
1521 /* Disable interrupt */
1522 Emios_Icu_Ip_DisableInterrupt(instance, hwChannel);
1523
1524 /* Enter GPIO Mode */
1525 Emios_Icu_Ip_UCSetMode(instance, hwChannel, EMIOS_ICU_IP_CCR_MODE_GPI_U32);
1526
1527 /* Set activation condition */
1528 Emios_Icu_Ip_SetActivation(instance, hwChannel, eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].edgeTrigger);
1529
1530 /* Get operation mode of hardware channel */
1531 if(EMIOS_ICU_MODE_WITH_DMA == eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].dmaMode)\
1532 {
1533 SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_52();
1534 s_emiosBase[instance]->CH.UC[hwChannel].C |= (eMIOS_C_DMA_MASK);
1535 SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_52();
1536 }
1537 eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].channelMode = EMIOS_ICU_MODE_SIGNAL_MEASUREMENT;
1538
1539 eMiosOperationMode = (eMios_Icu_Ip_UCModeType)eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].operationMode;
1540
1541 switch (eMiosOperationMode)
1542 {
1543 case EMIOS_ICU_IPWM:
1544 {
1545 /* Enable IPWM mode */
1546 Emios_Icu_Ip_UCSetMode(instance, hwChannel, EMIOS_ICU_IP_CCR_MODE_IPWM_U32);
1547 }
1548 break;
1549
1550 case EMIOS_ICU_IPM:
1551 {
1552 /* Enable IPM mode */
1553 Emios_Icu_Ip_UCSetMode(instance, hwChannel, EMIOS_ICU_IP_CCR_MODE_IPM_U32);
1554 }
1555 break;
1556
1557 default:
1558 {
1559 /* Enable SAIC mode */
1560 Emios_Icu_Ip_UCSetMode(instance, hwChannel, EMIOS_ICU_IP_CCR_MODE_SAIC_U32);
1561 }
1562 break;
1563 }
1564
1565 if (EMIOS_ICU_BUS_INTERNAL_COUNTER == eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].BusSelected)
1566 {
1567 /* Set Max. A value */
1568 s_emiosBase[instance]->CH.UC[hwChannel].A = EMIOS_ICU_IP_INIT_CADR_U32;
1569 }
1570 /* Clear pending interrupt flag (and other flags) for the channel */
1571 s_emiosBase[instance]->CH.UC[hwChannel].S |= (eMIOS_S_OVR_MASK | eMIOS_S_OVFL_MASK | eMIOS_S_FLAG_MASK);
1572 /* Clear the counter for signal measurement */
1573 eMios_Icu_Ip_aeInt_Counter[eMios_Icu_Ip_IndexInChState[instance][hwChannel]] = EMIOS_ICU_MEASUREMENT_PENDING;
1574 if (TRUE != eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].msWithoutInterrupt)
1575 {
1576 /* Enable Interrupt */
1577 Emios_Icu_Ip_EnableInterrupt(instance, hwChannel);
1578 }
1579
1580 #if (EMIOS_ICU_IP_OVERFLOW_NOTIFICATION_API == STD_ON)
1581 /* Enable Interrupt for masterbus*/
1582 Emios_Icu_Ip_EnableMasterBusInterrupt(instance, hwChannel);
1583 #endif
1584 }
1585
1586 /* @implements Emios_Icu_Ip_StopSignalMeasurement_Activity */
Emios_Icu_Ip_StopSignalMeasurement(uint8 instance,uint8 hwChannel)1587 void Emios_Icu_Ip_StopSignalMeasurement
1588 (
1589 uint8 instance,
1590 uint8 hwChannel
1591 )
1592 {
1593 #if (STD_ON == EMIOS_ICU_IP_DEV_ERROR_DETECT)
1594 DevAssert(instance < EMIOS_ICU_IP_INSTANCE_COUNT);
1595 DevAssert(hwChannel < EMIOS_ICU_IP_NUM_OF_CHANNELS);
1596 DevAssert(eMios_Icu_Ip_IndexInChState[instance][hwChannel] < EMIOS_ICU_IP_NUM_OF_CHANNELS_USED);
1597 #endif
1598 /* Disable interrupt */
1599 Emios_Icu_Ip_DisableInterrupt(instance, hwChannel);
1600
1601 /* Enter GPIO Mode */
1602 Emios_Icu_Ip_UCSetMode(instance, hwChannel, EMIOS_ICU_IP_CCR_MODE_GPI_U32);
1603
1604 SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_49();
1605 /* EDSEL is set to 1 to discard the input in GPIO mode (not to repond the input signal
1606 in GPIO mode)*/
1607 /* Disables the flag generation as defined by EDPOL Bit */
1608 s_emiosBase[instance]->CH.UC[hwChannel].C |= eMIOS_C_EDSEL_MASK;
1609 SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_49();
1610
1611 if (EMIOS_ICU_BUS_INTERNAL_COUNTER == eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].BusSelected)
1612 {
1613 /* Set Max. A value */
1614 s_emiosBase[instance]->CH.UC[hwChannel].A = EMIOS_ICU_IP_CCR_CLEAR_U32;
1615 }
1616 /* Clear pending interrupt flag (and other flags) for the channel */
1617 s_emiosBase[instance]->CH.UC[hwChannel].S |= (eMIOS_S_OVR_MASK | eMIOS_S_OVFL_MASK | eMIOS_S_FLAG_MASK);
1618 /* Clear channel config */
1619 eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].channelMode = EMIOS_ICU_MODE_NO_MEASUREMENT;
1620 #if (EMIOS_ICU_IP_OVERFLOW_NOTIFICATION_API == STD_ON)
1621 /* Disable Interrupt for masterbus*/
1622 Emios_Icu_Ip_DisableMasterBusInterrupt(instance, hwChannel);
1623 #endif
1624 }
1625
1626 /* @implements Emios_Icu_Ip_GetTimeElapsed_Activity */
Emios_Icu_Ip_GetTimeElapsed(uint8 instance,uint8 hwChannel)1627 eMios_Icu_ValueType Emios_Icu_Ip_GetTimeElapsed
1628 (
1629 uint8 instance,
1630 uint8 hwChannel
1631 )
1632 {
1633 eMios_Icu_ValueType timeElapsed = (eMios_Icu_ValueType)0U;
1634
1635 #if (STD_ON == EMIOS_ICU_IP_DEV_ERROR_DETECT)
1636 DevAssert(instance < EMIOS_ICU_IP_INSTANCE_COUNT);
1637 DevAssert(hwChannel < EMIOS_ICU_IP_NUM_OF_CHANNELS);
1638 DevAssert(eMios_Icu_Ip_IndexInChState[instance][hwChannel] < EMIOS_ICU_IP_NUM_OF_CHANNELS_USED);
1639 #endif
1640 if((EMIOS_ICU_DUTY_CYCLE != eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].measurement) && \
1641 (EMIOS_ICU_NO_MEASUREMENT != eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].measurement))
1642 {
1643 if ((eMios_Icu_Ip_MeasType)EMIOS_ICU_PERIOD_TIME == eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].measurement)
1644 {
1645 timeElapsed = eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].eMios_Icu_Ip_aPeriod;
1646 eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].eMios_Icu_Ip_aPeriod = (eMios_Icu_ValueType)0U;
1647 }
1648 else
1649 {
1650 timeElapsed = eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].eMios_Icu_Ip_aActivePulseWidth;
1651 eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].eMios_Icu_Ip_aActivePulseWidth = (eMios_Icu_ValueType)0U;
1652 }
1653 }
1654 #if (STD_ON == EMIOS_ICU_IP_DEV_ERROR_DETECT)
1655 else
1656 {
1657 DevAssert(TRUE);
1658 }
1659 #endif
1660 return timeElapsed;
1661 }
1662
1663 /* @implements Emios_Icu_Ip_GetDutyCycleValues_Activity */
Emios_Icu_Ip_GetDutyCycleValues(uint8 instance,uint8 hwChannel,eMios_Icu_Ip_DutyCycleType * dutyCycleValues)1664 void Emios_Icu_Ip_GetDutyCycleValues
1665 (
1666 uint8 instance,
1667 uint8 hwChannel,
1668 eMios_Icu_Ip_DutyCycleType* dutyCycleValues
1669 )
1670 {
1671
1672 #if (STD_ON == EMIOS_ICU_IP_DEV_ERROR_DETECT)
1673 DevAssert(instance < EMIOS_ICU_IP_INSTANCE_COUNT);
1674 DevAssert(hwChannel < EMIOS_ICU_IP_NUM_OF_CHANNELS);
1675 DevAssert(eMios_Icu_Ip_IndexInChState[instance][hwChannel] < EMIOS_ICU_IP_NUM_OF_CHANNELS_USED);
1676 #endif
1677 if(EMIOS_ICU_DUTY_CYCLE == eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].measurement)
1678 {
1679 if ((eMios_Icu_ValueType)0U != eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].eMios_Icu_Ip_aPeriod)
1680 {
1681 dutyCycleValues->ActiveTime = (eMios_Icu_ValueType)eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].eMios_Icu_Ip_aActivePulseWidth;
1682 dutyCycleValues->PeriodTime = (eMios_Icu_ValueType)eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].eMios_Icu_Ip_aPeriod;
1683 eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].eMios_Icu_Ip_aActivePulseWidth = (eMios_Icu_ValueType)0U;
1684 eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].eMios_Icu_Ip_aPeriod = (eMios_Icu_ValueType)0U;
1685 }
1686 else
1687 {
1688 dutyCycleValues->ActiveTime = (eMios_Icu_ValueType)0U;
1689 dutyCycleValues->PeriodTime = (eMios_Icu_ValueType)0U;
1690 }
1691 }
1692 #if (STD_ON == EMIOS_ICU_IP_DEV_ERROR_DETECT)
1693 else
1694 {
1695 DevAssert(TRUE);
1696 }
1697 #endif
1698 }
1699
1700 /**
1701 * @brief Emios_Icu_Ip_SetPWandPeriod
1702 */
Emios_Icu_Ip_SetPWandPeriod(uint8 instance,uint8 hwChannel,eMios_Icu_ValueType activePulseWidth,eMios_Icu_ValueType period)1703 void Emios_Icu_Ip_SetPWandPeriod(uint8 instance, \
1704 uint8 hwChannel, \
1705 eMios_Icu_ValueType activePulseWidth, \
1706 eMios_Icu_ValueType period)
1707 {
1708 eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].eMios_Icu_Ip_aActivePulseWidth = activePulseWidth;
1709 eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].eMios_Icu_Ip_aPeriod = period;
1710 }
1711 #endif /* EMIOS_ICU_IP_SIGNAL_MEASUREMENT_API */
1712
1713 #if (EMIOS_ICU_IP_GET_INPUT_STATE_API == STD_ON)
Emios_Icu_Ip_GetInputState(uint8 instance,uint8 hwChannel)1714 boolean Emios_Icu_Ip_GetInputState
1715 (
1716 uint8 instance,
1717 uint8 hwChannel
1718 )
1719 {
1720 boolean bResult = FALSE;
1721 uint32 u32ValueCCRFEN;
1722 uint32 u32ValueCSRFLAG;
1723
1724 #if (STD_ON == EMIOS_ICU_IP_DEV_ERROR_DETECT)
1725 DevAssert(instance < EMIOS_ICU_IP_INSTANCE_COUNT);
1726 DevAssert(hwChannel < EMIOS_ICU_IP_NUM_OF_CHANNELS);
1727 #endif
1728 u32ValueCCRFEN = (s_emiosBase[instance]->CH.UC[hwChannel].C & eMIOS_C_FEN_MASK);
1729 u32ValueCSRFLAG = (s_emiosBase[instance]->CH.UC[hwChannel].S & eMIOS_S_FLAG_MASK);
1730
1731 /* Interrupt not enabled, flag bit was set */
1732 if ((eMIOS_C_FEN_MASK != u32ValueCCRFEN) && (eMIOS_S_FLAG_MASK == u32ValueCSRFLAG))
1733 {
1734
1735 /* Clear pending interrupt */
1736 s_emiosBase[instance]->CH.UC[hwChannel].S |= eMIOS_S_FLAG_MASK;
1737 bResult = TRUE;
1738 }
1739
1740 if ((FALSE == eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].msWithoutInterrupt) && \
1741 (EMIOS_ICU_MODE_SIGNAL_MEASUREMENT == eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].channelMode))
1742 {
1743 bResult = FALSE;
1744 }
1745
1746 return bResult;
1747 }
1748 #endif /* EMIOS_ICU_IP_GET_INPUT_STATE_API */
1749
1750 #if (EMIOS_ICU_IP_GET_INPUT_LEVEL_API == STD_ON)
1751 /* @implements Emios_Icu_Ip_GetInputLevel_Activity */
Emios_Icu_Ip_GetInputLevel(uint8 instance,uint8 hwChannel)1752 eMios_Icu_Ip_LevelType Emios_Icu_Ip_GetInputLevel
1753 (
1754 uint8 instance,
1755 uint8 hwChannel
1756 )
1757 {
1758 #if (STD_ON == EMIOS_ICU_IP_DEV_ERROR_DETECT)
1759 DevAssert(instance < EMIOS_ICU_IP_INSTANCE_COUNT);
1760 DevAssert(hwChannel < EMIOS_ICU_IP_NUM_OF_CHANNELS);
1761 #endif
1762 return ((0U != ((s_emiosBase[instance]->CH.UC[hwChannel].S & eMIOS_S_UCIN_MASK)>> eMIOS_S_UCIN_SHIFT))? \
1763 EMIOS_ICU_LEVEL_HIGH : EMIOS_ICU_LEVEL_LOW);
1764 }
1765 #endif /* EMIOS_ICU_IP_GET_INPUT_LEVEL_API == STD_ON */
1766
Emios_Icu_Ip_GetOverflow(uint8 instance,uint8 hwChannel)1767 boolean Emios_Icu_Ip_GetOverflow
1768 (
1769 uint8 instance,
1770 uint8 hwChannel
1771 )
1772 {
1773 uint32 u32RegCSR = (uint32) 0U;
1774
1775 #if (STD_ON == EMIOS_ICU_IP_DEV_ERROR_DETECT)
1776 DevAssert(instance < EMIOS_ICU_IP_INSTANCE_COUNT);
1777 DevAssert(hwChannel < EMIOS_ICU_IP_NUM_OF_CHANNELS);
1778 #endif
1779 u32RegCSR = s_emiosBase[instance]->CH.UC[hwChannel].S;
1780
1781 /* Clear pending interrupt serviced */
1782 s_emiosBase[instance]->CH.UC[hwChannel].S |= eMIOS_S_OVFL_MASK;
1783
1784 return ((eMIOS_S_OVFL_MASK == (u32RegCSR & eMIOS_S_OVFL_MASK)) ? TRUE : FALSE);
1785 }
1786
1787 #if (EMIOS_ICU_IP_DUAL_CLOCK_MODE_API == STD_ON)
Emios_Icu_Ip_SetClockMode(uint8 instance,const eMios_Icu_Ip_ConfigType * peMiosIpConfig,const eMios_Icu_Ip_ClockModeType Prescaler)1788 void Emios_Icu_Ip_SetClockMode
1789 (
1790 uint8 instance,
1791 const eMios_Icu_Ip_ConfigType *peMiosIpConfig,
1792 const eMios_Icu_Ip_ClockModeType Prescaler
1793 )
1794 {
1795 /* logical channel */
1796 uint8 index;
1797 uint8 hwChannel;
1798 eMios_Icu_Ip_BusType nCtrlBus;
1799 uint8 u8MasterBusChannelIdx;
1800 uint8 u8MasterBusUse[EMIOS_ICU_IP_NUM_OF_CHANNELS];
1801
1802 #if (STD_ON == EMIOS_ICU_IP_DEV_ERROR_DETECT)
1803 DevAssert(instance < EMIOS_ICU_IP_INSTANCE_COUNT);
1804 #endif
1805 for (index=0U; index < (uint8)EMIOS_ICU_IP_NUM_OF_CHANNELS; index++)
1806 {
1807 u8MasterBusUse[index] = (uint8)EMIOS_ICU_IP_CB_NONE;
1808 }
1809
1810 for (index=0U; index < peMiosIpConfig->nNumChannels; index++)
1811 {
1812 hwChannel = (*peMiosIpConfig->pChannelsConfig)[index].hwChannel;
1813 nCtrlBus = eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].BusSelected;
1814
1815 if (EMIOS_ICU_BUS_INTERNAL_COUNTER == nCtrlBus)
1816 {
1817 if (EMIOS_ICU_NORMAL_CLK == Prescaler)
1818 {
1819 Emios_Icu_Ip_SetPrescaler( instance,
1820 hwChannel,
1821 (uint32)(*peMiosIpConfig->pChannelsConfig)[index].Prescaler
1822 );
1823 }
1824 else
1825 {
1826 Emios_Icu_Ip_SetPrescaler( instance,
1827 hwChannel,
1828 (uint32)(*peMiosIpConfig->pChannelsConfig)[index].AltPrescaler
1829 );
1830 }
1831 }
1832 else
1833 {
1834 u8MasterBusChannelIdx = (uint8)Emios_Icu_Ip_GetMasterBus(hwChannel, nCtrlBus);
1835
1836 if(u8MasterBusChannelIdx < EMIOS_ICU_IP_NUM_OF_CHANNELS)
1837 {
1838 if(u8MasterBusUse[u8MasterBusChannelIdx] == EMIOS_ICU_IP_CB_NONE)
1839 {
1840 if (EMIOS_ICU_NORMAL_CLK == Prescaler)
1841 {
1842 Emios_Icu_Ip_SetPrescaler( instance,
1843 u8MasterBusChannelIdx,
1844 (uint32)(*peMiosIpConfig->pChannelsConfig)[index].Prescaler
1845 );
1846 }
1847 else
1848 {
1849 Emios_Icu_Ip_SetPrescaler( instance,
1850 u8MasterBusChannelIdx,
1851 (uint32)(*peMiosIpConfig->pChannelsConfig)[index].AltPrescaler
1852 );
1853 }
1854 u8MasterBusUse[u8MasterBusChannelIdx] = (uint8)1U;
1855 }
1856 }
1857 }
1858 }
1859 }
1860 #endif /* EMIOS_ICU_IP_DUAL_CLOCK_MODE_API == STD_ON */
1861
1862 #if ((EMIOS_ICU_IP_CAPTURERGISTER_API == STD_ON) && ((EMIOS_ICU_IP_SIGNAL_MEASUREMENT_API == STD_ON) || (EMIOS_ICU_IP_TIMESTAMP_API == STD_ON)))
1863 /** @implements Emios_Icu_Ip_GetCaptureRegValue_Activity */
Emios_Icu_Ip_GetCaptureRegValue(uint8 instance,uint8 hwChannel)1864 uint32 Emios_Icu_Ip_GetCaptureRegValue
1865 (
1866 uint8 instance,
1867 uint8 hwChannel
1868 )
1869 {
1870 #if (STD_ON == EMIOS_ICU_IP_DEV_ERROR_DETECT)
1871 DevAssert(instance < EMIOS_ICU_IP_INSTANCE_COUNT);
1872 DevAssert(hwChannel < EMIOS_ICU_IP_NUM_OF_CHANNELS);
1873 #endif
1874 return s_emiosBase[instance]->CH.UC[hwChannel].A;
1875 }
1876 #endif /* (EMIOS_ICU_IP_CAPTURERGISTER_API == STD_ON) && ((EMIOS_ICU_IP_SIGNAL_MEASUREMENT_API == STD_ON) || (EMIOS_ICU_IP_TIMESTAMP_API == STD_ON)) */
1877
1878 #if ((EMIOS_ICU_IP_GET_PULSE_WIDTH_API == STD_ON) && (EMIOS_ICU_IP_SIGNAL_MEASUREMENT_API == STD_ON))
1879 /* @implements Emios_Icu_Ip_GetPulseWidth_Activity */
Emios_Icu_Ip_GetPulseWidth(uint8 instance,uint8 hwChannel)1880 void Emios_Icu_Ip_GetPulseWidth
1881 (
1882 uint8 instance,
1883 uint8 hwChannel
1884 )
1885 {
1886 #if (STD_ON == EMIOS_ICU_IP_DEV_ERROR_DETECT)
1887 DevAssert(instance < EMIOS_ICU_IP_INSTANCE_COUNT);
1888 DevAssert(hwChannel < EMIOS_ICU_IP_NUM_OF_CHANNELS);
1889 #endif
1890 Emios_Icu_Ip_SignalMeasurementHandler(instance, hwChannel, FALSE);
1891 }
1892 #endif /* ((EMIOS_ICU_IP_GET_PULSE_WIDTH_API == STD_ON) && (EMIOS_ICU_IP_SIGNAL_MEASUREMENT_API == STD_ON))*/
1893
1894 #if ((EMIOS_ICU_IP_VALIDATE_GLOBAL_CALL == STD_ON) && ((EMIOS_ICU_IP_GET_PULSE_WIDTH_API == STD_ON) && (EMIOS_ICU_IP_SIGNAL_MEASUREMENT_API == STD_ON)))
Emios_Icu_Ip_ValidateSignalMeasureWithoutInterrupt(uint8 instance,uint8 hwChannel)1895 Std_ReturnType Emios_Icu_Ip_ValidateSignalMeasureWithoutInterrupt
1896 (
1897 uint8 instance,
1898 uint8 hwChannel
1899 )
1900 {
1901 /*return ICU signal property without using interrupt*/
1902 return (eMios_Icu_Ip_ChState[eMios_Icu_Ip_IndexInChState[instance][hwChannel]].msWithoutInterrupt)?(Std_ReturnType)E_OK:(Std_ReturnType)E_NOT_OK;
1903 }
1904 #endif /* ((EMIOS_ICU_IP_GET_PULSE_WIDTH_API == STD_ON) && (EMIOS_ICU_IP_SIGNAL_MEASUREMENT_API == STD_ON))*/
1905
1906 #if (defined EMIOS_ICU_IP_WSC_SUPPORT)
1907 #if (EMIOS_ICU_IP_WSC_SUPPORT == STD_ON)
1908 /* @implements Emios_Icu_Ip_GetWheelSpeedTimeMeasurement_Activity */
Emios_Icu_Ip_GetWheelSpeedTimeMeasurement(uint8 instance,uint8 hwWSChannel)1909 uint32 Emios_Icu_Ip_GetWheelSpeedTimeMeasurement(uint8 instance, uint8 hwWSChannel)
1910 {
1911 uint32 timeValue;
1912 uint8 hwWSChannelId;
1913 uint8 wscMode;
1914
1915 #if (STD_ON == EMIOS_ICU_IP_DEV_ERROR_DETECT)
1916 DevAssert(instance < EMIOS_ICU_IP_INSTANCE_COUNT);
1917 DevAssert(hwWSChannel < EMIOS_ICU_IP_WSC_CHANNEL_OFFSET);
1918 #endif
1919 hwWSChannelId = hwWSChannel + EMIOS_ICU_IP_WSC_CHANNEL_OFFSET;
1920 wscMode = (uint8)((s_emiosBase[instance]->CH.WSC[hwWSChannelId].WSC1 & eMIOS_WSC1_MODE_MASK) >> eMIOS_WSC1_MODE_SHIFT);
1921 if ((uint8)EMIOS_WHEEL_SPEED_MODE == wscMode)
1922 {
1923 timeValue = (uint32)((s_emiosBase[instance]->CH.WSC[hwWSChannelId].WSPW & eMIOS_WSPW_T16PWCAP_MASK) >> eMIOS_WSPW_T16PWCAP_SHIFT);
1924 }
1925 else if ((uint8)EMIOS_SENT_MODE == wscMode)
1926 {
1927 timeValue = (uint32)((s_emiosBase[instance]->CH.WSC[hwWSChannelId].WSFR & eMIOS_WSFR_T24CAPA_T16PWD_VAL_MASK) >> eMIOS_WSFR_T24CAPA_T16PWD_VAL_SHIFT);
1928 }
1929 else /* DISABLE MODE */
1930 {
1931 timeValue = 0U;
1932 }
1933
1934 return timeValue;
1935 }
1936
1937 /* @implements Emios_Icu_Ip_GetWheelSpeedCaptureA_Activity */
Emios_Icu_Ip_GetWheelSpeedCaptureA(uint8 instance,uint8 hwWSChannel)1938 uint32 Emios_Icu_Ip_GetWheelSpeedCaptureA(uint8 instance, uint8 hwWSChannel)
1939 {
1940 uint8 hwWSChannelId = hwWSChannel + EMIOS_ICU_IP_WSC_CHANNEL_OFFSET;
1941 #if (STD_ON == EMIOS_ICU_IP_DEV_ERROR_DETECT)
1942 DevAssert(instance < EMIOS_ICU_IP_INSTANCE_COUNT);
1943 DevAssert(hwWSChannel < EMIOS_ICU_IP_WSC_CHANNEL_OFFSET);
1944 #endif
1945 return (uint32)((s_emiosBase[instance]->CH.WSC[hwWSChannelId].WSCAEC & eMIOS_WSCAEC_T24CAPA_MASK) >> eMIOS_WSCAEC_T24CAPA_SHIFT);
1946 }
1947
1948 /* @implements Emios_Icu_Ip_GetWheelSpeedCaptureB_Activity */
Emios_Icu_Ip_GetWheelSpeedCaptureB(uint8 instance,uint8 hwWSChannel)1949 uint32 Emios_Icu_Ip_GetWheelSpeedCaptureB(uint8 instance, uint8 hwWSChannel)
1950 {
1951 uint8 hwWSChannelId = hwWSChannel + EMIOS_ICU_IP_WSC_CHANNEL_OFFSET;
1952 #if (STD_ON == EMIOS_ICU_IP_DEV_ERROR_DETECT)
1953 DevAssert(instance < EMIOS_ICU_IP_INSTANCE_COUNT);
1954 DevAssert(hwWSChannel < EMIOS_ICU_IP_WSC_CHANNEL_OFFSET);
1955 #endif
1956 return (uint32)((s_emiosBase[instance]->CH.WSC[hwWSChannelId].WSCAPB & eMIOS_WSCAPB_T24CAPB_MASK) >> eMIOS_WSCAPB_T24CAPB_SHIFT);
1957 }
1958
1959 /* @implements Emios_Icu_Ip_SetWheelSpeedEvent_Activity */
Emios_Icu_Ip_SetWheelSpeedEvent(uint8 instance,uint8 hwWSChannel,uint8 event)1960 void Emios_Icu_Ip_SetWheelSpeedEvent(uint8 instance, uint8 hwWSChannel, uint8 event)
1961 {
1962 uint8 hwWSChannelId = hwWSChannel + EMIOS_ICU_IP_WSC_CHANNEL_OFFSET;
1963 #if (STD_ON == EMIOS_ICU_IP_DEV_ERROR_DETECT)
1964 DevAssert(instance < EMIOS_ICU_IP_INSTANCE_COUNT);
1965 DevAssert(hwWSChannel < EMIOS_ICU_IP_WSC_CHANNEL_OFFSET);
1966 #endif
1967 s_emiosBase[instance]->CH.WSC[hwWSChannelId].WSEV |= eMIOS_WSEV_EVENT(event);
1968 }
1969
1970 /* @implements Emios_Icu_Ip_GetWheelSpeedCaptureEvent_Activity */
Emios_Icu_Ip_GetWheelSpeedCaptureEvent(uint8 instance,uint8 hwWSChannel)1971 uint32 Emios_Icu_Ip_GetWheelSpeedCaptureEvent(uint8 instance, uint8 hwWSChannel)
1972 {
1973 uint8 hwWSChannelId = hwWSChannel + EMIOS_ICU_IP_WSC_CHANNEL_OFFSET;
1974 #if (STD_ON == EMIOS_ICU_IP_DEV_ERROR_DETECT)
1975 DevAssert(instance < EMIOS_ICU_IP_INSTANCE_COUNT);
1976 DevAssert(hwWSChannel < EMIOS_ICU_IP_WSC_CHANNEL_OFFSET);
1977 #endif
1978 return (uint32)((s_emiosBase[instance]->CH.WSC[hwWSChannelId].WSCEV & eMIOS_WSCEV_T24CAPEV_MASK) >> eMIOS_WSCEV_T24CAPEV_SHIFT);
1979 }
1980
1981 /* @implements Emios_Icu_Ip_GetWheelSpeedEventCnt_Activity */
Emios_Icu_Ip_GetWheelSpeedEventCnt(uint8 instance,uint8 hwWSChannel)1982 uint8 Emios_Icu_Ip_GetWheelSpeedEventCnt(uint8 instance, uint8 hwWSChannel)
1983 {
1984 uint8 hwWSChannelId = hwWSChannel + EMIOS_ICU_IP_WSC_CHANNEL_OFFSET;
1985 #if (STD_ON == EMIOS_ICU_IP_DEV_ERROR_DETECT)
1986 DevAssert(instance < EMIOS_ICU_IP_INSTANCE_COUNT);
1987 DevAssert(hwWSChannel < EMIOS_ICU_IP_WSC_CHANNEL_OFFSET);
1988 #endif
1989 return (uint8)((s_emiosBase[instance]->CH.WSC[hwWSChannelId].WSCAEC & eMIOS_WSCAEC_EVCNT_MASK) >> eMIOS_WSCAEC_EVCNT_SHIFT);
1990 }
1991
1992 /* @implements Emios_Icu_Ip_WheelSpeedEnableInterrupt_Activity */
Emios_Icu_Ip_WheelSpeedEnableInterrupt(uint8 instance,uint8 hwWSChannel,eMios_Icu_Ip_WscIsrSourceType isrSource)1993 void Emios_Icu_Ip_WheelSpeedEnableInterrupt(uint8 instance, uint8 hwWSChannel, eMios_Icu_Ip_WscIsrSourceType isrSource)
1994 {
1995 uint8 hwWSChannelId = hwWSChannel + EMIOS_ICU_IP_WSC_CHANNEL_OFFSET;
1996 #if (STD_ON == EMIOS_ICU_IP_DEV_ERROR_DETECT)
1997 DevAssert(instance < EMIOS_ICU_IP_INSTANCE_COUNT);
1998 DevAssert(hwWSChannel < EMIOS_ICU_IP_WSC_CHANNEL_OFFSET);
1999 #endif
2000 s_emiosBase[instance]->CH.WSC[hwWSChannelId].WSC2 |= eMIOS_WSC2_FLAGSEL(isrSource);
2001
2002 if ((uint8)0U == eMios_Icu_Ip_WsChState[instance][hwWSChannel].EnableInterruptStatus)
2003 {
2004 s_emiosBase[instance]->CH.WSC[hwWSChannelId].WSC1 |= (uint32)eMIOS_WSC1_FEN_MASK;
2005 }
2006 eMios_Icu_Ip_WsChState[instance][hwWSChannel].EnableInterruptStatus |= (uint8)isrSource;
2007 }
2008
2009 /* @implements Emios_Icu_Ip_WheelSpeedDisableInterrupt_Activity */
Emios_Icu_Ip_WheelSpeedDisableInterrupt(uint8 instance,uint8 hwWSChannel,eMios_Icu_Ip_WscIsrSourceType isrSource)2010 void Emios_Icu_Ip_WheelSpeedDisableInterrupt(uint8 instance, uint8 hwWSChannel, eMios_Icu_Ip_WscIsrSourceType isrSource)
2011 {
2012 uint8 hwWSChannelId = hwWSChannel + EMIOS_ICU_IP_WSC_CHANNEL_OFFSET;
2013 #if (STD_ON == EMIOS_ICU_IP_DEV_ERROR_DETECT)
2014 DevAssert(instance < EMIOS_ICU_IP_INSTANCE_COUNT);
2015 DevAssert(hwWSChannel < EMIOS_ICU_IP_WSC_CHANNEL_OFFSET);
2016 #endif
2017 s_emiosBase[instance]->CH.WSC[hwWSChannelId].WSC2 &= ~eMIOS_WSC2_FLAGSEL(isrSource);
2018
2019 if (EMIOS_FLAG_NONE == isrSource)
2020 {
2021 eMios_Icu_Ip_WsChState[instance][hwWSChannel].EnableInterruptStatus = 0U;
2022 }
2023 else
2024 {
2025 eMios_Icu_Ip_WsChState[instance][hwWSChannel].EnableInterruptStatus &= ~((uint8)isrSource);
2026 }
2027
2028 if (0U == eMios_Icu_Ip_WsChState[instance][hwWSChannel].EnableInterruptStatus)
2029 {
2030 s_emiosBase[instance]->CH.WSC[hwWSChannelId].WSC1 &= ~(uint32)eMIOS_WSC1_FEN_MASK;
2031 }
2032 }
2033
2034 /* @implements Emios_Icu_Ip_GetWheelSpeedFifo_Activity */
Emios_Icu_Ip_GetWheelSpeedFifo(uint8 instance,uint8 hwWSChannel,eMios_Icu_Ip_WscFifoType * eMiosWSCFifoData)2035 void Emios_Icu_Ip_GetWheelSpeedFifo(uint8 instance, uint8 hwWSChannel, eMios_Icu_Ip_WscFifoType* eMiosWSCFifoData)
2036 {
2037 uint8 hwWSChannelId = hwWSChannel + EMIOS_ICU_IP_WSC_CHANNEL_OFFSET;
2038 #if (STD_ON == EMIOS_ICU_IP_DEV_ERROR_DETECT)
2039 DevAssert(instance < EMIOS_ICU_IP_INSTANCE_COUNT);
2040 DevAssert(hwWSChannel < EMIOS_ICU_IP_WSC_CHANNEL_OFFSET);
2041 #endif
2042 eMiosWSCFifoData->FifoData = (uint32)((s_emiosBase[instance]->CH.WSC[hwWSChannelId].WSFR & eMIOS_WSFR_T24CAPA_T16PWD_VAL_MASK) >> eMIOS_WSFR_T24CAPA_T16PWD_VAL_SHIFT);
2043 eMiosWSCFifoData->FifoCounter = (uint8)((s_emiosBase[instance]->CH.WSC[hwWSChannelId].WSFCNT & eMIOS_WSFCNT_FCNTR_MASK) >> eMIOS_WSFCNT_FCNTR_SHIFT);
2044 eMiosWSCFifoData->pWrite = (uint8)((s_emiosBase[instance]->CH.WSC[hwWSChannelId].WSFPNT & eMIOS_WSFPNT_FIFOWRPT_MASK) >> eMIOS_WSFPNT_FIFOWRPT_SHIFT);
2045 eMiosWSCFifoData->pRead = (uint8)((s_emiosBase[instance]->CH.WSC[hwWSChannelId].WSFPNT & eMIOS_WSFPNT_FIFORDPT_MASK) >> eMIOS_WSFPNT_FIFORDPT_SHIFT);
2046 }
2047 #endif /* EMIOS_ICU_IP_WSC_SUPPORT */
2048 #endif /* defined EMIOS_ICU_IP_WSC_SUPPORT */
2049
2050 #define ICU_STOP_SEC_CODE
2051 #include "Icu_MemMap.h"
2052
2053 #endif /* EMIOS_ICU_IP_USED */
2054
2055 #ifdef __cplusplus
2056 }
2057 #endif
2058
2059 /** @} */
2060
