1 // Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 // 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 #pragma once 15 16 #ifdef __cplusplus 17 extern "C" { 18 #endif 19 20 #include "soc.h" 21 22 #define EXTMEM_DCACHE_CTRL_REG (DR_REG_EXTMEM_BASE + 0x000) 23 /* EXTMEM_DCACHE_BLOCKSIZE_MODE : R/W ;bitpos:[3] ;default: 1'b0 ; */ 24 /*description: The bit is used to configure cache block size.0: 16 bytes 1: 32 bytes*/ 25 #define EXTMEM_DCACHE_BLOCKSIZE_MODE (BIT(3)) 26 #define EXTMEM_DCACHE_BLOCKSIZE_MODE_M (BIT(3)) 27 #define EXTMEM_DCACHE_BLOCKSIZE_MODE_V 0x1 28 #define EXTMEM_DCACHE_BLOCKSIZE_MODE_S 3 29 /* EXTMEM_DCACHE_SIZE_MODE : R/W ;bitpos:[2] ;default: 1'b0 ; */ 30 /*description: The bit is used to configure cache memory size.0: 32KB 1: 64KB*/ 31 #define EXTMEM_DCACHE_SIZE_MODE (BIT(2)) 32 #define EXTMEM_DCACHE_SIZE_MODE_M (BIT(2)) 33 #define EXTMEM_DCACHE_SIZE_MODE_V 0x1 34 #define EXTMEM_DCACHE_SIZE_MODE_S 2 35 /* EXTMEM_DCACHE_ENABLE : R/W ;bitpos:[0] ;default: 1'b0 ; */ 36 /*description: The bit is used to activate the data cache. 0: disable 1: enable*/ 37 #define EXTMEM_DCACHE_ENABLE (BIT(0)) 38 #define EXTMEM_DCACHE_ENABLE_M (BIT(0)) 39 #define EXTMEM_DCACHE_ENABLE_V 0x1 40 #define EXTMEM_DCACHE_ENABLE_S 0 41 42 #define EXTMEM_DCACHE_CTRL1_REG (DR_REG_EXTMEM_BASE + 0x004) 43 /* EXTMEM_DCACHE_SHUT_CORE1_BUS : R/W ;bitpos:[1] ;default: 1'b1 ; */ 44 /*description: The bit is used to disable core1 dbus 0: enable 1: disable*/ 45 #define EXTMEM_DCACHE_SHUT_CORE1_BUS (BIT(1)) 46 #define EXTMEM_DCACHE_SHUT_CORE1_BUS_M (BIT(1)) 47 #define EXTMEM_DCACHE_SHUT_CORE1_BUS_V 0x1 48 #define EXTMEM_DCACHE_SHUT_CORE1_BUS_S 1 49 /* EXTMEM_DCACHE_SHUT_CORE0_BUS : R/W ;bitpos:[0] ;default: 1'b1 ; */ 50 /*description: The bit is used to disable core0 dbus 0: enable 1: disable*/ 51 #define EXTMEM_DCACHE_SHUT_CORE0_BUS (BIT(0)) 52 #define EXTMEM_DCACHE_SHUT_CORE0_BUS_M (BIT(0)) 53 #define EXTMEM_DCACHE_SHUT_CORE0_BUS_V 0x1 54 #define EXTMEM_DCACHE_SHUT_CORE0_BUS_S 0 55 56 #define EXTMEM_DCACHE_TAG_POWER_CTRL_REG (DR_REG_EXTMEM_BASE + 0x008) 57 /* EXTMEM_DCACHE_TAG_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b1 ; */ 58 /*description: The bit is used to power dcache tag memory up 0: follow rtc_lslp_pd 59 1: power up*/ 60 #define EXTMEM_DCACHE_TAG_MEM_FORCE_PU (BIT(2)) 61 #define EXTMEM_DCACHE_TAG_MEM_FORCE_PU_M (BIT(2)) 62 #define EXTMEM_DCACHE_TAG_MEM_FORCE_PU_V 0x1 63 #define EXTMEM_DCACHE_TAG_MEM_FORCE_PU_S 2 64 /* EXTMEM_DCACHE_TAG_MEM_FORCE_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */ 65 /*description: The bit is used to power dcache tag memory down 0: follow rtc_lslp_pd 66 1: power down*/ 67 #define EXTMEM_DCACHE_TAG_MEM_FORCE_PD (BIT(1)) 68 #define EXTMEM_DCACHE_TAG_MEM_FORCE_PD_M (BIT(1)) 69 #define EXTMEM_DCACHE_TAG_MEM_FORCE_PD_V 0x1 70 #define EXTMEM_DCACHE_TAG_MEM_FORCE_PD_S 1 71 /* EXTMEM_DCACHE_TAG_MEM_FORCE_ON : R/W ;bitpos:[0] ;default: 1'b1 ; */ 72 /*description: The bit is used to close clock gating of dcache tag memory. 1: 73 close gating 0: open clock gating.*/ 74 #define EXTMEM_DCACHE_TAG_MEM_FORCE_ON (BIT(0)) 75 #define EXTMEM_DCACHE_TAG_MEM_FORCE_ON_M (BIT(0)) 76 #define EXTMEM_DCACHE_TAG_MEM_FORCE_ON_V 0x1 77 #define EXTMEM_DCACHE_TAG_MEM_FORCE_ON_S 0 78 79 #define EXTMEM_DCACHE_PRELOCK_CTRL_REG (DR_REG_EXTMEM_BASE + 0x00C) 80 /* EXTMEM_DCACHE_PRELOCK_SCT1_EN : R/W ;bitpos:[1] ;default: 1'h0 ; */ 81 /*description: The bit is used to enable the second section of prelock function.*/ 82 #define EXTMEM_DCACHE_PRELOCK_SCT1_EN (BIT(1)) 83 #define EXTMEM_DCACHE_PRELOCK_SCT1_EN_M (BIT(1)) 84 #define EXTMEM_DCACHE_PRELOCK_SCT1_EN_V 0x1 85 #define EXTMEM_DCACHE_PRELOCK_SCT1_EN_S 1 86 /* EXTMEM_DCACHE_PRELOCK_SCT0_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */ 87 /*description: The bit is used to enable the first section of prelock function.*/ 88 #define EXTMEM_DCACHE_PRELOCK_SCT0_EN (BIT(0)) 89 #define EXTMEM_DCACHE_PRELOCK_SCT0_EN_M (BIT(0)) 90 #define EXTMEM_DCACHE_PRELOCK_SCT0_EN_V 0x1 91 #define EXTMEM_DCACHE_PRELOCK_SCT0_EN_S 0 92 93 #define EXTMEM_DCACHE_PRELOCK_SCT0_ADDR_REG (DR_REG_EXTMEM_BASE + 0x010) 94 /* EXTMEM_DCACHE_PRELOCK_SCT0_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 95 /*description: The bits are used to configure the first start virtual address 96 of data prelock which is combined with DCACHE_PRELOCK_SCT0_SIZE_REG*/ 97 #define EXTMEM_DCACHE_PRELOCK_SCT0_ADDR 0xFFFFFFFF 98 #define EXTMEM_DCACHE_PRELOCK_SCT0_ADDR_M ((EXTMEM_DCACHE_PRELOCK_SCT0_ADDR_V)<<(EXTMEM_DCACHE_PRELOCK_SCT0_ADDR_S)) 99 #define EXTMEM_DCACHE_PRELOCK_SCT0_ADDR_V 0xFFFFFFFF 100 #define EXTMEM_DCACHE_PRELOCK_SCT0_ADDR_S 0 101 102 #define EXTMEM_DCACHE_PRELOCK_SCT1_ADDR_REG (DR_REG_EXTMEM_BASE + 0x014) 103 /* EXTMEM_DCACHE_PRELOCK_SCT1_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 104 /*description: The bits are used to configure the second start virtual address 105 of data prelock which is combined with DCACHE_PRELOCK_SCT1_SIZE_REG*/ 106 #define EXTMEM_DCACHE_PRELOCK_SCT1_ADDR 0xFFFFFFFF 107 #define EXTMEM_DCACHE_PRELOCK_SCT1_ADDR_M ((EXTMEM_DCACHE_PRELOCK_SCT1_ADDR_V)<<(EXTMEM_DCACHE_PRELOCK_SCT1_ADDR_S)) 108 #define EXTMEM_DCACHE_PRELOCK_SCT1_ADDR_V 0xFFFFFFFF 109 #define EXTMEM_DCACHE_PRELOCK_SCT1_ADDR_S 0 110 111 #define EXTMEM_DCACHE_PRELOCK_SCT_SIZE_REG (DR_REG_EXTMEM_BASE + 0x018) 112 /* EXTMEM_DCACHE_PRELOCK_SCT0_SIZE : R/W ;bitpos:[31:16] ;default: 16'h0 ; */ 113 /*description: The bits are used to configure the first length of data locking 114 which is combined with DCACHE_PRELOCK_SCT0_ADDR_REG*/ 115 #define EXTMEM_DCACHE_PRELOCK_SCT0_SIZE 0x0000FFFF 116 #define EXTMEM_DCACHE_PRELOCK_SCT0_SIZE_M ((EXTMEM_DCACHE_PRELOCK_SCT0_SIZE_V)<<(EXTMEM_DCACHE_PRELOCK_SCT0_SIZE_S)) 117 #define EXTMEM_DCACHE_PRELOCK_SCT0_SIZE_V 0xFFFF 118 #define EXTMEM_DCACHE_PRELOCK_SCT0_SIZE_S 16 119 /* EXTMEM_DCACHE_PRELOCK_SCT1_SIZE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ 120 /*description: The bits are used to configure the second length of data locking 121 which is combined with DCACHE_PRELOCK_SCT1_ADDR_REG*/ 122 #define EXTMEM_DCACHE_PRELOCK_SCT1_SIZE 0x0000FFFF 123 #define EXTMEM_DCACHE_PRELOCK_SCT1_SIZE_M ((EXTMEM_DCACHE_PRELOCK_SCT1_SIZE_V)<<(EXTMEM_DCACHE_PRELOCK_SCT1_SIZE_S)) 124 #define EXTMEM_DCACHE_PRELOCK_SCT1_SIZE_V 0xFFFF 125 #define EXTMEM_DCACHE_PRELOCK_SCT1_SIZE_S 0 126 127 #define EXTMEM_DCACHE_LOCK_CTRL_REG (DR_REG_EXTMEM_BASE + 0x01C) 128 /* EXTMEM_DCACHE_LOCK_DONE : RO ;bitpos:[2] ;default: 1'b0 ; */ 129 /*description: The bit is used to indicate unlock/lock operation is finished.*/ 130 #define EXTMEM_DCACHE_LOCK_DONE (BIT(2)) 131 #define EXTMEM_DCACHE_LOCK_DONE_M (BIT(2)) 132 #define EXTMEM_DCACHE_LOCK_DONE_V 0x1 133 #define EXTMEM_DCACHE_LOCK_DONE_S 2 134 /* EXTMEM_DCACHE_UNLOCK_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ 135 /*description: The bit is used to enable unlock operation. It will be cleared 136 by hardware after unlock operation done.*/ 137 #define EXTMEM_DCACHE_UNLOCK_ENA (BIT(1)) 138 #define EXTMEM_DCACHE_UNLOCK_ENA_M (BIT(1)) 139 #define EXTMEM_DCACHE_UNLOCK_ENA_V 0x1 140 #define EXTMEM_DCACHE_UNLOCK_ENA_S 1 141 /* EXTMEM_DCACHE_LOCK_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ 142 /*description: The bit is used to enable lock operation. It will be cleared 143 by hardware after lock operation done.*/ 144 #define EXTMEM_DCACHE_LOCK_ENA (BIT(0)) 145 #define EXTMEM_DCACHE_LOCK_ENA_M (BIT(0)) 146 #define EXTMEM_DCACHE_LOCK_ENA_V 0x1 147 #define EXTMEM_DCACHE_LOCK_ENA_S 0 148 149 #define EXTMEM_DCACHE_LOCK_ADDR_REG (DR_REG_EXTMEM_BASE + 0x020) 150 /* EXTMEM_DCACHE_LOCK_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ 151 /*description: The bits are used to configure the start virtual address for 152 lock operations. It should be combined with DCACHE_LOCK_SIZE_REG.*/ 153 #define EXTMEM_DCACHE_LOCK_ADDR 0xFFFFFFFF 154 #define EXTMEM_DCACHE_LOCK_ADDR_M ((EXTMEM_DCACHE_LOCK_ADDR_V)<<(EXTMEM_DCACHE_LOCK_ADDR_S)) 155 #define EXTMEM_DCACHE_LOCK_ADDR_V 0xFFFFFFFF 156 #define EXTMEM_DCACHE_LOCK_ADDR_S 0 157 158 #define EXTMEM_DCACHE_LOCK_SIZE_REG (DR_REG_EXTMEM_BASE + 0x024) 159 /* EXTMEM_DCACHE_LOCK_SIZE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ 160 /*description: The bits are used to configure the length for lock operations. 161 The bits are the counts of cache block. It should be combined with DCACHE_LOCK_ADDR_REG.*/ 162 #define EXTMEM_DCACHE_LOCK_SIZE 0x0000FFFF 163 #define EXTMEM_DCACHE_LOCK_SIZE_M ((EXTMEM_DCACHE_LOCK_SIZE_V)<<(EXTMEM_DCACHE_LOCK_SIZE_S)) 164 #define EXTMEM_DCACHE_LOCK_SIZE_V 0xFFFF 165 #define EXTMEM_DCACHE_LOCK_SIZE_S 0 166 167 #define EXTMEM_DCACHE_SYNC_CTRL_REG (DR_REG_EXTMEM_BASE + 0x028) 168 /* EXTMEM_DCACHE_SYNC_DONE : RO ;bitpos:[3] ;default: 1'b0 ; */ 169 /*description: The bit is used to indicate clean/writeback/invalidate operation is finished.*/ 170 #define EXTMEM_DCACHE_SYNC_DONE (BIT(3)) 171 #define EXTMEM_DCACHE_SYNC_DONE_M (BIT(3)) 172 #define EXTMEM_DCACHE_SYNC_DONE_V 0x1 173 #define EXTMEM_DCACHE_SYNC_DONE_S 3 174 /* EXTMEM_DCACHE_CLEAN_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ 175 /*description: The bit is used to enable clean operation. It will be cleared 176 by hardware after clean operation done.*/ 177 #define EXTMEM_DCACHE_CLEAN_ENA (BIT(2)) 178 #define EXTMEM_DCACHE_CLEAN_ENA_M (BIT(2)) 179 #define EXTMEM_DCACHE_CLEAN_ENA_V 0x1 180 #define EXTMEM_DCACHE_CLEAN_ENA_S 2 181 /* EXTMEM_DCACHE_WRITEBACK_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ 182 /*description: The bit is used to enable writeback operation. It will be cleared 183 by hardware after writeback operation done.*/ 184 #define EXTMEM_DCACHE_WRITEBACK_ENA (BIT(1)) 185 #define EXTMEM_DCACHE_WRITEBACK_ENA_M (BIT(1)) 186 #define EXTMEM_DCACHE_WRITEBACK_ENA_V 0x1 187 #define EXTMEM_DCACHE_WRITEBACK_ENA_S 1 188 /* EXTMEM_DCACHE_INVALIDATE_ENA : R/W ;bitpos:[0] ;default: 1'b1 ; */ 189 /*description: The bit is used to enable invalidate operation. It will be cleared 190 by hardware after invalidate operation done.*/ 191 #define EXTMEM_DCACHE_INVALIDATE_ENA (BIT(0)) 192 #define EXTMEM_DCACHE_INVALIDATE_ENA_M (BIT(0)) 193 #define EXTMEM_DCACHE_INVALIDATE_ENA_V 0x1 194 #define EXTMEM_DCACHE_INVALIDATE_ENA_S 0 195 196 #define EXTMEM_DCACHE_SYNC_ADDR_REG (DR_REG_EXTMEM_BASE + 0x02C) 197 /* EXTMEM_DCACHE_SYNC_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ 198 /*description: The bits are used to configure the start virtual address for 199 clean operations. It should be combined with DCACHE_SYNC_SIZE_REG.*/ 200 #define EXTMEM_DCACHE_SYNC_ADDR 0xFFFFFFFF 201 #define EXTMEM_DCACHE_SYNC_ADDR_M ((EXTMEM_DCACHE_SYNC_ADDR_V)<<(EXTMEM_DCACHE_SYNC_ADDR_S)) 202 #define EXTMEM_DCACHE_SYNC_ADDR_V 0xFFFFFFFF 203 #define EXTMEM_DCACHE_SYNC_ADDR_S 0 204 205 #define EXTMEM_DCACHE_SYNC_SIZE_REG (DR_REG_EXTMEM_BASE + 0x030) 206 /* EXTMEM_DCACHE_SYNC_SIZE : R/W ;bitpos:[22:0] ;default: 23'h0 ; */ 207 /*description: The bits are used to configure the length for sync operations. 208 The bits are the counts of cache block. It should be combined with DCACHE_SYNC_ADDR_REG.*/ 209 #define EXTMEM_DCACHE_SYNC_SIZE 0x007FFFFF 210 #define EXTMEM_DCACHE_SYNC_SIZE_M ((EXTMEM_DCACHE_SYNC_SIZE_V)<<(EXTMEM_DCACHE_SYNC_SIZE_S)) 211 #define EXTMEM_DCACHE_SYNC_SIZE_V 0x7FFFFF 212 #define EXTMEM_DCACHE_SYNC_SIZE_S 0 213 214 #define EXTMEM_DCACHE_OCCUPY_CTRL_REG (DR_REG_EXTMEM_BASE + 0x034) 215 /* EXTMEM_DCACHE_OCCUPY_DONE : RO ;bitpos:[1] ;default: 1'b0 ; */ 216 /*description: The bit is used to indicate occupy operation is finished.*/ 217 #define EXTMEM_DCACHE_OCCUPY_DONE (BIT(1)) 218 #define EXTMEM_DCACHE_OCCUPY_DONE_M (BIT(1)) 219 #define EXTMEM_DCACHE_OCCUPY_DONE_V 0x1 220 #define EXTMEM_DCACHE_OCCUPY_DONE_S 1 221 /* EXTMEM_DCACHE_OCCUPY_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ 222 /*description: The bit is used to enable occupy operation. It will be cleared 223 by hardware after issuing Auot-Invalidate Operation.*/ 224 #define EXTMEM_DCACHE_OCCUPY_ENA (BIT(0)) 225 #define EXTMEM_DCACHE_OCCUPY_ENA_M (BIT(0)) 226 #define EXTMEM_DCACHE_OCCUPY_ENA_V 0x1 227 #define EXTMEM_DCACHE_OCCUPY_ENA_S 0 228 229 #define EXTMEM_DCACHE_OCCUPY_ADDR_REG (DR_REG_EXTMEM_BASE + 0x038) 230 /* EXTMEM_DCACHE_OCCUPY_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ 231 /*description: The bits are used to configure the start virtual address for 232 occupy operation. It should be combined with DCACHE_OCCUPY_SIZE_REG.*/ 233 #define EXTMEM_DCACHE_OCCUPY_ADDR 0xFFFFFFFF 234 #define EXTMEM_DCACHE_OCCUPY_ADDR_M ((EXTMEM_DCACHE_OCCUPY_ADDR_V)<<(EXTMEM_DCACHE_OCCUPY_ADDR_S)) 235 #define EXTMEM_DCACHE_OCCUPY_ADDR_V 0xFFFFFFFF 236 #define EXTMEM_DCACHE_OCCUPY_ADDR_S 0 237 238 #define EXTMEM_DCACHE_OCCUPY_SIZE_REG (DR_REG_EXTMEM_BASE + 0x03C) 239 /* EXTMEM_DCACHE_OCCUPY_SIZE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ 240 /*description: The bits are used to configure the length for occupy operation. 241 The bits are the counts of cache block. It should be combined with DCACHE_OCCUPY_ADDR_REG.*/ 242 #define EXTMEM_DCACHE_OCCUPY_SIZE 0x0000FFFF 243 #define EXTMEM_DCACHE_OCCUPY_SIZE_M ((EXTMEM_DCACHE_OCCUPY_SIZE_V)<<(EXTMEM_DCACHE_OCCUPY_SIZE_S)) 244 #define EXTMEM_DCACHE_OCCUPY_SIZE_V 0xFFFF 245 #define EXTMEM_DCACHE_OCCUPY_SIZE_S 0 246 247 #define EXTMEM_DCACHE_PRELOAD_CTRL_REG (DR_REG_EXTMEM_BASE + 0x040) 248 /* EXTMEM_DCACHE_PRELOAD_ORDER : R/W ;bitpos:[2] ;default: 1'b0 ; */ 249 /*description: The bit is used to configure the direction of preload operation. 250 1: descending 0: ascending.*/ 251 #define EXTMEM_DCACHE_PRELOAD_ORDER (BIT(2)) 252 #define EXTMEM_DCACHE_PRELOAD_ORDER_M (BIT(2)) 253 #define EXTMEM_DCACHE_PRELOAD_ORDER_V 0x1 254 #define EXTMEM_DCACHE_PRELOAD_ORDER_S 2 255 /* EXTMEM_DCACHE_PRELOAD_DONE : RO ;bitpos:[1] ;default: 1'b0 ; */ 256 /*description: The bit is used to indicate preload operation is finished.*/ 257 #define EXTMEM_DCACHE_PRELOAD_DONE (BIT(1)) 258 #define EXTMEM_DCACHE_PRELOAD_DONE_M (BIT(1)) 259 #define EXTMEM_DCACHE_PRELOAD_DONE_V 0x1 260 #define EXTMEM_DCACHE_PRELOAD_DONE_S 1 261 /* EXTMEM_DCACHE_PRELOAD_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ 262 /*description: The bit is used to enable preload operation. It will be cleared 263 by hardware after preload operation done.*/ 264 #define EXTMEM_DCACHE_PRELOAD_ENA (BIT(0)) 265 #define EXTMEM_DCACHE_PRELOAD_ENA_M (BIT(0)) 266 #define EXTMEM_DCACHE_PRELOAD_ENA_V 0x1 267 #define EXTMEM_DCACHE_PRELOAD_ENA_S 0 268 269 #define EXTMEM_DCACHE_PRELOAD_ADDR_REG (DR_REG_EXTMEM_BASE + 0x044) 270 /* EXTMEM_DCACHE_PRELOAD_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ 271 /*description: The bits are used to configure the start virtual address for 272 preload operation. It should be combined with DCACHE_PRELOAD_SIZE_REG.*/ 273 #define EXTMEM_DCACHE_PRELOAD_ADDR 0xFFFFFFFF 274 #define EXTMEM_DCACHE_PRELOAD_ADDR_M ((EXTMEM_DCACHE_PRELOAD_ADDR_V)<<(EXTMEM_DCACHE_PRELOAD_ADDR_S)) 275 #define EXTMEM_DCACHE_PRELOAD_ADDR_V 0xFFFFFFFF 276 #define EXTMEM_DCACHE_PRELOAD_ADDR_S 0 277 278 #define EXTMEM_DCACHE_PRELOAD_SIZE_REG (DR_REG_EXTMEM_BASE + 0x048) 279 /* EXTMEM_DCACHE_PRELOAD_SIZE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ 280 /*description: The bits are used to configure the length for preload operation. 281 The bits are the counts of cache block. It should be combined with DCACHE_PRELOAD_ADDR_REG..*/ 282 #define EXTMEM_DCACHE_PRELOAD_SIZE 0x0000FFFF 283 #define EXTMEM_DCACHE_PRELOAD_SIZE_M ((EXTMEM_DCACHE_PRELOAD_SIZE_V)<<(EXTMEM_DCACHE_PRELOAD_SIZE_S)) 284 #define EXTMEM_DCACHE_PRELOAD_SIZE_V 0xFFFF 285 #define EXTMEM_DCACHE_PRELOAD_SIZE_S 0 286 287 #define EXTMEM_DCACHE_AUTOLOAD_CTRL_REG (DR_REG_EXTMEM_BASE + 0x04C) 288 /* EXTMEM_DCACHE_AUTOLOAD_SIZE : R/W ;bitpos:[8:7] ;default: 2'h0 ; */ 289 /*description: The bits are used to configure the numbers of the cache block 290 for the issuing autoload operation.*/ 291 #define EXTMEM_DCACHE_AUTOLOAD_SIZE 0x00000003 292 #define EXTMEM_DCACHE_AUTOLOAD_SIZE_M ((EXTMEM_DCACHE_AUTOLOAD_SIZE_V)<<(EXTMEM_DCACHE_AUTOLOAD_SIZE_S)) 293 #define EXTMEM_DCACHE_AUTOLOAD_SIZE_V 0x3 294 #define EXTMEM_DCACHE_AUTOLOAD_SIZE_S 7 295 /* EXTMEM_DCACHE_AUTOLOAD_RQST : R/W ;bitpos:[6:5] ;default: 2'b0 ; */ 296 /*description: The bits are used to configure trigger conditions for autoload. 297 0/3: cache miss 1: cache hit 2: both cache miss and hit.*/ 298 #define EXTMEM_DCACHE_AUTOLOAD_RQST 0x00000003 299 #define EXTMEM_DCACHE_AUTOLOAD_RQST_M ((EXTMEM_DCACHE_AUTOLOAD_RQST_V)<<(EXTMEM_DCACHE_AUTOLOAD_RQST_S)) 300 #define EXTMEM_DCACHE_AUTOLOAD_RQST_V 0x3 301 #define EXTMEM_DCACHE_AUTOLOAD_RQST_S 5 302 /* EXTMEM_DCACHE_AUTOLOAD_ORDER : R/W ;bitpos:[4] ;default: 1'b0 ; */ 303 /*description: The bits are used to configure the direction of autoload. 1: 304 descending 0: ascending.*/ 305 #define EXTMEM_DCACHE_AUTOLOAD_ORDER (BIT(4)) 306 #define EXTMEM_DCACHE_AUTOLOAD_ORDER_M (BIT(4)) 307 #define EXTMEM_DCACHE_AUTOLOAD_ORDER_V 0x1 308 #define EXTMEM_DCACHE_AUTOLOAD_ORDER_S 4 309 /* EXTMEM_DCACHE_AUTOLOAD_DONE : RO ;bitpos:[3] ;default: 1'b0 ; */ 310 /*description: The bit is used to indicate autoload operation is finished.*/ 311 #define EXTMEM_DCACHE_AUTOLOAD_DONE (BIT(3)) 312 #define EXTMEM_DCACHE_AUTOLOAD_DONE_M (BIT(3)) 313 #define EXTMEM_DCACHE_AUTOLOAD_DONE_V 0x1 314 #define EXTMEM_DCACHE_AUTOLOAD_DONE_S 3 315 /* EXTMEM_DCACHE_AUTOLOAD_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ 316 /*description: The bit is used to enable and disable autoload operation. It 317 is combined with dcache_autoload_done. 1: enable 0: disable.*/ 318 #define EXTMEM_DCACHE_AUTOLOAD_ENA (BIT(2)) 319 #define EXTMEM_DCACHE_AUTOLOAD_ENA_M (BIT(2)) 320 #define EXTMEM_DCACHE_AUTOLOAD_ENA_V 0x1 321 #define EXTMEM_DCACHE_AUTOLOAD_ENA_S 2 322 /* EXTMEM_DCACHE_AUTOLOAD_SCT1_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ 323 /*description: The bits are used to enable the second section for autoload operation.*/ 324 #define EXTMEM_DCACHE_AUTOLOAD_SCT1_ENA (BIT(1)) 325 #define EXTMEM_DCACHE_AUTOLOAD_SCT1_ENA_M (BIT(1)) 326 #define EXTMEM_DCACHE_AUTOLOAD_SCT1_ENA_V 0x1 327 #define EXTMEM_DCACHE_AUTOLOAD_SCT1_ENA_S 1 328 /* EXTMEM_DCACHE_AUTOLOAD_SCT0_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ 329 /*description: The bits are used to enable the first section for autoload operation.*/ 330 #define EXTMEM_DCACHE_AUTOLOAD_SCT0_ENA (BIT(0)) 331 #define EXTMEM_DCACHE_AUTOLOAD_SCT0_ENA_M (BIT(0)) 332 #define EXTMEM_DCACHE_AUTOLOAD_SCT0_ENA_V 0x1 333 #define EXTMEM_DCACHE_AUTOLOAD_SCT0_ENA_S 0 334 335 #define EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR_REG (DR_REG_EXTMEM_BASE + 0x050) 336 /* EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ 337 /*description: The bits are used to configure the start virtual address of the 338 first section for autoload operation. It should be combined with dcache_autoload_sct0_ena.*/ 339 #define EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR 0xFFFFFFFF 340 #define EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR_M ((EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR_V)<<(EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR_S)) 341 #define EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR_V 0xFFFFFFFF 342 #define EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR_S 0 343 344 #define EXTMEM_DCACHE_AUTOLOAD_SCT0_SIZE_REG (DR_REG_EXTMEM_BASE + 0x054) 345 /* EXTMEM_DCACHE_AUTOLOAD_SCT0_SIZE : R/W ;bitpos:[26:0] ;default: 27'h0 ; */ 346 /*description: The bits are used to configure the length of the first section 347 for autoload operation. It should be combined with dcache_autoload_sct0_ena.*/ 348 #define EXTMEM_DCACHE_AUTOLOAD_SCT0_SIZE 0x07FFFFFF 349 #define EXTMEM_DCACHE_AUTOLOAD_SCT0_SIZE_M ((EXTMEM_DCACHE_AUTOLOAD_SCT0_SIZE_V)<<(EXTMEM_DCACHE_AUTOLOAD_SCT0_SIZE_S)) 350 #define EXTMEM_DCACHE_AUTOLOAD_SCT0_SIZE_V 0x7FFFFFF 351 #define EXTMEM_DCACHE_AUTOLOAD_SCT0_SIZE_S 0 352 353 #define EXTMEM_DCACHE_AUTOLOAD_SCT1_ADDR_REG (DR_REG_EXTMEM_BASE + 0x058) 354 /* EXTMEM_DCACHE_AUTOLOAD_SCT1_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ 355 /*description: The bits are used to configure the start virtual address of the 356 second section for autoload operation. It should be combined with dcache_autoload_sct1_ena.*/ 357 #define EXTMEM_DCACHE_AUTOLOAD_SCT1_ADDR 0xFFFFFFFF 358 #define EXTMEM_DCACHE_AUTOLOAD_SCT1_ADDR_M ((EXTMEM_DCACHE_AUTOLOAD_SCT1_ADDR_V)<<(EXTMEM_DCACHE_AUTOLOAD_SCT1_ADDR_S)) 359 #define EXTMEM_DCACHE_AUTOLOAD_SCT1_ADDR_V 0xFFFFFFFF 360 #define EXTMEM_DCACHE_AUTOLOAD_SCT1_ADDR_S 0 361 362 #define EXTMEM_DCACHE_AUTOLOAD_SCT1_SIZE_REG (DR_REG_EXTMEM_BASE + 0x05C) 363 /* EXTMEM_DCACHE_AUTOLOAD_SCT1_SIZE : R/W ;bitpos:[26:0] ;default: 27'h0 ; */ 364 /*description: The bits are used to configure the length of the second section 365 for autoload operation. It should be combined with dcache_autoload_sct1_ena.*/ 366 #define EXTMEM_DCACHE_AUTOLOAD_SCT1_SIZE 0x07FFFFFF 367 #define EXTMEM_DCACHE_AUTOLOAD_SCT1_SIZE_M ((EXTMEM_DCACHE_AUTOLOAD_SCT1_SIZE_V)<<(EXTMEM_DCACHE_AUTOLOAD_SCT1_SIZE_S)) 368 #define EXTMEM_DCACHE_AUTOLOAD_SCT1_SIZE_V 0x7FFFFFF 369 #define EXTMEM_DCACHE_AUTOLOAD_SCT1_SIZE_S 0 370 371 #define EXTMEM_ICACHE_CTRL_REG (DR_REG_EXTMEM_BASE + 0x060) 372 /* EXTMEM_ICACHE_BLOCKSIZE_MODE : R/W ;bitpos:[3] ;default: 1'b0 ; */ 373 /*description: The bit is used to configure cache block size.0: 16 bytes 1: 32 bytes*/ 374 #define EXTMEM_ICACHE_BLOCKSIZE_MODE (BIT(3)) 375 #define EXTMEM_ICACHE_BLOCKSIZE_MODE_M (BIT(3)) 376 #define EXTMEM_ICACHE_BLOCKSIZE_MODE_V 0x1 377 #define EXTMEM_ICACHE_BLOCKSIZE_MODE_S 3 378 /* EXTMEM_ICACHE_SIZE_MODE : R/W ;bitpos:[2] ;default: 1'b0 ; */ 379 /*description: The bit is used to configure cache memory size.0: 16KB 1: 32KB*/ 380 #define EXTMEM_ICACHE_SIZE_MODE (BIT(2)) 381 #define EXTMEM_ICACHE_SIZE_MODE_M (BIT(2)) 382 #define EXTMEM_ICACHE_SIZE_MODE_V 0x1 383 #define EXTMEM_ICACHE_SIZE_MODE_S 2 384 /* EXTMEM_ICACHE_WAY_MODE : R/W ;bitpos:[1] ;default: 1'b0 ; */ 385 /*description: The bit is used to configure cache way mode.0: 4-way 1: 8-way*/ 386 #define EXTMEM_ICACHE_WAY_MODE (BIT(1)) 387 #define EXTMEM_ICACHE_WAY_MODE_M (BIT(1)) 388 #define EXTMEM_ICACHE_WAY_MODE_V 0x1 389 #define EXTMEM_ICACHE_WAY_MODE_S 1 390 /* EXTMEM_ICACHE_ENABLE : R/W ;bitpos:[0] ;default: 1'b0 ; */ 391 /*description: The bit is used to activate the data cache. 0: disable 1: enable*/ 392 #define EXTMEM_ICACHE_ENABLE (BIT(0)) 393 #define EXTMEM_ICACHE_ENABLE_M (BIT(0)) 394 #define EXTMEM_ICACHE_ENABLE_V 0x1 395 #define EXTMEM_ICACHE_ENABLE_S 0 396 397 #define EXTMEM_ICACHE_CTRL1_REG (DR_REG_EXTMEM_BASE + 0x064) 398 /* EXTMEM_ICACHE_SHUT_CORE1_BUS : R/W ;bitpos:[1] ;default: 1'b1 ; */ 399 /*description: The bit is used to disable core1 ibus 0: enable 1: disable*/ 400 #define EXTMEM_ICACHE_SHUT_CORE1_BUS (BIT(1)) 401 #define EXTMEM_ICACHE_SHUT_CORE1_BUS_M (BIT(1)) 402 #define EXTMEM_ICACHE_SHUT_CORE1_BUS_V 0x1 403 #define EXTMEM_ICACHE_SHUT_CORE1_BUS_S 1 404 /* EXTMEM_ICACHE_SHUT_CORE0_BUS : R/W ;bitpos:[0] ;default: 1'b1 ; */ 405 /*description: The bit is used to disable core0 ibus 0: enable 1: disable*/ 406 #define EXTMEM_ICACHE_SHUT_CORE0_BUS (BIT(0)) 407 #define EXTMEM_ICACHE_SHUT_CORE0_BUS_M (BIT(0)) 408 #define EXTMEM_ICACHE_SHUT_CORE0_BUS_V 0x1 409 #define EXTMEM_ICACHE_SHUT_CORE0_BUS_S 0 410 411 #define EXTMEM_ICACHE_TAG_POWER_CTRL_REG (DR_REG_EXTMEM_BASE + 0x068) 412 /* EXTMEM_ICACHE_TAG_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b1 ; */ 413 /*description: The bit is used to power icache tag memory up 0: follow rtc_lslp 1: power up*/ 414 #define EXTMEM_ICACHE_TAG_MEM_FORCE_PU (BIT(2)) 415 #define EXTMEM_ICACHE_TAG_MEM_FORCE_PU_M (BIT(2)) 416 #define EXTMEM_ICACHE_TAG_MEM_FORCE_PU_V 0x1 417 #define EXTMEM_ICACHE_TAG_MEM_FORCE_PU_S 2 418 /* EXTMEM_ICACHE_TAG_MEM_FORCE_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */ 419 /*description: The bit is used to power icache tag memory down 0: follow rtc_lslp 420 1: power down*/ 421 #define EXTMEM_ICACHE_TAG_MEM_FORCE_PD (BIT(1)) 422 #define EXTMEM_ICACHE_TAG_MEM_FORCE_PD_M (BIT(1)) 423 #define EXTMEM_ICACHE_TAG_MEM_FORCE_PD_V 0x1 424 #define EXTMEM_ICACHE_TAG_MEM_FORCE_PD_S 1 425 /* EXTMEM_ICACHE_TAG_MEM_FORCE_ON : R/W ;bitpos:[0] ;default: 1'b1 ; */ 426 /*description: The bit is used to close clock gating of icache tag memory. 427 1: close gating 0: open clock gating.*/ 428 #define EXTMEM_ICACHE_TAG_MEM_FORCE_ON (BIT(0)) 429 #define EXTMEM_ICACHE_TAG_MEM_FORCE_ON_M (BIT(0)) 430 #define EXTMEM_ICACHE_TAG_MEM_FORCE_ON_V 0x1 431 #define EXTMEM_ICACHE_TAG_MEM_FORCE_ON_S 0 432 433 #define EXTMEM_ICACHE_PRELOCK_CTRL_REG (DR_REG_EXTMEM_BASE + 0x06C) 434 /* EXTMEM_ICACHE_PRELOCK_SCT1_EN : R/W ;bitpos:[1] ;default: 1'h0 ; */ 435 /*description: The bit is used to enable the second section of prelock function.*/ 436 #define EXTMEM_ICACHE_PRELOCK_SCT1_EN (BIT(1)) 437 #define EXTMEM_ICACHE_PRELOCK_SCT1_EN_M (BIT(1)) 438 #define EXTMEM_ICACHE_PRELOCK_SCT1_EN_V 0x1 439 #define EXTMEM_ICACHE_PRELOCK_SCT1_EN_S 1 440 /* EXTMEM_ICACHE_PRELOCK_SCT0_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */ 441 /*description: The bit is used to enable the first section of prelock function.*/ 442 #define EXTMEM_ICACHE_PRELOCK_SCT0_EN (BIT(0)) 443 #define EXTMEM_ICACHE_PRELOCK_SCT0_EN_M (BIT(0)) 444 #define EXTMEM_ICACHE_PRELOCK_SCT0_EN_V 0x1 445 #define EXTMEM_ICACHE_PRELOCK_SCT0_EN_S 0 446 447 #define EXTMEM_ICACHE_PRELOCK_SCT0_ADDR_REG (DR_REG_EXTMEM_BASE + 0x070) 448 /* EXTMEM_ICACHE_PRELOCK_SCT0_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 449 /*description: The bits are used to configure the first start virtual address 450 of data prelock which is combined with ICACHE_PRELOCK_SCT0_SIZE_REG*/ 451 #define EXTMEM_ICACHE_PRELOCK_SCT0_ADDR 0xFFFFFFFF 452 #define EXTMEM_ICACHE_PRELOCK_SCT0_ADDR_M ((EXTMEM_ICACHE_PRELOCK_SCT0_ADDR_V)<<(EXTMEM_ICACHE_PRELOCK_SCT0_ADDR_S)) 453 #define EXTMEM_ICACHE_PRELOCK_SCT0_ADDR_V 0xFFFFFFFF 454 #define EXTMEM_ICACHE_PRELOCK_SCT0_ADDR_S 0 455 456 #define EXTMEM_ICACHE_PRELOCK_SCT1_ADDR_REG (DR_REG_EXTMEM_BASE + 0x074) 457 /* EXTMEM_ICACHE_PRELOCK_SCT1_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 458 /*description: The bits are used to configure the second start virtual address 459 of data prelock which is combined with ICACHE_PRELOCK_SCT1_SIZE_REG*/ 460 #define EXTMEM_ICACHE_PRELOCK_SCT1_ADDR 0xFFFFFFFF 461 #define EXTMEM_ICACHE_PRELOCK_SCT1_ADDR_M ((EXTMEM_ICACHE_PRELOCK_SCT1_ADDR_V)<<(EXTMEM_ICACHE_PRELOCK_SCT1_ADDR_S)) 462 #define EXTMEM_ICACHE_PRELOCK_SCT1_ADDR_V 0xFFFFFFFF 463 #define EXTMEM_ICACHE_PRELOCK_SCT1_ADDR_S 0 464 465 #define EXTMEM_ICACHE_PRELOCK_SCT_SIZE_REG (DR_REG_EXTMEM_BASE + 0x078) 466 /* EXTMEM_ICACHE_PRELOCK_SCT0_SIZE : R/W ;bitpos:[31:16] ;default: 16'h0 ; */ 467 /*description: The bits are used to configure the first length of data locking 468 which is combined with ICACHE_PRELOCK_SCT0_ADDR_REG*/ 469 #define EXTMEM_ICACHE_PRELOCK_SCT0_SIZE 0x0000FFFF 470 #define EXTMEM_ICACHE_PRELOCK_SCT0_SIZE_M ((EXTMEM_ICACHE_PRELOCK_SCT0_SIZE_V)<<(EXTMEM_ICACHE_PRELOCK_SCT0_SIZE_S)) 471 #define EXTMEM_ICACHE_PRELOCK_SCT0_SIZE_V 0xFFFF 472 #define EXTMEM_ICACHE_PRELOCK_SCT0_SIZE_S 16 473 /* EXTMEM_ICACHE_PRELOCK_SCT1_SIZE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ 474 /*description: The bits are used to configure the second length of data locking 475 which is combined with ICACHE_PRELOCK_SCT1_ADDR_REG*/ 476 #define EXTMEM_ICACHE_PRELOCK_SCT1_SIZE 0x0000FFFF 477 #define EXTMEM_ICACHE_PRELOCK_SCT1_SIZE_M ((EXTMEM_ICACHE_PRELOCK_SCT1_SIZE_V)<<(EXTMEM_ICACHE_PRELOCK_SCT1_SIZE_S)) 478 #define EXTMEM_ICACHE_PRELOCK_SCT1_SIZE_V 0xFFFF 479 #define EXTMEM_ICACHE_PRELOCK_SCT1_SIZE_S 0 480 481 #define EXTMEM_ICACHE_LOCK_CTRL_REG (DR_REG_EXTMEM_BASE + 0x07C) 482 /* EXTMEM_ICACHE_LOCK_DONE : RO ;bitpos:[2] ;default: 1'b0 ; */ 483 /*description: The bit is used to indicate unlock/lock operation is finished.*/ 484 #define EXTMEM_ICACHE_LOCK_DONE (BIT(2)) 485 #define EXTMEM_ICACHE_LOCK_DONE_M (BIT(2)) 486 #define EXTMEM_ICACHE_LOCK_DONE_V 0x1 487 #define EXTMEM_ICACHE_LOCK_DONE_S 2 488 /* EXTMEM_ICACHE_UNLOCK_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ 489 /*description: The bit is used to enable unlock operation. It will be cleared 490 by hardware after unlock operation done.*/ 491 #define EXTMEM_ICACHE_UNLOCK_ENA (BIT(1)) 492 #define EXTMEM_ICACHE_UNLOCK_ENA_M (BIT(1)) 493 #define EXTMEM_ICACHE_UNLOCK_ENA_V 0x1 494 #define EXTMEM_ICACHE_UNLOCK_ENA_S 1 495 /* EXTMEM_ICACHE_LOCK_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ 496 /*description: The bit is used to enable lock operation. It will be cleared 497 by hardware after lock operation done.*/ 498 #define EXTMEM_ICACHE_LOCK_ENA (BIT(0)) 499 #define EXTMEM_ICACHE_LOCK_ENA_M (BIT(0)) 500 #define EXTMEM_ICACHE_LOCK_ENA_V 0x1 501 #define EXTMEM_ICACHE_LOCK_ENA_S 0 502 503 #define EXTMEM_ICACHE_LOCK_ADDR_REG (DR_REG_EXTMEM_BASE + 0x080) 504 /* EXTMEM_ICACHE_LOCK_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ 505 /*description: The bits are used to configure the start virtual address for 506 lock operations. It should be combined with ICACHE_LOCK_SIZE_REG.*/ 507 #define EXTMEM_ICACHE_LOCK_ADDR 0xFFFFFFFF 508 #define EXTMEM_ICACHE_LOCK_ADDR_M ((EXTMEM_ICACHE_LOCK_ADDR_V)<<(EXTMEM_ICACHE_LOCK_ADDR_S)) 509 #define EXTMEM_ICACHE_LOCK_ADDR_V 0xFFFFFFFF 510 #define EXTMEM_ICACHE_LOCK_ADDR_S 0 511 512 #define EXTMEM_ICACHE_LOCK_SIZE_REG (DR_REG_EXTMEM_BASE + 0x084) 513 /* EXTMEM_ICACHE_LOCK_SIZE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ 514 /*description: The bits are used to configure the length for lock operations. 515 The bits are the counts of cache block. It should be combined with ICACHE_LOCK_ADDR_REG.*/ 516 #define EXTMEM_ICACHE_LOCK_SIZE 0x0000FFFF 517 #define EXTMEM_ICACHE_LOCK_SIZE_M ((EXTMEM_ICACHE_LOCK_SIZE_V)<<(EXTMEM_ICACHE_LOCK_SIZE_S)) 518 #define EXTMEM_ICACHE_LOCK_SIZE_V 0xFFFF 519 #define EXTMEM_ICACHE_LOCK_SIZE_S 0 520 521 #define EXTMEM_ICACHE_SYNC_CTRL_REG (DR_REG_EXTMEM_BASE + 0x088) 522 /* EXTMEM_ICACHE_SYNC_DONE : RO ;bitpos:[1] ;default: 1'b0 ; */ 523 /*description: The bit is used to indicate invalidate operation is finished.*/ 524 #define EXTMEM_ICACHE_SYNC_DONE (BIT(1)) 525 #define EXTMEM_ICACHE_SYNC_DONE_M (BIT(1)) 526 #define EXTMEM_ICACHE_SYNC_DONE_V 0x1 527 #define EXTMEM_ICACHE_SYNC_DONE_S 1 528 /* EXTMEM_ICACHE_INVALIDATE_ENA : R/W ;bitpos:[0] ;default: 1'b1 ; */ 529 /*description: The bit is used to enable invalidate operation. It will be cleared 530 by hardware after invalidate operation done.*/ 531 #define EXTMEM_ICACHE_INVALIDATE_ENA (BIT(0)) 532 #define EXTMEM_ICACHE_INVALIDATE_ENA_M (BIT(0)) 533 #define EXTMEM_ICACHE_INVALIDATE_ENA_V 0x1 534 #define EXTMEM_ICACHE_INVALIDATE_ENA_S 0 535 536 #define EXTMEM_ICACHE_SYNC_ADDR_REG (DR_REG_EXTMEM_BASE + 0x08C) 537 /* EXTMEM_ICACHE_SYNC_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ 538 /*description: The bits are used to configure the start virtual address for 539 clean operations. It should be combined with ICACHE_SYNC_SIZE_REG.*/ 540 #define EXTMEM_ICACHE_SYNC_ADDR 0xFFFFFFFF 541 #define EXTMEM_ICACHE_SYNC_ADDR_M ((EXTMEM_ICACHE_SYNC_ADDR_V)<<(EXTMEM_ICACHE_SYNC_ADDR_S)) 542 #define EXTMEM_ICACHE_SYNC_ADDR_V 0xFFFFFFFF 543 #define EXTMEM_ICACHE_SYNC_ADDR_S 0 544 545 #define EXTMEM_ICACHE_SYNC_SIZE_REG (DR_REG_EXTMEM_BASE + 0x090) 546 /* EXTMEM_ICACHE_SYNC_SIZE : R/W ;bitpos:[22:0] ;default: 23'h0 ; */ 547 /*description: The bits are used to configure the length for sync operations. 548 The bits are the counts of cache block. It should be combined with ICACHE_SYNC_ADDR_REG.*/ 549 #define EXTMEM_ICACHE_SYNC_SIZE 0x007FFFFF 550 #define EXTMEM_ICACHE_SYNC_SIZE_M ((EXTMEM_ICACHE_SYNC_SIZE_V)<<(EXTMEM_ICACHE_SYNC_SIZE_S)) 551 #define EXTMEM_ICACHE_SYNC_SIZE_V 0x7FFFFF 552 #define EXTMEM_ICACHE_SYNC_SIZE_S 0 553 554 #define EXTMEM_ICACHE_PRELOAD_CTRL_REG (DR_REG_EXTMEM_BASE + 0x094) 555 /* EXTMEM_ICACHE_PRELOAD_ORDER : R/W ;bitpos:[2] ;default: 1'b0 ; */ 556 /*description: The bit is used to configure the direction of preload operation. 557 1: descending 0: ascending.*/ 558 #define EXTMEM_ICACHE_PRELOAD_ORDER (BIT(2)) 559 #define EXTMEM_ICACHE_PRELOAD_ORDER_M (BIT(2)) 560 #define EXTMEM_ICACHE_PRELOAD_ORDER_V 0x1 561 #define EXTMEM_ICACHE_PRELOAD_ORDER_S 2 562 /* EXTMEM_ICACHE_PRELOAD_DONE : RO ;bitpos:[1] ;default: 1'b0 ; */ 563 /*description: The bit is used to indicate preload operation is finished.*/ 564 #define EXTMEM_ICACHE_PRELOAD_DONE (BIT(1)) 565 #define EXTMEM_ICACHE_PRELOAD_DONE_M (BIT(1)) 566 #define EXTMEM_ICACHE_PRELOAD_DONE_V 0x1 567 #define EXTMEM_ICACHE_PRELOAD_DONE_S 1 568 /* EXTMEM_ICACHE_PRELOAD_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ 569 /*description: The bit is used to enable preload operation. It will be cleared 570 by hardware after preload operation done.*/ 571 #define EXTMEM_ICACHE_PRELOAD_ENA (BIT(0)) 572 #define EXTMEM_ICACHE_PRELOAD_ENA_M (BIT(0)) 573 #define EXTMEM_ICACHE_PRELOAD_ENA_V 0x1 574 #define EXTMEM_ICACHE_PRELOAD_ENA_S 0 575 576 #define EXTMEM_ICACHE_PRELOAD_ADDR_REG (DR_REG_EXTMEM_BASE + 0x098) 577 /* EXTMEM_ICACHE_PRELOAD_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ 578 /*description: The bits are used to configure the start virtual address for 579 preload operation. It should be combined with ICACHE_PRELOAD_SIZE_REG.*/ 580 #define EXTMEM_ICACHE_PRELOAD_ADDR 0xFFFFFFFF 581 #define EXTMEM_ICACHE_PRELOAD_ADDR_M ((EXTMEM_ICACHE_PRELOAD_ADDR_V)<<(EXTMEM_ICACHE_PRELOAD_ADDR_S)) 582 #define EXTMEM_ICACHE_PRELOAD_ADDR_V 0xFFFFFFFF 583 #define EXTMEM_ICACHE_PRELOAD_ADDR_S 0 584 585 #define EXTMEM_ICACHE_PRELOAD_SIZE_REG (DR_REG_EXTMEM_BASE + 0x09C) 586 /* EXTMEM_ICACHE_PRELOAD_SIZE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ 587 /*description: The bits are used to configure the length for preload operation. 588 The bits are the counts of cache block. It should be combined with ICACHE_PRELOAD_ADDR_REG..*/ 589 #define EXTMEM_ICACHE_PRELOAD_SIZE 0x0000FFFF 590 #define EXTMEM_ICACHE_PRELOAD_SIZE_M ((EXTMEM_ICACHE_PRELOAD_SIZE_V)<<(EXTMEM_ICACHE_PRELOAD_SIZE_S)) 591 #define EXTMEM_ICACHE_PRELOAD_SIZE_V 0xFFFF 592 #define EXTMEM_ICACHE_PRELOAD_SIZE_S 0 593 594 #define EXTMEM_ICACHE_AUTOLOAD_CTRL_REG (DR_REG_EXTMEM_BASE + 0x0A0) 595 /* EXTMEM_ICACHE_AUTOLOAD_SIZE : R/W ;bitpos:[8:7] ;default: 2'h0 ; */ 596 /*description: The bits are used to configure the numbers of the cache block 597 for the issuing autoload operation.*/ 598 #define EXTMEM_ICACHE_AUTOLOAD_SIZE 0x00000003 599 #define EXTMEM_ICACHE_AUTOLOAD_SIZE_M ((EXTMEM_ICACHE_AUTOLOAD_SIZE_V)<<(EXTMEM_ICACHE_AUTOLOAD_SIZE_S)) 600 #define EXTMEM_ICACHE_AUTOLOAD_SIZE_V 0x3 601 #define EXTMEM_ICACHE_AUTOLOAD_SIZE_S 7 602 /* EXTMEM_ICACHE_AUTOLOAD_RQST : R/W ;bitpos:[6:5] ;default: 2'b0 ; */ 603 /*description: The bits are used to configure trigger conditions for autoload. 604 0/3: cache miss 1: cache hit 2: both cache miss and hit.*/ 605 #define EXTMEM_ICACHE_AUTOLOAD_RQST 0x00000003 606 #define EXTMEM_ICACHE_AUTOLOAD_RQST_M ((EXTMEM_ICACHE_AUTOLOAD_RQST_V)<<(EXTMEM_ICACHE_AUTOLOAD_RQST_S)) 607 #define EXTMEM_ICACHE_AUTOLOAD_RQST_V 0x3 608 #define EXTMEM_ICACHE_AUTOLOAD_RQST_S 5 609 /* EXTMEM_ICACHE_AUTOLOAD_ORDER : R/W ;bitpos:[4] ;default: 1'b0 ; */ 610 /*description: The bits are used to configure the direction of autoload. 1: 611 descending 0: ascending.*/ 612 #define EXTMEM_ICACHE_AUTOLOAD_ORDER (BIT(4)) 613 #define EXTMEM_ICACHE_AUTOLOAD_ORDER_M (BIT(4)) 614 #define EXTMEM_ICACHE_AUTOLOAD_ORDER_V 0x1 615 #define EXTMEM_ICACHE_AUTOLOAD_ORDER_S 4 616 /* EXTMEM_ICACHE_AUTOLOAD_DONE : RO ;bitpos:[3] ;default: 1'b0 ; */ 617 /*description: The bit is used to indicate autoload operation is finished.*/ 618 #define EXTMEM_ICACHE_AUTOLOAD_DONE (BIT(3)) 619 #define EXTMEM_ICACHE_AUTOLOAD_DONE_M (BIT(3)) 620 #define EXTMEM_ICACHE_AUTOLOAD_DONE_V 0x1 621 #define EXTMEM_ICACHE_AUTOLOAD_DONE_S 3 622 /* EXTMEM_ICACHE_AUTOLOAD_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ 623 /*description: The bit is used to enable and disable autoload operation. It 624 is combined with dcache_autoload_done. 1: enable 0: disable.*/ 625 #define EXTMEM_ICACHE_AUTOLOAD_ENA (BIT(2)) 626 #define EXTMEM_ICACHE_AUTOLOAD_ENA_M (BIT(2)) 627 #define EXTMEM_ICACHE_AUTOLOAD_ENA_V 0x1 628 #define EXTMEM_ICACHE_AUTOLOAD_ENA_S 2 629 /* EXTMEM_ICACHE_AUTOLOAD_SCT1_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ 630 /*description: The bits are used to enable the second section for autoload operation.*/ 631 #define EXTMEM_ICACHE_AUTOLOAD_SCT1_ENA (BIT(1)) 632 #define EXTMEM_ICACHE_AUTOLOAD_SCT1_ENA_M (BIT(1)) 633 #define EXTMEM_ICACHE_AUTOLOAD_SCT1_ENA_V 0x1 634 #define EXTMEM_ICACHE_AUTOLOAD_SCT1_ENA_S 1 635 /* EXTMEM_ICACHE_AUTOLOAD_SCT0_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ 636 /*description: The bits are used to enable the first section for autoload operation.*/ 637 #define EXTMEM_ICACHE_AUTOLOAD_SCT0_ENA (BIT(0)) 638 #define EXTMEM_ICACHE_AUTOLOAD_SCT0_ENA_M (BIT(0)) 639 #define EXTMEM_ICACHE_AUTOLOAD_SCT0_ENA_V 0x1 640 #define EXTMEM_ICACHE_AUTOLOAD_SCT0_ENA_S 0 641 642 #define EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR_REG (DR_REG_EXTMEM_BASE + 0x0A4) 643 /* EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ 644 /*description: The bits are used to configure the start virtual address of the 645 first section for autoload operation. It should be combined with dcache_autoload_sct0_ena.*/ 646 #define EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR 0xFFFFFFFF 647 #define EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR_M ((EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR_V)<<(EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR_S)) 648 #define EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR_V 0xFFFFFFFF 649 #define EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR_S 0 650 651 #define EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE_REG (DR_REG_EXTMEM_BASE + 0x0A8) 652 /* EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE : R/W ;bitpos:[26:0] ;default: 27'h0 ; */ 653 /*description: The bits are used to configure the length of the first section 654 for autoload operation. It should be combined with dcache_autoload_sct0_ena.*/ 655 #define EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE 0x07FFFFFF 656 #define EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE_M ((EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE_V)<<(EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE_S)) 657 #define EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE_V 0x7FFFFFF 658 #define EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE_S 0 659 660 #define EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR_REG (DR_REG_EXTMEM_BASE + 0x0AC) 661 /* EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ 662 /*description: The bits are used to configure the start virtual address of the 663 second section for autoload operation. It should be combined with dcache_autoload_sct1_ena.*/ 664 #define EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR 0xFFFFFFFF 665 #define EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR_M ((EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR_V)<<(EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR_S)) 666 #define EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR_V 0xFFFFFFFF 667 #define EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR_S 0 668 669 #define EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE_REG (DR_REG_EXTMEM_BASE + 0x0B0) 670 /* EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE : R/W ;bitpos:[26:0] ;default: 27'h0 ; */ 671 /*description: The bits are used to configure the length of the second section 672 for autoload operation. It should be combined with dcache_autoload_sct1_ena.*/ 673 #define EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE 0x07FFFFFF 674 #define EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE_M ((EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE_V)<<(EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE_S)) 675 #define EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE_V 0x7FFFFFF 676 #define EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE_S 0 677 678 #define EXTMEM_IBUS_TO_FLASH_START_VADDR_REG (DR_REG_EXTMEM_BASE + 0x0B4) 679 /* EXTMEM_IBUS_TO_FLASH_START_VADDR : R/W ;bitpos:[31:0] ;default: 32'h44000000 ; */ 680 /*description: The bits are used to configure the start virtual address of ibus 681 to access flash. The register is used to give constraints to ibus access counter.*/ 682 #define EXTMEM_IBUS_TO_FLASH_START_VADDR 0xFFFFFFFF 683 #define EXTMEM_IBUS_TO_FLASH_START_VADDR_M ((EXTMEM_IBUS_TO_FLASH_START_VADDR_V)<<(EXTMEM_IBUS_TO_FLASH_START_VADDR_S)) 684 #define EXTMEM_IBUS_TO_FLASH_START_VADDR_V 0xFFFFFFFF 685 #define EXTMEM_IBUS_TO_FLASH_START_VADDR_S 0 686 687 #define EXTMEM_IBUS_TO_FLASH_END_VADDR_REG (DR_REG_EXTMEM_BASE + 0x0B8) 688 /* EXTMEM_IBUS_TO_FLASH_END_VADDR : R/W ;bitpos:[31:0] ;default: 32'h47ffffff ; */ 689 /*description: The bits are used to configure the end virtual address of ibus 690 to access flash. The register is used to give constraints to ibus access counter.*/ 691 #define EXTMEM_IBUS_TO_FLASH_END_VADDR 0xFFFFFFFF 692 #define EXTMEM_IBUS_TO_FLASH_END_VADDR_M ((EXTMEM_IBUS_TO_FLASH_END_VADDR_V)<<(EXTMEM_IBUS_TO_FLASH_END_VADDR_S)) 693 #define EXTMEM_IBUS_TO_FLASH_END_VADDR_V 0xFFFFFFFF 694 #define EXTMEM_IBUS_TO_FLASH_END_VADDR_S 0 695 696 #define EXTMEM_DBUS_TO_FLASH_START_VADDR_REG (DR_REG_EXTMEM_BASE + 0x0BC) 697 /* EXTMEM_DBUS_TO_FLASH_START_VADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ 698 /*description: The bits are used to configure the start virtual address of dbus 699 to access flash. The register is used to give constraints to dbus access counter.*/ 700 #define EXTMEM_DBUS_TO_FLASH_START_VADDR 0xFFFFFFFF 701 #define EXTMEM_DBUS_TO_FLASH_START_VADDR_M ((EXTMEM_DBUS_TO_FLASH_START_VADDR_V)<<(EXTMEM_DBUS_TO_FLASH_START_VADDR_S)) 702 #define EXTMEM_DBUS_TO_FLASH_START_VADDR_V 0xFFFFFFFF 703 #define EXTMEM_DBUS_TO_FLASH_START_VADDR_S 0 704 705 #define EXTMEM_DBUS_TO_FLASH_END_VADDR_REG (DR_REG_EXTMEM_BASE + 0x0C0) 706 /* EXTMEM_DBUS_TO_FLASH_END_VADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ 707 /*description: The bits are used to configure the end virtual address of dbus 708 to access flash. The register is used to give constraints to dbus access counter.*/ 709 #define EXTMEM_DBUS_TO_FLASH_END_VADDR 0xFFFFFFFF 710 #define EXTMEM_DBUS_TO_FLASH_END_VADDR_M ((EXTMEM_DBUS_TO_FLASH_END_VADDR_V)<<(EXTMEM_DBUS_TO_FLASH_END_VADDR_S)) 711 #define EXTMEM_DBUS_TO_FLASH_END_VADDR_V 0xFFFFFFFF 712 #define EXTMEM_DBUS_TO_FLASH_END_VADDR_S 0 713 714 #define EXTMEM_CACHE_ACS_CNT_CLR_REG (DR_REG_EXTMEM_BASE + 0x0C4) 715 /* EXTMEM_ICACHE_ACS_CNT_CLR : WOD ;bitpos:[1] ;default: 1'b0 ; */ 716 /*description: The bit is used to clear icache counter.*/ 717 #define EXTMEM_ICACHE_ACS_CNT_CLR (BIT(1)) 718 #define EXTMEM_ICACHE_ACS_CNT_CLR_M (BIT(1)) 719 #define EXTMEM_ICACHE_ACS_CNT_CLR_V 0x1 720 #define EXTMEM_ICACHE_ACS_CNT_CLR_S 1 721 /* EXTMEM_DCACHE_ACS_CNT_CLR : WOD ;bitpos:[0] ;default: 1'b0 ; */ 722 /*description: The bit is used to clear dcache counter.*/ 723 #define EXTMEM_DCACHE_ACS_CNT_CLR (BIT(0)) 724 #define EXTMEM_DCACHE_ACS_CNT_CLR_M (BIT(0)) 725 #define EXTMEM_DCACHE_ACS_CNT_CLR_V 0x1 726 #define EXTMEM_DCACHE_ACS_CNT_CLR_S 0 727 728 #define EXTMEM_IBUS_ACS_MISS_CNT_REG (DR_REG_EXTMEM_BASE + 0x0C8) 729 /* EXTMEM_IBUS_ACS_MISS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 730 /*description: The bits are used to count the number of the cache miss caused 731 by ibus access flash/spiram.*/ 732 #define EXTMEM_IBUS_ACS_MISS_CNT 0xFFFFFFFF 733 #define EXTMEM_IBUS_ACS_MISS_CNT_M ((EXTMEM_IBUS_ACS_MISS_CNT_V)<<(EXTMEM_IBUS_ACS_MISS_CNT_S)) 734 #define EXTMEM_IBUS_ACS_MISS_CNT_V 0xFFFFFFFF 735 #define EXTMEM_IBUS_ACS_MISS_CNT_S 0 736 737 #define EXTMEM_IBUS_ACS_CNT_REG (DR_REG_EXTMEM_BASE + 0x0CC) 738 /* EXTMEM_IBUS_ACS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 739 /*description: The bits are used to count the number of ibus access flash/spiram 740 through icache.*/ 741 #define EXTMEM_IBUS_ACS_CNT 0xFFFFFFFF 742 #define EXTMEM_IBUS_ACS_CNT_M ((EXTMEM_IBUS_ACS_CNT_V)<<(EXTMEM_IBUS_ACS_CNT_S)) 743 #define EXTMEM_IBUS_ACS_CNT_V 0xFFFFFFFF 744 #define EXTMEM_IBUS_ACS_CNT_S 0 745 746 #define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_REG (DR_REG_EXTMEM_BASE + 0x0D0) 747 /* EXTMEM_DBUS_ACS_FLASH_MISS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 748 /*description: The bits are used to count the number of the cache miss caused 749 by dbus access flash.*/ 750 #define EXTMEM_DBUS_ACS_FLASH_MISS_CNT 0xFFFFFFFF 751 #define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_M ((EXTMEM_DBUS_ACS_FLASH_MISS_CNT_V)<<(EXTMEM_DBUS_ACS_FLASH_MISS_CNT_S)) 752 #define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_V 0xFFFFFFFF 753 #define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_S 0 754 755 #define EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT_REG (DR_REG_EXTMEM_BASE + 0x0D4) 756 /* EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 757 /*description: The bits are used to count the number of the cache miss caused 758 by dbus access spiram.*/ 759 #define EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT 0xFFFFFFFF 760 #define EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT_M ((EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT_V)<<(EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT_S)) 761 #define EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT_V 0xFFFFFFFF 762 #define EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT_S 0 763 764 #define EXTMEM_DBUS_ACS_CNT_REG (DR_REG_EXTMEM_BASE + 0x0D8) 765 /* EXTMEM_DBUS_ACS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 766 /*description: The bits are used to count the number of dbus access flash/spiram 767 through dcache.*/ 768 #define EXTMEM_DBUS_ACS_CNT 0xFFFFFFFF 769 #define EXTMEM_DBUS_ACS_CNT_M ((EXTMEM_DBUS_ACS_CNT_V)<<(EXTMEM_DBUS_ACS_CNT_S)) 770 #define EXTMEM_DBUS_ACS_CNT_V 0xFFFFFFFF 771 #define EXTMEM_DBUS_ACS_CNT_S 0 772 773 #define EXTMEM_CACHE_ILG_INT_ENA_REG (DR_REG_EXTMEM_BASE + 0x0DC) 774 /* EXTMEM_DBUS_CNT_OVF_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ 775 /*description: The bit is used to enable interrupt by dbus counter overflow.*/ 776 #define EXTMEM_DBUS_CNT_OVF_INT_ENA (BIT(8)) 777 #define EXTMEM_DBUS_CNT_OVF_INT_ENA_M (BIT(8)) 778 #define EXTMEM_DBUS_CNT_OVF_INT_ENA_V 0x1 779 #define EXTMEM_DBUS_CNT_OVF_INT_ENA_S 8 780 /* EXTMEM_IBUS_CNT_OVF_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ 781 /*description: The bit is used to enable interrupt by ibus counter overflow.*/ 782 #define EXTMEM_IBUS_CNT_OVF_INT_ENA (BIT(7)) 783 #define EXTMEM_IBUS_CNT_OVF_INT_ENA_M (BIT(7)) 784 #define EXTMEM_IBUS_CNT_OVF_INT_ENA_V 0x1 785 #define EXTMEM_IBUS_CNT_OVF_INT_ENA_S 7 786 /* EXTMEM_DCACHE_OCCUPY_EXC_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ 787 /*description: The bit is used to enable interrupt by dcache trying to replace 788 a line whose blocks all have been occupied by occupy-mode.*/ 789 #define EXTMEM_DCACHE_OCCUPY_EXC_INT_ENA (BIT(6)) 790 #define EXTMEM_DCACHE_OCCUPY_EXC_INT_ENA_M (BIT(6)) 791 #define EXTMEM_DCACHE_OCCUPY_EXC_INT_ENA_V 0x1 792 #define EXTMEM_DCACHE_OCCUPY_EXC_INT_ENA_S 6 793 /* EXTMEM_MMU_ENTRY_FAULT_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ 794 /*description: The bit is used to enable interrupt by mmu entry fault.*/ 795 #define EXTMEM_MMU_ENTRY_FAULT_INT_ENA (BIT(5)) 796 #define EXTMEM_MMU_ENTRY_FAULT_INT_ENA_M (BIT(5)) 797 #define EXTMEM_MMU_ENTRY_FAULT_INT_ENA_V 0x1 798 #define EXTMEM_MMU_ENTRY_FAULT_INT_ENA_S 5 799 /* EXTMEM_DCACHE_WRITE_FLASH_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ 800 /*description: The bit is used to enable interrupt by dcache trying to write flash.*/ 801 #define EXTMEM_DCACHE_WRITE_FLASH_INT_ENA (BIT(4)) 802 #define EXTMEM_DCACHE_WRITE_FLASH_INT_ENA_M (BIT(4)) 803 #define EXTMEM_DCACHE_WRITE_FLASH_INT_ENA_V 0x1 804 #define EXTMEM_DCACHE_WRITE_FLASH_INT_ENA_S 4 805 /* EXTMEM_DCACHE_PRELOAD_OP_FAULT_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ 806 /*description: The bit is used to enable interrupt by preload configurations fault.*/ 807 #define EXTMEM_DCACHE_PRELOAD_OP_FAULT_INT_ENA (BIT(3)) 808 #define EXTMEM_DCACHE_PRELOAD_OP_FAULT_INT_ENA_M (BIT(3)) 809 #define EXTMEM_DCACHE_PRELOAD_OP_FAULT_INT_ENA_V 0x1 810 #define EXTMEM_DCACHE_PRELOAD_OP_FAULT_INT_ENA_S 3 811 /* EXTMEM_DCACHE_SYNC_OP_FAULT_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ 812 /*description: The bit is used to enable interrupt by sync configurations fault.*/ 813 #define EXTMEM_DCACHE_SYNC_OP_FAULT_INT_ENA (BIT(2)) 814 #define EXTMEM_DCACHE_SYNC_OP_FAULT_INT_ENA_M (BIT(2)) 815 #define EXTMEM_DCACHE_SYNC_OP_FAULT_INT_ENA_V 0x1 816 #define EXTMEM_DCACHE_SYNC_OP_FAULT_INT_ENA_S 2 817 /* EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ 818 /*description: The bit is used to enable interrupt by preload configurations fault.*/ 819 #define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA (BIT(1)) 820 #define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA_M (BIT(1)) 821 #define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA_V 0x1 822 #define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA_S 1 823 /* EXTMEM_ICACHE_SYNC_OP_FAULT_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ 824 /*description: The bit is used to enable interrupt by sync configurations fault.*/ 825 #define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_ENA (BIT(0)) 826 #define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_ENA_M (BIT(0)) 827 #define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_ENA_V 0x1 828 #define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_ENA_S 0 829 830 #define EXTMEM_CACHE_ILG_INT_CLR_REG (DR_REG_EXTMEM_BASE + 0x0E0) 831 /* EXTMEM_DBUS_CNT_OVF_INT_CLR : WOD ;bitpos:[8] ;default: 1'b0 ; */ 832 /*description: The bit is used to clear interrupt by dbus counter overflow.*/ 833 #define EXTMEM_DBUS_CNT_OVF_INT_CLR (BIT(8)) 834 #define EXTMEM_DBUS_CNT_OVF_INT_CLR_M (BIT(8)) 835 #define EXTMEM_DBUS_CNT_OVF_INT_CLR_V 0x1 836 #define EXTMEM_DBUS_CNT_OVF_INT_CLR_S 8 837 /* EXTMEM_IBUS_CNT_OVF_INT_CLR : WOD ;bitpos:[7] ;default: 1'b0 ; */ 838 /*description: The bit is used to clear interrupt by ibus counter overflow.*/ 839 #define EXTMEM_IBUS_CNT_OVF_INT_CLR (BIT(7)) 840 #define EXTMEM_IBUS_CNT_OVF_INT_CLR_M (BIT(7)) 841 #define EXTMEM_IBUS_CNT_OVF_INT_CLR_V 0x1 842 #define EXTMEM_IBUS_CNT_OVF_INT_CLR_S 7 843 /* EXTMEM_DCACHE_OCCUPY_EXC_INT_CLR : WOD ;bitpos:[6] ;default: 1'b0 ; */ 844 /*description: The bit is used to clear interrupt by dcache trying to replace 845 a line whose blocks all have been occupied by occupy-mode.*/ 846 #define EXTMEM_DCACHE_OCCUPY_EXC_INT_CLR (BIT(6)) 847 #define EXTMEM_DCACHE_OCCUPY_EXC_INT_CLR_M (BIT(6)) 848 #define EXTMEM_DCACHE_OCCUPY_EXC_INT_CLR_V 0x1 849 #define EXTMEM_DCACHE_OCCUPY_EXC_INT_CLR_S 6 850 /* EXTMEM_MMU_ENTRY_FAULT_INT_CLR : WOD ;bitpos:[5] ;default: 1'b0 ; */ 851 /*description: The bit is used to clear interrupt by mmu entry fault.*/ 852 #define EXTMEM_MMU_ENTRY_FAULT_INT_CLR (BIT(5)) 853 #define EXTMEM_MMU_ENTRY_FAULT_INT_CLR_M (BIT(5)) 854 #define EXTMEM_MMU_ENTRY_FAULT_INT_CLR_V 0x1 855 #define EXTMEM_MMU_ENTRY_FAULT_INT_CLR_S 5 856 /* EXTMEM_DCACHE_WRITE_FLASH_INT_CLR : WOD ;bitpos:[4] ;default: 1'b0 ; */ 857 /*description: The bit is used to clear interrupt by dcache trying to write flash.*/ 858 #define EXTMEM_DCACHE_WRITE_FLASH_INT_CLR (BIT(4)) 859 #define EXTMEM_DCACHE_WRITE_FLASH_INT_CLR_M (BIT(4)) 860 #define EXTMEM_DCACHE_WRITE_FLASH_INT_CLR_V 0x1 861 #define EXTMEM_DCACHE_WRITE_FLASH_INT_CLR_S 4 862 /* EXTMEM_DCACHE_PRELOAD_OP_FAULT_INT_CLR : WOD ;bitpos:[3] ;default: 1'b0 ; */ 863 /*description: The bit is used to clear interrupt by preload configurations fault.*/ 864 #define EXTMEM_DCACHE_PRELOAD_OP_FAULT_INT_CLR (BIT(3)) 865 #define EXTMEM_DCACHE_PRELOAD_OP_FAULT_INT_CLR_M (BIT(3)) 866 #define EXTMEM_DCACHE_PRELOAD_OP_FAULT_INT_CLR_V 0x1 867 #define EXTMEM_DCACHE_PRELOAD_OP_FAULT_INT_CLR_S 3 868 /* EXTMEM_DCACHE_SYNC_OP_FAULT_INT_CLR : WOD ;bitpos:[2] ;default: 1'b0 ; */ 869 /*description: The bit is used to clear interrupt by sync configurations fault.*/ 870 #define EXTMEM_DCACHE_SYNC_OP_FAULT_INT_CLR (BIT(2)) 871 #define EXTMEM_DCACHE_SYNC_OP_FAULT_INT_CLR_M (BIT(2)) 872 #define EXTMEM_DCACHE_SYNC_OP_FAULT_INT_CLR_V 0x1 873 #define EXTMEM_DCACHE_SYNC_OP_FAULT_INT_CLR_S 2 874 /* EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR : WOD ;bitpos:[1] ;default: 1'b0 ; */ 875 /*description: The bit is used to clear interrupt by preload configurations fault.*/ 876 #define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR (BIT(1)) 877 #define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR_M (BIT(1)) 878 #define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR_V 0x1 879 #define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR_S 1 880 /* EXTMEM_ICACHE_SYNC_OP_FAULT_INT_CLR : WOD ;bitpos:[0] ;default: 1'b0 ; */ 881 /*description: The bit is used to clear interrupt by sync configurations fault.*/ 882 #define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_CLR (BIT(0)) 883 #define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_CLR_M (BIT(0)) 884 #define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_CLR_V 0x1 885 #define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_CLR_S 0 886 887 #define EXTMEM_CACHE_ILG_INT_ST_REG (DR_REG_EXTMEM_BASE + 0x0E4) 888 /* EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT_OVF_ST : RO ;bitpos:[11] ;default: 1'b0 ; */ 889 /*description: The bit is used to indicate interrupt by dbus access spiram miss 890 counter overflow.*/ 891 #define EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT_OVF_ST (BIT(11)) 892 #define EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT_OVF_ST_M (BIT(11)) 893 #define EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT_OVF_ST_V 0x1 894 #define EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT_OVF_ST_S 11 895 /* EXTMEM_DBUS_ACS_FLASH_MISS_CNT_OVF_ST : RO ;bitpos:[10] ;default: 1'b0 ; */ 896 /*description: The bit is used to indicate interrupt by dbus access flash miss 897 counter overflow.*/ 898 #define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_OVF_ST (BIT(10)) 899 #define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_OVF_ST_M (BIT(10)) 900 #define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_OVF_ST_V 0x1 901 #define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_OVF_ST_S 10 902 /* EXTMEM_DBUS_ACS_CNT_OVF_ST : RO ;bitpos:[9] ;default: 1'b0 ; */ 903 /*description: The bit is used to indicate interrupt by dbus access flash/spiram 904 counter overflow.*/ 905 #define EXTMEM_DBUS_ACS_CNT_OVF_ST (BIT(9)) 906 #define EXTMEM_DBUS_ACS_CNT_OVF_ST_M (BIT(9)) 907 #define EXTMEM_DBUS_ACS_CNT_OVF_ST_V 0x1 908 #define EXTMEM_DBUS_ACS_CNT_OVF_ST_S 9 909 /* EXTMEM_IBUS_ACS_MISS_CNT_OVF_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ 910 /*description: The bit is used to indicate interrupt by ibus access flash/spiram 911 miss counter overflow.*/ 912 #define EXTMEM_IBUS_ACS_MISS_CNT_OVF_ST (BIT(8)) 913 #define EXTMEM_IBUS_ACS_MISS_CNT_OVF_ST_M (BIT(8)) 914 #define EXTMEM_IBUS_ACS_MISS_CNT_OVF_ST_V 0x1 915 #define EXTMEM_IBUS_ACS_MISS_CNT_OVF_ST_S 8 916 /* EXTMEM_IBUS_ACS_CNT_OVF_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ 917 /*description: The bit is used to indicate interrupt by ibus access flash/spiram 918 counter overflow.*/ 919 #define EXTMEM_IBUS_ACS_CNT_OVF_ST (BIT(7)) 920 #define EXTMEM_IBUS_ACS_CNT_OVF_ST_M (BIT(7)) 921 #define EXTMEM_IBUS_ACS_CNT_OVF_ST_V 0x1 922 #define EXTMEM_IBUS_ACS_CNT_OVF_ST_S 7 923 /* EXTMEM_DCACHE_OCCUPY_EXC_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ 924 /*description: The bit is used to indicate interrupt by dcache trying to replace 925 a line whose blocks all have been occupied by occupy-mode.*/ 926 #define EXTMEM_DCACHE_OCCUPY_EXC_ST (BIT(6)) 927 #define EXTMEM_DCACHE_OCCUPY_EXC_ST_M (BIT(6)) 928 #define EXTMEM_DCACHE_OCCUPY_EXC_ST_V 0x1 929 #define EXTMEM_DCACHE_OCCUPY_EXC_ST_S 6 930 /* EXTMEM_MMU_ENTRY_FAULT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ 931 /*description: The bit is used to indicate interrupt by mmu entry fault.*/ 932 #define EXTMEM_MMU_ENTRY_FAULT_ST (BIT(5)) 933 #define EXTMEM_MMU_ENTRY_FAULT_ST_M (BIT(5)) 934 #define EXTMEM_MMU_ENTRY_FAULT_ST_V 0x1 935 #define EXTMEM_MMU_ENTRY_FAULT_ST_S 5 936 /* EXTMEM_DCACHE_WRITE_FLASH_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ 937 /*description: The bit is used to indicate interrupt by dcache trying to write flash.*/ 938 #define EXTMEM_DCACHE_WRITE_FLASH_ST (BIT(4)) 939 #define EXTMEM_DCACHE_WRITE_FLASH_ST_M (BIT(4)) 940 #define EXTMEM_DCACHE_WRITE_FLASH_ST_V 0x1 941 #define EXTMEM_DCACHE_WRITE_FLASH_ST_S 4 942 /* EXTMEM_DCACHE_PRELOAD_OP_FAULT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ 943 /*description: The bit is used to indicate interrupt by preload configurations fault.*/ 944 #define EXTMEM_DCACHE_PRELOAD_OP_FAULT_ST (BIT(3)) 945 #define EXTMEM_DCACHE_PRELOAD_OP_FAULT_ST_M (BIT(3)) 946 #define EXTMEM_DCACHE_PRELOAD_OP_FAULT_ST_V 0x1 947 #define EXTMEM_DCACHE_PRELOAD_OP_FAULT_ST_S 3 948 /* EXTMEM_DCACHE_SYNC_OP_FAULT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ 949 /*description: The bit is used to indicate interrupt by sync configurations fault.*/ 950 #define EXTMEM_DCACHE_SYNC_OP_FAULT_ST (BIT(2)) 951 #define EXTMEM_DCACHE_SYNC_OP_FAULT_ST_M (BIT(2)) 952 #define EXTMEM_DCACHE_SYNC_OP_FAULT_ST_V 0x1 953 #define EXTMEM_DCACHE_SYNC_OP_FAULT_ST_S 2 954 /* EXTMEM_ICACHE_PRELOAD_OP_FAULT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ 955 /*description: The bit is used to indicate interrupt by preload configurations fault.*/ 956 #define EXTMEM_ICACHE_PRELOAD_OP_FAULT_ST (BIT(1)) 957 #define EXTMEM_ICACHE_PRELOAD_OP_FAULT_ST_M (BIT(1)) 958 #define EXTMEM_ICACHE_PRELOAD_OP_FAULT_ST_V 0x1 959 #define EXTMEM_ICACHE_PRELOAD_OP_FAULT_ST_S 1 960 /* EXTMEM_ICACHE_SYNC_OP_FAULT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ 961 /*description: The bit is used to indicate interrupt by sync configurations fault.*/ 962 #define EXTMEM_ICACHE_SYNC_OP_FAULT_ST (BIT(0)) 963 #define EXTMEM_ICACHE_SYNC_OP_FAULT_ST_M (BIT(0)) 964 #define EXTMEM_ICACHE_SYNC_OP_FAULT_ST_V 0x1 965 #define EXTMEM_ICACHE_SYNC_OP_FAULT_ST_S 0 966 967 #define EXTMEM_CORE0_ACS_CACHE_INT_ENA_REG (DR_REG_EXTMEM_BASE + 0x0E8) 968 /* EXTMEM_CORE0_DBUS_REJECT_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ 969 /*description: The bit is used to enable interrupt by authentication fail.*/ 970 #define EXTMEM_CORE0_DBUS_REJECT_INT_ENA (BIT(4)) 971 #define EXTMEM_CORE0_DBUS_REJECT_INT_ENA_M (BIT(4)) 972 #define EXTMEM_CORE0_DBUS_REJECT_INT_ENA_V 0x1 973 #define EXTMEM_CORE0_DBUS_REJECT_INT_ENA_S 4 974 /* EXTMEM_CORE0_DBUS_ACS_MSK_DC_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ 975 /*description: The bit is used to enable interrupt by cpu access dcache while 976 the corresponding dbus is disabled which include speculative access.*/ 977 #define EXTMEM_CORE0_DBUS_ACS_MSK_DC_INT_ENA (BIT(3)) 978 #define EXTMEM_CORE0_DBUS_ACS_MSK_DC_INT_ENA_M (BIT(3)) 979 #define EXTMEM_CORE0_DBUS_ACS_MSK_DC_INT_ENA_V 0x1 980 #define EXTMEM_CORE0_DBUS_ACS_MSK_DC_INT_ENA_S 3 981 /* EXTMEM_CORE0_IBUS_REJECT_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ 982 /*description: The bit is used to enable interrupt by authentication fail.*/ 983 #define EXTMEM_CORE0_IBUS_REJECT_INT_ENA (BIT(2)) 984 #define EXTMEM_CORE0_IBUS_REJECT_INT_ENA_M (BIT(2)) 985 #define EXTMEM_CORE0_IBUS_REJECT_INT_ENA_V 0x1 986 #define EXTMEM_CORE0_IBUS_REJECT_INT_ENA_S 2 987 /* EXTMEM_CORE0_IBUS_WR_IC_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ 988 /*description: The bit is used to enable interrupt by ibus trying to write icache*/ 989 #define EXTMEM_CORE0_IBUS_WR_IC_INT_ENA (BIT(1)) 990 #define EXTMEM_CORE0_IBUS_WR_IC_INT_ENA_M (BIT(1)) 991 #define EXTMEM_CORE0_IBUS_WR_IC_INT_ENA_V 0x1 992 #define EXTMEM_CORE0_IBUS_WR_IC_INT_ENA_S 1 993 /* EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ 994 /*description: The bit is used to enable interrupt by cpu access icache while 995 the corresponding ibus is disabled which include speculative access.*/ 996 #define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_ENA (BIT(0)) 997 #define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_ENA_M (BIT(0)) 998 #define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_ENA_V 0x1 999 #define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_ENA_S 0 1000 1001 #define EXTMEM_CORE0_ACS_CACHE_INT_CLR_REG (DR_REG_EXTMEM_BASE + 0x0EC) 1002 /* EXTMEM_CORE0_DBUS_REJECT_INT_CLR : WOD ;bitpos:[4] ;default: 1'b0 ; */ 1003 /*description: The bit is used to clear interrupt by authentication fail.*/ 1004 #define EXTMEM_CORE0_DBUS_REJECT_INT_CLR (BIT(4)) 1005 #define EXTMEM_CORE0_DBUS_REJECT_INT_CLR_M (BIT(4)) 1006 #define EXTMEM_CORE0_DBUS_REJECT_INT_CLR_V 0x1 1007 #define EXTMEM_CORE0_DBUS_REJECT_INT_CLR_S 4 1008 /* EXTMEM_CORE0_DBUS_ACS_MSK_DC_INT_CLR : WOD ;bitpos:[3] ;default: 1'b0 ; */ 1009 /*description: The bit is used to clear interrupt by cpu access dcache while 1010 the corresponding dbus is disabled or dcache is disabled which include speculative access.*/ 1011 #define EXTMEM_CORE0_DBUS_ACS_MSK_DC_INT_CLR (BIT(3)) 1012 #define EXTMEM_CORE0_DBUS_ACS_MSK_DC_INT_CLR_M (BIT(3)) 1013 #define EXTMEM_CORE0_DBUS_ACS_MSK_DC_INT_CLR_V 0x1 1014 #define EXTMEM_CORE0_DBUS_ACS_MSK_DC_INT_CLR_S 3 1015 /* EXTMEM_CORE0_IBUS_REJECT_INT_CLR : WOD ;bitpos:[2] ;default: 1'b0 ; */ 1016 /*description: The bit is used to clear interrupt by authentication fail.*/ 1017 #define EXTMEM_CORE0_IBUS_REJECT_INT_CLR (BIT(2)) 1018 #define EXTMEM_CORE0_IBUS_REJECT_INT_CLR_M (BIT(2)) 1019 #define EXTMEM_CORE0_IBUS_REJECT_INT_CLR_V 0x1 1020 #define EXTMEM_CORE0_IBUS_REJECT_INT_CLR_S 2 1021 /* EXTMEM_CORE0_IBUS_WR_IC_INT_CLR : WOD ;bitpos:[1] ;default: 1'b0 ; */ 1022 /*description: The bit is used to clear interrupt by ibus trying to write icache*/ 1023 #define EXTMEM_CORE0_IBUS_WR_IC_INT_CLR (BIT(1)) 1024 #define EXTMEM_CORE0_IBUS_WR_IC_INT_CLR_M (BIT(1)) 1025 #define EXTMEM_CORE0_IBUS_WR_IC_INT_CLR_V 0x1 1026 #define EXTMEM_CORE0_IBUS_WR_IC_INT_CLR_S 1 1027 /* EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_CLR : WOD ;bitpos:[0] ;default: 1'b0 ; */ 1028 /*description: The bit is used to clear interrupt by cpu access icache while 1029 the corresponding ibus is disabled or icache is disabled which include speculative access.*/ 1030 #define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_CLR (BIT(0)) 1031 #define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_CLR_M (BIT(0)) 1032 #define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_CLR_V 0x1 1033 #define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_CLR_S 0 1034 1035 #define EXTMEM_CORE0_ACS_CACHE_INT_ST_REG (DR_REG_EXTMEM_BASE + 0x0F0) 1036 /* EXTMEM_CORE0_DBUS_REJECT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ 1037 /*description: The bit is used to indicate interrupt by authentication fail.*/ 1038 #define EXTMEM_CORE0_DBUS_REJECT_ST (BIT(4)) 1039 #define EXTMEM_CORE0_DBUS_REJECT_ST_M (BIT(4)) 1040 #define EXTMEM_CORE0_DBUS_REJECT_ST_V 0x1 1041 #define EXTMEM_CORE0_DBUS_REJECT_ST_S 4 1042 /* EXTMEM_CORE0_DBUS_ACS_MSK_DCACHE_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ 1043 /*description: The bit is used to indicate interrupt by cpu access dcache while 1044 the core0_dbus is disabled or dcache is disabled which include speculative access.*/ 1045 #define EXTMEM_CORE0_DBUS_ACS_MSK_DCACHE_ST (BIT(3)) 1046 #define EXTMEM_CORE0_DBUS_ACS_MSK_DCACHE_ST_M (BIT(3)) 1047 #define EXTMEM_CORE0_DBUS_ACS_MSK_DCACHE_ST_V 0x1 1048 #define EXTMEM_CORE0_DBUS_ACS_MSK_DCACHE_ST_S 3 1049 /* EXTMEM_CORE0_IBUS_REJECT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ 1050 /*description: The bit is used to indicate interrupt by authentication fail.*/ 1051 #define EXTMEM_CORE0_IBUS_REJECT_ST (BIT(2)) 1052 #define EXTMEM_CORE0_IBUS_REJECT_ST_M (BIT(2)) 1053 #define EXTMEM_CORE0_IBUS_REJECT_ST_V 0x1 1054 #define EXTMEM_CORE0_IBUS_REJECT_ST_S 2 1055 /* EXTMEM_CORE0_IBUS_WR_ICACHE_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ 1056 /*description: The bit is used to indicate interrupt by ibus trying to write icache*/ 1057 #define EXTMEM_CORE0_IBUS_WR_ICACHE_ST (BIT(1)) 1058 #define EXTMEM_CORE0_IBUS_WR_ICACHE_ST_M (BIT(1)) 1059 #define EXTMEM_CORE0_IBUS_WR_ICACHE_ST_V 0x1 1060 #define EXTMEM_CORE0_IBUS_WR_ICACHE_ST_S 1 1061 /* EXTMEM_CORE0_IBUS_ACS_MSK_ICACHE_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ 1062 /*description: The bit is used to indicate interrupt by cpu access icache while 1063 the core0_ibus is disabled or icache is disabled which include speculative access.*/ 1064 #define EXTMEM_CORE0_IBUS_ACS_MSK_ICACHE_ST (BIT(0)) 1065 #define EXTMEM_CORE0_IBUS_ACS_MSK_ICACHE_ST_M (BIT(0)) 1066 #define EXTMEM_CORE0_IBUS_ACS_MSK_ICACHE_ST_V 0x1 1067 #define EXTMEM_CORE0_IBUS_ACS_MSK_ICACHE_ST_S 0 1068 1069 #define EXTMEM_CORE1_ACS_CACHE_INT_ENA_REG (DR_REG_EXTMEM_BASE + 0x0F4) 1070 /* EXTMEM_CORE1_DBUS_REJECT_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ 1071 /*description: The bit is used to enable interrupt by authentication fail.*/ 1072 #define EXTMEM_CORE1_DBUS_REJECT_INT_ENA (BIT(4)) 1073 #define EXTMEM_CORE1_DBUS_REJECT_INT_ENA_M (BIT(4)) 1074 #define EXTMEM_CORE1_DBUS_REJECT_INT_ENA_V 0x1 1075 #define EXTMEM_CORE1_DBUS_REJECT_INT_ENA_S 4 1076 /* EXTMEM_CORE1_DBUS_ACS_MSK_DC_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ 1077 /*description: The bit is used to enable interrupt by cpu access dcache while 1078 the corresponding dbus is disabled which include speculative access.*/ 1079 #define EXTMEM_CORE1_DBUS_ACS_MSK_DC_INT_ENA (BIT(3)) 1080 #define EXTMEM_CORE1_DBUS_ACS_MSK_DC_INT_ENA_M (BIT(3)) 1081 #define EXTMEM_CORE1_DBUS_ACS_MSK_DC_INT_ENA_V 0x1 1082 #define EXTMEM_CORE1_DBUS_ACS_MSK_DC_INT_ENA_S 3 1083 /* EXTMEM_CORE1_IBUS_REJECT_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ 1084 /*description: The bit is used to enable interrupt by authentication fail.*/ 1085 #define EXTMEM_CORE1_IBUS_REJECT_INT_ENA (BIT(2)) 1086 #define EXTMEM_CORE1_IBUS_REJECT_INT_ENA_M (BIT(2)) 1087 #define EXTMEM_CORE1_IBUS_REJECT_INT_ENA_V 0x1 1088 #define EXTMEM_CORE1_IBUS_REJECT_INT_ENA_S 2 1089 /* EXTMEM_CORE1_IBUS_WR_IC_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ 1090 /*description: The bit is used to enable interrupt by ibus trying to write icache*/ 1091 #define EXTMEM_CORE1_IBUS_WR_IC_INT_ENA (BIT(1)) 1092 #define EXTMEM_CORE1_IBUS_WR_IC_INT_ENA_M (BIT(1)) 1093 #define EXTMEM_CORE1_IBUS_WR_IC_INT_ENA_V 0x1 1094 #define EXTMEM_CORE1_IBUS_WR_IC_INT_ENA_S 1 1095 /* EXTMEM_CORE1_IBUS_ACS_MSK_IC_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ 1096 /*description: The bit is used to enable interrupt by cpu access icache while 1097 the corresponding ibus is disabled which include speculative access.*/ 1098 #define EXTMEM_CORE1_IBUS_ACS_MSK_IC_INT_ENA (BIT(0)) 1099 #define EXTMEM_CORE1_IBUS_ACS_MSK_IC_INT_ENA_M (BIT(0)) 1100 #define EXTMEM_CORE1_IBUS_ACS_MSK_IC_INT_ENA_V 0x1 1101 #define EXTMEM_CORE1_IBUS_ACS_MSK_IC_INT_ENA_S 0 1102 1103 #define EXTMEM_CORE1_ACS_CACHE_INT_CLR_REG (DR_REG_EXTMEM_BASE + 0x0F8) 1104 /* EXTMEM_CORE1_DBUS_REJECT_INT_CLR : WOD ;bitpos:[4] ;default: 1'b0 ; */ 1105 /*description: The bit is used to clear interrupt by authentication fail.*/ 1106 #define EXTMEM_CORE1_DBUS_REJECT_INT_CLR (BIT(4)) 1107 #define EXTMEM_CORE1_DBUS_REJECT_INT_CLR_M (BIT(4)) 1108 #define EXTMEM_CORE1_DBUS_REJECT_INT_CLR_V 0x1 1109 #define EXTMEM_CORE1_DBUS_REJECT_INT_CLR_S 4 1110 /* EXTMEM_CORE1_DBUS_ACS_MSK_DC_INT_CLR : WOD ;bitpos:[3] ;default: 1'b0 ; */ 1111 /*description: The bit is used to clear interrupt by cpu access dcache while 1112 the corresponding dbus is disabled or dcache is disabled which include speculative access.*/ 1113 #define EXTMEM_CORE1_DBUS_ACS_MSK_DC_INT_CLR (BIT(3)) 1114 #define EXTMEM_CORE1_DBUS_ACS_MSK_DC_INT_CLR_M (BIT(3)) 1115 #define EXTMEM_CORE1_DBUS_ACS_MSK_DC_INT_CLR_V 0x1 1116 #define EXTMEM_CORE1_DBUS_ACS_MSK_DC_INT_CLR_S 3 1117 /* EXTMEM_CORE1_IBUS_REJECT_INT_CLR : WOD ;bitpos:[2] ;default: 1'b0 ; */ 1118 /*description: The bit is used to clear interrupt by authentication fail.*/ 1119 #define EXTMEM_CORE1_IBUS_REJECT_INT_CLR (BIT(2)) 1120 #define EXTMEM_CORE1_IBUS_REJECT_INT_CLR_M (BIT(2)) 1121 #define EXTMEM_CORE1_IBUS_REJECT_INT_CLR_V 0x1 1122 #define EXTMEM_CORE1_IBUS_REJECT_INT_CLR_S 2 1123 /* EXTMEM_CORE1_IBUS_WR_IC_INT_CLR : WOD ;bitpos:[1] ;default: 1'b0 ; */ 1124 /*description: The bit is used to clear interrupt by ibus trying to write icache*/ 1125 #define EXTMEM_CORE1_IBUS_WR_IC_INT_CLR (BIT(1)) 1126 #define EXTMEM_CORE1_IBUS_WR_IC_INT_CLR_M (BIT(1)) 1127 #define EXTMEM_CORE1_IBUS_WR_IC_INT_CLR_V 0x1 1128 #define EXTMEM_CORE1_IBUS_WR_IC_INT_CLR_S 1 1129 /* EXTMEM_CORE1_IBUS_ACS_MSK_IC_INT_CLR : WOD ;bitpos:[0] ;default: 1'b0 ; */ 1130 /*description: The bit is used to clear interrupt by cpu access icache while 1131 the corresponding ibus is disabled or icache is disabled which include speculative access.*/ 1132 #define EXTMEM_CORE1_IBUS_ACS_MSK_IC_INT_CLR (BIT(0)) 1133 #define EXTMEM_CORE1_IBUS_ACS_MSK_IC_INT_CLR_M (BIT(0)) 1134 #define EXTMEM_CORE1_IBUS_ACS_MSK_IC_INT_CLR_V 0x1 1135 #define EXTMEM_CORE1_IBUS_ACS_MSK_IC_INT_CLR_S 0 1136 1137 #define EXTMEM_CORE1_ACS_CACHE_INT_ST_REG (DR_REG_EXTMEM_BASE + 0x0FC) 1138 /* EXTMEM_CORE1_DBUS_REJECT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ 1139 /*description: The bit is used to indicate interrupt by authentication fail.*/ 1140 #define EXTMEM_CORE1_DBUS_REJECT_ST (BIT(4)) 1141 #define EXTMEM_CORE1_DBUS_REJECT_ST_M (BIT(4)) 1142 #define EXTMEM_CORE1_DBUS_REJECT_ST_V 0x1 1143 #define EXTMEM_CORE1_DBUS_REJECT_ST_S 4 1144 /* EXTMEM_CORE1_DBUS_ACS_MSK_DCACHE_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ 1145 /*description: The bit is used to indicate interrupt by cpu access dcache while 1146 the core1_dbus is disabled or dcache is disabled which include speculative access.*/ 1147 #define EXTMEM_CORE1_DBUS_ACS_MSK_DCACHE_ST (BIT(3)) 1148 #define EXTMEM_CORE1_DBUS_ACS_MSK_DCACHE_ST_M (BIT(3)) 1149 #define EXTMEM_CORE1_DBUS_ACS_MSK_DCACHE_ST_V 0x1 1150 #define EXTMEM_CORE1_DBUS_ACS_MSK_DCACHE_ST_S 3 1151 /* EXTMEM_CORE1_IBUS_REJECT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ 1152 /*description: The bit is used to indicate interrupt by authentication fail.*/ 1153 #define EXTMEM_CORE1_IBUS_REJECT_ST (BIT(2)) 1154 #define EXTMEM_CORE1_IBUS_REJECT_ST_M (BIT(2)) 1155 #define EXTMEM_CORE1_IBUS_REJECT_ST_V 0x1 1156 #define EXTMEM_CORE1_IBUS_REJECT_ST_S 2 1157 /* EXTMEM_CORE1_IBUS_WR_ICACHE_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ 1158 /*description: The bit is used to indicate interrupt by ibus trying to write icache*/ 1159 #define EXTMEM_CORE1_IBUS_WR_ICACHE_ST (BIT(1)) 1160 #define EXTMEM_CORE1_IBUS_WR_ICACHE_ST_M (BIT(1)) 1161 #define EXTMEM_CORE1_IBUS_WR_ICACHE_ST_V 0x1 1162 #define EXTMEM_CORE1_IBUS_WR_ICACHE_ST_S 1 1163 /* EXTMEM_CORE1_IBUS_ACS_MSK_ICACHE_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ 1164 /*description: The bit is used to indicate interrupt by cpu access icache while 1165 the core1_ibus is disabled or icache is disabled which include speculative access.*/ 1166 #define EXTMEM_CORE1_IBUS_ACS_MSK_ICACHE_ST (BIT(0)) 1167 #define EXTMEM_CORE1_IBUS_ACS_MSK_ICACHE_ST_M (BIT(0)) 1168 #define EXTMEM_CORE1_IBUS_ACS_MSK_ICACHE_ST_V 0x1 1169 #define EXTMEM_CORE1_IBUS_ACS_MSK_ICACHE_ST_S 0 1170 1171 #define EXTMEM_CORE0_DBUS_REJECT_ST_REG (DR_REG_EXTMEM_BASE + 0x100) 1172 /* EXTMEM_CORE0_DBUS_WORLD : RO ;bitpos:[6] ;default: 1'b0 ; */ 1173 /*description: The bit is used to indicate the world of CPU access dbus when 1174 authentication fail. 0: WORLD0 1: WORLD1*/ 1175 #define EXTMEM_CORE0_DBUS_WORLD (BIT(6)) 1176 #define EXTMEM_CORE0_DBUS_WORLD_M (BIT(6)) 1177 #define EXTMEM_CORE0_DBUS_WORLD_V 0x1 1178 #define EXTMEM_CORE0_DBUS_WORLD_S 6 1179 /* EXTMEM_CORE0_DBUS_ATTR : RO ;bitpos:[5:3] ;default: 3'b0 ; */ 1180 /*description: The bits are used to indicate the attribute of CPU access dbus 1181 when authentication fail. 0: invalidate 1: execute-able 2: read-able 4: write-able.*/ 1182 #define EXTMEM_CORE0_DBUS_ATTR 0x00000007 1183 #define EXTMEM_CORE0_DBUS_ATTR_M ((EXTMEM_CORE0_DBUS_ATTR_V)<<(EXTMEM_CORE0_DBUS_ATTR_S)) 1184 #define EXTMEM_CORE0_DBUS_ATTR_V 0x7 1185 #define EXTMEM_CORE0_DBUS_ATTR_S 3 1186 /* EXTMEM_CORE0_DBUS_TAG_ATTR : RO ;bitpos:[2:0] ;default: 3'b0 ; */ 1187 /*description: The bits are used to indicate the attribute of data from external 1188 memory when authentication fail. 0: invalidate 1: execute-able 2: read-able 4: write-able.*/ 1189 #define EXTMEM_CORE0_DBUS_TAG_ATTR 0x00000007 1190 #define EXTMEM_CORE0_DBUS_TAG_ATTR_M ((EXTMEM_CORE0_DBUS_TAG_ATTR_V)<<(EXTMEM_CORE0_DBUS_TAG_ATTR_S)) 1191 #define EXTMEM_CORE0_DBUS_TAG_ATTR_V 0x7 1192 #define EXTMEM_CORE0_DBUS_TAG_ATTR_S 0 1193 1194 #define EXTMEM_CORE0_DBUS_REJECT_VADDR_REG (DR_REG_EXTMEM_BASE + 0x104) 1195 /* EXTMEM_CORE0_DBUS_VADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 1196 /*description: The bits are used to indicate the virtual address of CPU access 1197 dbus when authentication fail.*/ 1198 #define EXTMEM_CORE0_DBUS_VADDR 0xFFFFFFFF 1199 #define EXTMEM_CORE0_DBUS_VADDR_M ((EXTMEM_CORE0_DBUS_VADDR_V)<<(EXTMEM_CORE0_DBUS_VADDR_S)) 1200 #define EXTMEM_CORE0_DBUS_VADDR_V 0xFFFFFFFF 1201 #define EXTMEM_CORE0_DBUS_VADDR_S 0 1202 1203 #define EXTMEM_CORE0_IBUS_REJECT_ST_REG (DR_REG_EXTMEM_BASE + 0x108) 1204 /* EXTMEM_CORE0_IBUS_WORLD : RO ;bitpos:[6] ;default: 1'b0 ; */ 1205 /*description: The bit is used to indicate the world of CPU access ibus when 1206 authentication fail. 0: WORLD0 1: WORLD1*/ 1207 #define EXTMEM_CORE0_IBUS_WORLD (BIT(6)) 1208 #define EXTMEM_CORE0_IBUS_WORLD_M (BIT(6)) 1209 #define EXTMEM_CORE0_IBUS_WORLD_V 0x1 1210 #define EXTMEM_CORE0_IBUS_WORLD_S 6 1211 /* EXTMEM_CORE0_IBUS_ATTR : RO ;bitpos:[5:3] ;default: 3'b0 ; */ 1212 /*description: The bits are used to indicate the attribute of CPU access ibus 1213 when authentication fail. 0: invalidate 1: execute-able 2: read-able*/ 1214 #define EXTMEM_CORE0_IBUS_ATTR 0x00000007 1215 #define EXTMEM_CORE0_IBUS_ATTR_M ((EXTMEM_CORE0_IBUS_ATTR_V)<<(EXTMEM_CORE0_IBUS_ATTR_S)) 1216 #define EXTMEM_CORE0_IBUS_ATTR_V 0x7 1217 #define EXTMEM_CORE0_IBUS_ATTR_S 3 1218 /* EXTMEM_CORE0_IBUS_TAG_ATTR : RO ;bitpos:[2:0] ;default: 3'b0 ; */ 1219 /*description: The bits are used to indicate the attribute of data from external 1220 memory when authentication fail. 0: invalidate 1: execute-able 2: read-able 4: write-able.*/ 1221 #define EXTMEM_CORE0_IBUS_TAG_ATTR 0x00000007 1222 #define EXTMEM_CORE0_IBUS_TAG_ATTR_M ((EXTMEM_CORE0_IBUS_TAG_ATTR_V)<<(EXTMEM_CORE0_IBUS_TAG_ATTR_S)) 1223 #define EXTMEM_CORE0_IBUS_TAG_ATTR_V 0x7 1224 #define EXTMEM_CORE0_IBUS_TAG_ATTR_S 0 1225 1226 #define EXTMEM_CORE0_IBUS_REJECT_VADDR_REG (DR_REG_EXTMEM_BASE + 0x10C) 1227 /* EXTMEM_CORE0_IBUS_VADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 1228 /*description: The bits are used to indicate the virtual address of CPU access 1229 ibus when authentication fail.*/ 1230 #define EXTMEM_CORE0_IBUS_VADDR 0xFFFFFFFF 1231 #define EXTMEM_CORE0_IBUS_VADDR_M ((EXTMEM_CORE0_IBUS_VADDR_V)<<(EXTMEM_CORE0_IBUS_VADDR_S)) 1232 #define EXTMEM_CORE0_IBUS_VADDR_V 0xFFFFFFFF 1233 #define EXTMEM_CORE0_IBUS_VADDR_S 0 1234 1235 #define EXTMEM_CORE1_DBUS_REJECT_ST_REG (DR_REG_EXTMEM_BASE + 0x110) 1236 /* EXTMEM_CORE1_DBUS_WORLD : RO ;bitpos:[6] ;default: 1'b0 ; */ 1237 /*description: The bit is used to indicate the world of CPU access dbus when 1238 authentication fail. 0: WORLD0 1: WORLD1*/ 1239 #define EXTMEM_CORE1_DBUS_WORLD (BIT(6)) 1240 #define EXTMEM_CORE1_DBUS_WORLD_M (BIT(6)) 1241 #define EXTMEM_CORE1_DBUS_WORLD_V 0x1 1242 #define EXTMEM_CORE1_DBUS_WORLD_S 6 1243 /* EXTMEM_CORE1_DBUS_ATTR : RO ;bitpos:[5:3] ;default: 3'b0 ; */ 1244 /*description: The bits are used to indicate the attribute of CPU access dbus 1245 when authentication fail. 0: invalidate 1: execute-able 2: read-able 4: write-able.*/ 1246 #define EXTMEM_CORE1_DBUS_ATTR 0x00000007 1247 #define EXTMEM_CORE1_DBUS_ATTR_M ((EXTMEM_CORE1_DBUS_ATTR_V)<<(EXTMEM_CORE1_DBUS_ATTR_S)) 1248 #define EXTMEM_CORE1_DBUS_ATTR_V 0x7 1249 #define EXTMEM_CORE1_DBUS_ATTR_S 3 1250 /* EXTMEM_CORE1_DBUS_TAG_ATTR : RO ;bitpos:[2:0] ;default: 3'b0 ; */ 1251 /*description: The bits are used to indicate the attribute of data from external 1252 memory when authentication fail. 0: invalidate 1: execute-able 2: read-able 4: write-able.*/ 1253 #define EXTMEM_CORE1_DBUS_TAG_ATTR 0x00000007 1254 #define EXTMEM_CORE1_DBUS_TAG_ATTR_M ((EXTMEM_CORE1_DBUS_TAG_ATTR_V)<<(EXTMEM_CORE1_DBUS_TAG_ATTR_S)) 1255 #define EXTMEM_CORE1_DBUS_TAG_ATTR_V 0x7 1256 #define EXTMEM_CORE1_DBUS_TAG_ATTR_S 0 1257 1258 #define EXTMEM_CORE1_DBUS_REJECT_VADDR_REG (DR_REG_EXTMEM_BASE + 0x114) 1259 /* EXTMEM_CORE1_DBUS_VADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 1260 /*description: The bits are used to indicate the virtual address of CPU access 1261 dbus when authentication fail.*/ 1262 #define EXTMEM_CORE1_DBUS_VADDR 0xFFFFFFFF 1263 #define EXTMEM_CORE1_DBUS_VADDR_M ((EXTMEM_CORE1_DBUS_VADDR_V)<<(EXTMEM_CORE1_DBUS_VADDR_S)) 1264 #define EXTMEM_CORE1_DBUS_VADDR_V 0xFFFFFFFF 1265 #define EXTMEM_CORE1_DBUS_VADDR_S 0 1266 1267 #define EXTMEM_CORE1_IBUS_REJECT_ST_REG (DR_REG_EXTMEM_BASE + 0x118) 1268 /* EXTMEM_CORE1_IBUS_WORLD : RO ;bitpos:[6] ;default: 1'b0 ; */ 1269 /*description: The bit is used to indicate the world of CPU access ibus when 1270 authentication fail. 0: WORLD0 1: WORLD1*/ 1271 #define EXTMEM_CORE1_IBUS_WORLD (BIT(6)) 1272 #define EXTMEM_CORE1_IBUS_WORLD_M (BIT(6)) 1273 #define EXTMEM_CORE1_IBUS_WORLD_V 0x1 1274 #define EXTMEM_CORE1_IBUS_WORLD_S 6 1275 /* EXTMEM_CORE1_IBUS_ATTR : RO ;bitpos:[5:3] ;default: 3'b0 ; */ 1276 /*description: The bits are used to indicate the attribute of CPU access ibus 1277 when authentication fail. 0: invalidate 1: execute-able 2: read-able*/ 1278 #define EXTMEM_CORE1_IBUS_ATTR 0x00000007 1279 #define EXTMEM_CORE1_IBUS_ATTR_M ((EXTMEM_CORE1_IBUS_ATTR_V)<<(EXTMEM_CORE1_IBUS_ATTR_S)) 1280 #define EXTMEM_CORE1_IBUS_ATTR_V 0x7 1281 #define EXTMEM_CORE1_IBUS_ATTR_S 3 1282 /* EXTMEM_CORE1_IBUS_TAG_ATTR : RO ;bitpos:[2:0] ;default: 3'b0 ; */ 1283 /*description: The bits are used to indicate the attribute of data from external 1284 memory when authentication fail. 0: invalidate 1: execute-able 2: read-able 4: write-able.*/ 1285 #define EXTMEM_CORE1_IBUS_TAG_ATTR 0x00000007 1286 #define EXTMEM_CORE1_IBUS_TAG_ATTR_M ((EXTMEM_CORE1_IBUS_TAG_ATTR_V)<<(EXTMEM_CORE1_IBUS_TAG_ATTR_S)) 1287 #define EXTMEM_CORE1_IBUS_TAG_ATTR_V 0x7 1288 #define EXTMEM_CORE1_IBUS_TAG_ATTR_S 0 1289 1290 #define EXTMEM_CORE1_IBUS_REJECT_VADDR_REG (DR_REG_EXTMEM_BASE + 0x11C) 1291 /* EXTMEM_CORE1_IBUS_VADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 1292 /*description: The bits are used to indicate the virtual address of CPU access 1293 ibus when authentication fail.*/ 1294 #define EXTMEM_CORE1_IBUS_VADDR 0xFFFFFFFF 1295 #define EXTMEM_CORE1_IBUS_VADDR_M ((EXTMEM_CORE1_IBUS_VADDR_V)<<(EXTMEM_CORE1_IBUS_VADDR_S)) 1296 #define EXTMEM_CORE1_IBUS_VADDR_V 0xFFFFFFFF 1297 #define EXTMEM_CORE1_IBUS_VADDR_S 0 1298 1299 #define EXTMEM_CACHE_MMU_FAULT_CONTENT_REG (DR_REG_EXTMEM_BASE + 0x120) 1300 /* EXTMEM_CACHE_MMU_FAULT_CODE : RO ;bitpos:[19:16] ;default: 4'h0 ; */ 1301 /*description: The right-most 3 bits are used to indicate the operations which 1302 cause mmu fault occurrence. 0: default 1: cpu miss 2: preload miss 3: writeback 4: cpu miss evict recovery address 5: load miss evict recovery address 6: external dma tx 7: external dma rx. The most significant bit is used to indicate this operation occurs in which one icache.*/ 1303 #define EXTMEM_CACHE_MMU_FAULT_CODE 0x0000000F 1304 #define EXTMEM_CACHE_MMU_FAULT_CODE_M ((EXTMEM_CACHE_MMU_FAULT_CODE_V)<<(EXTMEM_CACHE_MMU_FAULT_CODE_S)) 1305 #define EXTMEM_CACHE_MMU_FAULT_CODE_V 0xF 1306 #define EXTMEM_CACHE_MMU_FAULT_CODE_S 16 1307 /* EXTMEM_CACHE_MMU_FAULT_CONTENT : RO ;bitpos:[15:0] ;default: 17'h0 ; */ 1308 /*description: The bits are used to indicate the content of mmu entry which cause mmu fault..*/ 1309 #define EXTMEM_CACHE_MMU_FAULT_CONTENT 0x0000FFFF 1310 #define EXTMEM_CACHE_MMU_FAULT_CONTENT_M ((EXTMEM_CACHE_MMU_FAULT_CONTENT_V)<<(EXTMEM_CACHE_MMU_FAULT_CONTENT_S)) 1311 #define EXTMEM_CACHE_MMU_FAULT_CONTENT_V 0xFFFF 1312 #define EXTMEM_CACHE_MMU_FAULT_CONTENT_S 0 1313 1314 #define EXTMEM_CACHE_MMU_FAULT_VADDR_REG (DR_REG_EXTMEM_BASE + 0x124) 1315 /* EXTMEM_CACHE_MMU_FAULT_VADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 1316 /*description: The bits are used to indicate the virtual address which cause mmu fault..*/ 1317 #define EXTMEM_CACHE_MMU_FAULT_VADDR 0xFFFFFFFF 1318 #define EXTMEM_CACHE_MMU_FAULT_VADDR_M ((EXTMEM_CACHE_MMU_FAULT_VADDR_V)<<(EXTMEM_CACHE_MMU_FAULT_VADDR_S)) 1319 #define EXTMEM_CACHE_MMU_FAULT_VADDR_V 0xFFFFFFFF 1320 #define EXTMEM_CACHE_MMU_FAULT_VADDR_S 0 1321 1322 #define EXTMEM_CACHE_WRAP_AROUND_CTRL_REG (DR_REG_EXTMEM_BASE + 0x128) 1323 /* EXTMEM_CACHE_SRAM_RD_WRAP_AROUND : R/W ;bitpos:[1] ;default: 1'b0 ; */ 1324 /*description: The bit is used to enable wrap around mode when read data from spiram.*/ 1325 #define EXTMEM_CACHE_SRAM_RD_WRAP_AROUND (BIT(1)) 1326 #define EXTMEM_CACHE_SRAM_RD_WRAP_AROUND_M (BIT(1)) 1327 #define EXTMEM_CACHE_SRAM_RD_WRAP_AROUND_V 0x1 1328 #define EXTMEM_CACHE_SRAM_RD_WRAP_AROUND_S 1 1329 /* EXTMEM_CACHE_FLASH_WRAP_AROUND : R/W ;bitpos:[0] ;default: 1'b0 ; */ 1330 /*description: The bit is used to enable wrap around mode when read data from flash.*/ 1331 #define EXTMEM_CACHE_FLASH_WRAP_AROUND (BIT(0)) 1332 #define EXTMEM_CACHE_FLASH_WRAP_AROUND_M (BIT(0)) 1333 #define EXTMEM_CACHE_FLASH_WRAP_AROUND_V 0x1 1334 #define EXTMEM_CACHE_FLASH_WRAP_AROUND_S 0 1335 1336 #define EXTMEM_CACHE_MMU_POWER_CTRL_REG (DR_REG_EXTMEM_BASE + 0x12C) 1337 /* EXTMEM_CACHE_MMU_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b1 ; */ 1338 /*description: The bit is used to power mmu memory down 0: follow_rtc_lslp_pd 1: power up*/ 1339 #define EXTMEM_CACHE_MMU_MEM_FORCE_PU (BIT(2)) 1340 #define EXTMEM_CACHE_MMU_MEM_FORCE_PU_M (BIT(2)) 1341 #define EXTMEM_CACHE_MMU_MEM_FORCE_PU_V 0x1 1342 #define EXTMEM_CACHE_MMU_MEM_FORCE_PU_S 2 1343 /* EXTMEM_CACHE_MMU_MEM_FORCE_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */ 1344 /*description: The bit is used to power mmu memory down 0: follow_rtc_lslp_pd 1: power down*/ 1345 #define EXTMEM_CACHE_MMU_MEM_FORCE_PD (BIT(1)) 1346 #define EXTMEM_CACHE_MMU_MEM_FORCE_PD_M (BIT(1)) 1347 #define EXTMEM_CACHE_MMU_MEM_FORCE_PD_V 0x1 1348 #define EXTMEM_CACHE_MMU_MEM_FORCE_PD_S 1 1349 /* EXTMEM_CACHE_MMU_MEM_FORCE_ON : R/W ;bitpos:[0] ;default: 1'b1 ; */ 1350 /*description: The bit is used to enable clock gating to save power when access 1351 mmu memory 0: enable 1: disable*/ 1352 #define EXTMEM_CACHE_MMU_MEM_FORCE_ON (BIT(0)) 1353 #define EXTMEM_CACHE_MMU_MEM_FORCE_ON_M (BIT(0)) 1354 #define EXTMEM_CACHE_MMU_MEM_FORCE_ON_V 0x1 1355 #define EXTMEM_CACHE_MMU_MEM_FORCE_ON_S 0 1356 1357 #define EXTMEM_CACHE_STATE_REG (DR_REG_EXTMEM_BASE + 0x130) 1358 /* EXTMEM_DCACHE_STATE : RO ;bitpos:[23:12] ;default: 12'h0 ; */ 1359 /*description: The bit is used to indicate whether dcache main fsm is in idle 1360 state or not. 1: in idle state 0: not in idle state*/ 1361 #define EXTMEM_DCACHE_STATE 0x00000FFF 1362 #define EXTMEM_DCACHE_STATE_M ((EXTMEM_DCACHE_STATE_V)<<(EXTMEM_DCACHE_STATE_S)) 1363 #define EXTMEM_DCACHE_STATE_V 0xFFF 1364 #define EXTMEM_DCACHE_STATE_S 12 1365 /* EXTMEM_ICACHE_STATE : RO ;bitpos:[11:0] ;default: 12'h0 ; */ 1366 /*description: The bit is used to indicate whether icache main fsm is in idle 1367 state or not. 1: in idle state 0: not in idle state*/ 1368 #define EXTMEM_ICACHE_STATE 0x00000FFF 1369 #define EXTMEM_ICACHE_STATE_M ((EXTMEM_ICACHE_STATE_V)<<(EXTMEM_ICACHE_STATE_S)) 1370 #define EXTMEM_ICACHE_STATE_V 0xFFF 1371 #define EXTMEM_ICACHE_STATE_S 0 1372 1373 #define EXTMEM_CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE_REG (DR_REG_EXTMEM_BASE + 0x134) 1374 /* EXTMEM_RECORD_DISABLE_G0CB_DECRYPT : R/W ;bitpos:[1] ;default: 1'b0 ; */ 1375 /*description: Reserved.*/ 1376 #define EXTMEM_RECORD_DISABLE_G0CB_DECRYPT (BIT(1)) 1377 #define EXTMEM_RECORD_DISABLE_G0CB_DECRYPT_M (BIT(1)) 1378 #define EXTMEM_RECORD_DISABLE_G0CB_DECRYPT_V 0x1 1379 #define EXTMEM_RECORD_DISABLE_G0CB_DECRYPT_S 1 1380 /* EXTMEM_RECORD_DISABLE_DB_ENCRYPT : R/W ;bitpos:[0] ;default: 1'b0 ; */ 1381 /*description: Reserved.*/ 1382 #define EXTMEM_RECORD_DISABLE_DB_ENCRYPT (BIT(0)) 1383 #define EXTMEM_RECORD_DISABLE_DB_ENCRYPT_M (BIT(0)) 1384 #define EXTMEM_RECORD_DISABLE_DB_ENCRYPT_V 0x1 1385 #define EXTMEM_RECORD_DISABLE_DB_ENCRYPT_S 0 1386 1387 #define EXTMEM_CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON_REG (DR_REG_EXTMEM_BASE + 0x138) 1388 /* EXTMEM_CLK_FORCE_ON_CRYPT : R/W ;bitpos:[2] ;default: 1'b1 ; */ 1389 /*description: The bit is used to close clock gating of external memory encrypt 1390 and decrypt clock. 1: close gating 0: open clock gating.*/ 1391 #define EXTMEM_CLK_FORCE_ON_CRYPT (BIT(2)) 1392 #define EXTMEM_CLK_FORCE_ON_CRYPT_M (BIT(2)) 1393 #define EXTMEM_CLK_FORCE_ON_CRYPT_V 0x1 1394 #define EXTMEM_CLK_FORCE_ON_CRYPT_S 2 1395 /* EXTMEM_CLK_FORCE_ON_AUTO_CRYPT : R/W ;bitpos:[1] ;default: 1'b1 ; */ 1396 /*description: The bit is used to close clock gating of automatic crypt clock. 1397 1: close gating 0: open clock gating.*/ 1398 #define EXTMEM_CLK_FORCE_ON_AUTO_CRYPT (BIT(1)) 1399 #define EXTMEM_CLK_FORCE_ON_AUTO_CRYPT_M (BIT(1)) 1400 #define EXTMEM_CLK_FORCE_ON_AUTO_CRYPT_V 0x1 1401 #define EXTMEM_CLK_FORCE_ON_AUTO_CRYPT_S 1 1402 /* EXTMEM_CLK_FORCE_ON_MANUAL_CRYPT : R/W ;bitpos:[0] ;default: 1'b1 ; */ 1403 /*description: The bit is used to close clock gating of manual crypt clock. 1404 1: close gating 0: open clock gating.*/ 1405 #define EXTMEM_CLK_FORCE_ON_MANUAL_CRYPT (BIT(0)) 1406 #define EXTMEM_CLK_FORCE_ON_MANUAL_CRYPT_M (BIT(0)) 1407 #define EXTMEM_CLK_FORCE_ON_MANUAL_CRYPT_V 0x1 1408 #define EXTMEM_CLK_FORCE_ON_MANUAL_CRYPT_S 0 1409 1410 #define EXTMEM_CACHE_BRIDGE_ARBITER_CTRL_REG (DR_REG_EXTMEM_BASE + 0x13C) 1411 /* EXTMEM_ALLOC_WB_HOLD_ARBITER : R/W ;bitpos:[0] ;default: 1'b0 ; */ 1412 /*description: Reserved.*/ 1413 #define EXTMEM_ALLOC_WB_HOLD_ARBITER (BIT(0)) 1414 #define EXTMEM_ALLOC_WB_HOLD_ARBITER_M (BIT(0)) 1415 #define EXTMEM_ALLOC_WB_HOLD_ARBITER_V 0x1 1416 #define EXTMEM_ALLOC_WB_HOLD_ARBITER_S 0 1417 1418 #define EXTMEM_CACHE_PRELOAD_INT_CTRL_REG (DR_REG_EXTMEM_BASE + 0x140) 1419 /* EXTMEM_DCACHE_PRELOAD_INT_CLR : WOD ;bitpos:[5] ;default: 1'b0 ; */ 1420 /*description: The bit is used to clear the interrupt by dcache pre-load done.*/ 1421 #define EXTMEM_DCACHE_PRELOAD_INT_CLR (BIT(5)) 1422 #define EXTMEM_DCACHE_PRELOAD_INT_CLR_M (BIT(5)) 1423 #define EXTMEM_DCACHE_PRELOAD_INT_CLR_V 0x1 1424 #define EXTMEM_DCACHE_PRELOAD_INT_CLR_S 5 1425 /* EXTMEM_DCACHE_PRELOAD_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ 1426 /*description: The bit is used to enable the interrupt by dcache pre-load done.*/ 1427 #define EXTMEM_DCACHE_PRELOAD_INT_ENA (BIT(4)) 1428 #define EXTMEM_DCACHE_PRELOAD_INT_ENA_M (BIT(4)) 1429 #define EXTMEM_DCACHE_PRELOAD_INT_ENA_V 0x1 1430 #define EXTMEM_DCACHE_PRELOAD_INT_ENA_S 4 1431 /* EXTMEM_DCACHE_PRELOAD_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ 1432 /*description: The bit is used to indicate the interrupt by dcache pre-load done.*/ 1433 #define EXTMEM_DCACHE_PRELOAD_INT_ST (BIT(3)) 1434 #define EXTMEM_DCACHE_PRELOAD_INT_ST_M (BIT(3)) 1435 #define EXTMEM_DCACHE_PRELOAD_INT_ST_V 0x1 1436 #define EXTMEM_DCACHE_PRELOAD_INT_ST_S 3 1437 /* EXTMEM_ICACHE_PRELOAD_INT_CLR : WOD ;bitpos:[2] ;default: 1'b0 ; */ 1438 /*description: The bit is used to clear the interrupt by icache pre-load done.*/ 1439 #define EXTMEM_ICACHE_PRELOAD_INT_CLR (BIT(2)) 1440 #define EXTMEM_ICACHE_PRELOAD_INT_CLR_M (BIT(2)) 1441 #define EXTMEM_ICACHE_PRELOAD_INT_CLR_V 0x1 1442 #define EXTMEM_ICACHE_PRELOAD_INT_CLR_S 2 1443 /* EXTMEM_ICACHE_PRELOAD_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ 1444 /*description: The bit is used to enable the interrupt by icache pre-load done.*/ 1445 #define EXTMEM_ICACHE_PRELOAD_INT_ENA (BIT(1)) 1446 #define EXTMEM_ICACHE_PRELOAD_INT_ENA_M (BIT(1)) 1447 #define EXTMEM_ICACHE_PRELOAD_INT_ENA_V 0x1 1448 #define EXTMEM_ICACHE_PRELOAD_INT_ENA_S 1 1449 /* EXTMEM_ICACHE_PRELOAD_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ 1450 /*description: The bit is used to indicate the interrupt by icache pre-load done.*/ 1451 #define EXTMEM_ICACHE_PRELOAD_INT_ST (BIT(0)) 1452 #define EXTMEM_ICACHE_PRELOAD_INT_ST_M (BIT(0)) 1453 #define EXTMEM_ICACHE_PRELOAD_INT_ST_V 0x1 1454 #define EXTMEM_ICACHE_PRELOAD_INT_ST_S 0 1455 1456 #define EXTMEM_CACHE_SYNC_INT_CTRL_REG (DR_REG_EXTMEM_BASE + 0x144) 1457 /* EXTMEM_DCACHE_SYNC_INT_CLR : WOD ;bitpos:[5] ;default: 1'b0 ; */ 1458 /*description: The bit is used to clear the interrupt by dcache sync done.*/ 1459 #define EXTMEM_DCACHE_SYNC_INT_CLR (BIT(5)) 1460 #define EXTMEM_DCACHE_SYNC_INT_CLR_M (BIT(5)) 1461 #define EXTMEM_DCACHE_SYNC_INT_CLR_V 0x1 1462 #define EXTMEM_DCACHE_SYNC_INT_CLR_S 5 1463 /* EXTMEM_DCACHE_SYNC_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ 1464 /*description: The bit is used to enable the interrupt by dcache sync done.*/ 1465 #define EXTMEM_DCACHE_SYNC_INT_ENA (BIT(4)) 1466 #define EXTMEM_DCACHE_SYNC_INT_ENA_M (BIT(4)) 1467 #define EXTMEM_DCACHE_SYNC_INT_ENA_V 0x1 1468 #define EXTMEM_DCACHE_SYNC_INT_ENA_S 4 1469 /* EXTMEM_DCACHE_SYNC_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ 1470 /*description: The bit is used to indicate the interrupt by dcache sync done.*/ 1471 #define EXTMEM_DCACHE_SYNC_INT_ST (BIT(3)) 1472 #define EXTMEM_DCACHE_SYNC_INT_ST_M (BIT(3)) 1473 #define EXTMEM_DCACHE_SYNC_INT_ST_V 0x1 1474 #define EXTMEM_DCACHE_SYNC_INT_ST_S 3 1475 /* EXTMEM_ICACHE_SYNC_INT_CLR : WOD ;bitpos:[2] ;default: 1'b0 ; */ 1476 /*description: The bit is used to clear the interrupt by icache sync done.*/ 1477 #define EXTMEM_ICACHE_SYNC_INT_CLR (BIT(2)) 1478 #define EXTMEM_ICACHE_SYNC_INT_CLR_M (BIT(2)) 1479 #define EXTMEM_ICACHE_SYNC_INT_CLR_V 0x1 1480 #define EXTMEM_ICACHE_SYNC_INT_CLR_S 2 1481 /* EXTMEM_ICACHE_SYNC_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ 1482 /*description: The bit is used to enable the interrupt by icache sync done.*/ 1483 #define EXTMEM_ICACHE_SYNC_INT_ENA (BIT(1)) 1484 #define EXTMEM_ICACHE_SYNC_INT_ENA_M (BIT(1)) 1485 #define EXTMEM_ICACHE_SYNC_INT_ENA_V 0x1 1486 #define EXTMEM_ICACHE_SYNC_INT_ENA_S 1 1487 /* EXTMEM_ICACHE_SYNC_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ 1488 /*description: The bit is used to indicate the interrupt by icache sync done.*/ 1489 #define EXTMEM_ICACHE_SYNC_INT_ST (BIT(0)) 1490 #define EXTMEM_ICACHE_SYNC_INT_ST_M (BIT(0)) 1491 #define EXTMEM_ICACHE_SYNC_INT_ST_V 0x1 1492 #define EXTMEM_ICACHE_SYNC_INT_ST_S 0 1493 1494 #define EXTMEM_CACHE_MMU_OWNER_REG (DR_REG_EXTMEM_BASE + 0x148) 1495 /* EXTMEM_CACHE_MMU_OWNER : R/W ;bitpos:[23:0] ;default: 24'h0 ; */ 1496 /*description: The bits are used to specify the owner of MMU.bit0: icache bit1: 1497 dcache bit2: dma bit3: reserved.*/ 1498 #define EXTMEM_CACHE_MMU_OWNER 0x00FFFFFF 1499 #define EXTMEM_CACHE_MMU_OWNER_M ((EXTMEM_CACHE_MMU_OWNER_V)<<(EXTMEM_CACHE_MMU_OWNER_S)) 1500 #define EXTMEM_CACHE_MMU_OWNER_V 0xFFFFFF 1501 #define EXTMEM_CACHE_MMU_OWNER_S 0 1502 1503 #define EXTMEM_CACHE_CONF_MISC_REG (DR_REG_EXTMEM_BASE + 0x14C) 1504 /* EXTMEM_CACHE_TRACE_ENA : R/W ;bitpos:[2] ;default: 1'b1 ; */ 1505 /*description: The bit is used to enable cache trace function.*/ 1506 #define EXTMEM_CACHE_TRACE_ENA (BIT(2)) 1507 #define EXTMEM_CACHE_TRACE_ENA_M (BIT(2)) 1508 #define EXTMEM_CACHE_TRACE_ENA_V 0x1 1509 #define EXTMEM_CACHE_TRACE_ENA_S 2 1510 /* EXTMEM_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT : R/W ;bitpos:[1] ;default: 1'b1 ; */ 1511 /*description: The bit is used to disable checking mmu entry fault by sync operation.*/ 1512 #define EXTMEM_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT (BIT(1)) 1513 #define EXTMEM_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT_M (BIT(1)) 1514 #define EXTMEM_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT_V 0x1 1515 #define EXTMEM_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT_S 1 1516 /* EXTMEM_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT : R/W ;bitpos:[0] ;default: 1'b1 ; */ 1517 /*description: The bit is used to disable checking mmu entry fault by preload operation.*/ 1518 #define EXTMEM_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT (BIT(0)) 1519 #define EXTMEM_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT_M (BIT(0)) 1520 #define EXTMEM_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT_V 0x1 1521 #define EXTMEM_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT_S 0 1522 1523 #define EXTMEM_DCACHE_FREEZE_REG (DR_REG_EXTMEM_BASE + 0x150) 1524 /* EXTMEM_DCACHE_FREEZE_DONE : RO ;bitpos:[2] ;default: 1'b0 ; */ 1525 /*description: The bit is used to indicate dcache freeze success*/ 1526 #define EXTMEM_DCACHE_FREEZE_DONE (BIT(2)) 1527 #define EXTMEM_DCACHE_FREEZE_DONE_M (BIT(2)) 1528 #define EXTMEM_DCACHE_FREEZE_DONE_V 0x1 1529 #define EXTMEM_DCACHE_FREEZE_DONE_S 2 1530 /* EXTMEM_DCACHE_FREEZE_MODE : R/W ;bitpos:[1] ;default: 1'b0 ; */ 1531 /*description: The bit is used to configure freeze mode 0: assert busy if 1532 CPU miss 1: assert hit if CPU miss*/ 1533 #define EXTMEM_DCACHE_FREEZE_MODE (BIT(1)) 1534 #define EXTMEM_DCACHE_FREEZE_MODE_M (BIT(1)) 1535 #define EXTMEM_DCACHE_FREEZE_MODE_V 0x1 1536 #define EXTMEM_DCACHE_FREEZE_MODE_S 1 1537 /* EXTMEM_DCACHE_FREEZE_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ 1538 /*description: The bit is used to enable dcache freeze mode*/ 1539 #define EXTMEM_DCACHE_FREEZE_ENA (BIT(0)) 1540 #define EXTMEM_DCACHE_FREEZE_ENA_M (BIT(0)) 1541 #define EXTMEM_DCACHE_FREEZE_ENA_V 0x1 1542 #define EXTMEM_DCACHE_FREEZE_ENA_S 0 1543 1544 #define EXTMEM_ICACHE_FREEZE_REG (DR_REG_EXTMEM_BASE + 0x154) 1545 /* EXTMEM_ICACHE_FREEZE_DONE : RO ;bitpos:[2] ;default: 1'b0 ; */ 1546 /*description: The bit is used to indicate icache freeze success*/ 1547 #define EXTMEM_ICACHE_FREEZE_DONE (BIT(2)) 1548 #define EXTMEM_ICACHE_FREEZE_DONE_M (BIT(2)) 1549 #define EXTMEM_ICACHE_FREEZE_DONE_V 0x1 1550 #define EXTMEM_ICACHE_FREEZE_DONE_S 2 1551 /* EXTMEM_ICACHE_FREEZE_MODE : R/W ;bitpos:[1] ;default: 1'b0 ; */ 1552 /*description: The bit is used to configure freeze mode 0: assert busy if 1553 CPU miss 1: assert hit if CPU miss*/ 1554 #define EXTMEM_ICACHE_FREEZE_MODE (BIT(1)) 1555 #define EXTMEM_ICACHE_FREEZE_MODE_M (BIT(1)) 1556 #define EXTMEM_ICACHE_FREEZE_MODE_V 0x1 1557 #define EXTMEM_ICACHE_FREEZE_MODE_S 1 1558 /* EXTMEM_ICACHE_FREEZE_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ 1559 /*description: The bit is used to enable icache freeze mode*/ 1560 #define EXTMEM_ICACHE_FREEZE_ENA (BIT(0)) 1561 #define EXTMEM_ICACHE_FREEZE_ENA_M (BIT(0)) 1562 #define EXTMEM_ICACHE_FREEZE_ENA_V 0x1 1563 #define EXTMEM_ICACHE_FREEZE_ENA_S 0 1564 1565 #define EXTMEM_ICACHE_ATOMIC_OPERATE_ENA_REG (DR_REG_EXTMEM_BASE + 0x158) 1566 /* EXTMEM_ICACHE_ATOMIC_OPERATE_ENA : R/W ;bitpos:[0] ;default: 1'b1 ; */ 1567 /*description: The bit is used to activate icache atomic operation protection. 1568 In this case sync/lock operation can not interrupt miss-work. This feature does not work during invalidateAll operation.*/ 1569 #define EXTMEM_ICACHE_ATOMIC_OPERATE_ENA (BIT(0)) 1570 #define EXTMEM_ICACHE_ATOMIC_OPERATE_ENA_M (BIT(0)) 1571 #define EXTMEM_ICACHE_ATOMIC_OPERATE_ENA_V 0x1 1572 #define EXTMEM_ICACHE_ATOMIC_OPERATE_ENA_S 0 1573 1574 #define EXTMEM_DCACHE_ATOMIC_OPERATE_ENA_REG (DR_REG_EXTMEM_BASE + 0x15C) 1575 /* EXTMEM_DCACHE_ATOMIC_OPERATE_ENA : R/W ;bitpos:[0] ;default: 1'b1 ; */ 1576 /*description: The bit is used to activate dcache atomic operation protection. 1577 In this case sync/lock/occupy operation can not interrupt miss-work. This feature does not work during invalidateAll operation.*/ 1578 #define EXTMEM_DCACHE_ATOMIC_OPERATE_ENA (BIT(0)) 1579 #define EXTMEM_DCACHE_ATOMIC_OPERATE_ENA_M (BIT(0)) 1580 #define EXTMEM_DCACHE_ATOMIC_OPERATE_ENA_V 0x1 1581 #define EXTMEM_DCACHE_ATOMIC_OPERATE_ENA_S 0 1582 1583 #define EXTMEM_CACHE_REQUEST_REG (DR_REG_EXTMEM_BASE + 0x160) 1584 /* EXTMEM_CACHE_REQUEST_BYPASS : R/W ;bitpos:[0] ;default: 1'b0 ; */ 1585 /*description: The bit is used to disable request recording which could cause performance issue*/ 1586 #define EXTMEM_CACHE_REQUEST_BYPASS (BIT(0)) 1587 #define EXTMEM_CACHE_REQUEST_BYPASS_M (BIT(0)) 1588 #define EXTMEM_CACHE_REQUEST_BYPASS_V 0x1 1589 #define EXTMEM_CACHE_REQUEST_BYPASS_S 0 1590 1591 #define EXTMEM_CLOCK_GATE_REG (DR_REG_EXTMEM_BASE + 0x164) 1592 /* EXTMEM_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ 1593 /*description: Reserved.*/ 1594 #define EXTMEM_CLK_EN (BIT(0)) 1595 #define EXTMEM_CLK_EN_M (BIT(0)) 1596 #define EXTMEM_CLK_EN_V 0x1 1597 #define EXTMEM_CLK_EN_S 0 1598 1599 #define EXTMEM_DATE_REG (DR_REG_EXTMEM_BASE + 0x3FC) 1600 /* EXTMEM_DATE : R/W ;bitpos:[27:0] ;default: 28'h2003242 ; */ 1601 /*description: Reserved.*/ 1602 #define EXTMEM_DATE 0x0FFFFFFF 1603 #define EXTMEM_DATE_M ((EXTMEM_DATE_V)<<(EXTMEM_DATE_S)) 1604 #define EXTMEM_DATE_V 0xFFFFFFF 1605 #define EXTMEM_DATE_S 0 1606 1607 #ifdef __cplusplus 1608 } 1609 #endif 1610
