1 /* ieee802154_cc2520_regs.h - Registers definition for TI CC2520 */ 2 3 /* 4 * Copyright (c) 2016 Intel Corporation. 5 * 6 * SPDX-License-Identifier: Apache-2.0 7 */ 8 9 #ifndef ZEPHYR_DRIVERS_IEEE802154_IEEE802154_CC2520_REGS_H_ 10 #define ZEPHYR_DRIVERS_IEEE802154_IEEE802154_CC2520_REGS_H_ 11 12 /* Instructions (see chapter 13) */ 13 #define CC2520_INS_SNOP (0x00) 14 #define CC2520_INS_IBUFLD (0x02) 15 #define CC2520_INS_SIBUFEX (0x03) 16 #define CC2520_INS_SSAMPLECCA (0x04) 17 #define CC2520_INS_SRES (0x0F) 18 #define CC2520_INS_MEMRD (0x10) 19 #define CC2520_INS_MEMWR (0x20) 20 #define CC2520_INS_RXBUF (0x30) 21 #define CC2520_INS_RXBUFCP (0x38) 22 #define CC2520_INS_RXBUFMOV (0x32) 23 #define CC2520_INS_TXBUF (0x3A) 24 #define CC2520_INS_TXBUFCP (0x3E) 25 #define CC2520_INS_RANDOM (0x3C) 26 #define CC2520_INS_SXOSCON (0x40) 27 #define CC2520_INS_STXCAL (0x41) 28 #define CC2520_INS_SRXON (0x42) 29 #define CC2520_INS_STXON (0x43) 30 #define CC2520_INS_STXONCCA (0x44) 31 #define CC2520_INS_SRFOFF (0x45) 32 #define CC2520_INS_SXOSCOFF (0x46) 33 #define CC2520_INS_SFLUSHRX (0x47) 34 #define CC2520_INS_SFLUSHTX (0x48) 35 #define CC2520_INS_SACK (0x49) 36 #define CC2520_INS_SACKPEND (0x4A) 37 #define CC2520_INS_SNACK (0x4B) 38 #define CC2520_INS_SRXMASKBITSET (0x4C) 39 #define CC2520_INS_SRXMASKBITCLR (0x4D) 40 #define CC2520_INS_RXMASKAND (0x4E) 41 #define CC2520_INS_RXMASKOR (0x4F) 42 #define CC2520_INS_MEMCP (0x50) 43 #define CC2520_INS_MEMCPR (0x52) 44 #define CC2520_INS_MEMXCP (0x54) 45 #define CC2520_INS_MEMXWR (0x56) 46 #define CC2520_INS_BCLR (0x58) 47 #define CC2520_INS_BSET (0x59) 48 #define CC2520_INS_CTR_UCTR (0x60) 49 #define CC2520_INS_CBCMAC (0x64) 50 #define CC2520_INS_UCBCMAC (0x66) 51 #define CC2520_INS_CCM (0x68) 52 #define CC2520_INS_UCCM (0x6A) 53 #define CC2520_INS_ECB (0x70) 54 #define CC2520_INS_ECBO (0x72) 55 #define CC2520_INS_ECBX (0x74) 56 #define CC2520_INS_INC (0x78) 57 #define CC2520_INS_ABORT (0x7F) 58 #define CC2520_INS_REGRD (0x80) 59 #define CC2520_INS_REGWR (0xC0) 60 61 /* FREG registers (see chapter 28 part 3) */ 62 #define CC2520_FREG_FRMFILT0 (0x00) 63 #define FRMFILT0_FRAME_FILTER_EN BIT(0) 64 #define FRMFILT0_PAN_COORDINATOR BIT(1) 65 #define FRMFILT0_MAX_FRAME_VERSION(_mfv_) (_mfv_ << 2) 66 67 #define CC2520_FREG_FRMFILT1 (0x01) 68 #define FRMFILT1_ACCEPT_FT_0_BEACON BIT(3) 69 #define FRMFILT1_ACCEPT_FT_1_DATA BIT(4) 70 #define FRMFILT1_ACCEPT_FT_2_ACK BIT(5) 71 #define FRMFILT1_ACCEPT_FT_3_MAC_CMD BIT(6) 72 #define FRMFILT1_ACCEPT_ALL (FRMFILT1_ACCEPT_FT_0_BEACON | \ 73 FRMFILT1_ACCEPT_FT_1_DATA | \ 74 FRMFILT1_ACCEPT_FT_2_ACK | \ 75 FRMFILT1_ACCEPT_FT_3_MAC_CMD) 76 77 #define CC2520_FREG_SRCMATCH (0x02) 78 #define SRCMATCH_SRC_MATCH_EN BIT(0) 79 #define SRCMATCH_AUTOPEND BIT(1) 80 #define SRCMATCH_PEND_DATAREQ_ONLY BIT(2) 81 #define SRCMATCH_DEFAULTS (SRCMATCH_SRC_MATCH_EN | \ 82 SRCMATCH_AUTOPEND | \ 83 SRCMATCH_PEND_DATAREQ_ONLY) 84 85 #define CC2520_FREG_SRCSHORTEN0 (0x04) 86 #define CC2520_FREG_SRCSHORTEN1 (0x05) 87 #define CC2520_FREG_SRCSHORTEN2 (0x06) 88 #define CC2520_FREG_SRCEXTEN0 (0x08) 89 #define CC2520_FREG_SRCEXTEN1 (0x09) 90 #define CC2520_FREG_SRCEXTEN2 (0x0A) 91 92 #define CC2520_FREG_FRMCTRL0 (0x0C) 93 #define FRMCTRL0_ENERGY_SCAN BIT(4) 94 #define FRMCTRL0_AUTOACK BIT(5) 95 #define FRMCTRL0_AUTOCRC BIT(6) 96 #define FRMCTRL0_APPEND_DATA_MODE BIT(7) 97 98 #define CC2520_FREG_FRMCTRL1 (0x0D) 99 #define FRMCTRL1_SET_RXENMASK_ON_TX BIT(0) 100 #define FRMCTRL1_IGNORE_TX_UNDERF BIT(1) 101 #define FRMCTRL1_PENDING_OR BIT(2) 102 103 #define CC2520_FREG_RXENABLE0 (0x0E) 104 #define CC2520_FREG_RXENABLE1 (0x0F) 105 #define CC2520_FREG_EXCFLAG0 (0x10) 106 #define EXCFLAG0_RF_IDLE BIT(0) 107 #define EXCFLAG0_TX_FRM_DONE BIT(1) 108 #define EXCFLAG0_TX_ACK_DONE BIT(2) 109 #define EXCFLAG0_TX_UNDERFLOW BIT(3) 110 #define EXCFLAG0_TX_OVERFLOW BIT(4) 111 #define EXCFLAG0_RX_UNDERFLOW BIT(5) 112 #define EXCFLAG0_RX_OVERFLOW BIT(6) 113 #define EXCFLAG0_RXENABLE_ZERO BIT(7) 114 #define EXCFLAG0_RESET_TX_FLAGS ((uint8_t) \ 115 ~(EXCFLAG0_TX_FRM_DONE | \ 116 EXCFLAG0_TX_ACK_DONE | \ 117 EXCFLAG0_TX_UNDERFLOW | \ 118 EXCFLAG0_TX_OVERFLOW)) 119 #define EXCFLAG0_RESET_RX_FLAGS ((uint8_t) \ 120 ~(EXCFLAG0_RX_UNDERFLOW | \ 121 EXCFLAG0_RX_OVERFLOW | \ 122 EXCFLAG0_RXENABLE_ZERO)) 123 124 #define CC2520_FREG_EXCFLAG1 (0x11) 125 #define EXCFLAG1_RX_FRM_DONE BIT(0) 126 #define EXCFLAG1_RX_FRM_ACCEPTED BIT(1) 127 #define EXCFLAG1_SRC_MATCH_DONE BIT(2) 128 #define EXCFLAG1_SRC_MATCH_FOUND BIT(3) 129 #define EXCFLAG1_FIFOP BIT(4) 130 #define EXCFLAG1_SFD BIT(5) 131 #define EXCFLAG1_DPU_DONE_L BIT(6) 132 #define EXCFLAG1_DPU_DONE_H BIT(7) 133 #define EXCFLAG1_RESET_RX_FLAGS ((uint8_t) \ 134 ~(EXCFLAG1_RX_FRM_DONE | \ 135 EXCFLAG1_RX_FRM_ACCEPTED | \ 136 EXCFLAG1_FIFOP)) 137 138 #define CC2520_FREG_EXCFLAG2 (0x12) 139 #define EXCFLAG2_MEMADDR_ERROR BIT(0) 140 #define EXCFLAG2_USAGE_ERROR BIT(1) 141 #define EXCFLAG2_OPERAND_ERROR BIT(2) 142 #define EXCFLAG2_SPI_ERROR BIT(3) 143 #define EXCFLAG2_RF_NO_LOCK BIT(4) 144 #define EXCFLAG2_RX_FRM_ABORTED BIT(5) 145 #define EXCFLAG2_RFBUFMOV_TIMEOUT BIT(6) 146 #define EXCFLAG2_UNUSED BIT(7) 147 148 #define CC2520_FREG_EXMASKA0 (0x13) 149 #define CC2520_FREG_EXMASKA1 (0x14) 150 #define CC2520_FREG_EXMASKA2 (0x15) 151 #define CC2520_FREG_EXMASKB0 (0x18) 152 #define CC2520_FREG_EXMASKB1 (0x19) 153 #define CC2520_FREG_EXMASKB2 (0x1A) 154 #define CC2520_FREG_EXCBINDX0 (0x1C) 155 #define CC2520_FREG_EXCBINDX1 (0x1D) 156 #define CC2520_FREG_EXCBINDY0 (0x1E) 157 #define CC2520_FREG_EXCBINDY1 (0x1F) 158 159 #define CC2520_FREG_GPIOCTRL0 (0x20) 160 #define GPIOCTRL0_CTRL0(_ctrl_) (_ctrl_ & 0x7F) 161 #define GPIOCTRL0_IN0 BIT(7) 162 163 #define CC2520_FREG_GPIOCTRL1 (0x21) 164 #define GPIOCTRL1_CTRL1(_ctrl_) (_ctrl_ & 0x7F) 165 #define GPIOCTRL1_IN1 BIT(7) 166 167 #define CC2520_FREG_GPIOCTRL2 (0x22) 168 #define GPIOCTRL2_CTRL2(_ctrl_) (_ctrl_ & 0x7F) 169 #define GPIOCTRL2_IN2 BIT(7) 170 171 #define CC2520_FREG_GPIOCTRL3 (0x23) 172 #define GPIOCTRL3_CTRL3(_ctrl_) (_ctrl_ & 0x7F) 173 #define GPIOCTRL3_IN3 BIT(7) 174 175 #define CC2520_FREG_GPIOCTRL4 (0x24) 176 #define GPIOCTRL4_CTRL4(_ctrl_) (_ctrl_ & 0x7F) 177 #define GPIOCTRL4_IN4 BIT(7) 178 179 #define CC2520_FREG_GPIOCTRL5 (0x25) 180 #define GPIOCTRL5_CTRL5(_ctrl_) (_ctrl_ & 0x7F) 181 #define GPIOCTRL5_IN5 BIT(7) 182 183 #define CC2520_FREG_GPIOPOLARITY (0x26) 184 #define GPIOPOLARITY_POLARITY0 BIT(0) 185 #define GPIOPOLARITY_POLARITY1 BIT(1) 186 #define GPIOPOLARITY_POLARITY2 BIT(2) 187 #define GPIOPOLARITY_POLARITY3 BIT(3) 188 #define GPIOPOLARITY_POLARITY4 BIT(4) 189 #define GPIOPOLARITY_POLARITY5 BIT(5) 190 191 #define CC2520_FREG_GPIOCTRL (0x28) 192 #define GPIOCTRL_GPIO_PUE0 BIT(0) 193 #define GPIOCTRL_GPIO_PUE1 BIT(1) 194 #define GPIOCTRL_GPIO_PUE2 BIT(2) 195 #define GPIOCTRL_GPIO_PUE3 BIT(3) 196 #define GPIOCTRL_GPIO_PUE4 BIT(4) 197 #define GPIOCTRL_GPIO_PUE5 BIT(5) 198 #define GPIOCTRL_GPIO_ACTRL BIT(6) 199 #define GPIOCTRL_SC BIT(7) 200 201 #define CC2520_FREG_DPUCON (0x2A) 202 #define DPUCON_RXTIMEOUT BIT(0) 203 204 #define CC2520_FREG_DPUSTAT (0x2C) 205 #define DPUSTAT_DPUL_ACTIVE BIT(0) 206 #define DPUSTAT_DPUH_ACTIVE BIT(1) 207 #define DPUSTAT_AUTHSTAT_L BIT(2) 208 #define DPUSTAT_AUTHSTAT_H BIT(3) 209 210 #define CC2520_FREG_FREQCTRL (0x2E) 211 #define FREQCTRL_FREQ(_f_) (_f_ & 0x7F) 212 213 #define CC2520_FREG_FREQTUNE (0x2F) 214 #define FREQTUNE_XOSC32M_TUNE(_xt_) (_xt_ & 0x07) 215 216 #define CC2520_FREG_TXPOWER (0x30) 217 #define CC2520_FREG_TXCTRL (0x31) 218 219 #define CC2520_FREG_FSMSTAT0 (0x32) 220 #define FSMSTAT0_CAL_RUNNING BIT(6) 221 #define FSMSTAT0_CAL_DONE BIT(7) 222 223 #define CC2520_FREG_FSMSTAT1 (0x33) 224 #define FSMSTAT1_RX_ACTIVE BIT(0) 225 #define FSMSTAT1_TX_ACTIVE BIT(1) 226 #define FSMSTAT1_LOCK_STATUS BIT(2) 227 #define FSMSTAT1_CCA_SAMPLED BIT(3) 228 #define FSMSTAT1_CCA BIT(4) 229 #define FSMSTAT1_SFD BIT(5) 230 #define FSMSTAT1_FIFOP BIT(6) 231 #define FSMSTAT1_FIFO BIT(7) 232 233 #define CC2520_FREG_FIFOPCTRL (0x34) 234 #define FIFOPCTRL_FIFOP_THR(_ft_) (_ft_ & 0x7F) 235 236 #define CC2520_FREG_FSMCTRL (0x35) 237 #define FSMCTRL_RX2RX_TIME_OFF BIT(0) 238 #define FSMCTRL_SLOTTED_ACK BIT(1) 239 240 #define CC2520_FREG_CCACTRL0 (0x36) 241 #define CC2520_FREG_CCACTRL1 (0x37) 242 #define CCACTRL1_CCA_HYST(_ch_) (_ch_ & 0x07) 243 #define CCACTRL1_CCA_MODE(_cm_) ((_cm_ << 3) & 0x18) 244 245 #define CC2520_FREG_RSSI (0x38) 246 #define RSSI_RSSI_VALID BIT(0) 247 248 #define CC2520_FREG_RSSISTAT (0x39) 249 #define CC2520_FREG_RXFIRST (0x3C) 250 #define CC2520_FREG_RXFIFOCNT (0x3E) 251 #define CC2520_FREG_TXFIFOCNT (0x3F) 252 253 254 /* SREG registers (see chapter 28 part 3) */ 255 #define CC2520_SREG_CHIPID (0x40) 256 #define CC2520_SREG_VERSION (0x42) 257 258 #define CC2520_SREG_EXTCLOCK (0x44) 259 #define EXTCLOCK_EXT_FREQ(_ef_) (_ef_ & 0x1F) 260 #define EXTCLOCK_EXTCLOCK_EN BIT(5) 261 262 #define CC2520_SREG_MDMCTRL0 (0x46) 263 #define MDMCTRL0_TX_FILTER BIT(0) 264 #define MDMCTRL0_PREAMBLE_LENGTH(_pl_) ((_pl_ << 1) & 0x1E) 265 #define MDMCTRL0_DEMOD_AVG_MODE BIT(5) 266 #define MDMCTRL0_DEM_NUM_ZEROS(_dnz_) ((_dnz_ << 6) & 0xC0) 267 268 #define CC2520_SREG_MDMCTRL1 (0x47) 269 #define MDMCTRL1_CORR_THR(_ct_) (_ct_ & 0x1F) 270 #define MDMCTRL1_CORR_THR_SFD BIT(5) 271 272 #define CC2520_SREG_FREQEST (0x48) 273 274 #define CC2520_SREG_MDMTEST1 (0x49) 275 #define MDMTEST1_MODULATION_MODE BIT(1) 276 #define MDMTEST1_RFC_SNIFF_EN BIT(2) 277 278 #define CC2520_SREG_RXCTRL (0x4A) 279 #define CC2520_SREG_FSCTRL (0x4C) 280 #define CC2520_SREG_FSCAL0 (0x4E) 281 #define CC2520_SREG_FSCAL1 (0x4F) 282 #define CC2520_SREG_FSCAL2 (0x50) 283 #define CC2520_SREG_FSCAL3 (0x51) 284 #define CC2520_SREG_AGCCTRL0 (0x52) 285 #define CC2520_SREG_AGCCTRL1 (0x53) 286 #define CC2520_SREG_AGCCTRL2 (0x54) 287 #define CC2520_SREG_AGCCTRL3 (0x55) 288 #define CC2520_SREG_ADCTEST0 (0x56) 289 #define CC2520_SREG_ADCTEST1 (0x57) 290 #define CC2520_SREG_ADCTEST2 (0x58) 291 #define CC2520_SREG_MDMTEST0 (0x5A) 292 #define CC2520_SREG_DACTEST0 (0x5C) 293 #define CC2520_SREG_DACTEST1 (0x5D) 294 #define CC2520_SREG_ATEST (0x5E) 295 #define CC2520_SREG_DACTEST2 (0x5F) 296 #define CC2520_SREG_PTEST0 (0x60) 297 #define CC2520_SREG_PTEST1 (0x61) 298 #define CC2520_SREG_DPUBIST (0x7A) 299 #define CC2520_SREG_ACTBIST (0x7C) 300 #define CC2520_SREG_RAMBIST (0x7E) 301 302 /* Useful RAM addresses (see chapter 15 part 6) */ 303 #define CC2520_MEM_SHORT_ADDR (0x03F4) 304 #define CC2520_MEM_PAN_ID (0x03F2) 305 #define CC2520_MEM_EXT_ADDR (0x03EA) 306 #define CC2520_MEM_SRCSHORTPENDEN2 (0x03E9) 307 #define CC2520_MEM_SRCSHORTPENDEN1 (0x03E8) 308 #define CC2520_MEM_SRCSHORTPENDEN0 (0x03E7) 309 #define CC2520_MEM_SRCEXTPENDEN2 (0x03E6) 310 #define CC2520_MEM_SRCEXTPENDEN1 (0x03E5) 311 #define CC2520_MEM_SRCEXTPENDEN0 (0x03E4) 312 #define CC2520_MEM_SRCRESINDEX (0x03E3) 313 #define CC2520_MEM_SRCRESMASK2 (0x03E2) 314 #define CC2520_MEM_SRCRESMASK1 (0x03E1) 315 #define CC2520_MEM_SRCRESMASK0 (0x03E0) 316 317 #define CC2520_MEM_START (0x0200) 318 #define CC2520_MEM_DATA (CC2520_MEM_START) 319 #define CC2520_MEM_KEY_POS (0x90) 320 #define CC2520_MEM_KEY (CC2520_MEM_START + \ 321 CC2520_MEM_KEY_POS) 322 #define CC2520_MEM_NONCE_POS (0xa0) 323 #define CC2520_MEM_NONCE (CC2520_MEM_START + \ 324 CC2520_MEM_NONCE_POS) 325 326 /* Default settings (see chapter 28 part 1) */ 327 #define CC2520_TXPOWER_DEFAULT (0x32) 328 #define CC2520_CCACTRL0_DEFAULT (0xF8) 329 #define CC2520_MDMCTRL0_DEFAULT (0x85) 330 #define CC2520_MDMCTRL1_DEFAULT (0x14) 331 #define CC2520_RXCTRL_DEFAULT (0x3F) 332 #define CC2520_FSCTRL_DEFAULT (0x5A) 333 #define CC2520_FSCAL1_DEFAULT (0x2B) 334 #define CC2520_AGCCTRL1_DEFAULT (0x11) 335 #define CC2520_ADCTEST0_DEFAULT (0x10) 336 #define CC2520_ADCTEST1_DEFAULT (0x0E) 337 #define CC2520_ADCTEST2_DEFAULT (0x03) 338 339 /* Status bits (see chapter 13 part 4) */ 340 #define CC2520_STATUS_RX_ACTIVE BIT(0) 341 #define CC2520_STATUS_TX_ACTIVE BIT(1) 342 #define CC2520_STATUS_DPU_L_ACTIVE BIT(2) 343 #define CC2520_STATUS_DPU_H_ACTIVE BIT(3) 344 #define CC2520_STATUS_EXCEPTION_CHANNEL_B BIT(4) 345 #define CC2520_STATUS_EXCEPTION_CHANNEL_A BIT(5) 346 #define CC2520_STATUS_RSSI_VALID BIT(6) 347 #define CC2520_STATUS_XOSC_STABLE_N_RUNNING BIT(7) 348 349 #define CC2520_FCS_CRC_OK (0x80) 350 #define CC2520_FCS_CORRELATION (0x7f) 351 352 #endif /* ZEPHYR_DRIVERS_IEEE802154_IEEE802154_CC2520_REGS_H_ */ 353
