1 /****************************************************************************** 2 * Filename: hw_evtull_h 3 ****************************************************************************** 4 * Copyright (c) 2021 Texas Instruments Incorporated. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * 9 * 1) Redistributions of source code must retain the above copyright notice, 10 * this list of conditions and the following disclaimer. 11 * 12 * 2) Redistributions in binary form must reproduce the above copyright notice, 13 * this list of conditions and the following disclaimer in the documentation 14 * and/or other materials provided with the distribution. 15 * 16 * 3) Neither the name of the copyright holder nor the names of its contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 24 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 ******************************************************************************/ 32 33 #ifndef __HW_EVTULL_H__ 34 #define __HW_EVTULL_H__ 35 36 //***************************************************************************** 37 // 38 // This section defines the register offsets of 39 // EVTULL component 40 // 41 //***************************************************************************** 42 // Description 43 #define EVTULL_O_DESC 0x00000000U 44 45 // Extended Description 46 #define EVTULL_O_DESCEX 0x00000004U 47 48 // Digital test bus control register 49 #define EVTULL_O_DTB 0x00000064U 50 51 // Output Selection for CPU NMI Exception 52 #define EVTULL_O_NMISEL 0x00000400U 53 54 // Output Selection for RTCCPT 55 #define EVTULL_O_RTCCPTSEL 0x00000404U 56 57 // WAKEUP Mask 58 #define EVTULL_O_WKUPMASK 0x00000800U 59 60 //***************************************************************************** 61 // 62 // Register: EVTULL_O_DESC 63 // 64 //***************************************************************************** 65 // Field: [31:16] MODID 66 // 67 // Module identifier used to uniquely identify this IP. 68 #define EVTULL_DESC_MODID_W 16U 69 #define EVTULL_DESC_MODID_M 0xFFFF0000U 70 #define EVTULL_DESC_MODID_S 16U 71 72 // Field: [15:12] STDIPOFF 73 // 74 // Standard IP MMR block offset. Standard IP MMRs are the set of from 75 // aggregated IRQ registers till DTB. 76 // 0: Standard IP MMRs do not exist 77 // 0x1-0xF: Standard IP MMRs begin at offset of (64*STDIPOFF from the base IP 78 // address) 79 #define EVTULL_DESC_STDIPOFF_W 4U 80 #define EVTULL_DESC_STDIPOFF_M 0x0000F000U 81 #define EVTULL_DESC_STDIPOFF_S 12U 82 83 // Field: [11:8] INSTIDX 84 // 85 // IP Instance ID number. If multiple instances of IP exist in the device, this 86 // field can identify the instance number (0-15). 87 #define EVTULL_DESC_INSTIDX_W 4U 88 #define EVTULL_DESC_INSTIDX_M 0x00000F00U 89 #define EVTULL_DESC_INSTIDX_S 8U 90 91 // Field: [7:4] MAJREV 92 // 93 // Major revision of IP (0-15). 94 #define EVTULL_DESC_MAJREV_W 4U 95 #define EVTULL_DESC_MAJREV_M 0x000000F0U 96 #define EVTULL_DESC_MAJREV_S 4U 97 98 // Field: [3:0] MINREV 99 // 100 // Minor revision of IP (0-15). 101 #define EVTULL_DESC_MINREV_W 4U 102 #define EVTULL_DESC_MINREV_M 0x0000000FU 103 #define EVTULL_DESC_MINREV_S 0U 104 105 //***************************************************************************** 106 // 107 // Register: EVTULL_O_DESCEX 108 // 109 //***************************************************************************** 110 // Field: [31:22] IDMA 111 // 112 // Number of DMA input channels 113 #define EVTULL_DESCEX_IDMA_W 10U 114 #define EVTULL_DESCEX_IDMA_M 0xFFC00000U 115 #define EVTULL_DESCEX_IDMA_S 22U 116 117 // Field: [21:17] NDMA 118 // 119 // Number of DMA output channels 120 #define EVTULL_DESCEX_NDMA_W 5U 121 #define EVTULL_DESCEX_NDMA_M 0x003E0000U 122 #define EVTULL_DESCEX_NDMA_S 17U 123 124 // Field: [16] PD 125 // 126 // Power Domain. 127 // 0 : SVT 128 // 1 : ULL 129 #define EVTULL_DESCEX_PD 0x00010000U 130 #define EVTULL_DESCEX_PD_M 0x00010000U 131 #define EVTULL_DESCEX_PD_S 16U 132 133 // Field: [15:8] NSUB 134 // 135 // Number of Subscribers 136 #define EVTULL_DESCEX_NSUB_W 8U 137 #define EVTULL_DESCEX_NSUB_M 0x0000FF00U 138 #define EVTULL_DESCEX_NSUB_S 8U 139 140 // Field: [7:0] NPUB 141 // 142 // Number of Publishers 143 #define EVTULL_DESCEX_NPUB_W 8U 144 #define EVTULL_DESCEX_NPUB_M 0x000000FFU 145 #define EVTULL_DESCEX_NPUB_S 0U 146 147 //***************************************************************************** 148 // 149 // Register: EVTULL_O_DTB 150 // 151 //***************************************************************************** 152 // Field: [0] SEL 153 // 154 // Digital test bus selection mux control 155 // 156 // Non-zero select values output a 16 bit selected group of signals 157 // per value. 158 // ENUMs: 159 // DIS All 16 observation signals are set to zero. 160 #define EVTULL_DTB_SEL 0x00000001U 161 #define EVTULL_DTB_SEL_M 0x00000001U 162 #define EVTULL_DTB_SEL_S 0U 163 #define EVTULL_DTB_SEL_DIS 0x00000000U 164 165 //***************************************************************************** 166 // 167 // Register: EVTULL_O_NMISEL 168 // 169 //***************************************************************************** 170 // Field: [5:0] PUBID 171 // 172 // Read/write selection value. 173 // Writing any other value than values defined by a ENUM may result in 174 // undefined behavior. 175 // ENUMs: 176 // AON_IOC_COMB IOC synchronous combined event, controlled by 177 // IOC:EVTCFG 178 // AON_LPMCMP_IRQ AON LPCMP interrupt, controlled by SYS0:LPCMPCFG 179 // AON_DBG_COMB DebugSS combined interrupt, interrupt flags can be 180 // found here DBGSS:MIS 181 // AON_RTC_COMB AON_RTC event, controlled by the RTC:IMASK setting 182 // AON_CKM_COMB CKMD combined interrupt request, interrupt flags 183 // can be found here CKMD:MIS 184 // AON_PMU_COMB PMU combined interrupt request for BATMON, 185 // interrupt flags can be found here PMUD:EVENT 186 // NONE Always inactive 187 #define EVTULL_NMISEL_PUBID_W 6U 188 #define EVTULL_NMISEL_PUBID_M 0x0000003FU 189 #define EVTULL_NMISEL_PUBID_S 0U 190 #define EVTULL_NMISEL_PUBID_AON_IOC_COMB 0x00000007U 191 #define EVTULL_NMISEL_PUBID_AON_LPMCMP_IRQ 0x00000006U 192 #define EVTULL_NMISEL_PUBID_AON_DBG_COMB 0x00000005U 193 #define EVTULL_NMISEL_PUBID_AON_RTC_COMB 0x00000004U 194 #define EVTULL_NMISEL_PUBID_AON_CKM_COMB 0x00000003U 195 #define EVTULL_NMISEL_PUBID_AON_PMU_COMB 0x00000002U 196 #define EVTULL_NMISEL_PUBID_NONE 0x00000000U 197 198 //***************************************************************************** 199 // 200 // Register: EVTULL_O_RTCCPTSEL 201 // 202 //***************************************************************************** 203 // Field: [5:0] PUBID 204 // 205 // Read/write selection value. 206 // Writing any other value than values defined by a ENUM may result in 207 // undefined behavior. 208 // ENUMs: 209 // AON_IOC_COMB IOC synchronous combined event, controlled by 210 // IOC:EVTCFG 211 // AON_LPMCMP_IRQ AON LPCMP interrupt, controlled by SYS0:LPCMPCFG 212 // AON_DBG_COMB DebugSS combined interrupt, interrupt flags can be 213 // found here DBGSS:MIS 214 // AON_RTC_COMB AON_RTC event, controlled by the RTC:IMASK setting 215 // AON_CKM_COMB CKMD combined interrupt request, interrupt flags 216 // can be found here CKMD:MIS 217 // AON_PMU_COMB PMU combined interrupt request for BATMON, 218 // interrupt flags can be found here PMUD:EVENT 219 // NONE Always inactive 220 #define EVTULL_RTCCPTSEL_PUBID_W 6U 221 #define EVTULL_RTCCPTSEL_PUBID_M 0x0000003FU 222 #define EVTULL_RTCCPTSEL_PUBID_S 0U 223 #define EVTULL_RTCCPTSEL_PUBID_AON_IOC_COMB 0x00000007U 224 #define EVTULL_RTCCPTSEL_PUBID_AON_LPMCMP_IRQ 0x00000006U 225 #define EVTULL_RTCCPTSEL_PUBID_AON_DBG_COMB 0x00000005U 226 #define EVTULL_RTCCPTSEL_PUBID_AON_RTC_COMB 0x00000004U 227 #define EVTULL_RTCCPTSEL_PUBID_AON_CKM_COMB 0x00000003U 228 #define EVTULL_RTCCPTSEL_PUBID_AON_PMU_COMB 0x00000002U 229 #define EVTULL_RTCCPTSEL_PUBID_NONE 0x00000000U 230 231 //***************************************************************************** 232 // 233 // Register: EVTULL_O_WKUPMASK 234 // 235 //***************************************************************************** 236 // Field: [7] AON_IOC_COMB 237 // 238 // Wake-up mask for AON_IOC_COMB. 239 // 0 - Wakeup Disabled 240 // 1 - Wakeup Enabled 241 #define EVTULL_WKUPMASK_AON_IOC_COMB 0x00000080U 242 #define EVTULL_WKUPMASK_AON_IOC_COMB_M 0x00000080U 243 #define EVTULL_WKUPMASK_AON_IOC_COMB_S 7U 244 245 // Field: [6] AON_LPMCMP_IRQ 246 // 247 // Wake-up mask for AON_LPMCMP_IRQ. 248 // 0 - Wakeup Disabled 249 // 1 - Wakeup Enabled 250 #define EVTULL_WKUPMASK_AON_LPMCMP_IRQ 0x00000040U 251 #define EVTULL_WKUPMASK_AON_LPMCMP_IRQ_M 0x00000040U 252 #define EVTULL_WKUPMASK_AON_LPMCMP_IRQ_S 6U 253 254 // Field: [5] AON_DBG_COMB 255 // 256 // Wake-up mask for AON_DBG_COMB. 257 // 0 - Wakeup Disabled 258 // 1 - Wakeup Enabled 259 #define EVTULL_WKUPMASK_AON_DBG_COMB 0x00000020U 260 #define EVTULL_WKUPMASK_AON_DBG_COMB_M 0x00000020U 261 #define EVTULL_WKUPMASK_AON_DBG_COMB_S 5U 262 263 // Field: [4] AON_RTC_COMB 264 // 265 // Wake-up mask for AON_RTC_COMB. 266 // 0 - Wakeup Disabled 267 // 1 - Wakeup Enabled 268 #define EVTULL_WKUPMASK_AON_RTC_COMB 0x00000010U 269 #define EVTULL_WKUPMASK_AON_RTC_COMB_M 0x00000010U 270 #define EVTULL_WKUPMASK_AON_RTC_COMB_S 4U 271 272 // Field: [3] AON_CKM_COMB 273 // 274 // Wake-up mask for AON_CKM_COMB. 275 // 0 - Wakeup Disabled 276 // 1 - Wakeup Enabled 277 #define EVTULL_WKUPMASK_AON_CKM_COMB 0x00000008U 278 #define EVTULL_WKUPMASK_AON_CKM_COMB_M 0x00000008U 279 #define EVTULL_WKUPMASK_AON_CKM_COMB_S 3U 280 281 // Field: [2] AON_PMU_COMB 282 // 283 // Wake-up mask for AON_PMU_COMB. 284 // 0 - Wakeup Disabled 285 // 1 - Wakeup Enabled 286 #define EVTULL_WKUPMASK_AON_PMU_COMB 0x00000004U 287 #define EVTULL_WKUPMASK_AON_PMU_COMB_M 0x00000004U 288 #define EVTULL_WKUPMASK_AON_PMU_COMB_S 2U 289 290 291 #endif // __EVTULL__ 292
