1 /*
2 * Copyright 2022 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 #include "fsl_evtg.h"
9
10 /* Component ID definition, used by tools. */
11 #ifndef FSL_COMPONENT_ID
12 #define FSL_COMPONENT_ID "platform.drivers.evtg"
13 #endif
14
15 /*******************************************************************************
16 * Code
17 ******************************************************************************/
18
19 /*!
20 * brief Initialize EVTG with a user configuration structure.
21 *
22 * param base EVTG base address.
23 * param evtgIndex EVTG instance index.
24 * param psConfig EVTG initial configuration structure pointer.
25 */
EVTG_Init(EVTG_Type * base,evtg_index_t evtgIndex,evtg_config_t * psConfig)26 void EVTG_Init(EVTG_Type *base, evtg_index_t evtgIndex, evtg_config_t *psConfig)
27 {
28 /* Configure Flip-Flop as expected mode. */
29 base->EVTG_INST[(uint8_t)evtgIndex].EVTG_CTRL = EVTG_EVTG_INST_EVTG_CTRL_MODE_SEL((uint16_t)psConfig->flipflopMode);
30
31 if (kEVTG_FFModeJKFF == psConfig->flipflopMode)
32 {
33 /* When FF Mode is configured as JK-FF mode, need EVTG_OUTA feedback to EVTG input and replace one of the four
34 * inputs.*/
35 base->EVTG_INST[(uint8_t)evtgIndex].EVTG_CTRL |=
36 EVTG_EVTG_INST_EVTG_CTRL_FB_OVRD((uint16_t)psConfig->outfdbkOverideinput);
37 }
38
39 if (psConfig->enableFlipflopInitOutput == true)
40 {
41 EVTG_ForceFlipflopInitOutput(base, evtgIndex, psConfig->flipflopInitOutputValue);
42 }
43
44 #if defined(FSL_FEATURE_EVTG_HAS_FORCE_BYPASS_FLIPFLOP) && FSL_FEATURE_EVTG_HAS_FORCE_BYPASS_FLIPFLOP
45 base->EVTG_INST[(uint8_t)evtgIndex].EVTG_CTRL |= EVTG_EVTG_INST_EVTG_CTRL_FORCE_BYPASS(
46 ((uint16_t)psConfig->enableForceBypassFlipFlopAOI1 << 1U) | (uint16_t)psConfig->enableForceBypassFlipFlopAOI0);
47 #endif
48
49 /* Configure EVTG input sync. */
50 base->EVTG_INST[(uint8_t)evtgIndex].EVTG_CTRL |= EVTG_EVTG_INST_EVTG_CTRL_SYNC_CTRL(
51 (((uint16_t)psConfig->enableInputDSync << 3U) | ((uint16_t)psConfig->enableInputCSync << 2U) |
52 ((uint16_t)psConfig->enableInputBSync << 1U) | ((uint16_t)psConfig->enableInputASync)));
53
54 /* Configure AOI0. */
55 base->EVTG_INST[(uint8_t)evtgIndex].EVTG_AOI0_BFT01 =
56 (EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_AC((uint8_t)psConfig->aoi0Config.productTerm0.aInput) |
57 EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_BC((uint8_t)psConfig->aoi0Config.productTerm0.bInput) |
58 EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_CC((uint8_t)psConfig->aoi0Config.productTerm0.cInput) |
59 EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_DC((uint8_t)psConfig->aoi0Config.productTerm0.dInput) |
60 EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_AC((uint8_t)psConfig->aoi0Config.productTerm1.aInput) |
61 EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_BC((uint8_t)psConfig->aoi0Config.productTerm1.bInput) |
62 EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_CC((uint8_t)psConfig->aoi0Config.productTerm1.cInput) |
63 EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_DC((uint8_t)psConfig->aoi0Config.productTerm1.dInput));
64
65 base->EVTG_INST[(uint8_t)evtgIndex].EVTG_AOI0_BFT23 =
66 (EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_AC((uint8_t)psConfig->aoi0Config.productTerm2.aInput) |
67 EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_BC((uint8_t)psConfig->aoi0Config.productTerm2.bInput) |
68 EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_CC((uint8_t)psConfig->aoi0Config.productTerm2.cInput) |
69 EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_DC((uint8_t)psConfig->aoi0Config.productTerm2.dInput) |
70 EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_AC((uint8_t)psConfig->aoi0Config.productTerm3.aInput) |
71 EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_BC((uint8_t)psConfig->aoi0Config.productTerm3.bInput) |
72 EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_CC((uint8_t)psConfig->aoi0Config.productTerm3.cInput) |
73 EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_DC((uint8_t)psConfig->aoi0Config.productTerm3.dInput));
74
75 base->EVTG_INST[(uint8_t)evtgIndex].EVTG_AOI0_FILT |=
76 (EVTG_EVTG_INST_EVTG_AOI0_FILT_FILT_CNT((uint16_t)psConfig->aoi0Config.aoiOutFilterConfig.sampleCount) |
77 EVTG_EVTG_INST_EVTG_AOI0_FILT_FILT_PER(psConfig->aoi0Config.aoiOutFilterConfig.samplePeriod));
78
79 /* Configure AOI1. */
80 base->EVTG_INST[(uint8_t)evtgIndex].EVTG_AOI1_BFT01 =
81 (EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT0_AC((uint8_t)psConfig->aoi1Config.productTerm0.aInput) |
82 EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT0_BC((uint8_t)psConfig->aoi1Config.productTerm0.bInput) |
83 EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT0_CC((uint8_t)psConfig->aoi1Config.productTerm0.cInput) |
84 EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT0_DC((uint8_t)psConfig->aoi1Config.productTerm0.dInput) |
85 EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT1_AC((uint8_t)psConfig->aoi1Config.productTerm1.aInput) |
86 EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT1_BC((uint8_t)psConfig->aoi1Config.productTerm1.bInput) |
87 EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT1_CC((uint8_t)psConfig->aoi1Config.productTerm1.cInput) |
88 EVTG_EVTG_INST_EVTG_AOI1_BFT01_PT1_DC((uint8_t)psConfig->aoi1Config.productTerm1.dInput));
89
90 base->EVTG_INST[(uint8_t)evtgIndex].EVTG_AOI1_BFT23 =
91 (EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT2_AC((uint8_t)psConfig->aoi1Config.productTerm2.aInput) |
92 EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT2_BC((uint8_t)psConfig->aoi1Config.productTerm2.bInput) |
93 EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT2_CC((uint8_t)psConfig->aoi1Config.productTerm2.cInput) |
94 EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT2_DC((uint8_t)psConfig->aoi1Config.productTerm2.dInput) |
95 EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT3_AC((uint8_t)psConfig->aoi1Config.productTerm3.aInput) |
96 EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT3_BC((uint8_t)psConfig->aoi1Config.productTerm3.bInput) |
97 EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT3_CC((uint8_t)psConfig->aoi1Config.productTerm3.cInput) |
98 EVTG_EVTG_INST_EVTG_AOI1_BFT23_PT3_DC((uint8_t)psConfig->aoi1Config.productTerm3.dInput));
99
100 base->EVTG_INST[(uint8_t)evtgIndex].EVTG_AOI1_FILT |=
101 (EVTG_EVTG_INST_EVTG_AOI1_FILT_FILT_CNT((uint16_t)psConfig->aoi1Config.aoiOutFilterConfig.sampleCount) |
102 EVTG_EVTG_INST_EVTG_AOI1_FILT_FILT_PER(psConfig->aoi1Config.aoiOutFilterConfig.samplePeriod));
103 }
104
105 /*!
106 * brief Configure AOI product term by initializing the product term
107 * configuration structure.
108 *
109 * param base EVTG base address.
110 * param evtgIndex EVTG instance index.
111 * param aoiIndex EVTG AOI index. see enum ref evtg_aoi_index_t
112 * param productTerm EVTG AOI product term index.
113 * param psProductTermConfig Pointer to EVTG product term configuration structure.
114 * see ref _evtg_product_term_config
115 */
EVTG_ConfigAOIProductTerm(EVTG_Type * base,evtg_index_t evtgIndex,evtg_aoi_index_t aoiIndex,evtg_aoi_product_term_t productTerm,evtg_aoi_product_term_config_t * psProductTermConfig)116 void EVTG_ConfigAOIProductTerm(EVTG_Type *base,
117 evtg_index_t evtgIndex,
118 evtg_aoi_index_t aoiIndex,
119 evtg_aoi_product_term_t productTerm,
120 evtg_aoi_product_term_config_t *psProductTermConfig)
121 {
122 volatile uint16_t *pu16AOIPT01Config;
123 volatile uint16_t *pu16AOIPT23Config;
124
125 if (kEVTG_AOI0 == aoiIndex)
126 {
127 pu16AOIPT01Config = &base->EVTG_INST[(uint8_t)evtgIndex].EVTG_AOI0_BFT01;
128 pu16AOIPT23Config = &base->EVTG_INST[(uint8_t)evtgIndex].EVTG_AOI0_BFT23;
129 }
130 else
131 {
132 pu16AOIPT01Config = &base->EVTG_INST[(uint8_t)evtgIndex].EVTG_AOI1_BFT01;
133 pu16AOIPT23Config = &base->EVTG_INST[(uint8_t)evtgIndex].EVTG_AOI1_BFT23;
134 }
135
136 if (kEVTG_ProductTerm0 == productTerm)
137 {
138 *pu16AOIPT01Config &=
139 ~(uint16_t)(EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_AC_MASK | EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_BC_MASK |
140 EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_CC_MASK | EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_DC_MASK);
141 *pu16AOIPT01Config |= (EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_AC((uint8_t)psProductTermConfig->aInput) |
142 EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_BC((uint8_t)psProductTermConfig->bInput) |
143 EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_CC((uint8_t)psProductTermConfig->cInput) |
144 EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT0_DC((uint8_t)psProductTermConfig->dInput));
145 }
146 else if (kEVTG_ProductTerm1 == productTerm)
147 {
148 *pu16AOIPT01Config &=
149 ~(uint16_t)(EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_AC_MASK | EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_BC_MASK |
150 EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_CC_MASK | EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_DC_MASK);
151 *pu16AOIPT01Config |= (EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_AC((uint8_t)psProductTermConfig->aInput) |
152 EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_BC((uint8_t)psProductTermConfig->bInput) |
153 EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_CC((uint8_t)psProductTermConfig->cInput) |
154 EVTG_EVTG_INST_EVTG_AOI0_BFT01_PT1_DC((uint8_t)psProductTermConfig->dInput));
155 }
156 else if (kEVTG_ProductTerm2 == productTerm)
157 {
158 *pu16AOIPT23Config &=
159 ~(uint16_t)(EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_AC_MASK | EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_BC_MASK |
160 EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_CC_MASK | EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_DC_MASK);
161 *pu16AOIPT23Config |= (EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_AC((uint8_t)psProductTermConfig->aInput) |
162 EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_BC((uint8_t)psProductTermConfig->bInput) |
163 EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_CC((uint8_t)psProductTermConfig->cInput) |
164 EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT2_DC((uint8_t)psProductTermConfig->dInput));
165 }
166 else
167 {
168 *pu16AOIPT23Config &=
169 ~(uint16_t)(EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_AC_MASK | EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_BC_MASK |
170 EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_CC_MASK | EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_DC_MASK);
171 *pu16AOIPT23Config |= (EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_AC((uint8_t)psProductTermConfig->aInput) |
172 EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_BC((uint8_t)psProductTermConfig->bInput) |
173 EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_CC((uint8_t)psProductTermConfig->cInput) |
174 EVTG_EVTG_INST_EVTG_AOI0_BFT23_PT3_DC((uint8_t)psProductTermConfig->dInput));
175 }
176 }
177
178 /*!
179 * @brief Loads default values to the EVTG configuration structure.
180 *
181 * The purpose of this API is to initialize the configuration structure to default value for @ref EVTG_Init()
182 * to use.
183 * The Flip-Flop can be configured as Bypass mode, RS trigger mode, T-FF mode, D-FF mode, JK-FF mode, Latch mode.
184 * Please check RM INTC chapter for more details.
185 *
186 * @param psConfig EVTG initial configuration structure pointer.
187 * @param flipflopMode EVTG flip flop mode. see @ ref _evtg_flipflop_mode
188 */
EVTG_GetDefaultConfig(evtg_config_t * psConfig,evtg_flipflop_mode_t flipflopMode)189 void EVTG_GetDefaultConfig(evtg_config_t *psConfig, evtg_flipflop_mode_t flipflopMode)
190 {
191 /* Initializes the configure structure to zero. */
192 (void)memset(psConfig, 0, sizeof(evtg_config_t));
193
194 switch (flipflopMode)
195 {
196 case kEVTG_FFModeBypass:
197
198 /*
199 * In this mode, filp-flop will be passed, The two AOI expressions "AOI_0" and "AOI_1"
200 * will be directly assigned to EVTG outputs(EVTG_OUTA and EVTG_OUTB).
201 *
202 * In this mode, user can choose to enable or disable input sync logic and filter function.
203 * Here disable both input sync logic and filter function.
204 */
205 psConfig->flipflopMode = kEVTG_FFModeBypass;
206
207 psConfig->enableInputASync = false;
208 psConfig->enableInputBSync = false;
209 psConfig->enableInputCSync = false;
210 psConfig->enableInputDSync = false;
211
212 break;
213
214 case kEVTG_FFModeRSTrigger:
215
216 /*
217 * In this mode, AOI_0 expression is Reset port, and AOI_1 is Set port. Both are active
218 * high. When "R"(Reset) is high, whatever "S"(Set) is, EVTG_OUTA will be "0". When "R" is
219 * low and "S" is high, EVTG_OUTA will be "1". If both "R" and "S" are low, EVTG output
220 * will be kept. EVTG_OUTB is always the complement of EVTG_OUTA.
221 *
222 * In this mode, user can choose to enable or disable input sync logic and filter function.
223 * Here disable both input sync logic and filter function.
224 */
225 psConfig->flipflopMode = kEVTG_FFModeRSTrigger;
226
227 psConfig->enableInputASync = false;
228 psConfig->enableInputBSync = false;
229 psConfig->enableInputCSync = false;
230 psConfig->enableInputDSync = false;
231
232 break;
233
234 case kEVTG_FFModeTFF:
235
236 /*
237 * In this mode, AOI_0 expression is T port of T-FF, AOI_1 is CLK port. When T assert,
238 * the Q port (EVTG_OUTA) will turnover at the rising edge of "CLK". When T dis-assert,
239 * Q(EVTG_OUTA) will be kept. EVTG_OUTB is always the complement of EVTG_OUTA.
240 *
241 * In this mode, input sync or filter has to be enabled to remove the possible glitch.
242 * Here input sync is enabled, filter is disabled. User could override corresponding fields
243 * depends on the actual user case to choose to enable or disable input sync logic and filter
244 * function.
245 */
246 psConfig->flipflopMode = kEVTG_FFModeTFF;
247
248 psConfig->enableInputASync = true;
249 psConfig->enableInputBSync = true;
250 psConfig->enableInputCSync = true;
251 psConfig->enableInputDSync = true;
252
253 break;
254
255 case kEVTG_FFModeJKFF:
256
257 /*
258 * In general, JK Flip-Flop have four input ports: J, K , Q and CLK(Q is output of Flip-Flop).
259 * And the logical expression is J&~Q | ~K&Q; Here we implement the logic expression by AOI
260 * so that we can reuse the D-FF to implement JK-FF. Suppose we set EVTG input "An" as "J" port,
261 * "Cn" as "K" port, "Dn" as "CLK" port, and "Q" port of FF feed back and override "Bn".
262 * According to the JK logic expression, the AOI_0 expression will be "An&~Bn | Bn&~Cn",
263 * AOI_1 expression will be "Dn".
264 *
265 * In this mode, input sync or filter has to be enabled to remove the possible glitch.
266 * Here input sync is enabled, filter is disabled. User could override corresponding fields
267 * depends on the actual user case to choose to enable or disable input sync logic and filter
268 * function.
269 *
270 * When FF Mode is configured as JK-FF mode, need EVTG_OUTA feedback to EVTG input and replace
271 * one of the four inputs. Here input Bn is replaced, represents which EVTG input(EVTG_OUTA)
272 * is replaced by FF output.
273 */
274 psConfig->flipflopMode = kEVTG_FFModeJKFF;
275 psConfig->outfdbkOverideinput = kEVTG_OutputOverrideInputB;
276
277 psConfig->enableInputASync = true;
278 psConfig->enableInputBSync = true;
279 psConfig->enableInputCSync = true;
280 psConfig->enableInputDSync = true;
281
282 break;
283
284 case kEVTG_FFModeLatch:
285
286 /*
287 * In this mode, AOI_0 expression is D port, AOI_1 is CLK port. Different from D-FF
288 * mode, in Latch mode, D port will be passed only when CLK is high, and output will be
289 * kept when CLK is low. EVTG_OUTB is always the complement of EVTG_OUTA.
290 *
291 * In this mode, input sync or filter has to be enabled to remove the possible glitch.
292 * Here input sync is enabled, filter is disabled. User could override corresponding fields
293 * depends on the actual user case to choose to enable or disable input sync logic and filter
294 * function.
295 */
296 psConfig->flipflopMode = kEVTG_FFModeLatch;
297
298 psConfig->enableInputASync = true;
299 psConfig->enableInputBSync = true;
300 psConfig->enableInputCSync = true;
301 psConfig->enableInputDSync = true;
302
303 break;
304
305 default:
306 assert(false);
307 break;
308 }
309 /* User could choose to enable or disable Flip-flop initial output value. */
310 psConfig->enableFlipflopInitOutput = false;
311 psConfig->flipflopInitOutputValue = kEVTG_FFInitOut0;
312
313 /* User could choose to override this fields to enable filter function. */
314 psConfig->aoi0Config.aoiOutFilterConfig.sampleCount = kEVTG_AOIOutFilterSampleCount3;
315 psConfig->aoi0Config.aoiOutFilterConfig.samplePeriod = 0U;
316
317 psConfig->aoi1Config.aoiOutFilterConfig.sampleCount = kEVTG_AOIOutFilterSampleCount3;
318 psConfig->aoi1Config.aoiOutFilterConfig.samplePeriod = 0U;
319
320 #if defined(FSL_FEATURE_EVTG_HAS_FORCE_BYPASS_FLIPFLOP) && FSL_FEATURE_EVTG_HAS_FORCE_BYPASS_FLIPFLOP
321 psConfig->enableForceBypassFlipFlopAOI0 = false;
322 psConfig->enableForceBypassFlipFlopAOI1 = false;
323 #endif
324
325 /*
326 * For JK-FF Mode, Here we implement the logic expression by AOI so that we can reuse the
327 * D-FF to implement JK-FF. Suppose we set EVTG input "An" as "J" port, "Cn" as "K" port, "Dn"
328 * as "CLK" port, and "Q" port of FF feed back and override "Bn". According to the JK logic
329 * expression, the AOI_0 expression will be "An&~Bn | Bn&~Cn", AOI_1 expression will be "Dn".
330 *
331 * For other FF Mode, the default input here is logical 0. User can configure to produce a logical 0
332 * or 1 or pass the true or complement of the selected event input according to their requirement.
333 */
334 if (kEVTG_FFModeJKFF == flipflopMode)
335 {
336 psConfig->aoi0Config.productTerm0.aInput = kEVTG_InputDirectPass;
337 psConfig->aoi0Config.productTerm0.bInput = kEVTG_InputComplement;
338 psConfig->aoi0Config.productTerm0.cInput = kEVTG_InputLogicOne;
339 psConfig->aoi0Config.productTerm0.dInput = kEVTG_InputLogicOne;
340
341 psConfig->aoi0Config.productTerm1.aInput = kEVTG_InputLogicOne;
342 psConfig->aoi0Config.productTerm1.bInput = kEVTG_InputDirectPass;
343 psConfig->aoi0Config.productTerm1.cInput = kEVTG_InputComplement;
344 psConfig->aoi0Config.productTerm1.dInput = kEVTG_InputLogicOne;
345
346 psConfig->aoi0Config.productTerm2.aInput = kEVTG_InputLogicZero;
347 psConfig->aoi0Config.productTerm2.bInput = kEVTG_InputLogicZero;
348 psConfig->aoi0Config.productTerm2.cInput = kEVTG_InputLogicZero;
349 psConfig->aoi0Config.productTerm2.dInput = kEVTG_InputLogicZero;
350
351 psConfig->aoi0Config.productTerm3.aInput = kEVTG_InputLogicZero;
352 psConfig->aoi0Config.productTerm3.bInput = kEVTG_InputLogicZero;
353 psConfig->aoi0Config.productTerm3.cInput = kEVTG_InputLogicZero;
354 psConfig->aoi0Config.productTerm3.dInput = kEVTG_InputLogicZero;
355
356 psConfig->aoi1Config.productTerm0.aInput = kEVTG_InputLogicOne;
357 psConfig->aoi1Config.productTerm0.bInput = kEVTG_InputLogicOne;
358 psConfig->aoi1Config.productTerm0.cInput = kEVTG_InputLogicOne;
359 psConfig->aoi1Config.productTerm0.dInput = kEVTG_InputDirectPass;
360
361 psConfig->aoi1Config.productTerm1.aInput = kEVTG_InputLogicZero;
362 psConfig->aoi1Config.productTerm1.bInput = kEVTG_InputLogicZero;
363 psConfig->aoi1Config.productTerm1.cInput = kEVTG_InputLogicZero;
364 psConfig->aoi1Config.productTerm1.dInput = kEVTG_InputLogicZero;
365
366 psConfig->aoi1Config.productTerm2.aInput = kEVTG_InputLogicZero;
367 psConfig->aoi1Config.productTerm2.bInput = kEVTG_InputLogicZero;
368 psConfig->aoi1Config.productTerm2.cInput = kEVTG_InputLogicZero;
369 psConfig->aoi1Config.productTerm2.dInput = kEVTG_InputLogicZero;
370
371 psConfig->aoi1Config.productTerm3.aInput = kEVTG_InputLogicZero;
372 psConfig->aoi1Config.productTerm3.bInput = kEVTG_InputLogicZero;
373 psConfig->aoi1Config.productTerm3.cInput = kEVTG_InputLogicZero;
374 psConfig->aoi1Config.productTerm3.dInput = kEVTG_InputLogicZero;
375 }
376 else
377 {
378 psConfig->aoi0Config.productTerm0.aInput = kEVTG_InputLogicZero;
379 psConfig->aoi0Config.productTerm0.bInput = kEVTG_InputLogicZero;
380 psConfig->aoi0Config.productTerm0.cInput = kEVTG_InputLogicZero;
381 psConfig->aoi0Config.productTerm0.dInput = kEVTG_InputLogicZero;
382
383 psConfig->aoi0Config.productTerm1.aInput = kEVTG_InputLogicZero;
384 psConfig->aoi0Config.productTerm1.bInput = kEVTG_InputLogicZero;
385 psConfig->aoi0Config.productTerm1.cInput = kEVTG_InputLogicZero;
386 psConfig->aoi0Config.productTerm1.dInput = kEVTG_InputLogicZero;
387
388 psConfig->aoi0Config.productTerm2.aInput = kEVTG_InputLogicZero;
389 psConfig->aoi0Config.productTerm2.bInput = kEVTG_InputLogicZero;
390 psConfig->aoi0Config.productTerm2.cInput = kEVTG_InputLogicZero;
391 psConfig->aoi0Config.productTerm2.dInput = kEVTG_InputLogicZero;
392
393 psConfig->aoi0Config.productTerm3.aInput = kEVTG_InputLogicZero;
394 psConfig->aoi0Config.productTerm3.bInput = kEVTG_InputLogicZero;
395 psConfig->aoi0Config.productTerm3.cInput = kEVTG_InputLogicZero;
396 psConfig->aoi0Config.productTerm3.dInput = kEVTG_InputLogicZero;
397
398 psConfig->aoi1Config.productTerm0.aInput = kEVTG_InputLogicZero;
399 psConfig->aoi1Config.productTerm0.bInput = kEVTG_InputLogicZero;
400 psConfig->aoi1Config.productTerm0.cInput = kEVTG_InputLogicZero;
401 psConfig->aoi1Config.productTerm0.dInput = kEVTG_InputLogicZero;
402
403 psConfig->aoi1Config.productTerm1.aInput = kEVTG_InputLogicZero;
404 psConfig->aoi1Config.productTerm1.bInput = kEVTG_InputLogicZero;
405 psConfig->aoi1Config.productTerm1.cInput = kEVTG_InputLogicZero;
406 psConfig->aoi1Config.productTerm1.dInput = kEVTG_InputLogicZero;
407
408 psConfig->aoi1Config.productTerm2.aInput = kEVTG_InputLogicZero;
409 psConfig->aoi1Config.productTerm2.bInput = kEVTG_InputLogicZero;
410 psConfig->aoi1Config.productTerm2.cInput = kEVTG_InputLogicZero;
411 psConfig->aoi1Config.productTerm2.dInput = kEVTG_InputLogicZero;
412
413 psConfig->aoi1Config.productTerm3.aInput = kEVTG_InputLogicZero;
414 psConfig->aoi1Config.productTerm3.bInput = kEVTG_InputLogicZero;
415 psConfig->aoi1Config.productTerm3.cInput = kEVTG_InputLogicZero;
416 psConfig->aoi1Config.productTerm3.dInput = kEVTG_InputLogicZero;
417 }
418 }
419
