1 /*
2 ** ###################################################################
3 ** Processors: RV32M1_ri5cy
4 ** RV32M1_ri5cy
5 **
6 ** Compilers: Keil ARM C/C++ Compiler
7 ** GNU C Compiler
8 ** IAR ANSI C/C++ Compiler for ARM
9 ** MCUXpresso Compiler
10 **
11 ** Reference manual: RV32M1 Series Reference Manual, Rev. 1 , 8/10/2018
12 ** Version: rev. 1.0, 2018-10-02
13 ** Build: b180926
14 **
15 ** Abstract:
16 ** Provides a system configuration function and a global variable that
17 ** contains the system frequency. It configures the device and initializes
18 ** the oscillator (PLL) that is part of the microcontroller device.
19 **
20 ** Copyright 2016 Freescale Semiconductor, Inc.
21 ** Copyright 2016-2018 NXP
22 ** All rights reserved.
23 **
24 ** SPDX-License-Identifier: BSD-3-Clause
25 **
26 ** http: www.nxp.com
27 ** mail: support@nxp.com
28 **
29 ** Revisions:
30 ** - rev. 1.0 (2018-10-02)
31 ** Initial version.
32 **
33 ** ###################################################################
34 */
35
36 /*!
37 * @file RV32M1_ri5cy
38 * @version 1.0
39 * @date 2018-10-02
40 * @brief Device specific configuration file for RV32M1_ri5cy
41 * (implementation file)
42 *
43 * Provides a system configuration function and a global variable that contains
44 * the system frequency. It configures the device and initializes the oscillator
45 * (PLL) that is part of the microcontroller device.
46 */
47
48 #include <stdint.h>
49 #include "fsl_device_registers.h"
50 #include "fsl_common.h"
51
52 typedef void (*irq_handler_t)(void);
53
54 extern void DMA0_0_4_8_12_DriverIRQHandler(void);
55 extern void DMA0_1_5_9_13_DriverIRQHandler(void);
56 extern void DMA0_2_6_10_14_DriverIRQHandler(void);
57 extern void DMA0_3_7_11_15_DriverIRQHandler(void);
58 extern void DMA0_Error_IRQHandler(void);
59 extern void CMC0_IRQHandler(void);
60 extern void EWM_IRQHandler(void);
61 extern void FTFE_Command_Complete_IRQHandler(void);
62 extern void FTFE_Read_Collision_IRQHandler(void);
63 extern void LLWU0_IRQHandler(void);
64 extern void MUA_IRQHandler(void);
65 extern void SPM_IRQHandler(void);
66 extern void WDOG0_IRQHandler(void);
67 extern void SCG_IRQHandler(void);
68 extern void LPIT0_IRQHandler(void);
69 extern void RTC_IRQHandler(void);
70 extern void LPTMR0_IRQHandler(void);
71 extern void LPTMR1_IRQHandler(void);
72 extern void TPM0_IRQHandler(void);
73 extern void TPM1_IRQHandler(void);
74 extern void TPM2_IRQHandler(void);
75 extern void EMVSIM0_IRQHandler(void);
76 extern void FLEXIO0_DriverIRQHandler(void);
77 extern void LPI2C0_DriverIRQHandler(void);
78 extern void LPI2C1_DriverIRQHandler(void);
79 extern void LPI2C2_DriverIRQHandler(void);
80 extern void I2S0_DriverIRQHandler(void);
81 extern void USDHC0_DriverIRQHandler(void);
82 extern void LPSPI0_DriverIRQHandler(void);
83 extern void LPSPI1_DriverIRQHandler(void);
84 extern void LPSPI2_DriverIRQHandler(void);
85 extern void LPUART0_DriverIRQHandler(void);
86 extern void LPUART1_DriverIRQHandler(void);
87 extern void LPUART2_DriverIRQHandler(void);
88 extern void USB0_IRQHandler(void);
89 extern void PORTA_IRQHandler(void);
90 extern void PORTB_IRQHandler(void);
91 extern void PORTC_IRQHandler(void);
92 extern void PORTD_IRQHandler(void);
93 extern void ADC0_IRQHandler(void);
94 extern void LPCMP0_IRQHandler(void);
95 extern void LPDAC0_IRQHandler(void);
96 extern void CAU3_Task_Complete_IRQHandler(void);
97 extern void CAU3_Security_Violation_IRQHandler(void);
98 extern void TRNG_IRQHandler(void);
99 extern void LPIT1_IRQHandler(void);
100 extern void LPTMR2_IRQHandler(void);
101 extern void TPM3_IRQHandler(void);
102 extern void LPI2C3_DriverIRQHandler(void);
103 extern void LPSPI3_DriverIRQHandler(void);
104 extern void LPUART3_DriverIRQHandler(void);
105 extern void PORTE_IRQHandler(void);
106 extern void LPCMP1_IRQHandler(void);
107 extern void RF0_0_IRQHandler(void);
108 extern void RF0_1_IRQHandler(void);
109 extern void INTMUX0_0_DriverIRQHandler(void);
110 extern void INTMUX0_1_DriverIRQHandler(void);
111 extern void INTMUX0_2_DriverIRQHandler(void);
112 extern void INTMUX0_3_DriverIRQHandler(void);
113 extern void INTMUX0_4_DriverIRQHandler(void);
114 extern void INTMUX0_5_DriverIRQHandler(void);
115 extern void INTMUX0_6_DriverIRQHandler(void);
116 extern void INTMUX0_7_DriverIRQHandler(void);
117 extern void INTMUX0_8_DriverIRQHandler(void);
118 extern void DMA0_0_4_8_12_IRQHandler(void);
119 extern void DMA0_1_5_9_13_IRQHandler(void);
120 extern void DMA0_2_6_10_14_IRQHandler(void);
121 extern void DMA0_3_7_11_15_IRQHandler(void);
122 extern void FLEXIO0_IRQHandler(void);
123 extern void LPI2C0_IRQHandler(void);
124 extern void LPI2C1_IRQHandler(void);
125 extern void LPI2C2_IRQHandler(void);
126 extern void I2S0_IRQHandler(void);
127 extern void USDHC0_IRQHandler(void);
128 extern void LPSPI0_IRQHandler(void);
129 extern void LPSPI1_IRQHandler(void);
130 extern void LPSPI2_IRQHandler(void);
131 extern void LPUART0_IRQHandler(void);
132 extern void LPUART1_IRQHandler(void);
133 extern void LPUART2_IRQHandler(void);
134 extern void LPI2C3_IRQHandler(void);
135 extern void LPSPI3_IRQHandler(void);
136 extern void LPUART3_IRQHandler(void);
137 extern void INTMUX0_0_IRQHandler(void);
138 extern void INTMUX0_1_IRQHandler(void);
139 extern void INTMUX0_2_IRQHandler(void);
140 extern void INTMUX0_3_IRQHandler(void);
141 extern void INTMUX0_4_IRQHandler(void);
142 extern void INTMUX0_5_IRQHandler(void);
143 extern void INTMUX0_6_IRQHandler(void);
144 extern void INTMUX0_7_IRQHandler(void);
145
146 /* ----------------------------------------------------------------------------
147 -- Core clock
148 ---------------------------------------------------------------------------- */
149 uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
150
151 extern uint32_t __etext;
152 extern uint32_t __data_start__;
153 extern uint32_t __data_end__;
154
155 extern uint32_t __bss_start__;
156 extern uint32_t __bss_end__;
157
copy_section(uint32_t * p_load,uint32_t * p_vma,uint32_t * p_vma_end)158 static void copy_section(uint32_t * p_load, uint32_t * p_vma, uint32_t * p_vma_end)
159 {
160 while(p_vma <= p_vma_end)
161 {
162 *p_vma = *p_load;
163 ++p_load;
164 ++p_vma;
165 }
166 }
167
zero_section(uint32_t * start,uint32_t * end)168 static void zero_section(uint32_t * start, uint32_t * end)
169 {
170 uint32_t * p_zero = start;
171
172 while(p_zero <= end)
173 {
174 *p_zero = 0;
175 ++p_zero;
176 }
177 }
178
179 #define DEFINE_IRQ_HANDLER(irq_handler, driver_irq_handler) \
180 void __attribute__((weak)) irq_handler(void) { driver_irq_handler();}
181
182 #define DEFINE_DEFAULT_IRQ_HANDLER(irq_handler) void irq_handler() __attribute__((weak, alias("DefaultIRQHandler")))
183
184 DEFINE_DEFAULT_IRQ_HANDLER(DMA0_0_4_8_12_DriverIRQHandler);
185 DEFINE_DEFAULT_IRQ_HANDLER(DMA0_1_5_9_13_DriverIRQHandler);
186 DEFINE_DEFAULT_IRQ_HANDLER(DMA0_2_6_10_14_DriverIRQHandler);
187 DEFINE_DEFAULT_IRQ_HANDLER(DMA0_3_7_11_15_DriverIRQHandler);
188 DEFINE_DEFAULT_IRQ_HANDLER(DMA0_Error_IRQHandler);
189 DEFINE_DEFAULT_IRQ_HANDLER(CMC0_IRQHandler);
190 DEFINE_DEFAULT_IRQ_HANDLER(EWM_IRQHandler);
191 DEFINE_DEFAULT_IRQ_HANDLER(FTFE_Command_Complete_IRQHandler);
192 DEFINE_DEFAULT_IRQ_HANDLER(FTFE_Read_Collision_IRQHandler);
193 DEFINE_DEFAULT_IRQ_HANDLER(LLWU0_IRQHandler);
194 DEFINE_DEFAULT_IRQ_HANDLER(MUA_IRQHandler);
195 DEFINE_DEFAULT_IRQ_HANDLER(SPM_IRQHandler);
196 DEFINE_DEFAULT_IRQ_HANDLER(WDOG0_IRQHandler);
197 DEFINE_DEFAULT_IRQ_HANDLER(SCG_IRQHandler);
198 DEFINE_DEFAULT_IRQ_HANDLER(LPIT0_IRQHandler);
199 DEFINE_DEFAULT_IRQ_HANDLER(RTC_IRQHandler);
200 DEFINE_DEFAULT_IRQ_HANDLER(LPTMR0_IRQHandler);
201 DEFINE_DEFAULT_IRQ_HANDLER(LPTMR1_IRQHandler);
202 DEFINE_DEFAULT_IRQ_HANDLER(TPM0_IRQHandler);
203 DEFINE_DEFAULT_IRQ_HANDLER(TPM1_IRQHandler);
204 DEFINE_DEFAULT_IRQ_HANDLER(TPM2_IRQHandler);
205 DEFINE_DEFAULT_IRQ_HANDLER(EMVSIM0_IRQHandler);
206 DEFINE_DEFAULT_IRQ_HANDLER(FLEXIO0_DriverIRQHandler);
207 DEFINE_DEFAULT_IRQ_HANDLER(LPI2C0_DriverIRQHandler);
208 DEFINE_DEFAULT_IRQ_HANDLER(LPI2C1_DriverIRQHandler);
209 DEFINE_DEFAULT_IRQ_HANDLER(LPI2C2_DriverIRQHandler);
210 DEFINE_DEFAULT_IRQ_HANDLER(I2S0_DriverIRQHandler);
211 DEFINE_DEFAULT_IRQ_HANDLER(USDHC0_DriverIRQHandler);
212 DEFINE_DEFAULT_IRQ_HANDLER(LPSPI0_DriverIRQHandler);
213 DEFINE_DEFAULT_IRQ_HANDLER(LPSPI1_DriverIRQHandler);
214 DEFINE_DEFAULT_IRQ_HANDLER(LPSPI2_DriverIRQHandler);
215 DEFINE_DEFAULT_IRQ_HANDLER(LPUART0_DriverIRQHandler);
216 DEFINE_DEFAULT_IRQ_HANDLER(LPUART1_DriverIRQHandler);
217 DEFINE_DEFAULT_IRQ_HANDLER(LPUART2_DriverIRQHandler);
218 DEFINE_DEFAULT_IRQ_HANDLER(USB0_IRQHandler);
219 DEFINE_DEFAULT_IRQ_HANDLER(PORTA_IRQHandler);
220 DEFINE_DEFAULT_IRQ_HANDLER(PORTB_IRQHandler);
221 DEFINE_DEFAULT_IRQ_HANDLER(PORTC_IRQHandler);
222 DEFINE_DEFAULT_IRQ_HANDLER(PORTD_IRQHandler);
223 DEFINE_DEFAULT_IRQ_HANDLER(ADC0_IRQHandler);
224 DEFINE_DEFAULT_IRQ_HANDLER(LPCMP0_IRQHandler);
225 DEFINE_DEFAULT_IRQ_HANDLER(LPDAC0_IRQHandler);
226 DEFINE_DEFAULT_IRQ_HANDLER(CAU3_Task_Complete_IRQHandler);
227 DEFINE_DEFAULT_IRQ_HANDLER(CAU3_Security_Violation_IRQHandler);
228 DEFINE_DEFAULT_IRQ_HANDLER(TRNG_IRQHandler);
229 DEFINE_DEFAULT_IRQ_HANDLER(LPIT1_IRQHandler);
230 DEFINE_DEFAULT_IRQ_HANDLER(LPTMR2_IRQHandler);
231 DEFINE_DEFAULT_IRQ_HANDLER(TPM3_IRQHandler);
232 DEFINE_DEFAULT_IRQ_HANDLER(LPI2C3_DriverIRQHandler);
233 DEFINE_DEFAULT_IRQ_HANDLER(LPSPI3_DriverIRQHandler);
234 DEFINE_DEFAULT_IRQ_HANDLER(LPUART3_DriverIRQHandler);
235 DEFINE_DEFAULT_IRQ_HANDLER(PORTE_IRQHandler);
236 DEFINE_DEFAULT_IRQ_HANDLER(LPCMP1_IRQHandler);
237 DEFINE_DEFAULT_IRQ_HANDLER(RF0_0_IRQHandler);
238 DEFINE_DEFAULT_IRQ_HANDLER(RF0_1_IRQHandler);
239 DEFINE_DEFAULT_IRQ_HANDLER(INTMUX0_0_DriverIRQHandler);
240 DEFINE_DEFAULT_IRQ_HANDLER(INTMUX0_1_DriverIRQHandler);
241 DEFINE_DEFAULT_IRQ_HANDLER(INTMUX0_2_DriverIRQHandler);
242 DEFINE_DEFAULT_IRQ_HANDLER(INTMUX0_3_DriverIRQHandler);
243 DEFINE_DEFAULT_IRQ_HANDLER(INTMUX0_4_DriverIRQHandler);
244 DEFINE_DEFAULT_IRQ_HANDLER(INTMUX0_5_DriverIRQHandler);
245 DEFINE_DEFAULT_IRQ_HANDLER(INTMUX0_6_DriverIRQHandler);
246 DEFINE_DEFAULT_IRQ_HANDLER(INTMUX0_7_DriverIRQHandler);
247 DEFINE_DEFAULT_IRQ_HANDLER(INTMUX0_8_DriverIRQHandler);
248
249 DEFINE_IRQ_HANDLER(DMA0_0_4_8_12_IRQHandler, DMA0_0_4_8_12_DriverIRQHandler);
250 DEFINE_IRQ_HANDLER(DMA0_1_5_9_13_IRQHandler, DMA0_1_5_9_13_DriverIRQHandler);
251 DEFINE_IRQ_HANDLER(DMA0_2_6_10_14_IRQHandler, DMA0_2_6_10_14_DriverIRQHandler);
252 DEFINE_IRQ_HANDLER(DMA0_3_7_11_15_IRQHandler, DMA0_3_7_11_15_DriverIRQHandler);
253 DEFINE_IRQ_HANDLER(FLEXIO0_IRQHandler, FLEXIO0_DriverIRQHandler);
254 DEFINE_IRQ_HANDLER(LPI2C0_IRQHandler, LPI2C0_DriverIRQHandler);
255 DEFINE_IRQ_HANDLER(LPI2C1_IRQHandler, LPI2C1_DriverIRQHandler);
256 DEFINE_IRQ_HANDLER(LPI2C2_IRQHandler, LPI2C2_DriverIRQHandler);
257 DEFINE_IRQ_HANDLER(I2S0_IRQHandler, I2S0_DriverIRQHandler);
258 DEFINE_IRQ_HANDLER(USDHC0_IRQHandler, USDHC0_DriverIRQHandler);
259 DEFINE_IRQ_HANDLER(LPSPI0_IRQHandler, LPSPI0_DriverIRQHandler);
260 DEFINE_IRQ_HANDLER(LPSPI1_IRQHandler, LPSPI1_DriverIRQHandler);
261 DEFINE_IRQ_HANDLER(LPSPI2_IRQHandler, LPSPI2_DriverIRQHandler);
262 DEFINE_IRQ_HANDLER(LPUART0_IRQHandler, LPUART0_DriverIRQHandler);
263 DEFINE_IRQ_HANDLER(LPUART1_IRQHandler, LPUART1_DriverIRQHandler);
264 DEFINE_IRQ_HANDLER(LPUART2_IRQHandler, LPUART2_DriverIRQHandler);
265 DEFINE_IRQ_HANDLER(LPI2C3_IRQHandler, LPI2C3_DriverIRQHandler);
266 DEFINE_IRQ_HANDLER(LPSPI3_IRQHandler, LPSPI3_DriverIRQHandler);
267 DEFINE_IRQ_HANDLER(LPUART3_IRQHandler, LPUART3_DriverIRQHandler);
268 DEFINE_IRQ_HANDLER(INTMUX0_0_IRQHandler, INTMUX0_0_DriverIRQHandler);
269 DEFINE_IRQ_HANDLER(INTMUX0_1_IRQHandler, INTMUX0_1_DriverIRQHandler);
270 DEFINE_IRQ_HANDLER(INTMUX0_2_IRQHandler, INTMUX0_2_DriverIRQHandler);
271 DEFINE_IRQ_HANDLER(INTMUX0_3_IRQHandler, INTMUX0_3_DriverIRQHandler);
272 DEFINE_IRQ_HANDLER(INTMUX0_4_IRQHandler, INTMUX0_4_DriverIRQHandler);
273 DEFINE_IRQ_HANDLER(INTMUX0_5_IRQHandler, INTMUX0_5_DriverIRQHandler);
274 DEFINE_IRQ_HANDLER(INTMUX0_6_IRQHandler, INTMUX0_6_DriverIRQHandler);
275 DEFINE_IRQ_HANDLER(INTMUX0_7_IRQHandler, INTMUX0_7_DriverIRQHandler);
276
277 __attribute__((section("user_vectors"))) const irq_handler_t isrTable[] =
278 {
279 DMA0_0_4_8_12_IRQHandler,
280 DMA0_1_5_9_13_IRQHandler,
281 DMA0_2_6_10_14_IRQHandler,
282 DMA0_3_7_11_15_IRQHandler,
283 DMA0_Error_IRQHandler,
284 CMC0_IRQHandler,
285 MUA_IRQHandler,
286 USB0_IRQHandler,
287 USDHC0_IRQHandler,
288 I2S0_IRQHandler,
289 FLEXIO0_IRQHandler,
290 EMVSIM0_IRQHandler,
291 LPIT0_IRQHandler,
292 LPSPI0_IRQHandler,
293 LPSPI1_IRQHandler,
294 LPI2C0_IRQHandler,
295 LPI2C1_IRQHandler,
296 LPUART0_IRQHandler,
297 PORTA_IRQHandler,
298 TPM0_IRQHandler,
299 LPDAC0_IRQHandler,
300 ADC0_IRQHandler,
301 LPCMP0_IRQHandler,
302 RTC_IRQHandler,
303 INTMUX0_0_IRQHandler,
304 INTMUX0_1_IRQHandler,
305 INTMUX0_2_IRQHandler,
306 INTMUX0_3_IRQHandler,
307 INTMUX0_4_IRQHandler,
308 INTMUX0_5_IRQHandler,
309 INTMUX0_6_IRQHandler,
310 INTMUX0_7_IRQHandler,
311 EWM_IRQHandler,
312 FTFE_Command_Complete_IRQHandler,
313 FTFE_Read_Collision_IRQHandler,
314 LLWU0_IRQHandler,
315 SPM_IRQHandler,
316 WDOG0_IRQHandler,
317 SCG_IRQHandler,
318 LPTMR0_IRQHandler,
319 LPTMR1_IRQHandler,
320 TPM1_IRQHandler,
321 TPM2_IRQHandler,
322 LPI2C2_IRQHandler,
323 LPSPI2_IRQHandler,
324 LPUART1_IRQHandler,
325 LPUART2_IRQHandler,
326 PORTB_IRQHandler,
327 PORTC_IRQHandler,
328 PORTD_IRQHandler,
329 CAU3_Task_Complete_IRQHandler,
330 CAU3_Security_Violation_IRQHandler,
331 TRNG_IRQHandler,
332 LPIT1_IRQHandler,
333 LPTMR2_IRQHandler,
334 TPM3_IRQHandler,
335 LPI2C3_IRQHandler,
336 LPSPI3_IRQHandler,
337 LPUART3_IRQHandler,
338 PORTE_IRQHandler,
339 LPCMP1_IRQHandler,
340 RF0_0_IRQHandler,
341 RF0_1_IRQHandler,
342 };
343
344 extern uint32_t __VECTOR_TABLE[];
345
346 static uint32_t irqNesting = 0;
347
DefaultIRQHandler(void)348 static void DefaultIRQHandler(void)
349 {
350 for (;;)
351 {
352 }
353 }
354
355 /* ----------------------------------------------------------------------------
356 -- SystemInit()
357 ---------------------------------------------------------------------------- */
358
SystemInit(void)359 void SystemInit (void) {
360 #if (DISABLE_WDOG)
361 WDOG0->CNT = 0xD928C520U;
362 WDOG0->TOVAL = 0xFFFF;
363 WDOG0->CS = (uint32_t) ((WDOG0->CS) & ~WDOG_CS_EN_MASK) | WDOG_CS_UPDATE_MASK;
364 #endif /* (DISABLE_WDOG) */
365
366 SystemInitHook();
367
368 copy_section(&__etext, &__data_start__, &__data_end__);
369 zero_section(&__bss_start__, &__bss_end__);
370
371 /* Setup the vector table address. */
372 irqNesting = 0;
373
374 __ASM volatile("csrw 0x305, %0" :: "r"((uint32_t)__VECTOR_TABLE)); /* MTVEC */
375 __ASM volatile("csrw 0x005, %0" :: "r"((uint32_t)__VECTOR_TABLE)); /* UTVEC */
376
377 /* Clear all pending flags. */
378 EVENT_UNIT->INTPTPENDCLEAR = 0xFFFFFFFF;
379 EVENT_UNIT->EVTPENDCLEAR = 0xFFFFFFFF;
380 /* Set all interrupt as secure interrupt. */
381 EVENT_UNIT->INTPTSECURE = 0xFFFFFFFF;
382 }
383
384 /* ----------------------------------------------------------------------------
385 -- SystemCoreClockUpdate()
386 ---------------------------------------------------------------------------- */
387
SystemCoreClockUpdate(void)388 void SystemCoreClockUpdate (void) {
389
390 uint32_t SCGOUTClock; /* Variable to store output clock frequency of the SCG module */
391 uint16_t Divider;
392 Divider = ((SCG->CSR & SCG_CSR_DIVCORE_MASK) >> SCG_CSR_DIVCORE_SHIFT) + 1;
393
394 switch ((SCG->CSR & SCG_CSR_SCS_MASK) >> SCG_CSR_SCS_SHIFT) {
395 case 0x1:
396 /* System OSC */
397 SCGOUTClock = CPU_XTAL_CLK_HZ;
398 break;
399 case 0x2:
400 /* Slow IRC */
401 SCGOUTClock = (((SCG->SIRCCFG & SCG_SIRCCFG_RANGE_MASK) >> SCG_SIRCCFG_RANGE_SHIFT) ? 8000000 : 2000000);
402 break;
403 case 0x3:
404 /* Fast IRC */
405 SCGOUTClock = 48000000 + ((SCG->FIRCCFG & SCG_FIRCCFG_RANGE_MASK) >> SCG_FIRCCFG_RANGE_SHIFT) * 4000000;
406 break;
407 case 0x5:
408 /* Low Power FLL */
409 SCGOUTClock = 48000000 + ((SCG->LPFLLCFG & SCG_LPFLLCFG_FSEL_MASK) >> SCG_LPFLLCFG_FSEL_SHIFT) * 24000000;
410 break;
411 default:
412 return;
413 }
414 SystemCoreClock = (SCGOUTClock / Divider);
415 }
416
417 /* ----------------------------------------------------------------------------
418 -- SystemInitHook()
419 ---------------------------------------------------------------------------- */
420
SystemInitHook(void)421 __attribute__ ((weak)) void SystemInitHook (void) {
422 /* Void implementation of the weak function. */
423 }
424
425 #if defined(__IAR_SYSTEMS_ICC__)
426 #pragma weak SystemIrqHandler
SystemIrqHandler(uint32_t mcause)427 void SystemIrqHandler(uint32_t mcause) {
428 #elif defined(__GNUC__)
429 __attribute__((weak)) void SystemIrqHandler(uint32_t mcause) {
430 #else
431 #error Not supported compiler type
432 #endif
433 uint32_t intNum;
434
435 if (mcause & 0x80000000) /* For external interrupt. */
436 {
437 intNum = mcause & 0x1FUL;
438
439 irqNesting++;
440
441 /* Clear pending flag in EVENT unit .*/
442 EVENT_UNIT->INTPTPENDCLEAR = (1U << intNum);
443
444 /* Read back to make sure write finished. */
445 (void)(EVENT_UNIT->INTPTPENDCLEAR);
446
447 __enable_irq(); /* Support nesting interrupt */
448
449 /* Now call the real irq handler for intNum */
450 isrTable[intNum]();
451
452 __disable_irq();
453
454 irqNesting--;
455 }
456 }
457
458 /* Use LIPT0 channel 0 for systick. */
459 #define SYSTICK_LPIT LPIT0
460 #define SYSTICK_LPIT_CH 0
461 #define SYSTICK_LPIT_IRQn LPIT0_IRQn
462
463 /* Leverage LPIT0 to provide Systick */
464 void SystemSetupSystick(uint32_t tickRateHz, uint32_t intPriority)
465 {
466 /* Init pit module */
467 CLOCK_EnableClock(kCLOCK_Lpit0);
468
469 /* Reset the timer channels and registers except the MCR register */
470 SYSTICK_LPIT->MCR |= LPIT_MCR_SW_RST_MASK;
471 SYSTICK_LPIT->MCR &= ~LPIT_MCR_SW_RST_MASK;
472
473 /* Setup timer operation in debug and doze modes and enable the module */
474 SYSTICK_LPIT->MCR = LPIT_MCR_DBG_EN_MASK | LPIT_MCR_DOZE_EN_MASK | LPIT_MCR_M_CEN_MASK;
475
476 /* Set timer period for channel 0 */
477 SYSTICK_LPIT->CHANNEL[SYSTICK_LPIT_CH].TVAL = (CLOCK_GetIpFreq(kCLOCK_Lpit0) / tickRateHz) - 1;
478
479 /* Enable timer interrupts for channel 0 */
480 SYSTICK_LPIT->MIER |= (1U << SYSTICK_LPIT_CH);
481
482 /* Set interrupt priority. */
483 EVENT_SetIRQPriority(SYSTICK_LPIT_IRQn, intPriority);
484
485 /* Enable interrupt at the EVENT unit */
486 EnableIRQ(SYSTICK_LPIT_IRQn);
487
488 /* Start channel 0 */
489 SYSTICK_LPIT->SETTEN |= (LPIT_SETTEN_SET_T_EN_0_MASK << SYSTICK_LPIT_CH);
490 }
491
492 uint32_t SystemGetIRQNestingLevel(void)
493 {
494 return irqNesting;
495 }
496
497 void SystemClearSystickFlag(void)
498 {
499 /* Channel 0. */
500 SYSTICK_LPIT->MSR = (1U << SYSTICK_LPIT_CH);
501 }
502
503 void EVENT_SetIRQPriority(IRQn_Type IRQn, uint8_t intPriority)
504 {
505 uint8_t regIdx;
506 uint8_t regOffset;
507
508 if ((IRQn < 32) && (intPriority < 8))
509 {
510 /*
511 * 4 priority control registers, each register controls 8 interrupts.
512 * Bit 0-2: interrupt 0
513 * Bit 4-7: interrupt 1
514 * ...
515 * Bit 28-30: interrupt 7
516 */
517 regIdx = IRQn >> 3U;
518 regOffset = (IRQn & 0x07U) * 4U;
519
520 EVENT_UNIT->INTPTPRI[regIdx] = (EVENT_UNIT->INTPTPRI[regIdx] & ~(0x0F << regOffset)) | (intPriority << regOffset);
521 }
522 }
523
524 uint8_t EVENT_GetIRQPriority(IRQn_Type IRQn)
525 {
526 uint8_t regIdx;
527 uint8_t regOffset;
528 int32_t intPriority;
529
530 if ((IRQn < 32))
531 {
532 /*
533 * 4 priority control registers, each register controls 8 interrupts.
534 * Bit 0-2: interrupt 0
535 * Bit 4-7: interrupt 1
536 * ...
537 * Bit 28-30: interrupt 7
538 */
539 regIdx = IRQn >> 3U;
540 regOffset = (IRQn & 0x07U) << 2U;
541
542 intPriority = (EVENT_UNIT->INTPTPRI[regIdx] >> regOffset) & 0xF;
543 return (uint8_t)intPriority;
544 }
545 return 0;
546 }
547
548 bool SystemInISR(void)
549 {
550 return ((EVENT_UNIT->INTPTENACTIVE) != 0);;
551 }
552
553 void EVENT_SystemReset(void)
554 {
555 EVENT_UNIT->SLPCTRL |= EVENT_SLPCTRL_SYSRSTREQST_MASK;
556 }
557
