1 /* --COPYRIGHT--,BSD
2 * Copyright (c) 2017, Texas Instruments Incorporated
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * * Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 *
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * * Neither the name of Texas Instruments Incorporated nor the names of
17 * its contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
22 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
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29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 * --/COPYRIGHT--*/
32 #include <ti/devices/msp432p4xx/driverlib/spi.h>
33 #include <ti/devices/msp432p4xx/driverlib/interrupt.h>
34 #include <ti/devices/msp432p4xx/driverlib/debug.h>
35 #include <ti/devices/msp432p4xx/driverlib/eusci.h>
36
is_A_Module(uint32_t module)37 static bool is_A_Module(uint32_t module)
38 {
39 if (module == EUSCI_A0_BASE || module == EUSCI_A1_BASE
40 #ifdef EUSCI_A2_BASE
41 || module == EUSCI_A2_BASE
42 #endif
43 #ifdef EUSCI_A3_BASE
44 || module == EUSCI_A3_BASE
45 #endif
46 )
47 return true;
48 else
49 return false;
50 }
51
SPI_initMaster(uint32_t moduleInstance,const eUSCI_SPI_MasterConfig * config)52 bool SPI_initMaster(uint32_t moduleInstance, const eUSCI_SPI_MasterConfig *config)
53 {
54 if (is_A_Module(moduleInstance))
55 {
56 ASSERT(
57 (EUSCI_A_SPI_CLOCKSOURCE_ACLK == config->selectClockSource)
58 || (EUSCI_A_SPI_CLOCKSOURCE_SMCLK
59 == config->selectClockSource));
60
61 ASSERT(
62 (EUSCI_A_SPI_MSB_FIRST == config->msbFirst)
63 || (EUSCI_A_SPI_LSB_FIRST == config->msbFirst));
64
65 ASSERT(
66 (EUSCI_A_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT
67 == config->clockPhase)
68 || (EUSCI_A_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT
69 == config->clockPhase));
70
71 ASSERT(
72 (EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_HIGH
73 == config->clockPolarity)
74 || (EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_LOW
75 == config->clockPolarity));
76
77 ASSERT(
78 (EUSCI_A_SPI_3PIN == config->spiMode)
79 || (EUSCI_A_SPI_4PIN_UCxSTE_ACTIVE_HIGH
80 == config->spiMode)
81 || (EUSCI_A_SPI_4PIN_UCxSTE_ACTIVE_LOW
82 == config->spiMode));
83
84 //Disable the USCI Module
85 BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 1;
86
87 /*
88 * Configure as SPI master mode.
89 * Clock phase select, polarity, msb
90 * EUSCI_A_CTLW0_MST = Master mode
91 * EUSCI_A_CTLW0_SYNC = Synchronous mode
92 * UCMODE_0 = 3-pin SPI
93 */
94 EUSCI_A_CMSIS(moduleInstance)->CTLW0 =
95 (EUSCI_A_CMSIS(moduleInstance)->CTLW0
96 & ~(EUSCI_A_CTLW0_SSEL_MASK + EUSCI_A_CTLW0_CKPH + EUSCI_A_CTLW0_CKPL + EUSCI_A_CTLW0_SEVENBIT + EUSCI_A_CTLW0_MSB + EUSCI_A_CTLW0_MST
97 + EUSCI_A_CTLW0_MODE_3 + EUSCI_A_CTLW0_SYNC))
98 | (config->selectClockSource + config->msbFirst
99 + config->clockPhase + config->clockPolarity
100 + EUSCI_A_CTLW0_MST + EUSCI_A_CTLW0_SYNC + config->spiMode);
101
102 EUSCI_A_CMSIS(moduleInstance)->BRW =
103 (uint16_t) (config->clockSourceFrequency
104 / config->desiredSpiClock);
105
106 //No modulation
107 EUSCI_A_CMSIS(moduleInstance)->MCTLW = 0;
108
109 return true;
110 } else
111 {
112 ASSERT(
113 (EUSCI_B_SPI_CLOCKSOURCE_ACLK == config->selectClockSource)
114 || (EUSCI_B_SPI_CLOCKSOURCE_SMCLK
115 == config->selectClockSource));
116
117 ASSERT(
118 (EUSCI_B_SPI_MSB_FIRST == config->msbFirst)
119 || (EUSCI_B_SPI_LSB_FIRST == config->msbFirst));
120
121 ASSERT(
122 (EUSCI_B_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT
123 == config->clockPhase)
124 || (EUSCI_B_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT
125 == config->clockPhase));
126
127 ASSERT(
128 (EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_HIGH
129 == config->clockPolarity)
130 || (EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_LOW
131 == config->clockPolarity));
132
133 ASSERT(
134 (EUSCI_B_SPI_3PIN == config->spiMode)
135 || (EUSCI_B_SPI_4PIN_UCxSTE_ACTIVE_HIGH
136 == config->spiMode)
137 || (EUSCI_B_SPI_4PIN_UCxSTE_ACTIVE_LOW
138 == config->spiMode));
139
140 //Disable the USCI Module
141 BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 1;
142
143 /*
144 * Configure as SPI master mode.
145 * Clock phase select, polarity, msb
146 * EUSCI_A_CTLW0_MST = Master mode
147 * EUSCI_A_CTLW0_SYNC = Synchronous mode
148 * UCMODE_0 = 3-pin SPI
149 */
150 EUSCI_B_CMSIS(moduleInstance)->CTLW0 =
151 (EUSCI_B_CMSIS(moduleInstance)->CTLW0
152 & ~(EUSCI_A_CTLW0_SSEL_MASK + EUSCI_A_CTLW0_CKPH + EUSCI_A_CTLW0_CKPL + EUSCI_A_CTLW0_SEVENBIT + EUSCI_A_CTLW0_MSB + EUSCI_A_CTLW0_MST
153 + EUSCI_A_CTLW0_MODE_3 + EUSCI_A_CTLW0_SYNC))
154 | (config->selectClockSource + config->msbFirst
155 + config->clockPhase + config->clockPolarity
156 + EUSCI_A_CTLW0_MST + EUSCI_A_CTLW0_SYNC + config->spiMode);
157
158 EUSCI_B_CMSIS(moduleInstance)->BRW =
159 (uint16_t) (config->clockSourceFrequency
160 / config->desiredSpiClock);
161
162 return true;
163 }
164
165 }
166
SPI_selectFourPinFunctionality(uint32_t moduleInstance,uint_fast8_t select4PinFunctionality)167 void SPI_selectFourPinFunctionality(uint32_t moduleInstance,
168 uint_fast8_t select4PinFunctionality)
169 {
170 if (is_A_Module(moduleInstance))
171 {
172 EUSCI_A_SPI_select4PinFunctionality(moduleInstance,
173 select4PinFunctionality);
174 } else
175 {
176 EUSCI_B_SPI_select4PinFunctionality(moduleInstance,
177 select4PinFunctionality);
178 }
179
180 }
181
SPI_changeMasterClock(uint32_t moduleInstance,uint32_t clockSourceFrequency,uint32_t desiredSpiClock)182 void SPI_changeMasterClock(uint32_t moduleInstance,
183 uint32_t clockSourceFrequency, uint32_t desiredSpiClock)
184 {
185 if (is_A_Module(moduleInstance))
186 {
187 EUSCI_A_SPI_masterChangeClock(moduleInstance, clockSourceFrequency,
188 desiredSpiClock);
189 } else
190 {
191 EUSCI_B_SPI_masterChangeClock(moduleInstance, clockSourceFrequency,
192 desiredSpiClock);
193 }
194
195 }
196
SPI_initSlave(uint32_t moduleInstance,const eUSCI_SPI_SlaveConfig * config)197 bool SPI_initSlave(uint32_t moduleInstance, const eUSCI_SPI_SlaveConfig *config)
198 {
199 if (is_A_Module(moduleInstance))
200 {
201 ASSERT(
202 (EUSCI_A_SPI_MSB_FIRST == config->msbFirst)
203 || (EUSCI_A_SPI_LSB_FIRST == config->msbFirst));
204
205 ASSERT(
206 (EUSCI_A_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT
207 == config->clockPhase)
208 || (EUSCI_A_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT
209 == config->clockPhase));
210
211 ASSERT(
212 (EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_HIGH
213 == config->clockPolarity)
214 || (EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_LOW
215 == config->clockPolarity));
216
217 ASSERT(
218 (EUSCI_A_SPI_3PIN == config->spiMode)
219 || (EUSCI_A_SPI_4PIN_UCxSTE_ACTIVE_HIGH
220 == config->spiMode)
221 || (EUSCI_A_SPI_4PIN_UCxSTE_ACTIVE_LOW
222 == config->spiMode));
223
224 //Disable USCI Module
225 BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 1;
226
227 //Reset OFS_UCAxCTLW0 register
228 EUSCI_A_CMSIS(moduleInstance)->CTLW0 =
229 (EUSCI_A_CMSIS(moduleInstance)->CTLW0
230 & ~(EUSCI_A_CTLW0_MSB + EUSCI_A_CTLW0_SEVENBIT + EUSCI_A_CTLW0_MST + EUSCI_A_CTLW0_CKPL + EUSCI_A_CTLW0_CKPH + EUSCI_A_CTLW0_MODE_3))
231 | (config->clockPhase + config->clockPolarity
232 + config->msbFirst + EUSCI_A_CTLW0_SYNC + config->spiMode);
233
234 return true;
235 } else
236 {
237 ASSERT(
238 (EUSCI_B_SPI_MSB_FIRST == config->msbFirst)
239 || (EUSCI_B_SPI_LSB_FIRST == config->msbFirst));
240
241 ASSERT(
242 (EUSCI_B_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT
243 == config->clockPhase)
244 || (EUSCI_B_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT
245 == config->clockPhase));
246
247 ASSERT(
248 (EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_HIGH
249 == config->clockPolarity)
250 || (EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_LOW
251 == config->clockPolarity));
252
253 ASSERT(
254 (EUSCI_B_SPI_3PIN == config->spiMode)
255 || (EUSCI_B_SPI_4PIN_UCxSTE_ACTIVE_HIGH
256 == config->spiMode)
257 || (EUSCI_B_SPI_4PIN_UCxSTE_ACTIVE_LOW
258 == config->spiMode));
259
260 //Disable USCI Module
261 BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 1;
262
263 //Reset OFS_UCBxCTLW0 register
264 EUSCI_B_CMSIS(moduleInstance)->CTLW0 =
265 (EUSCI_B_CMSIS(moduleInstance)->CTLW0
266 & ~(EUSCI_A_CTLW0_MSB + EUSCI_A_CTLW0_SEVENBIT + EUSCI_A_CTLW0_MST + EUSCI_A_CTLW0_CKPL + EUSCI_A_CTLW0_CKPH + EUSCI_A_CTLW0_MODE_3))
267 | (config->clockPhase + config->clockPolarity
268 + config->msbFirst + EUSCI_A_CTLW0_SYNC + config->spiMode);
269
270 return true;
271 }
272
273 }
274
SPI_changeClockPhasePolarity(uint32_t moduleInstance,uint_fast16_t clockPhase,uint_fast16_t clockPolarity)275 void SPI_changeClockPhasePolarity(uint32_t moduleInstance,
276 uint_fast16_t clockPhase, uint_fast16_t clockPolarity)
277 {
278 if (is_A_Module(moduleInstance))
279 {
280 EUSCI_A_SPI_changeClockPhasePolarity(moduleInstance, clockPhase,
281 clockPolarity);
282 } else
283 {
284 EUSCI_B_SPI_changeClockPhasePolarity(moduleInstance, clockPhase,
285 clockPolarity);
286 }
287
288 }
289
SPI_transmitData(uint32_t moduleInstance,uint_fast8_t transmitData)290 void SPI_transmitData(uint32_t moduleInstance, uint_fast8_t transmitData)
291 {
292 if (is_A_Module(moduleInstance))
293 {
294 EUSCI_A_SPI_transmitData(moduleInstance, transmitData);
295 } else
296 {
297 EUSCI_B_SPI_transmitData(moduleInstance, transmitData);
298 }
299
300 }
301
SPI_receiveData(uint32_t moduleInstance)302 uint8_t SPI_receiveData(uint32_t moduleInstance)
303 {
304 if (is_A_Module(moduleInstance))
305 {
306 return EUSCI_A_SPI_receiveData(moduleInstance);
307 } else
308 {
309 return EUSCI_B_SPI_receiveData(moduleInstance);
310 }
311
312 }
313
SPI_enableModule(uint32_t moduleInstance)314 void SPI_enableModule(uint32_t moduleInstance)
315 {
316 if (is_A_Module(moduleInstance))
317 {
318 EUSCI_A_SPI_enable(moduleInstance);
319 } else
320 {
321 EUSCI_B_SPI_enable(moduleInstance);
322 }
323
324 }
325
SPI_disableModule(uint32_t moduleInstance)326 void SPI_disableModule(uint32_t moduleInstance)
327 {
328 if (is_A_Module(moduleInstance))
329 {
330 EUSCI_A_SPI_disable(moduleInstance);
331 } else
332 {
333 EUSCI_B_SPI_disable(moduleInstance);
334 }
335
336 }
337
SPI_getReceiveBufferAddressForDMA(uint32_t moduleInstance)338 uint32_t SPI_getReceiveBufferAddressForDMA(uint32_t moduleInstance)
339 {
340 if (is_A_Module(moduleInstance))
341 {
342 return EUSCI_A_SPI_getReceiveBufferAddressForDMA(moduleInstance);
343 } else
344 {
345 return EUSCI_B_SPI_getReceiveBufferAddressForDMA(moduleInstance);
346 }
347
348 }
349
SPI_getTransmitBufferAddressForDMA(uint32_t moduleInstance)350 uint32_t SPI_getTransmitBufferAddressForDMA(uint32_t moduleInstance)
351 {
352 if (is_A_Module(moduleInstance))
353 {
354 return EUSCI_A_SPI_getTransmitBufferAddressForDMA(moduleInstance);
355 } else
356 {
357 return EUSCI_B_SPI_getTransmitBufferAddressForDMA(moduleInstance);
358 }
359
360 }
361
SPI_isBusy(uint32_t moduleInstance)362 uint_fast8_t SPI_isBusy(uint32_t moduleInstance)
363 {
364 if (is_A_Module(moduleInstance))
365 {
366 return EUSCI_A_SPI_isBusy(moduleInstance);
367 } else
368 {
369 return EUSCI_B_SPI_isBusy(moduleInstance);
370 }
371
372 }
373
SPI_enableInterrupt(uint32_t moduleInstance,uint_fast8_t mask)374 void SPI_enableInterrupt(uint32_t moduleInstance, uint_fast8_t mask)
375 {
376 if (is_A_Module(moduleInstance))
377 {
378 EUSCI_A_SPI_enableInterrupt(moduleInstance, mask);
379 } else
380 {
381 EUSCI_B_SPI_enableInterrupt(moduleInstance, mask);
382 }
383
384 }
385
SPI_disableInterrupt(uint32_t moduleInstance,uint_fast8_t mask)386 void SPI_disableInterrupt(uint32_t moduleInstance, uint_fast8_t mask)
387 {
388 if (is_A_Module(moduleInstance))
389 {
390 EUSCI_A_SPI_disableInterrupt(moduleInstance, mask);
391 } else
392 {
393 EUSCI_B_SPI_disableInterrupt(moduleInstance, mask);
394 }
395
396 }
397
SPI_getInterruptStatus(uint32_t moduleInstance,uint16_t mask)398 uint_fast8_t SPI_getInterruptStatus(uint32_t moduleInstance, uint16_t mask)
399 {
400 if (is_A_Module(moduleInstance))
401 {
402 return EUSCI_A_SPI_getInterruptStatus(moduleInstance, mask);
403 } else
404 {
405 return EUSCI_B_SPI_getInterruptStatus(moduleInstance, mask);
406 }
407
408 }
409
SPI_getEnabledInterruptStatus(uint32_t moduleInstance)410 uint_fast8_t SPI_getEnabledInterruptStatus(uint32_t moduleInstance)
411 {
412 if (is_A_Module(moduleInstance))
413 {
414 return SPI_getInterruptStatus(moduleInstance,
415 EUSCI_SPI_TRANSMIT_INTERRUPT | EUSCI_SPI_RECEIVE_INTERRUPT)
416 & EUSCI_A_CMSIS(moduleInstance)->IE;
417
418 } else
419 {
420 return SPI_getInterruptStatus(moduleInstance,
421 EUSCI_SPI_TRANSMIT_INTERRUPT | EUSCI_SPI_RECEIVE_INTERRUPT)
422 & EUSCI_B_CMSIS(moduleInstance)->IE;
423
424 }
425 }
426
SPI_clearInterruptFlag(uint32_t moduleInstance,uint_fast8_t mask)427 void SPI_clearInterruptFlag(uint32_t moduleInstance, uint_fast8_t mask)
428 {
429 if (is_A_Module(moduleInstance))
430 {
431 EUSCI_A_SPI_clearInterruptFlag(moduleInstance, mask);
432 } else
433 {
434 EUSCI_B_SPI_clearInterruptFlag(moduleInstance, mask);
435 }
436
437 }
438
SPI_registerInterrupt(uint32_t moduleInstance,void (* intHandler)(void))439 void SPI_registerInterrupt(uint32_t moduleInstance, void (*intHandler)(void))
440 {
441 switch (moduleInstance)
442 {
443 case EUSCI_A0_BASE:
444 Interrupt_registerInterrupt(INT_EUSCIA0, intHandler);
445 Interrupt_enableInterrupt(INT_EUSCIA0);
446 break;
447 case EUSCI_A1_BASE:
448 Interrupt_registerInterrupt(INT_EUSCIA1, intHandler);
449 Interrupt_enableInterrupt(INT_EUSCIA1);
450 break;
451 #ifdef EUSCI_A2_BASE
452 case EUSCI_A2_BASE:
453 Interrupt_registerInterrupt(INT_EUSCIA2, intHandler);
454 Interrupt_enableInterrupt(INT_EUSCIA2);
455 break;
456 #endif
457 #ifdef EUSCI_A3_BASE
458 case EUSCI_A3_BASE:
459 Interrupt_registerInterrupt(INT_EUSCIA3, intHandler);
460 Interrupt_enableInterrupt(INT_EUSCIA3);
461 break;
462 #endif
463 case EUSCI_B0_BASE:
464 Interrupt_registerInterrupt(INT_EUSCIB0, intHandler);
465 Interrupt_enableInterrupt(INT_EUSCIB0);
466 break;
467 case EUSCI_B1_BASE:
468 Interrupt_registerInterrupt(INT_EUSCIB1, intHandler);
469 Interrupt_enableInterrupt(INT_EUSCIB1);
470 break;
471 #ifdef EUSCI_B2_BASE
472 case EUSCI_B2_BASE:
473 Interrupt_registerInterrupt(INT_EUSCIB2, intHandler);
474 Interrupt_enableInterrupt(INT_EUSCIB2);
475 break;
476 #endif
477 #ifdef EUSCI_B3_BASE
478 case EUSCI_B3_BASE:
479 Interrupt_registerInterrupt(INT_EUSCIB3, intHandler);
480 Interrupt_enableInterrupt(INT_EUSCIB3);
481 break;
482 #endif
483 default:
484 ASSERT(false);
485 }
486 }
487
SPI_unregisterInterrupt(uint32_t moduleInstance)488 void SPI_unregisterInterrupt(uint32_t moduleInstance)
489 {
490 switch (moduleInstance)
491 {
492 case EUSCI_A0_BASE:
493 Interrupt_disableInterrupt(INT_EUSCIA0);
494 Interrupt_unregisterInterrupt(INT_EUSCIA0);
495 break;
496 case EUSCI_A1_BASE:
497 Interrupt_disableInterrupt(INT_EUSCIA1);
498 Interrupt_unregisterInterrupt(INT_EUSCIA1);
499 break;
500 #ifdef EUSCI_A2_BASE
501 case EUSCI_A2_BASE:
502 Interrupt_disableInterrupt(INT_EUSCIA2);
503 Interrupt_unregisterInterrupt(INT_EUSCIA2);
504 break;
505 #endif
506 #ifdef EUSCI_A3_BASE
507 case EUSCI_A3_BASE:
508 Interrupt_disableInterrupt(INT_EUSCIA3);
509 Interrupt_unregisterInterrupt(INT_EUSCIA3);
510 break;
511 #endif
512 case EUSCI_B0_BASE:
513 Interrupt_disableInterrupt(INT_EUSCIB0);
514 Interrupt_unregisterInterrupt(INT_EUSCIB0);
515 break;
516 case EUSCI_B1_BASE:
517 Interrupt_disableInterrupt(INT_EUSCIB1);
518 Interrupt_unregisterInterrupt(INT_EUSCIB1);
519 break;
520 #ifdef EUSCI_B2_BASE
521 case EUSCI_B2_BASE:
522 Interrupt_disableInterrupt(INT_EUSCIB2);
523 Interrupt_unregisterInterrupt(INT_EUSCIB2);
524 break;
525 #endif
526 #ifdef EUSCI_B3_BASE
527 case EUSCI_B3_BASE:
528 Interrupt_disableInterrupt(INT_EUSCIB3);
529 Interrupt_unregisterInterrupt(INT_EUSCIB3);
530 break;
531 #endif
532 default:
533 ASSERT(false);
534 }
535
536 }
537
538 /* Backwards Compatibility Layer */
539
540 //*****************************************************************************
541 //
542 //! \brief Selects 4Pin Functionality
543 //!
544 //! This function should be invoked only in 4-wire mode. Invoking this function
545 //! has no effect in 3-wire mode.
546 //!
547 //! \param baseAddress is the base address of the EUSCI_B_SPI module.
548 //! \param select4PinFunctionality selects 4 pin functionality
549 //! Valid values are:
550 //! - \b EUSCI_B_SPI_PREVENT_CONFLICTS_WITH_OTHER_MASTERS
551 //! - \b EUSCI_B_SPI_ENABLE_SIGNAL_FOR_4WIRE_SLAVE
552 //!
553 //! Modified bits are \b UCSTEM of \b UCAxCTLW0 register.
554 //!
555 //! \return None
556 //
557 //*****************************************************************************
EUSCI_B_SPI_select4PinFunctionality(uint32_t baseAddress,uint8_t select4PinFunctionality)558 void EUSCI_B_SPI_select4PinFunctionality(uint32_t baseAddress,
559 uint8_t select4PinFunctionality)
560 {
561 ASSERT(
562 (EUSCI_B_SPI_PREVENT_CONFLICTS_WITH_OTHER_MASTERS
563 == select4PinFunctionality)
564 || (EUSCI_B_SPI_ENABLE_SIGNAL_FOR_4WIRE_SLAVE
565 == select4PinFunctionality));
566
567 EUSCI_B_CMSIS(baseAddress)->CTLW0 = (EUSCI_B_CMSIS(baseAddress)->CTLW0
568 & ~EUSCI_B_CTLW0_STEM) | select4PinFunctionality;
569 }
570
571 //*****************************************************************************
572 //
573 //! \brief Initializes the SPI Master clock. At the end of this function call,
574 //! SPI module is left enabled.
575 //!
576 //! \param baseAddress is the base address of the EUSCI_B_SPI module.
577 //! \param clockSourceFrequency is the frequency of the slected clock source
578 //! \param desiredSpiClock is the desired clock rate for SPI communication
579 //!
580 //! Modified bits are \b UCSWRST of \b UCAxCTLW0 register.
581 //!
582 //! \return None
583 //
584 //*****************************************************************************
EUSCI_B_SPI_masterChangeClock(uint32_t baseAddress,uint32_t clockSourceFrequency,uint32_t desiredSpiClock)585 void EUSCI_B_SPI_masterChangeClock(uint32_t baseAddress,
586 uint32_t clockSourceFrequency, uint32_t desiredSpiClock)
587 {
588 //Disable the USCI Module
589 BITBAND_PERI(EUSCI_B_CMSIS(baseAddress)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 1;
590
591 EUSCI_B_CMSIS(baseAddress)->BRW = (uint16_t) (clockSourceFrequency
592 / desiredSpiClock);
593
594 //Reset the UCSWRST bit to enable the USCI Module
595 BITBAND_PERI(EUSCI_B_CMSIS(baseAddress)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 0;
596 }
597
598 //*****************************************************************************
599 //
600 //! \brief Initializes the SPI Slave block.
601 //!
602 //! Upon successful initialization of the SPI slave block, this function will
603 //! have initailized the slave block, but the SPI Slave block still remains
604 //! disabled and must be enabled with EUSCI_B_SPI_enable()
605 //!
606 //! \param baseAddress is the base address of the EUSCI_B_SPI Slave module.
607 //! \param msbFirst controls the direction of the receive and transmit shift
608 //! register.
609 //! Valid values are:
610 //! - \b EUSCI_B_SPI_MSB_FIRST
611 //! - \b EUSCI_B_SPI_LSB_FIRST [Default]
612 //! \param clockPhase is clock phase select.
613 //! Valid values are:
614 //! - \b EUSCI_B_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT
615 //! [Default]
616 //! - \b EUSCI_B_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT
617 //! \param clockPolarity is clock polarity select
618 //! Valid values are:
619 //! - \b EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_HIGH
620 //! - \b EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_LOW [Default]
621 //! \param spiMode is SPI mode select
622 //! Valid values are:
623 //! - \b EUSCI_B_SPI_3PIN
624 //! - \b EUSCI_B_SPI_4PIN_UCxSTE_ACTIVE_HIGH
625 //! - \b EUSCI_B_SPI_4PIN_UCxSTE_ACTIVE_LOW
626 //!
627 //! Modified bits are \b EUSCI_A_CTLW0_MSB, \b EUSCI_A_CTLW0_MST, \b EUSCI_A_CTLW0_SEVENBIT, \b EUSCI_A_CTLW0_CKPL, \b EUSCI_A_CTLW0_CKPH, \b
628 //! UCMODE and \b UCSWRST of \b UCAxCTLW0 register.
629 //!
630 //! \return true
631 //
632 //*****************************************************************************
EUSCI_B_SPI_slaveInit(uint32_t baseAddress,uint16_t msbFirst,uint16_t clockPhase,uint16_t clockPolarity,uint16_t spiMode)633 bool EUSCI_B_SPI_slaveInit(uint32_t baseAddress, uint16_t msbFirst,
634 uint16_t clockPhase, uint16_t clockPolarity, uint16_t spiMode)
635 {
636 ASSERT(
637 (EUSCI_B_SPI_MSB_FIRST == msbFirst)
638 || (EUSCI_B_SPI_LSB_FIRST == msbFirst));
639
640 ASSERT(
641 (EUSCI_B_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT
642 == clockPhase)
643 || (EUSCI_B_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT
644 == clockPhase));
645
646 ASSERT(
647 (EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_HIGH == clockPolarity)
648 || (EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_LOW
649 == clockPolarity));
650
651 ASSERT(
652 (EUSCI_B_SPI_3PIN == spiMode)
653 || (EUSCI_B_SPI_4PIN_UCxSTE_ACTIVE_HIGH == spiMode)
654 || (EUSCI_B_SPI_4PIN_UCxSTE_ACTIVE_LOW == spiMode));
655
656 //Disable USCI Module
657 BITBAND_PERI(EUSCI_B_CMSIS(baseAddress)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 1;
658
659 //Reset OFS_UCBxCTLW0 register
660 EUSCI_B_CMSIS(baseAddress)->CTLW0 = (EUSCI_B_CMSIS(baseAddress)->CTLW0
661 & ~(EUSCI_A_CTLW0_MSB + EUSCI_A_CTLW0_SEVENBIT + EUSCI_A_CTLW0_MST + EUSCI_A_CTLW0_CKPL + EUSCI_A_CTLW0_CKPH + EUSCI_A_CTLW0_MODE_3))
662 | (clockPhase + clockPolarity + msbFirst + EUSCI_A_CTLW0_SYNC + spiMode);
663
664 return true;
665 }
666
667 //*****************************************************************************
668 //
669 //! \brief Changes the SPI colock phase and polarity. At the end of this
670 //! function call, SPI module is left enabled.
671 //!
672 //! \param baseAddress is the base address of the EUSCI_B_SPI module.
673 //! \param clockPhase is clock phase select.
674 //! Valid values are:
675 //! - \b EUSCI_B_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT
676 //! [Default]
677 //! - \b EUSCI_B_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT
678 //! \param clockPolarity is clock polarity select
679 //! Valid values are:
680 //! - \b EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_HIGH
681 //! - \b EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_LOW [Default]
682 //!
683 //! Modified bits are \b EUSCI_A_CTLW0_CKPL, \b EUSCI_A_CTLW0_CKPH and \b UCSWRST of \b UCAxCTLW0
684 //! register.
685 //!
686 //! \return None
687 //
688 //*****************************************************************************
EUSCI_B_SPI_changeClockPhasePolarity(uint32_t baseAddress,uint16_t clockPhase,uint16_t clockPolarity)689 void EUSCI_B_SPI_changeClockPhasePolarity(uint32_t baseAddress,
690 uint16_t clockPhase, uint16_t clockPolarity)
691 {
692
693 ASSERT(
694 (EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_HIGH == clockPolarity)
695 || (EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_LOW
696 == clockPolarity));
697
698 ASSERT(
699 (EUSCI_B_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT
700 == clockPhase)
701 || (EUSCI_B_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT
702 == clockPhase));
703
704 //Disable the USCI Module
705 BITBAND_PERI(EUSCI_B_CMSIS(baseAddress)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 1;
706
707 EUSCI_B_CMSIS(baseAddress)->CTLW0 = (EUSCI_B_CMSIS(baseAddress)->CTLW0
708 & ~(EUSCI_A_CTLW0_CKPH + EUSCI_A_CTLW0_CKPL)) | (clockPhase + clockPolarity);
709
710 //Reset the UCSWRST bit to enable the USCI Module
711 BITBAND_PERI(EUSCI_B_CMSIS(baseAddress)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 0;
712 }
713
714 //*****************************************************************************
715 //
716 //! \brief Transmits a byte from the SPI Module.
717 //!
718 //! This function will place the supplied data into SPI trasmit data register
719 //! to start transmission.
720 //!
721 //! \param baseAddress is the base address of the EUSCI_B_SPI module.
722 //! \param transmitData data to be transmitted from the SPI module
723 //!
724 //! \return None
725 //
726 //*****************************************************************************
EUSCI_B_SPI_transmitData(uint32_t baseAddress,uint8_t transmitData)727 void EUSCI_B_SPI_transmitData(uint32_t baseAddress, uint8_t transmitData)
728 {
729 EUSCI_B_CMSIS(baseAddress)->TXBUF = transmitData;
730 }
731
732 //*****************************************************************************
733 //
734 //! \brief Receives a byte that has been sent to the SPI Module.
735 //!
736 //! This function reads a byte of data from the SPI receive data Register.
737 //!
738 //! \param baseAddress is the base address of the EUSCI_B_SPI module.
739 //!
740 //! \return Returns the byte received from by the SPI module, cast as an
741 //! uint8_t.
742 //
743 //*****************************************************************************
EUSCI_B_SPI_receiveData(uint32_t baseAddress)744 uint8_t EUSCI_B_SPI_receiveData(uint32_t baseAddress)
745 {
746 return EUSCI_B_CMSIS(baseAddress)->RXBUF;
747 }
748
749 //*****************************************************************************
750 //
751 //! \brief Enables individual SPI interrupt sources.
752 //!
753 //! Enables the indicated SPI interrupt sources. Only the sources that are
754 //! enabled can be reflected to the processor interrupt; disabled sources have
755 //! no effect on the processor. Does not clear interrupt flags.
756 //!
757 //! \param baseAddress is the base address of the EUSCI_B_SPI module.
758 //! \param mask is the bit mask of the interrupt sources to be enabled.
759 //! Mask value is the logical OR of any of the following:
760 //! - \b EUSCI_B_SPI_TRANSMIT_INTERRUPT
761 //! - \b EUSCI_B_SPI_RECEIVE_INTERRUPT
762 //!
763 //! Modified bits of \b UCAxIFG register and bits of \b UCAxIE register.
764 //!
765 //! \return None
766 //
767 //*****************************************************************************
EUSCI_B_SPI_enableInterrupt(uint32_t baseAddress,uint8_t mask)768 void EUSCI_B_SPI_enableInterrupt(uint32_t baseAddress, uint8_t mask)
769 {
770 ASSERT(
771 !(mask
772 & ~(EUSCI_B_SPI_RECEIVE_INTERRUPT
773 | EUSCI_B_SPI_TRANSMIT_INTERRUPT)));
774
775 EUSCI_B_CMSIS(baseAddress)->IE |= mask;
776 }
777
778 //*****************************************************************************
779 //
780 //! \brief Disables individual SPI interrupt sources.
781 //!
782 //! Disables the indicated SPI interrupt sources. Only the sources that are
783 //! enabled can be reflected to the processor interrupt; disabled sources have
784 //! no effect on the processor.
785 //!
786 //! \param baseAddress is the base address of the EUSCI_B_SPI module.
787 //! \param mask is the bit mask of the interrupt sources to be disabled.
788 //! Mask value is the logical OR of any of the following:
789 //! - \b EUSCI_B_SPI_TRANSMIT_INTERRUPT
790 //! - \b EUSCI_B_SPI_RECEIVE_INTERRUPT
791 //!
792 //! Modified bits of \b UCAxIE register.
793 //!
794 //! \return None
795 //
796 //*****************************************************************************
EUSCI_B_SPI_disableInterrupt(uint32_t baseAddress,uint8_t mask)797 void EUSCI_B_SPI_disableInterrupt(uint32_t baseAddress, uint8_t mask)
798 {
799 ASSERT(
800 !(mask
801 & ~(EUSCI_B_SPI_RECEIVE_INTERRUPT
802 | EUSCI_B_SPI_TRANSMIT_INTERRUPT)));
803
804 EUSCI_B_CMSIS(baseAddress)->IE &= ~mask;
805 }
806
807 //*****************************************************************************
808 //
809 //! \brief Gets the current SPI interrupt status.
810 //!
811 //! This returns the interrupt status for the SPI module based on which flag is
812 //! passed.
813 //!
814 //! \param baseAddress is the base address of the EUSCI_B_SPI module.
815 //! \param mask is the masked interrupt flag status to be returned.
816 //! Mask value is the logical OR of any of the following:
817 //! - \b EUSCI_B_SPI_TRANSMIT_INTERRUPT
818 //! - \b EUSCI_B_SPI_RECEIVE_INTERRUPT
819 //!
820 //! \return Logical OR of any of the following:
821 //! - \b EUSCI_B_SPI_TRANSMIT_INTERRUPT
822 //! - \b EUSCI_B_SPI_RECEIVE_INTERRUPT
823 //! \n indicating the status of the masked interrupts
824 //
825 //*****************************************************************************
EUSCI_B_SPI_getInterruptStatus(uint32_t baseAddress,uint8_t mask)826 uint8_t EUSCI_B_SPI_getInterruptStatus(uint32_t baseAddress, uint8_t mask)
827 {
828 ASSERT(
829 !(mask
830 & ~(EUSCI_B_SPI_RECEIVE_INTERRUPT
831 | EUSCI_B_SPI_TRANSMIT_INTERRUPT)));
832
833 return EUSCI_B_CMSIS(baseAddress)->IFG & mask;
834 }
835
836 //*****************************************************************************
837 //
838 //! \brief Clears the selected SPI interrupt status flag.
839 //!
840 //! \param baseAddress is the base address of the EUSCI_B_SPI module.
841 //! \param mask is the masked interrupt flag to be cleared.
842 //! Mask value is the logical OR of any of the following:
843 //! - \b EUSCI_B_SPI_TRANSMIT_INTERRUPT
844 //! - \b EUSCI_B_SPI_RECEIVE_INTERRUPT
845 //!
846 //! Modified bits of \b UCAxIFG register.
847 //!
848 //! \return None
849 //
850 //*****************************************************************************
EUSCI_B_SPI_clearInterruptFlag(uint32_t baseAddress,uint8_t mask)851 void EUSCI_B_SPI_clearInterruptFlag(uint32_t baseAddress, uint8_t mask)
852 {
853 ASSERT(
854 !(mask
855 & ~(EUSCI_B_SPI_RECEIVE_INTERRUPT
856 | EUSCI_B_SPI_TRANSMIT_INTERRUPT)));
857
858 EUSCI_B_CMSIS(baseAddress)->IFG &= ~mask;
859 }
860
861 //*****************************************************************************
862 //
863 //! \brief Enables the SPI block.
864 //!
865 //! This will enable operation of the SPI block.
866 //!
867 //! \param baseAddress is the base address of the EUSCI_B_SPI module.
868 //!
869 //! Modified bits are \b UCSWRST of \b UCBxCTLW0 register.
870 //!
871 //! \return None
872 //
873 //*****************************************************************************
EUSCI_B_SPI_enable(uint32_t baseAddress)874 void EUSCI_B_SPI_enable(uint32_t baseAddress)
875 {
876 //Reset the UCSWRST bit to enable the USCI Module
877 BITBAND_PERI(EUSCI_B_CMSIS(baseAddress)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 0;
878 }
879
880 //*****************************************************************************
881 //
882 //! \brief Disables the SPI block.
883 //!
884 //! This will disable operation of the SPI block.
885 //!
886 //! \param baseAddress is the base address of the EUSCI_B_SPI module.
887 //!
888 //! Modified bits are \b UCSWRST of \b UCBxCTLW0 register.
889 //!
890 //! \return None
891 //
892 //*****************************************************************************
EUSCI_B_SPI_disable(uint32_t baseAddress)893 void EUSCI_B_SPI_disable(uint32_t baseAddress)
894 {
895 //Set the UCSWRST bit to disable the USCI Module
896 BITBAND_PERI(EUSCI_B_CMSIS(baseAddress)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 1;
897 }
898
899 //*****************************************************************************
900 //
901 //! \brief Returns the address of the RX Buffer of the SPI for the DMA module.
902 //!
903 //! Returns the address of the SPI RX Buffer. This can be used in conjunction
904 //! with the DMA to store the received data directly to memory.
905 //!
906 //! \param baseAddress is the base address of the EUSCI_B_SPI module.
907 //!
908 //! \return the address of the RX Buffer
909 //
910 //*****************************************************************************
EUSCI_B_SPI_getReceiveBufferAddressForDMA(uint32_t baseAddress)911 uint32_t EUSCI_B_SPI_getReceiveBufferAddressForDMA(uint32_t baseAddress)
912 {
913 return ((uint32_t)(&EUSCI_B_CMSIS(baseAddress)->RXBUF));
914 }
915
916 //*****************************************************************************
917 //
918 //! \brief Returns the address of the TX Buffer of the SPI for the DMA module.
919 //!
920 //! Returns the address of the SPI TX Buffer. This can be used in conjunction
921 //! with the DMA to obtain transmitted data directly from memory.
922 //!
923 //! \param baseAddress is the base address of the EUSCI_B_SPI module.
924 //!
925 //! \return the address of the TX Buffer
926 //
927 //*****************************************************************************
EUSCI_B_SPI_getTransmitBufferAddressForDMA(uint32_t baseAddress)928 uint32_t EUSCI_B_SPI_getTransmitBufferAddressForDMA(uint32_t baseAddress)
929 {
930 return ((uint32_t)(&EUSCI_B_CMSIS(baseAddress)->TXBUF));
931 }
932
933 //*****************************************************************************
934 //
935 //! \brief Indicates whether or not the SPI bus is busy.
936 //!
937 //! This function returns an indication of whether or not the SPI bus is
938 //! busy.This function checks the status of the bus via UCBBUSY bit
939 //!
940 //! \param baseAddress is the base address of the EUSCI_B_SPI module.
941 //!
942 //! \return true if busy, false otherwise
943 //
944 //*****************************************************************************
EUSCI_B_SPI_isBusy(uint32_t baseAddress)945 bool EUSCI_B_SPI_isBusy(uint32_t baseAddress)
946 {
947 //Return the bus busy status.
948 return BITBAND_PERI(EUSCI_B_CMSIS(baseAddress)->STATW, EUSCI_B_STATW_BBUSY_OFS);
949 }
950
951 //*****************************************************************************
952 //
953 //! \brief Selects 4Pin Functionality
954 //!
955 //! This function should be invoked only in 4-wire mode. Invoking this function
956 //! has no effect in 3-wire mode.
957 //!
958 //! \param baseAddress is the base address of the EUSCI_A_SPI module.
959 //! \param select4PinFunctionality selects 4 pin functionality
960 //! Valid values are:
961 //! - \b EUSCI_A_SPI_PREVENT_CONFLICTS_WITH_OTHER_MASTERS
962 //! - \b EUSCI_A_SPI_ENABLE_SIGNAL_FOR_4WIRE_SLAVE
963 //!
964 //! Modified bits are \b UCSTEM of \b UCAxCTLW0 register.
965 //!
966 //! \return None
967 //
968 //*****************************************************************************
EUSCI_A_SPI_select4PinFunctionality(uint32_t baseAddress,uint8_t select4PinFunctionality)969 void EUSCI_A_SPI_select4PinFunctionality(uint32_t baseAddress,
970 uint8_t select4PinFunctionality)
971 {
972 ASSERT(
973 (EUSCI_A_SPI_PREVENT_CONFLICTS_WITH_OTHER_MASTERS
974 == select4PinFunctionality)
975 || (EUSCI_A_SPI_ENABLE_SIGNAL_FOR_4WIRE_SLAVE
976 == select4PinFunctionality));
977
978 EUSCI_A_CMSIS(baseAddress)->CTLW0 = (EUSCI_A_CMSIS(baseAddress)->CTLW0
979 & ~EUSCI_A_CTLW0_STEM) | select4PinFunctionality;
980 }
981
982 //*****************************************************************************
983 //
984 //! \brief Initializes the SPI Master clock. At the end of this function call,
985 //! SPI module is left enabled.
986 //!
987 //! \param baseAddress is the base address of the EUSCI_A_SPI module.
988 //! \param clockSourceFrequency is the frequency of the slected clock source
989 //! \param desiredSpiClock is the desired clock rate for SPI communication
990 //!
991 //! Modified bits are \b UCSWRST of \b UCAxCTLW0 register.
992 //!
993 //! \return None
994 //
995 //*****************************************************************************
EUSCI_A_SPI_masterChangeClock(uint32_t baseAddress,uint32_t clockSourceFrequency,uint32_t desiredSpiClock)996 void EUSCI_A_SPI_masterChangeClock(uint32_t baseAddress,
997 uint32_t clockSourceFrequency, uint32_t desiredSpiClock)
998 {
999 //Disable the USCI Module
1000 BITBAND_PERI(EUSCI_A_CMSIS(baseAddress)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 1;
1001
1002 EUSCI_A_CMSIS(baseAddress)->BRW = (uint16_t) (clockSourceFrequency
1003 / desiredSpiClock);
1004
1005 //Reset the UCSWRST bit to enable the USCI Module
1006 BITBAND_PERI(EUSCI_A_CMSIS(baseAddress)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 0;
1007 }
1008
1009 //*****************************************************************************
1010 //
1011 //! \brief Initializes the SPI Slave block.
1012 //!
1013 //! Upon successful initialization of the SPI slave block, this function will
1014 //! have initailized the slave block, but the SPI Slave block still remains
1015 //! disabled and must be enabled with EUSCI_A_SPI_enable()
1016 //!
1017 //! \param baseAddress is the base address of the EUSCI_A_SPI Slave module.
1018 //! \param msbFirst controls the direction of the receive and transmit shift
1019 //! register.
1020 //! Valid values are:
1021 //! - \b EUSCI_A_SPI_MSB_FIRST
1022 //! - \b EUSCI_A_SPI_LSB_FIRST [Default]
1023 //! \param clockPhase is clock phase select.
1024 //! Valid values are:
1025 //! - \b EUSCI_A_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT
1026 //! [Default]
1027 //! - \b EUSCI_A_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT
1028 //! \param clockPolarity is clock polarity select
1029 //! Valid values are:
1030 //! - \b EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_HIGH
1031 //! - \b EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_LOW [Default]
1032 //! \param spiMode is SPI mode select
1033 //! Valid values are:
1034 //! - \b EUSCI_A_SPI_3PIN
1035 //! - \b EUSCI_A_SPI_4PIN_UCxSTE_ACTIVE_HIGH
1036 //! - \b EUSCI_A_SPI_4PIN_UCxSTE_ACTIVE_LOW
1037 //!
1038 //! Modified bits are \b EUSCI_A_CTLW0_MSB, \b EUSCI_A_CTLW0_MST, \b EUSCI_A_CTLW0_SEVENBIT, \b EUSCI_A_CTLW0_CKPL, \b EUSCI_A_CTLW0_CKPH, \b
1039 //! UCMODE and \b UCSWRST of \b UCAxCTLW0 register.
1040 //!
1041 //! \return true
1042 //
1043 //*****************************************************************************
EUSCI_A_SPI_slaveInit(uint32_t baseAddress,uint16_t msbFirst,uint16_t clockPhase,uint16_t clockPolarity,uint16_t spiMode)1044 bool EUSCI_A_SPI_slaveInit(uint32_t baseAddress, uint16_t msbFirst,
1045 uint16_t clockPhase, uint16_t clockPolarity, uint16_t spiMode)
1046 {
1047 ASSERT(
1048 (EUSCI_A_SPI_MSB_FIRST == msbFirst)
1049 || (EUSCI_A_SPI_LSB_FIRST == msbFirst));
1050
1051 ASSERT(
1052 (EUSCI_A_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT
1053 == clockPhase)
1054 || (EUSCI_A_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT
1055 == clockPhase));
1056
1057 ASSERT(
1058 (EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_HIGH == clockPolarity)
1059 || (EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_LOW
1060 == clockPolarity));
1061
1062 ASSERT(
1063 (EUSCI_A_SPI_3PIN == spiMode)
1064 || (EUSCI_A_SPI_4PIN_UCxSTE_ACTIVE_HIGH == spiMode)
1065 || (EUSCI_A_SPI_4PIN_UCxSTE_ACTIVE_LOW == spiMode));
1066
1067 //Disable USCI Module
1068 BITBAND_PERI(EUSCI_A_CMSIS(baseAddress)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 1;
1069
1070 //Reset OFS_UCAxCTLW0 register
1071 EUSCI_A_CMSIS(baseAddress)->CTLW0 = (EUSCI_A_CMSIS(baseAddress)->CTLW0
1072 & ~(EUSCI_A_CTLW0_MSB + EUSCI_A_CTLW0_SEVENBIT + EUSCI_A_CTLW0_MST + EUSCI_A_CTLW0_CKPL + EUSCI_A_CTLW0_CKPH + EUSCI_A_CTLW0_MODE_3))
1073 | (clockPhase + clockPolarity + msbFirst + EUSCI_A_CTLW0_SYNC + spiMode);
1074
1075 return true;
1076 }
1077
1078 //*****************************************************************************
1079 //
1080 //! \brief Changes the SPI colock phase and polarity. At the end of this
1081 //! function call, SPI module is left enabled.
1082 //!
1083 //! \param baseAddress is the base address of the EUSCI_A_SPI module.
1084 //! \param clockPhase is clock phase select.
1085 //! Valid values are:
1086 //! - \b EUSCI_A_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT
1087 //! [Default]
1088 //! - \b EUSCI_A_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT
1089 //! \param clockPolarity is clock polarity select
1090 //! Valid values are:
1091 //! - \b EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_HIGH
1092 //! - \b EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_LOW [Default]
1093 //!
1094 //! Modified bits are \b EUSCI_A_CTLW0_CKPL, \b EUSCI_A_CTLW0_CKPH and \b UCSWRST of \b UCAxCTLW0
1095 //! register.
1096 //!
1097 //! \return None
1098 //
1099 //*****************************************************************************
EUSCI_A_SPI_changeClockPhasePolarity(uint32_t baseAddress,uint16_t clockPhase,uint16_t clockPolarity)1100 void EUSCI_A_SPI_changeClockPhasePolarity(uint32_t baseAddress,
1101 uint16_t clockPhase, uint16_t clockPolarity)
1102 {
1103
1104 ASSERT(
1105 (EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_HIGH == clockPolarity)
1106 || (EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_LOW
1107 == clockPolarity));
1108
1109 ASSERT(
1110 (EUSCI_A_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT
1111 == clockPhase)
1112 || (EUSCI_A_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT
1113 == clockPhase));
1114
1115 //Disable the USCI Module
1116 BITBAND_PERI(EUSCI_A_CMSIS(baseAddress)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 1;
1117
1118 EUSCI_A_CMSIS(baseAddress)->CTLW0 = (EUSCI_A_CMSIS(baseAddress)->CTLW0
1119 & ~(EUSCI_A_CTLW0_CKPH + EUSCI_A_CTLW0_CKPL)) | (clockPhase + clockPolarity);
1120
1121 //Reset the UCSWRST bit to enable the USCI Module
1122 BITBAND_PERI(EUSCI_A_CMSIS(baseAddress)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 0;
1123 }
1124
1125 //*****************************************************************************
1126 //
1127 //! \brief Transmits a byte from the SPI Module.
1128 //!
1129 //! This function will place the supplied data into SPI trasmit data register
1130 //! to start transmission.
1131 //!
1132 //! \param baseAddress is the base address of the EUSCI_A_SPI module.
1133 //! \param transmitData data to be transmitted from the SPI module
1134 //!
1135 //! \return None
1136 //
1137 //*****************************************************************************
EUSCI_A_SPI_transmitData(uint32_t baseAddress,uint8_t transmitData)1138 void EUSCI_A_SPI_transmitData(uint32_t baseAddress, uint8_t transmitData)
1139 {
1140 EUSCI_A_CMSIS(baseAddress)->TXBUF = transmitData;
1141 }
1142
1143 //*****************************************************************************
1144 //
1145 //! \brief Receives a byte that has been sent to the SPI Module.
1146 //!
1147 //! This function reads a byte of data from the SPI receive data Register.
1148 //!
1149 //! \param baseAddress is the base address of the EUSCI_A_SPI module.
1150 //!
1151 //! \return Returns the byte received from by the SPI module, cast as an
1152 //! uint8_t.
1153 //
1154 //*****************************************************************************
EUSCI_A_SPI_receiveData(uint32_t baseAddress)1155 uint8_t EUSCI_A_SPI_receiveData(uint32_t baseAddress)
1156 {
1157 return EUSCI_A_CMSIS(baseAddress)->RXBUF;
1158 }
1159
1160 //*****************************************************************************
1161 //
1162 //! \brief Enables individual SPI interrupt sources.
1163 //!
1164 //! Enables the indicated SPI interrupt sources. Only the sources that are
1165 //! enabled can be reflected to the processor interrupt; disabled sources have
1166 //! no effect on the processor. Does not clear interrupt flags.
1167 //!
1168 //! \param baseAddress is the base address of the EUSCI_A_SPI module.
1169 //! \param mask is the bit mask of the interrupt sources to be enabled.
1170 //! Mask value is the logical OR of any of the following:
1171 //! - \b EUSCI_A_SPI_TRANSMIT_INTERRUPT
1172 //! - \b EUSCI_A_SPI_RECEIVE_INTERRUPT
1173 //!
1174 //! Modified bits of \b UCAxIFG register and bits of \b UCAxIE register.
1175 //!
1176 //! \return None
1177 //
1178 //*****************************************************************************
EUSCI_A_SPI_enableInterrupt(uint32_t baseAddress,uint8_t mask)1179 void EUSCI_A_SPI_enableInterrupt(uint32_t baseAddress, uint8_t mask)
1180 {
1181 ASSERT(
1182 !(mask
1183 & ~(EUSCI_A_SPI_RECEIVE_INTERRUPT
1184 | EUSCI_A_SPI_TRANSMIT_INTERRUPT)));
1185
1186 EUSCI_A_CMSIS(baseAddress)->IE |= mask;
1187 }
1188
1189 //*****************************************************************************
1190 //
1191 //! \brief Disables individual SPI interrupt sources.
1192 //!
1193 //! Disables the indicated SPI interrupt sources. Only the sources that are
1194 //! enabled can be reflected to the processor interrupt; disabled sources have
1195 //! no effect on the processor.
1196 //!
1197 //! \param baseAddress is the base address of the EUSCI_A_SPI module.
1198 //! \param mask is the bit mask of the interrupt sources to be disabled.
1199 //! Mask value is the logical OR of any of the following:
1200 //! - \b EUSCI_A_SPI_TRANSMIT_INTERRUPT
1201 //! - \b EUSCI_A_SPI_RECEIVE_INTERRUPT
1202 //!
1203 //! Modified bits of \b UCAxIE register.
1204 //!
1205 //! \return None
1206 //
1207 //*****************************************************************************
EUSCI_A_SPI_disableInterrupt(uint32_t baseAddress,uint8_t mask)1208 void EUSCI_A_SPI_disableInterrupt(uint32_t baseAddress, uint8_t mask)
1209 {
1210 ASSERT(
1211 !(mask
1212 & ~(EUSCI_A_SPI_RECEIVE_INTERRUPT
1213 | EUSCI_A_SPI_TRANSMIT_INTERRUPT)));
1214
1215 EUSCI_A_CMSIS(baseAddress)->IE &= ~mask;
1216 }
1217
1218 //*****************************************************************************
1219 //
1220 //! \brief Gets the current SPI interrupt status.
1221 //!
1222 //! This returns the interrupt status for the SPI module based on which flag is
1223 //! passed.
1224 //!
1225 //! \param baseAddress is the base address of the EUSCI_A_SPI module.
1226 //! \param mask is the masked interrupt flag status to be returned.
1227 //! Mask value is the logical OR of any of the following:
1228 //! - \b EUSCI_A_SPI_TRANSMIT_INTERRUPT
1229 //! - \b EUSCI_A_SPI_RECEIVE_INTERRUPT
1230 //!
1231 //! \return Logical OR of any of the following:
1232 //! - \b EUSCI_A_SPI_TRANSMIT_INTERRUPT
1233 //! - \b EUSCI_A_SPI_RECEIVE_INTERRUPT
1234 //! \n indicating the status of the masked interrupts
1235 //
1236 //*****************************************************************************
EUSCI_A_SPI_getInterruptStatus(uint32_t baseAddress,uint8_t mask)1237 uint8_t EUSCI_A_SPI_getInterruptStatus(uint32_t baseAddress, uint8_t mask)
1238 {
1239 ASSERT(
1240 !(mask
1241 & ~(EUSCI_A_SPI_RECEIVE_INTERRUPT
1242 | EUSCI_A_SPI_TRANSMIT_INTERRUPT)));
1243
1244 return EUSCI_A_CMSIS(baseAddress)->IFG & mask;
1245 }
1246
1247 //*****************************************************************************
1248 //
1249 //! \brief Clears the selected SPI interrupt status flag.
1250 //!
1251 //! \param baseAddress is the base address of the EUSCI_A_SPI module.
1252 //! \param mask is the masked interrupt flag to be cleared.
1253 //! Mask value is the logical OR of any of the following:
1254 //! - \b EUSCI_A_SPI_TRANSMIT_INTERRUPT
1255 //! - \b EUSCI_A_SPI_RECEIVE_INTERRUPT
1256 //!
1257 //! Modified bits of \b UCAxIFG register.
1258 //!
1259 //! \return None
1260 //
1261 //*****************************************************************************
EUSCI_A_SPI_clearInterruptFlag(uint32_t baseAddress,uint8_t mask)1262 void EUSCI_A_SPI_clearInterruptFlag(uint32_t baseAddress, uint8_t mask)
1263 {
1264 ASSERT(
1265 !(mask
1266 & ~(EUSCI_A_SPI_RECEIVE_INTERRUPT
1267 | EUSCI_A_SPI_TRANSMIT_INTERRUPT)));
1268
1269 EUSCI_A_CMSIS(baseAddress)->IFG &= ~mask;
1270 }
1271
1272 //*****************************************************************************
1273 //
1274 //! \brief Enables the SPI block.
1275 //!
1276 //! This will enable operation of the SPI block.
1277 //!
1278 //! \param baseAddress is the base address of the EUSCI_A_SPI module.
1279 //!
1280 //! Modified bits are \b UCSWRST of \b UCAxCTLW0 register.
1281 //!
1282 //! \return None
1283 //
1284 //*****************************************************************************
EUSCI_A_SPI_enable(uint32_t baseAddress)1285 void EUSCI_A_SPI_enable(uint32_t baseAddress)
1286 {
1287 //Reset the UCSWRST bit to enable the USCI Module
1288 BITBAND_PERI(EUSCI_A_CMSIS(baseAddress)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 0;
1289 }
1290
1291 //*****************************************************************************
1292 //
1293 //! \brief Disables the SPI block.
1294 //!
1295 //! This will disable operation of the SPI block.
1296 //!
1297 //! \param baseAddress is the base address of the EUSCI_A_SPI module.
1298 //!
1299 //! Modified bits are \b UCSWRST of \b UCAxCTLW0 register.
1300 //!
1301 //! \return None
1302 //
1303 //*****************************************************************************
EUSCI_A_SPI_disable(uint32_t baseAddress)1304 void EUSCI_A_SPI_disable(uint32_t baseAddress)
1305 {
1306 //Set the UCSWRST bit to disable the USCI Module
1307 BITBAND_PERI(EUSCI_A_CMSIS(baseAddress)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 1;
1308 }
1309
1310 //*****************************************************************************
1311 //
1312 //! \brief Returns the address of the RX Buffer of the SPI for the DMA module.
1313 //!
1314 //! Returns the address of the SPI RX Buffer. This can be used in conjunction
1315 //! with the DMA to store the received data directly to memory.
1316 //!
1317 //! \param baseAddress is the base address of the EUSCI_A_SPI module.
1318 //!
1319 //! \return the address of the RX Buffer
1320 //
1321 //*****************************************************************************
EUSCI_A_SPI_getReceiveBufferAddressForDMA(uint32_t baseAddress)1322 uint32_t EUSCI_A_SPI_getReceiveBufferAddressForDMA(uint32_t baseAddress)
1323 {
1324 return (uint32_t)&EUSCI_A_CMSIS(baseAddress)->RXBUF;
1325 }
1326
1327 //*****************************************************************************
1328 //
1329 //! \brief Returns the address of the TX Buffer of the SPI for the DMA module.
1330 //!
1331 //! Returns the address of the SPI TX Buffer. This can be used in conjunction
1332 //! with the DMA to obtain transmitted data directly from memory.
1333 //!
1334 //! \param baseAddress is the base address of the EUSCI_A_SPI module.
1335 //!
1336 //! \return the address of the TX Buffer
1337 //
1338 //*****************************************************************************
EUSCI_A_SPI_getTransmitBufferAddressForDMA(uint32_t baseAddress)1339 uint32_t EUSCI_A_SPI_getTransmitBufferAddressForDMA(uint32_t baseAddress)
1340 {
1341 return (uint32_t)&EUSCI_A_CMSIS(baseAddress)->TXBUF;
1342 }
1343
1344 //*****************************************************************************
1345 //
1346 //! \brief Indicates whether or not the SPI bus is busy.
1347 //!
1348 //! This function returns an indication of whether or not the SPI bus is
1349 //! busy.This function checks the status of the bus via UCBBUSY bit
1350 //!
1351 //! \param baseAddress is the base address of the EUSCI_A_SPI module.
1352 //!
1353 //! \return true if busy, false otherwise
1354 //*****************************************************************************
EUSCI_A_SPI_isBusy(uint32_t baseAddress)1355 bool EUSCI_A_SPI_isBusy(uint32_t baseAddress)
1356 {
1357 //Return the bus busy status.
1358 return BITBAND_PERI(EUSCI_A_CMSIS(baseAddress)->STATW, EUSCI_B_STATW_BBUSY_OFS);
1359 }
1360
