1 /**************************************************************************//** 2 * @file 3 * @brief EFR32BG22 CMU register and bit field definitions 4 ****************************************************************************** 5 * # License 6 * <b>Copyright 2023 Silicon Laboratories, Inc. www.silabs.com</b> 7 ****************************************************************************** 8 * 9 * SPDX-License-Identifier: Zlib 10 * 11 * The licensor of this software is Silicon Laboratories Inc. 12 * 13 * This software is provided 'as-is', without any express or implied 14 * warranty. In no event will the authors be held liable for any damages 15 * arising from the use of this software. 16 * 17 * Permission is granted to anyone to use this software for any purpose, 18 * including commercial applications, and to alter it and redistribute it 19 * freely, subject to the following restrictions: 20 * 21 * 1. The origin of this software must not be misrepresented; you must not 22 * claim that you wrote the original software. If you use this software 23 * in a product, an acknowledgment in the product documentation would be 24 * appreciated but is not required. 25 * 2. Altered source versions must be plainly marked as such, and must not be 26 * misrepresented as being the original software. 27 * 3. This notice may not be removed or altered from any source distribution. 28 * 29 *****************************************************************************/ 30 #ifndef EFR32BG22_CMU_H 31 #define EFR32BG22_CMU_H 32 #define CMU_HAS_SET_CLEAR 33 34 /**************************************************************************//** 35 * @addtogroup Parts 36 * @{ 37 ******************************************************************************/ 38 /**************************************************************************//** 39 * @defgroup EFR32BG22_CMU CMU 40 * @{ 41 * @brief EFR32BG22 CMU Register Declaration. 42 *****************************************************************************/ 43 44 /** CMU Register Declaration. */ 45 typedef struct { 46 __IM uint32_t IPVERSION; /**< IP version ID */ 47 uint32_t RESERVED0[1U]; /**< Reserved for future use */ 48 __IM uint32_t STATUS; /**< Status Register */ 49 uint32_t RESERVED1[1U]; /**< Reserved for future use */ 50 __IOM uint32_t LOCK; /**< Configuration Lock Register */ 51 __IOM uint32_t WDOGLOCK; /**< WDOG Configuration Lock Register */ 52 uint32_t RESERVED2[2U]; /**< Reserved for future use */ 53 __IOM uint32_t IF; /**< Interrupt Flag Register */ 54 __IOM uint32_t IEN; /**< Interrupt Enable Register */ 55 uint32_t RESERVED3[10U]; /**< Reserved for future use */ 56 __IOM uint32_t CALCMD; /**< Calibration Command Register */ 57 __IOM uint32_t CALCTRL; /**< Calibration Control Register */ 58 __IM uint32_t CALCNT; /**< Calibration Result Counter Register */ 59 uint32_t RESERVED4[2U]; /**< Reserved for future use */ 60 __IOM uint32_t CLKEN0; /**< Clock Enable Register 0 */ 61 __IOM uint32_t CLKEN1; /**< Clock Enable Register 1 */ 62 uint32_t RESERVED5[1U]; /**< Reserved for future use */ 63 __IOM uint32_t SYSCLKCTRL; /**< System Clock Control */ 64 uint32_t RESERVED6[3U]; /**< Reserved for future use */ 65 __IOM uint32_t TRACECLKCTRL; /**< Debug Trace Clock Control */ 66 uint32_t RESERVED7[3U]; /**< Reserved for future use */ 67 __IOM uint32_t EXPORTCLKCTRL; /**< Export Clock Control */ 68 uint32_t RESERVED8[27U]; /**< Reserved for future use */ 69 __IOM uint32_t DPLLREFCLKCTRL; /**< Digital PLL Reference Clock Control */ 70 uint32_t RESERVED9[7U]; /**< Reserved for future use */ 71 __IOM uint32_t EM01GRPACLKCTRL; /**< EM01 Peripheral Group A Clock Control */ 72 __IOM uint32_t EM01GRPBCLKCTRL; /**< EM01 Peripheral Group B Clock Control */ 73 uint32_t RESERVED10[6U]; /**< Reserved for future use */ 74 __IOM uint32_t EM23GRPACLKCTRL; /**< EM23 Peripheral Group A Clock Control */ 75 uint32_t RESERVED11[7U]; /**< Reserved for future use */ 76 __IOM uint32_t EM4GRPACLKCTRL; /**< EM4 Peripheral Group A Clock Control */ 77 uint32_t RESERVED12[7U]; /**< Reserved for future use */ 78 __IOM uint32_t IADCCLKCTRL; /**< IADC Clock Control */ 79 uint32_t RESERVED13[31U]; /**< Reserved for future use */ 80 __IOM uint32_t WDOG0CLKCTRL; /**< Watchdog0 Clock Control */ 81 uint32_t RESERVED14[7U]; /**< Reserved for future use */ 82 __IOM uint32_t EUART0CLKCTRL; /**< UART Clock Control */ 83 uint32_t RESERVED15[7U]; /**< Reserved for future use */ 84 __IOM uint32_t RTCCCLKCTRL; /**< RTCC Clock Control */ 85 uint32_t RESERVED16[1U]; /**< Reserved for future use */ 86 __IOM uint32_t PRORTCCLKCTRL; /**< Protocol RTC Clock Control */ 87 uint32_t RESERVED17[5U]; /**< Reserved for future use */ 88 __IOM uint32_t CRYPTOACCCLKCTRL; /**< CRYPTOACC Clock Control */ 89 uint32_t RESERVED18[7U]; /**< Reserved for future use */ 90 __IOM uint32_t RADIOCLKCTRL; /**< Radio Clock Control */ 91 uint32_t RESERVED19[863U]; /**< Reserved for future use */ 92 __IM uint32_t IPVERSION_SET; /**< IP version ID */ 93 uint32_t RESERVED20[1U]; /**< Reserved for future use */ 94 __IM uint32_t STATUS_SET; /**< Status Register */ 95 uint32_t RESERVED21[1U]; /**< Reserved for future use */ 96 __IOM uint32_t LOCK_SET; /**< Configuration Lock Register */ 97 __IOM uint32_t WDOGLOCK_SET; /**< WDOG Configuration Lock Register */ 98 uint32_t RESERVED22[2U]; /**< Reserved for future use */ 99 __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ 100 __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ 101 uint32_t RESERVED23[10U]; /**< Reserved for future use */ 102 __IOM uint32_t CALCMD_SET; /**< Calibration Command Register */ 103 __IOM uint32_t CALCTRL_SET; /**< Calibration Control Register */ 104 __IM uint32_t CALCNT_SET; /**< Calibration Result Counter Register */ 105 uint32_t RESERVED24[2U]; /**< Reserved for future use */ 106 __IOM uint32_t CLKEN0_SET; /**< Clock Enable Register 0 */ 107 __IOM uint32_t CLKEN1_SET; /**< Clock Enable Register 1 */ 108 uint32_t RESERVED25[1U]; /**< Reserved for future use */ 109 __IOM uint32_t SYSCLKCTRL_SET; /**< System Clock Control */ 110 uint32_t RESERVED26[3U]; /**< Reserved for future use */ 111 __IOM uint32_t TRACECLKCTRL_SET; /**< Debug Trace Clock Control */ 112 uint32_t RESERVED27[3U]; /**< Reserved for future use */ 113 __IOM uint32_t EXPORTCLKCTRL_SET; /**< Export Clock Control */ 114 uint32_t RESERVED28[27U]; /**< Reserved for future use */ 115 __IOM uint32_t DPLLREFCLKCTRL_SET; /**< Digital PLL Reference Clock Control */ 116 uint32_t RESERVED29[7U]; /**< Reserved for future use */ 117 __IOM uint32_t EM01GRPACLKCTRL_SET; /**< EM01 Peripheral Group A Clock Control */ 118 __IOM uint32_t EM01GRPBCLKCTRL_SET; /**< EM01 Peripheral Group B Clock Control */ 119 uint32_t RESERVED30[6U]; /**< Reserved for future use */ 120 __IOM uint32_t EM23GRPACLKCTRL_SET; /**< EM23 Peripheral Group A Clock Control */ 121 uint32_t RESERVED31[7U]; /**< Reserved for future use */ 122 __IOM uint32_t EM4GRPACLKCTRL_SET; /**< EM4 Peripheral Group A Clock Control */ 123 uint32_t RESERVED32[7U]; /**< Reserved for future use */ 124 __IOM uint32_t IADCCLKCTRL_SET; /**< IADC Clock Control */ 125 uint32_t RESERVED33[31U]; /**< Reserved for future use */ 126 __IOM uint32_t WDOG0CLKCTRL_SET; /**< Watchdog0 Clock Control */ 127 uint32_t RESERVED34[7U]; /**< Reserved for future use */ 128 __IOM uint32_t EUART0CLKCTRL_SET; /**< UART Clock Control */ 129 uint32_t RESERVED35[7U]; /**< Reserved for future use */ 130 __IOM uint32_t RTCCCLKCTRL_SET; /**< RTCC Clock Control */ 131 uint32_t RESERVED36[1U]; /**< Reserved for future use */ 132 __IOM uint32_t PRORTCCLKCTRL_SET; /**< Protocol RTC Clock Control */ 133 uint32_t RESERVED37[5U]; /**< Reserved for future use */ 134 __IOM uint32_t CRYPTOACCCLKCTRL_SET; /**< CRYPTOACC Clock Control */ 135 uint32_t RESERVED38[7U]; /**< Reserved for future use */ 136 __IOM uint32_t RADIOCLKCTRL_SET; /**< Radio Clock Control */ 137 uint32_t RESERVED39[863U]; /**< Reserved for future use */ 138 __IM uint32_t IPVERSION_CLR; /**< IP version ID */ 139 uint32_t RESERVED40[1U]; /**< Reserved for future use */ 140 __IM uint32_t STATUS_CLR; /**< Status Register */ 141 uint32_t RESERVED41[1U]; /**< Reserved for future use */ 142 __IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */ 143 __IOM uint32_t WDOGLOCK_CLR; /**< WDOG Configuration Lock Register */ 144 uint32_t RESERVED42[2U]; /**< Reserved for future use */ 145 __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ 146 __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ 147 uint32_t RESERVED43[10U]; /**< Reserved for future use */ 148 __IOM uint32_t CALCMD_CLR; /**< Calibration Command Register */ 149 __IOM uint32_t CALCTRL_CLR; /**< Calibration Control Register */ 150 __IM uint32_t CALCNT_CLR; /**< Calibration Result Counter Register */ 151 uint32_t RESERVED44[2U]; /**< Reserved for future use */ 152 __IOM uint32_t CLKEN0_CLR; /**< Clock Enable Register 0 */ 153 __IOM uint32_t CLKEN1_CLR; /**< Clock Enable Register 1 */ 154 uint32_t RESERVED45[1U]; /**< Reserved for future use */ 155 __IOM uint32_t SYSCLKCTRL_CLR; /**< System Clock Control */ 156 uint32_t RESERVED46[3U]; /**< Reserved for future use */ 157 __IOM uint32_t TRACECLKCTRL_CLR; /**< Debug Trace Clock Control */ 158 uint32_t RESERVED47[3U]; /**< Reserved for future use */ 159 __IOM uint32_t EXPORTCLKCTRL_CLR; /**< Export Clock Control */ 160 uint32_t RESERVED48[27U]; /**< Reserved for future use */ 161 __IOM uint32_t DPLLREFCLKCTRL_CLR; /**< Digital PLL Reference Clock Control */ 162 uint32_t RESERVED49[7U]; /**< Reserved for future use */ 163 __IOM uint32_t EM01GRPACLKCTRL_CLR; /**< EM01 Peripheral Group A Clock Control */ 164 __IOM uint32_t EM01GRPBCLKCTRL_CLR; /**< EM01 Peripheral Group B Clock Control */ 165 uint32_t RESERVED50[6U]; /**< Reserved for future use */ 166 __IOM uint32_t EM23GRPACLKCTRL_CLR; /**< EM23 Peripheral Group A Clock Control */ 167 uint32_t RESERVED51[7U]; /**< Reserved for future use */ 168 __IOM uint32_t EM4GRPACLKCTRL_CLR; /**< EM4 Peripheral Group A Clock Control */ 169 uint32_t RESERVED52[7U]; /**< Reserved for future use */ 170 __IOM uint32_t IADCCLKCTRL_CLR; /**< IADC Clock Control */ 171 uint32_t RESERVED53[31U]; /**< Reserved for future use */ 172 __IOM uint32_t WDOG0CLKCTRL_CLR; /**< Watchdog0 Clock Control */ 173 uint32_t RESERVED54[7U]; /**< Reserved for future use */ 174 __IOM uint32_t EUART0CLKCTRL_CLR; /**< UART Clock Control */ 175 uint32_t RESERVED55[7U]; /**< Reserved for future use */ 176 __IOM uint32_t RTCCCLKCTRL_CLR; /**< RTCC Clock Control */ 177 uint32_t RESERVED56[1U]; /**< Reserved for future use */ 178 __IOM uint32_t PRORTCCLKCTRL_CLR; /**< Protocol RTC Clock Control */ 179 uint32_t RESERVED57[5U]; /**< Reserved for future use */ 180 __IOM uint32_t CRYPTOACCCLKCTRL_CLR; /**< CRYPTOACC Clock Control */ 181 uint32_t RESERVED58[7U]; /**< Reserved for future use */ 182 __IOM uint32_t RADIOCLKCTRL_CLR; /**< Radio Clock Control */ 183 uint32_t RESERVED59[863U]; /**< Reserved for future use */ 184 __IM uint32_t IPVERSION_TGL; /**< IP version ID */ 185 uint32_t RESERVED60[1U]; /**< Reserved for future use */ 186 __IM uint32_t STATUS_TGL; /**< Status Register */ 187 uint32_t RESERVED61[1U]; /**< Reserved for future use */ 188 __IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */ 189 __IOM uint32_t WDOGLOCK_TGL; /**< WDOG Configuration Lock Register */ 190 uint32_t RESERVED62[2U]; /**< Reserved for future use */ 191 __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ 192 __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ 193 uint32_t RESERVED63[10U]; /**< Reserved for future use */ 194 __IOM uint32_t CALCMD_TGL; /**< Calibration Command Register */ 195 __IOM uint32_t CALCTRL_TGL; /**< Calibration Control Register */ 196 __IM uint32_t CALCNT_TGL; /**< Calibration Result Counter Register */ 197 uint32_t RESERVED64[2U]; /**< Reserved for future use */ 198 __IOM uint32_t CLKEN0_TGL; /**< Clock Enable Register 0 */ 199 __IOM uint32_t CLKEN1_TGL; /**< Clock Enable Register 1 */ 200 uint32_t RESERVED65[1U]; /**< Reserved for future use */ 201 __IOM uint32_t SYSCLKCTRL_TGL; /**< System Clock Control */ 202 uint32_t RESERVED66[3U]; /**< Reserved for future use */ 203 __IOM uint32_t TRACECLKCTRL_TGL; /**< Debug Trace Clock Control */ 204 uint32_t RESERVED67[3U]; /**< Reserved for future use */ 205 __IOM uint32_t EXPORTCLKCTRL_TGL; /**< Export Clock Control */ 206 uint32_t RESERVED68[27U]; /**< Reserved for future use */ 207 __IOM uint32_t DPLLREFCLKCTRL_TGL; /**< Digital PLL Reference Clock Control */ 208 uint32_t RESERVED69[7U]; /**< Reserved for future use */ 209 __IOM uint32_t EM01GRPACLKCTRL_TGL; /**< EM01 Peripheral Group A Clock Control */ 210 __IOM uint32_t EM01GRPBCLKCTRL_TGL; /**< EM01 Peripheral Group B Clock Control */ 211 uint32_t RESERVED70[6U]; /**< Reserved for future use */ 212 __IOM uint32_t EM23GRPACLKCTRL_TGL; /**< EM23 Peripheral Group A Clock Control */ 213 uint32_t RESERVED71[7U]; /**< Reserved for future use */ 214 __IOM uint32_t EM4GRPACLKCTRL_TGL; /**< EM4 Peripheral Group A Clock Control */ 215 uint32_t RESERVED72[7U]; /**< Reserved for future use */ 216 __IOM uint32_t IADCCLKCTRL_TGL; /**< IADC Clock Control */ 217 uint32_t RESERVED73[31U]; /**< Reserved for future use */ 218 __IOM uint32_t WDOG0CLKCTRL_TGL; /**< Watchdog0 Clock Control */ 219 uint32_t RESERVED74[7U]; /**< Reserved for future use */ 220 __IOM uint32_t EUART0CLKCTRL_TGL; /**< UART Clock Control */ 221 uint32_t RESERVED75[7U]; /**< Reserved for future use */ 222 __IOM uint32_t RTCCCLKCTRL_TGL; /**< RTCC Clock Control */ 223 uint32_t RESERVED76[1U]; /**< Reserved for future use */ 224 __IOM uint32_t PRORTCCLKCTRL_TGL; /**< Protocol RTC Clock Control */ 225 uint32_t RESERVED77[5U]; /**< Reserved for future use */ 226 __IOM uint32_t CRYPTOACCCLKCTRL_TGL; /**< CRYPTOACC Clock Control */ 227 uint32_t RESERVED78[7U]; /**< Reserved for future use */ 228 __IOM uint32_t RADIOCLKCTRL_TGL; /**< Radio Clock Control */ 229 } CMU_TypeDef; 230 /** @} End of group EFR32BG22_CMU */ 231 232 /**************************************************************************//** 233 * @addtogroup EFR32BG22_CMU 234 * @{ 235 * @defgroup EFR32BG22_CMU_BitFields CMU Bit Fields 236 * @{ 237 *****************************************************************************/ 238 239 /* Bit fields for CMU IPVERSION */ 240 #define _CMU_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for CMU_IPVERSION */ 241 #define _CMU_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for CMU_IPVERSION */ 242 #define _CMU_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for CMU_IPVERSION */ 243 #define _CMU_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for CMU_IPVERSION */ 244 #define _CMU_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_IPVERSION */ 245 #define CMU_IPVERSION_IPVERSION_DEFAULT (_CMU_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IPVERSION */ 246 247 /* Bit fields for CMU STATUS */ 248 #define _CMU_STATUS_RESETVALUE 0x00000000UL /**< Default value for CMU_STATUS */ 249 #define _CMU_STATUS_MASK 0xC0030001UL /**< Mask for CMU_STATUS */ 250 #define CMU_STATUS_CALRDY (0x1UL << 0) /**< Calibration Ready */ 251 #define _CMU_STATUS_CALRDY_SHIFT 0 /**< Shift value for CMU_CALRDY */ 252 #define _CMU_STATUS_CALRDY_MASK 0x1UL /**< Bit mask for CMU_CALRDY */ 253 #define _CMU_STATUS_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ 254 #define CMU_STATUS_CALRDY_DEFAULT (_CMU_STATUS_CALRDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_STATUS */ 255 #define CMU_STATUS_WDOGLOCK (0x1UL << 30) /**< Configuration Lock Status for WDOG */ 256 #define _CMU_STATUS_WDOGLOCK_SHIFT 30 /**< Shift value for CMU_WDOGLOCK */ 257 #define _CMU_STATUS_WDOGLOCK_MASK 0x40000000UL /**< Bit mask for CMU_WDOGLOCK */ 258 #define _CMU_STATUS_WDOGLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ 259 #define _CMU_STATUS_WDOGLOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for CMU_STATUS */ 260 #define _CMU_STATUS_WDOGLOCK_LOCKED 0x00000001UL /**< Mode LOCKED for CMU_STATUS */ 261 #define CMU_STATUS_WDOGLOCK_DEFAULT (_CMU_STATUS_WDOGLOCK_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_STATUS */ 262 #define CMU_STATUS_WDOGLOCK_UNLOCKED (_CMU_STATUS_WDOGLOCK_UNLOCKED << 30) /**< Shifted mode UNLOCKED for CMU_STATUS */ 263 #define CMU_STATUS_WDOGLOCK_LOCKED (_CMU_STATUS_WDOGLOCK_LOCKED << 30) /**< Shifted mode LOCKED for CMU_STATUS */ 264 #define CMU_STATUS_LOCK (0x1UL << 31) /**< Configuration Lock Status */ 265 #define _CMU_STATUS_LOCK_SHIFT 31 /**< Shift value for CMU_LOCK */ 266 #define _CMU_STATUS_LOCK_MASK 0x80000000UL /**< Bit mask for CMU_LOCK */ 267 #define _CMU_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */ 268 #define _CMU_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for CMU_STATUS */ 269 #define _CMU_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for CMU_STATUS */ 270 #define CMU_STATUS_LOCK_DEFAULT (_CMU_STATUS_LOCK_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_STATUS */ 271 #define CMU_STATUS_LOCK_UNLOCKED (_CMU_STATUS_LOCK_UNLOCKED << 31) /**< Shifted mode UNLOCKED for CMU_STATUS */ 272 #define CMU_STATUS_LOCK_LOCKED (_CMU_STATUS_LOCK_LOCKED << 31) /**< Shifted mode LOCKED for CMU_STATUS */ 273 274 /* Bit fields for CMU LOCK */ 275 #define _CMU_LOCK_RESETVALUE 0x000093F7UL /**< Default value for CMU_LOCK */ 276 #define _CMU_LOCK_MASK 0x0000FFFFUL /**< Mask for CMU_LOCK */ 277 #define _CMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for CMU_LOCKKEY */ 278 #define _CMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for CMU_LOCKKEY */ 279 #define _CMU_LOCK_LOCKKEY_DEFAULT 0x000093F7UL /**< Mode DEFAULT for CMU_LOCK */ 280 #define _CMU_LOCK_LOCKKEY_UNLOCK 0x000093F7UL /**< Mode UNLOCK for CMU_LOCK */ 281 #define CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LOCK */ 282 #define CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_LOCK */ 283 284 /* Bit fields for CMU WDOGLOCK */ 285 #define _CMU_WDOGLOCK_RESETVALUE 0x00005257UL /**< Default value for CMU_WDOGLOCK */ 286 #define _CMU_WDOGLOCK_MASK 0x0000FFFFUL /**< Mask for CMU_WDOGLOCK */ 287 #define _CMU_WDOGLOCK_LOCKKEY_SHIFT 0 /**< Shift value for CMU_LOCKKEY */ 288 #define _CMU_WDOGLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for CMU_LOCKKEY */ 289 #define _CMU_WDOGLOCK_LOCKKEY_DEFAULT 0x00005257UL /**< Mode DEFAULT for CMU_WDOGLOCK */ 290 #define _CMU_WDOGLOCK_LOCKKEY_UNLOCK 0x000093F7UL /**< Mode UNLOCK for CMU_WDOGLOCK */ 291 #define CMU_WDOGLOCK_LOCKKEY_DEFAULT (_CMU_WDOGLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_WDOGLOCK */ 292 #define CMU_WDOGLOCK_LOCKKEY_UNLOCK (_CMU_WDOGLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_WDOGLOCK */ 293 294 /* Bit fields for CMU IF */ 295 #define _CMU_IF_RESETVALUE 0x00000000UL /**< Default value for CMU_IF */ 296 #define _CMU_IF_MASK 0x00000003UL /**< Mask for CMU_IF */ 297 #define CMU_IF_CALRDY (0x1UL << 0) /**< Calibration Ready Interrupt Flag */ 298 #define _CMU_IF_CALRDY_SHIFT 0 /**< Shift value for CMU_CALRDY */ 299 #define _CMU_IF_CALRDY_MASK 0x1UL /**< Bit mask for CMU_CALRDY */ 300 #define _CMU_IF_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ 301 #define CMU_IF_CALRDY_DEFAULT (_CMU_IF_CALRDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IF */ 302 #define CMU_IF_CALOF (0x1UL << 1) /**< Calibration Overflow Interrupt Flag */ 303 #define _CMU_IF_CALOF_SHIFT 1 /**< Shift value for CMU_CALOF */ 304 #define _CMU_IF_CALOF_MASK 0x2UL /**< Bit mask for CMU_CALOF */ 305 #define _CMU_IF_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */ 306 #define CMU_IF_CALOF_DEFAULT (_CMU_IF_CALOF_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IF */ 307 308 /* Bit fields for CMU IEN */ 309 #define _CMU_IEN_RESETVALUE 0x00000000UL /**< Default value for CMU_IEN */ 310 #define _CMU_IEN_MASK 0x00000003UL /**< Mask for CMU_IEN */ 311 #define CMU_IEN_CALRDY (0x1UL << 0) /**< Calibration Ready Interrupt Enable */ 312 #define _CMU_IEN_CALRDY_SHIFT 0 /**< Shift value for CMU_CALRDY */ 313 #define _CMU_IEN_CALRDY_MASK 0x1UL /**< Bit mask for CMU_CALRDY */ 314 #define _CMU_IEN_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ 315 #define CMU_IEN_CALRDY_DEFAULT (_CMU_IEN_CALRDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IEN */ 316 #define CMU_IEN_CALOF (0x1UL << 1) /**< Calibration Overflow Interrupt Enable */ 317 #define _CMU_IEN_CALOF_SHIFT 1 /**< Shift value for CMU_CALOF */ 318 #define _CMU_IEN_CALOF_MASK 0x2UL /**< Bit mask for CMU_CALOF */ 319 #define _CMU_IEN_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */ 320 #define CMU_IEN_CALOF_DEFAULT (_CMU_IEN_CALOF_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IEN */ 321 322 /* Bit fields for CMU CALCMD */ 323 #define _CMU_CALCMD_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCMD */ 324 #define _CMU_CALCMD_MASK 0x00000003UL /**< Mask for CMU_CALCMD */ 325 #define CMU_CALCMD_CALSTART (0x1UL << 0) /**< Calibration Start */ 326 #define _CMU_CALCMD_CALSTART_SHIFT 0 /**< Shift value for CMU_CALSTART */ 327 #define _CMU_CALCMD_CALSTART_MASK 0x1UL /**< Bit mask for CMU_CALSTART */ 328 #define _CMU_CALCMD_CALSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCMD */ 329 #define CMU_CALCMD_CALSTART_DEFAULT (_CMU_CALCMD_CALSTART_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCMD */ 330 #define CMU_CALCMD_CALSTOP (0x1UL << 1) /**< Calibration Stop */ 331 #define _CMU_CALCMD_CALSTOP_SHIFT 1 /**< Shift value for CMU_CALSTOP */ 332 #define _CMU_CALCMD_CALSTOP_MASK 0x2UL /**< Bit mask for CMU_CALSTOP */ 333 #define _CMU_CALCMD_CALSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCMD */ 334 #define CMU_CALCMD_CALSTOP_DEFAULT (_CMU_CALCMD_CALSTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_CALCMD */ 335 336 /* Bit fields for CMU CALCTRL */ 337 #define _CMU_CALCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCTRL */ 338 #define _CMU_CALCTRL_MASK 0xFF8FFFFFUL /**< Mask for CMU_CALCTRL */ 339 #define _CMU_CALCTRL_CALTOP_SHIFT 0 /**< Shift value for CMU_CALTOP */ 340 #define _CMU_CALCTRL_CALTOP_MASK 0xFFFFFUL /**< Bit mask for CMU_CALTOP */ 341 #define _CMU_CALCTRL_CALTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ 342 #define CMU_CALCTRL_CALTOP_DEFAULT (_CMU_CALCTRL_CALTOP_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCTRL */ 343 #define CMU_CALCTRL_CONT (0x1UL << 23) /**< Continuous Calibration */ 344 #define _CMU_CALCTRL_CONT_SHIFT 23 /**< Shift value for CMU_CONT */ 345 #define _CMU_CALCTRL_CONT_MASK 0x800000UL /**< Bit mask for CMU_CONT */ 346 #define _CMU_CALCTRL_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ 347 #define CMU_CALCTRL_CONT_DEFAULT (_CMU_CALCTRL_CONT_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_CALCTRL */ 348 #define _CMU_CALCTRL_UPSEL_SHIFT 24 /**< Shift value for CMU_UPSEL */ 349 #define _CMU_CALCTRL_UPSEL_MASK 0xF000000UL /**< Bit mask for CMU_UPSEL */ 350 #define _CMU_CALCTRL_UPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ 351 #define _CMU_CALCTRL_UPSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CALCTRL */ 352 #define _CMU_CALCTRL_UPSEL_PRS 0x00000001UL /**< Mode PRS for CMU_CALCTRL */ 353 #define _CMU_CALCTRL_UPSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_CALCTRL */ 354 #define _CMU_CALCTRL_UPSEL_LFXO 0x00000003UL /**< Mode LFXO for CMU_CALCTRL */ 355 #define _CMU_CALCTRL_UPSEL_HFRCODPLL 0x00000004UL /**< Mode HFRCODPLL for CMU_CALCTRL */ 356 #define _CMU_CALCTRL_UPSEL_FSRCO 0x00000008UL /**< Mode FSRCO for CMU_CALCTRL */ 357 #define _CMU_CALCTRL_UPSEL_LFRCO 0x00000009UL /**< Mode LFRCO for CMU_CALCTRL */ 358 #define _CMU_CALCTRL_UPSEL_ULFRCO 0x0000000AUL /**< Mode ULFRCO for CMU_CALCTRL */ 359 #define CMU_CALCTRL_UPSEL_DEFAULT (_CMU_CALCTRL_UPSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_CALCTRL */ 360 #define CMU_CALCTRL_UPSEL_DISABLED (_CMU_CALCTRL_UPSEL_DISABLED << 24) /**< Shifted mode DISABLED for CMU_CALCTRL */ 361 #define CMU_CALCTRL_UPSEL_PRS (_CMU_CALCTRL_UPSEL_PRS << 24) /**< Shifted mode PRS for CMU_CALCTRL */ 362 #define CMU_CALCTRL_UPSEL_HFXO (_CMU_CALCTRL_UPSEL_HFXO << 24) /**< Shifted mode HFXO for CMU_CALCTRL */ 363 #define CMU_CALCTRL_UPSEL_LFXO (_CMU_CALCTRL_UPSEL_LFXO << 24) /**< Shifted mode LFXO for CMU_CALCTRL */ 364 #define CMU_CALCTRL_UPSEL_HFRCODPLL (_CMU_CALCTRL_UPSEL_HFRCODPLL << 24) /**< Shifted mode HFRCODPLL for CMU_CALCTRL */ 365 #define CMU_CALCTRL_UPSEL_FSRCO (_CMU_CALCTRL_UPSEL_FSRCO << 24) /**< Shifted mode FSRCO for CMU_CALCTRL */ 366 #define CMU_CALCTRL_UPSEL_LFRCO (_CMU_CALCTRL_UPSEL_LFRCO << 24) /**< Shifted mode LFRCO for CMU_CALCTRL */ 367 #define CMU_CALCTRL_UPSEL_ULFRCO (_CMU_CALCTRL_UPSEL_ULFRCO << 24) /**< Shifted mode ULFRCO for CMU_CALCTRL */ 368 #define _CMU_CALCTRL_DOWNSEL_SHIFT 28 /**< Shift value for CMU_DOWNSEL */ 369 #define _CMU_CALCTRL_DOWNSEL_MASK 0xF0000000UL /**< Bit mask for CMU_DOWNSEL */ 370 #define _CMU_CALCTRL_DOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */ 371 #define _CMU_CALCTRL_DOWNSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_CALCTRL */ 372 #define _CMU_CALCTRL_DOWNSEL_HCLK 0x00000001UL /**< Mode HCLK for CMU_CALCTRL */ 373 #define _CMU_CALCTRL_DOWNSEL_PRS 0x00000002UL /**< Mode PRS for CMU_CALCTRL */ 374 #define _CMU_CALCTRL_DOWNSEL_HFXO 0x00000003UL /**< Mode HFXO for CMU_CALCTRL */ 375 #define _CMU_CALCTRL_DOWNSEL_LFXO 0x00000004UL /**< Mode LFXO for CMU_CALCTRL */ 376 #define _CMU_CALCTRL_DOWNSEL_HFRCODPLL 0x00000005UL /**< Mode HFRCODPLL for CMU_CALCTRL */ 377 #define _CMU_CALCTRL_DOWNSEL_FSRCO 0x00000009UL /**< Mode FSRCO for CMU_CALCTRL */ 378 #define _CMU_CALCTRL_DOWNSEL_LFRCO 0x0000000AUL /**< Mode LFRCO for CMU_CALCTRL */ 379 #define _CMU_CALCTRL_DOWNSEL_ULFRCO 0x0000000BUL /**< Mode ULFRCO for CMU_CALCTRL */ 380 #define CMU_CALCTRL_DOWNSEL_DEFAULT (_CMU_CALCTRL_DOWNSEL_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_CALCTRL */ 381 #define CMU_CALCTRL_DOWNSEL_DISABLED (_CMU_CALCTRL_DOWNSEL_DISABLED << 28) /**< Shifted mode DISABLED for CMU_CALCTRL */ 382 #define CMU_CALCTRL_DOWNSEL_HCLK (_CMU_CALCTRL_DOWNSEL_HCLK << 28) /**< Shifted mode HCLK for CMU_CALCTRL */ 383 #define CMU_CALCTRL_DOWNSEL_PRS (_CMU_CALCTRL_DOWNSEL_PRS << 28) /**< Shifted mode PRS for CMU_CALCTRL */ 384 #define CMU_CALCTRL_DOWNSEL_HFXO (_CMU_CALCTRL_DOWNSEL_HFXO << 28) /**< Shifted mode HFXO for CMU_CALCTRL */ 385 #define CMU_CALCTRL_DOWNSEL_LFXO (_CMU_CALCTRL_DOWNSEL_LFXO << 28) /**< Shifted mode LFXO for CMU_CALCTRL */ 386 #define CMU_CALCTRL_DOWNSEL_HFRCODPLL (_CMU_CALCTRL_DOWNSEL_HFRCODPLL << 28) /**< Shifted mode HFRCODPLL for CMU_CALCTRL */ 387 #define CMU_CALCTRL_DOWNSEL_FSRCO (_CMU_CALCTRL_DOWNSEL_FSRCO << 28) /**< Shifted mode FSRCO for CMU_CALCTRL */ 388 #define CMU_CALCTRL_DOWNSEL_LFRCO (_CMU_CALCTRL_DOWNSEL_LFRCO << 28) /**< Shifted mode LFRCO for CMU_CALCTRL */ 389 #define CMU_CALCTRL_DOWNSEL_ULFRCO (_CMU_CALCTRL_DOWNSEL_ULFRCO << 28) /**< Shifted mode ULFRCO for CMU_CALCTRL */ 390 391 /* Bit fields for CMU CALCNT */ 392 #define _CMU_CALCNT_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCNT */ 393 #define _CMU_CALCNT_MASK 0x000FFFFFUL /**< Mask for CMU_CALCNT */ 394 #define _CMU_CALCNT_CALCNT_SHIFT 0 /**< Shift value for CMU_CALCNT */ 395 #define _CMU_CALCNT_CALCNT_MASK 0xFFFFFUL /**< Bit mask for CMU_CALCNT */ 396 #define _CMU_CALCNT_CALCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCNT */ 397 #define CMU_CALCNT_CALCNT_DEFAULT (_CMU_CALCNT_CALCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCNT */ 398 399 /* Bit fields for CMU CLKEN0 */ 400 #define _CMU_CLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_CLKEN0 */ 401 #define _CMU_CLKEN0_MASK 0xFFFFFFFFUL /**< Mask for CMU_CLKEN0 */ 402 #define CMU_CLKEN0_LDMA (0x1UL << 0) /**< Enable Bus Clock */ 403 #define _CMU_CLKEN0_LDMA_SHIFT 0 /**< Shift value for CMU_LDMA */ 404 #define _CMU_CLKEN0_LDMA_MASK 0x1UL /**< Bit mask for CMU_LDMA */ 405 #define _CMU_CLKEN0_LDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ 406 #define CMU_CLKEN0_LDMA_DEFAULT (_CMU_CLKEN0_LDMA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ 407 #define CMU_CLKEN0_LDMAXBAR (0x1UL << 1) /**< Enable Bus Clock */ 408 #define _CMU_CLKEN0_LDMAXBAR_SHIFT 1 /**< Shift value for CMU_LDMAXBAR */ 409 #define _CMU_CLKEN0_LDMAXBAR_MASK 0x2UL /**< Bit mask for CMU_LDMAXBAR */ 410 #define _CMU_CLKEN0_LDMAXBAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ 411 #define CMU_CLKEN0_LDMAXBAR_DEFAULT (_CMU_CLKEN0_LDMAXBAR_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ 412 #define CMU_CLKEN0_RADIOAES (0x1UL << 2) /**< Enable Bus Clock */ 413 #define _CMU_CLKEN0_RADIOAES_SHIFT 2 /**< Shift value for CMU_RADIOAES */ 414 #define _CMU_CLKEN0_RADIOAES_MASK 0x4UL /**< Bit mask for CMU_RADIOAES */ 415 #define _CMU_CLKEN0_RADIOAES_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ 416 #define CMU_CLKEN0_RADIOAES_DEFAULT (_CMU_CLKEN0_RADIOAES_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ 417 #define CMU_CLKEN0_GPCRC (0x1UL << 3) /**< Enable Bus Clock */ 418 #define _CMU_CLKEN0_GPCRC_SHIFT 3 /**< Shift value for CMU_GPCRC */ 419 #define _CMU_CLKEN0_GPCRC_MASK 0x8UL /**< Bit mask for CMU_GPCRC */ 420 #define _CMU_CLKEN0_GPCRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ 421 #define CMU_CLKEN0_GPCRC_DEFAULT (_CMU_CLKEN0_GPCRC_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ 422 #define CMU_CLKEN0_TIMER0 (0x1UL << 4) /**< Enable Bus Clock */ 423 #define _CMU_CLKEN0_TIMER0_SHIFT 4 /**< Shift value for CMU_TIMER0 */ 424 #define _CMU_CLKEN0_TIMER0_MASK 0x10UL /**< Bit mask for CMU_TIMER0 */ 425 #define _CMU_CLKEN0_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ 426 #define CMU_CLKEN0_TIMER0_DEFAULT (_CMU_CLKEN0_TIMER0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ 427 #define CMU_CLKEN0_TIMER1 (0x1UL << 5) /**< Enable Bus Clock */ 428 #define _CMU_CLKEN0_TIMER1_SHIFT 5 /**< Shift value for CMU_TIMER1 */ 429 #define _CMU_CLKEN0_TIMER1_MASK 0x20UL /**< Bit mask for CMU_TIMER1 */ 430 #define _CMU_CLKEN0_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ 431 #define CMU_CLKEN0_TIMER1_DEFAULT (_CMU_CLKEN0_TIMER1_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ 432 #define CMU_CLKEN0_TIMER2 (0x1UL << 6) /**< Enable Bus Clock */ 433 #define _CMU_CLKEN0_TIMER2_SHIFT 6 /**< Shift value for CMU_TIMER2 */ 434 #define _CMU_CLKEN0_TIMER2_MASK 0x40UL /**< Bit mask for CMU_TIMER2 */ 435 #define _CMU_CLKEN0_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ 436 #define CMU_CLKEN0_TIMER2_DEFAULT (_CMU_CLKEN0_TIMER2_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ 437 #define CMU_CLKEN0_TIMER3 (0x1UL << 7) /**< Enable Bus Clock */ 438 #define _CMU_CLKEN0_TIMER3_SHIFT 7 /**< Shift value for CMU_TIMER3 */ 439 #define _CMU_CLKEN0_TIMER3_MASK 0x80UL /**< Bit mask for CMU_TIMER3 */ 440 #define _CMU_CLKEN0_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ 441 #define CMU_CLKEN0_TIMER3_DEFAULT (_CMU_CLKEN0_TIMER3_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ 442 #define CMU_CLKEN0_USART0 (0x1UL << 8) /**< Enable Bus Clock */ 443 #define _CMU_CLKEN0_USART0_SHIFT 8 /**< Shift value for CMU_USART0 */ 444 #define _CMU_CLKEN0_USART0_MASK 0x100UL /**< Bit mask for CMU_USART0 */ 445 #define _CMU_CLKEN0_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ 446 #define CMU_CLKEN0_USART0_DEFAULT (_CMU_CLKEN0_USART0_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ 447 #define CMU_CLKEN0_USART1 (0x1UL << 9) /**< Enable Bus Clock */ 448 #define _CMU_CLKEN0_USART1_SHIFT 9 /**< Shift value for CMU_USART1 */ 449 #define _CMU_CLKEN0_USART1_MASK 0x200UL /**< Bit mask for CMU_USART1 */ 450 #define _CMU_CLKEN0_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ 451 #define CMU_CLKEN0_USART1_DEFAULT (_CMU_CLKEN0_USART1_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ 452 #define CMU_CLKEN0_IADC0 (0x1UL << 10) /**< Enable Bus Clock */ 453 #define _CMU_CLKEN0_IADC0_SHIFT 10 /**< Shift value for CMU_IADC0 */ 454 #define _CMU_CLKEN0_IADC0_MASK 0x400UL /**< Bit mask for CMU_IADC0 */ 455 #define _CMU_CLKEN0_IADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ 456 #define CMU_CLKEN0_IADC0_DEFAULT (_CMU_CLKEN0_IADC0_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ 457 #define CMU_CLKEN0_AMUXCP0 (0x1UL << 11) /**< Enable Bus Clock */ 458 #define _CMU_CLKEN0_AMUXCP0_SHIFT 11 /**< Shift value for CMU_AMUXCP0 */ 459 #define _CMU_CLKEN0_AMUXCP0_MASK 0x800UL /**< Bit mask for CMU_AMUXCP0 */ 460 #define _CMU_CLKEN0_AMUXCP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ 461 #define CMU_CLKEN0_AMUXCP0_DEFAULT (_CMU_CLKEN0_AMUXCP0_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ 462 #define CMU_CLKEN0_LETIMER0 (0x1UL << 12) /**< Enable Bus Clock */ 463 #define _CMU_CLKEN0_LETIMER0_SHIFT 12 /**< Shift value for CMU_LETIMER0 */ 464 #define _CMU_CLKEN0_LETIMER0_MASK 0x1000UL /**< Bit mask for CMU_LETIMER0 */ 465 #define _CMU_CLKEN0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ 466 #define CMU_CLKEN0_LETIMER0_DEFAULT (_CMU_CLKEN0_LETIMER0_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ 467 #define CMU_CLKEN0_WDOG0 (0x1UL << 13) /**< Enable Bus Clock */ 468 #define _CMU_CLKEN0_WDOG0_SHIFT 13 /**< Shift value for CMU_WDOG0 */ 469 #define _CMU_CLKEN0_WDOG0_MASK 0x2000UL /**< Bit mask for CMU_WDOG0 */ 470 #define _CMU_CLKEN0_WDOG0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ 471 #define CMU_CLKEN0_WDOG0_DEFAULT (_CMU_CLKEN0_WDOG0_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ 472 #define CMU_CLKEN0_I2C0 (0x1UL << 14) /**< Enable Bus Clock */ 473 #define _CMU_CLKEN0_I2C0_SHIFT 14 /**< Shift value for CMU_I2C0 */ 474 #define _CMU_CLKEN0_I2C0_MASK 0x4000UL /**< Bit mask for CMU_I2C0 */ 475 #define _CMU_CLKEN0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ 476 #define CMU_CLKEN0_I2C0_DEFAULT (_CMU_CLKEN0_I2C0_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ 477 #define CMU_CLKEN0_I2C1 (0x1UL << 15) /**< Enable Bus Clock */ 478 #define _CMU_CLKEN0_I2C1_SHIFT 15 /**< Shift value for CMU_I2C1 */ 479 #define _CMU_CLKEN0_I2C1_MASK 0x8000UL /**< Bit mask for CMU_I2C1 */ 480 #define _CMU_CLKEN0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ 481 #define CMU_CLKEN0_I2C1_DEFAULT (_CMU_CLKEN0_I2C1_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ 482 #define CMU_CLKEN0_SYSCFG (0x1UL << 16) /**< Enable Bus Clock */ 483 #define _CMU_CLKEN0_SYSCFG_SHIFT 16 /**< Shift value for CMU_SYSCFG */ 484 #define _CMU_CLKEN0_SYSCFG_MASK 0x10000UL /**< Bit mask for CMU_SYSCFG */ 485 #define _CMU_CLKEN0_SYSCFG_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ 486 #define CMU_CLKEN0_SYSCFG_DEFAULT (_CMU_CLKEN0_SYSCFG_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ 487 #define CMU_CLKEN0_DPLL0 (0x1UL << 17) /**< Enable Bus Clock */ 488 #define _CMU_CLKEN0_DPLL0_SHIFT 17 /**< Shift value for CMU_DPLL0 */ 489 #define _CMU_CLKEN0_DPLL0_MASK 0x20000UL /**< Bit mask for CMU_DPLL0 */ 490 #define _CMU_CLKEN0_DPLL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ 491 #define CMU_CLKEN0_DPLL0_DEFAULT (_CMU_CLKEN0_DPLL0_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ 492 #define CMU_CLKEN0_HFRCO0 (0x1UL << 18) /**< Enable Bus Clock */ 493 #define _CMU_CLKEN0_HFRCO0_SHIFT 18 /**< Shift value for CMU_HFRCO0 */ 494 #define _CMU_CLKEN0_HFRCO0_MASK 0x40000UL /**< Bit mask for CMU_HFRCO0 */ 495 #define _CMU_CLKEN0_HFRCO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ 496 #define CMU_CLKEN0_HFRCO0_DEFAULT (_CMU_CLKEN0_HFRCO0_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ 497 #define CMU_CLKEN0_HFXO0 (0x1UL << 19) /**< Enable Bus Clock */ 498 #define _CMU_CLKEN0_HFXO0_SHIFT 19 /**< Shift value for CMU_HFXO0 */ 499 #define _CMU_CLKEN0_HFXO0_MASK 0x80000UL /**< Bit mask for CMU_HFXO0 */ 500 #define _CMU_CLKEN0_HFXO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ 501 #define CMU_CLKEN0_HFXO0_DEFAULT (_CMU_CLKEN0_HFXO0_DEFAULT << 19) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ 502 #define CMU_CLKEN0_FSRCO (0x1UL << 20) /**< Enable Bus Clock */ 503 #define _CMU_CLKEN0_FSRCO_SHIFT 20 /**< Shift value for CMU_FSRCO */ 504 #define _CMU_CLKEN0_FSRCO_MASK 0x100000UL /**< Bit mask for CMU_FSRCO */ 505 #define _CMU_CLKEN0_FSRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ 506 #define CMU_CLKEN0_FSRCO_DEFAULT (_CMU_CLKEN0_FSRCO_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ 507 #define CMU_CLKEN0_LFRCO (0x1UL << 21) /**< Enable Bus Clock */ 508 #define _CMU_CLKEN0_LFRCO_SHIFT 21 /**< Shift value for CMU_LFRCO */ 509 #define _CMU_CLKEN0_LFRCO_MASK 0x200000UL /**< Bit mask for CMU_LFRCO */ 510 #define _CMU_CLKEN0_LFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ 511 #define CMU_CLKEN0_LFRCO_DEFAULT (_CMU_CLKEN0_LFRCO_DEFAULT << 21) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ 512 #define CMU_CLKEN0_LFXO (0x1UL << 22) /**< Enable Bus Clock */ 513 #define _CMU_CLKEN0_LFXO_SHIFT 22 /**< Shift value for CMU_LFXO */ 514 #define _CMU_CLKEN0_LFXO_MASK 0x400000UL /**< Bit mask for CMU_LFXO */ 515 #define _CMU_CLKEN0_LFXO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ 516 #define CMU_CLKEN0_LFXO_DEFAULT (_CMU_CLKEN0_LFXO_DEFAULT << 22) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ 517 #define CMU_CLKEN0_ULFRCO (0x1UL << 23) /**< Enable Bus Clock */ 518 #define _CMU_CLKEN0_ULFRCO_SHIFT 23 /**< Shift value for CMU_ULFRCO */ 519 #define _CMU_CLKEN0_ULFRCO_MASK 0x800000UL /**< Bit mask for CMU_ULFRCO */ 520 #define _CMU_CLKEN0_ULFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ 521 #define CMU_CLKEN0_ULFRCO_DEFAULT (_CMU_CLKEN0_ULFRCO_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ 522 #define CMU_CLKEN0_EUART0 (0x1UL << 24) /**< Enable Bus Clock */ 523 #define _CMU_CLKEN0_EUART0_SHIFT 24 /**< Shift value for CMU_EUART0 */ 524 #define _CMU_CLKEN0_EUART0_MASK 0x1000000UL /**< Bit mask for CMU_EUART0 */ 525 #define _CMU_CLKEN0_EUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ 526 #define CMU_CLKEN0_EUART0_DEFAULT (_CMU_CLKEN0_EUART0_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ 527 #define CMU_CLKEN0_PDM (0x1UL << 25) /**< Enable Bus Clock */ 528 #define _CMU_CLKEN0_PDM_SHIFT 25 /**< Shift value for CMU_PDM */ 529 #define _CMU_CLKEN0_PDM_MASK 0x2000000UL /**< Bit mask for CMU_PDM */ 530 #define _CMU_CLKEN0_PDM_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ 531 #define CMU_CLKEN0_PDM_DEFAULT (_CMU_CLKEN0_PDM_DEFAULT << 25) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ 532 #define CMU_CLKEN0_GPIO (0x1UL << 26) /**< Enable Bus Clock */ 533 #define _CMU_CLKEN0_GPIO_SHIFT 26 /**< Shift value for CMU_GPIO */ 534 #define _CMU_CLKEN0_GPIO_MASK 0x4000000UL /**< Bit mask for CMU_GPIO */ 535 #define _CMU_CLKEN0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ 536 #define CMU_CLKEN0_GPIO_DEFAULT (_CMU_CLKEN0_GPIO_DEFAULT << 26) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ 537 #define CMU_CLKEN0_PRS (0x1UL << 27) /**< Enable Bus Clock */ 538 #define _CMU_CLKEN0_PRS_SHIFT 27 /**< Shift value for CMU_PRS */ 539 #define _CMU_CLKEN0_PRS_MASK 0x8000000UL /**< Bit mask for CMU_PRS */ 540 #define _CMU_CLKEN0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ 541 #define CMU_CLKEN0_PRS_DEFAULT (_CMU_CLKEN0_PRS_DEFAULT << 27) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ 542 #define CMU_CLKEN0_BURAM (0x1UL << 28) /**< Enable Bus Clock */ 543 #define _CMU_CLKEN0_BURAM_SHIFT 28 /**< Shift value for CMU_BURAM */ 544 #define _CMU_CLKEN0_BURAM_MASK 0x10000000UL /**< Bit mask for CMU_BURAM */ 545 #define _CMU_CLKEN0_BURAM_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ 546 #define CMU_CLKEN0_BURAM_DEFAULT (_CMU_CLKEN0_BURAM_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ 547 #define CMU_CLKEN0_BURTC (0x1UL << 29) /**< Enable Bus Clock */ 548 #define _CMU_CLKEN0_BURTC_SHIFT 29 /**< Shift value for CMU_BURTC */ 549 #define _CMU_CLKEN0_BURTC_MASK 0x20000000UL /**< Bit mask for CMU_BURTC */ 550 #define _CMU_CLKEN0_BURTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ 551 #define CMU_CLKEN0_BURTC_DEFAULT (_CMU_CLKEN0_BURTC_DEFAULT << 29) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ 552 #define CMU_CLKEN0_RTCC (0x1UL << 30) /**< Enable Bus Clock */ 553 #define _CMU_CLKEN0_RTCC_SHIFT 30 /**< Shift value for CMU_RTCC */ 554 #define _CMU_CLKEN0_RTCC_MASK 0x40000000UL /**< Bit mask for CMU_RTCC */ 555 #define _CMU_CLKEN0_RTCC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ 556 #define CMU_CLKEN0_RTCC_DEFAULT (_CMU_CLKEN0_RTCC_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ 557 #define CMU_CLKEN0_DCDC (0x1UL << 31) /**< Enable Bus Clock */ 558 #define _CMU_CLKEN0_DCDC_SHIFT 31 /**< Shift value for CMU_DCDC */ 559 #define _CMU_CLKEN0_DCDC_MASK 0x80000000UL /**< Bit mask for CMU_DCDC */ 560 #define _CMU_CLKEN0_DCDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN0 */ 561 #define CMU_CLKEN0_DCDC_DEFAULT (_CMU_CLKEN0_DCDC_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_CLKEN0 */ 562 563 /* Bit fields for CMU CLKEN1 */ 564 #define _CMU_CLKEN1_RESETVALUE 0x00000000UL /**< Default value for CMU_CLKEN1 */ 565 #define _CMU_CLKEN1_MASK 0x0007FFFFUL /**< Mask for CMU_CLKEN1 */ 566 #define CMU_CLKEN1_AGC (0x1UL << 0) /**< Enable Bus Clock */ 567 #define _CMU_CLKEN1_AGC_SHIFT 0 /**< Shift value for CMU_AGC */ 568 #define _CMU_CLKEN1_AGC_MASK 0x1UL /**< Bit mask for CMU_AGC */ 569 #define _CMU_CLKEN1_AGC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ 570 #define CMU_CLKEN1_AGC_DEFAULT (_CMU_CLKEN1_AGC_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ 571 #define CMU_CLKEN1_MODEM (0x1UL << 1) /**< Enable Bus Clock */ 572 #define _CMU_CLKEN1_MODEM_SHIFT 1 /**< Shift value for CMU_MODEM */ 573 #define _CMU_CLKEN1_MODEM_MASK 0x2UL /**< Bit mask for CMU_MODEM */ 574 #define _CMU_CLKEN1_MODEM_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ 575 #define CMU_CLKEN1_MODEM_DEFAULT (_CMU_CLKEN1_MODEM_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ 576 #define CMU_CLKEN1_RFCRC (0x1UL << 2) /**< Enable Bus Clock */ 577 #define _CMU_CLKEN1_RFCRC_SHIFT 2 /**< Shift value for CMU_RFCRC */ 578 #define _CMU_CLKEN1_RFCRC_MASK 0x4UL /**< Bit mask for CMU_RFCRC */ 579 #define _CMU_CLKEN1_RFCRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ 580 #define CMU_CLKEN1_RFCRC_DEFAULT (_CMU_CLKEN1_RFCRC_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ 581 #define CMU_CLKEN1_FRC (0x1UL << 3) /**< Enable Bus Clock */ 582 #define _CMU_CLKEN1_FRC_SHIFT 3 /**< Shift value for CMU_FRC */ 583 #define _CMU_CLKEN1_FRC_MASK 0x8UL /**< Bit mask for CMU_FRC */ 584 #define _CMU_CLKEN1_FRC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ 585 #define CMU_CLKEN1_FRC_DEFAULT (_CMU_CLKEN1_FRC_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ 586 #define CMU_CLKEN1_PROTIMER (0x1UL << 4) /**< Enable Bus Clock */ 587 #define _CMU_CLKEN1_PROTIMER_SHIFT 4 /**< Shift value for CMU_PROTIMER */ 588 #define _CMU_CLKEN1_PROTIMER_MASK 0x10UL /**< Bit mask for CMU_PROTIMER */ 589 #define _CMU_CLKEN1_PROTIMER_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ 590 #define CMU_CLKEN1_PROTIMER_DEFAULT (_CMU_CLKEN1_PROTIMER_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ 591 #define CMU_CLKEN1_RAC (0x1UL << 5) /**< Enable Bus Clock */ 592 #define _CMU_CLKEN1_RAC_SHIFT 5 /**< Shift value for CMU_RAC */ 593 #define _CMU_CLKEN1_RAC_MASK 0x20UL /**< Bit mask for CMU_RAC */ 594 #define _CMU_CLKEN1_RAC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ 595 #define CMU_CLKEN1_RAC_DEFAULT (_CMU_CLKEN1_RAC_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ 596 #define CMU_CLKEN1_SYNTH (0x1UL << 6) /**< Enable Bus Clock */ 597 #define _CMU_CLKEN1_SYNTH_SHIFT 6 /**< Shift value for CMU_SYNTH */ 598 #define _CMU_CLKEN1_SYNTH_MASK 0x40UL /**< Bit mask for CMU_SYNTH */ 599 #define _CMU_CLKEN1_SYNTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ 600 #define CMU_CLKEN1_SYNTH_DEFAULT (_CMU_CLKEN1_SYNTH_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ 601 #define CMU_CLKEN1_RDSCRATCHPAD (0x1UL << 7) /**< Enable Bus Clock */ 602 #define _CMU_CLKEN1_RDSCRATCHPAD_SHIFT 7 /**< Shift value for CMU_RDSCRATCHPAD */ 603 #define _CMU_CLKEN1_RDSCRATCHPAD_MASK 0x80UL /**< Bit mask for CMU_RDSCRATCHPAD */ 604 #define _CMU_CLKEN1_RDSCRATCHPAD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ 605 #define CMU_CLKEN1_RDSCRATCHPAD_DEFAULT (_CMU_CLKEN1_RDSCRATCHPAD_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ 606 #define CMU_CLKEN1_RDMAILBOX0 (0x1UL << 8) /**< Enable Bus Clock */ 607 #define _CMU_CLKEN1_RDMAILBOX0_SHIFT 8 /**< Shift value for CMU_RDMAILBOX0 */ 608 #define _CMU_CLKEN1_RDMAILBOX0_MASK 0x100UL /**< Bit mask for CMU_RDMAILBOX0 */ 609 #define _CMU_CLKEN1_RDMAILBOX0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ 610 #define CMU_CLKEN1_RDMAILBOX0_DEFAULT (_CMU_CLKEN1_RDMAILBOX0_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ 611 #define CMU_CLKEN1_RDMAILBOX1 (0x1UL << 9) /**< Enable Bus Clock */ 612 #define _CMU_CLKEN1_RDMAILBOX1_SHIFT 9 /**< Shift value for CMU_RDMAILBOX1 */ 613 #define _CMU_CLKEN1_RDMAILBOX1_MASK 0x200UL /**< Bit mask for CMU_RDMAILBOX1 */ 614 #define _CMU_CLKEN1_RDMAILBOX1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ 615 #define CMU_CLKEN1_RDMAILBOX1_DEFAULT (_CMU_CLKEN1_RDMAILBOX1_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ 616 #define CMU_CLKEN1_PRORTC (0x1UL << 10) /**< Enable Bus Clock */ 617 #define _CMU_CLKEN1_PRORTC_SHIFT 10 /**< Shift value for CMU_PRORTC */ 618 #define _CMU_CLKEN1_PRORTC_MASK 0x400UL /**< Bit mask for CMU_PRORTC */ 619 #define _CMU_CLKEN1_PRORTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ 620 #define CMU_CLKEN1_PRORTC_DEFAULT (_CMU_CLKEN1_PRORTC_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ 621 #define CMU_CLKEN1_BUFC (0x1UL << 11) /**< Enable Bus Clock */ 622 #define _CMU_CLKEN1_BUFC_SHIFT 11 /**< Shift value for CMU_BUFC */ 623 #define _CMU_CLKEN1_BUFC_MASK 0x800UL /**< Bit mask for CMU_BUFC */ 624 #define _CMU_CLKEN1_BUFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ 625 #define CMU_CLKEN1_BUFC_DEFAULT (_CMU_CLKEN1_BUFC_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ 626 #define CMU_CLKEN1_IFADCDEBUG (0x1UL << 12) /**< Enable Bus Clock */ 627 #define _CMU_CLKEN1_IFADCDEBUG_SHIFT 12 /**< Shift value for CMU_IFADCDEBUG */ 628 #define _CMU_CLKEN1_IFADCDEBUG_MASK 0x1000UL /**< Bit mask for CMU_IFADCDEBUG */ 629 #define _CMU_CLKEN1_IFADCDEBUG_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ 630 #define CMU_CLKEN1_IFADCDEBUG_DEFAULT (_CMU_CLKEN1_IFADCDEBUG_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ 631 #define CMU_CLKEN1_CRYPTOACC (0x1UL << 13) /**< Enable Bus Clock */ 632 #define _CMU_CLKEN1_CRYPTOACC_SHIFT 13 /**< Shift value for CMU_CRYPTOACC */ 633 #define _CMU_CLKEN1_CRYPTOACC_MASK 0x2000UL /**< Bit mask for CMU_CRYPTOACC */ 634 #define _CMU_CLKEN1_CRYPTOACC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ 635 #define CMU_CLKEN1_CRYPTOACC_DEFAULT (_CMU_CLKEN1_CRYPTOACC_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ 636 #define CMU_CLKEN1_RFSENSE (0x1UL << 14) /**< Enable Bus Clock */ 637 #define _CMU_CLKEN1_RFSENSE_SHIFT 14 /**< Shift value for CMU_RFSENSE */ 638 #define _CMU_CLKEN1_RFSENSE_MASK 0x4000UL /**< Bit mask for CMU_RFSENSE */ 639 #define _CMU_CLKEN1_RFSENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ 640 #define CMU_CLKEN1_RFSENSE_DEFAULT (_CMU_CLKEN1_RFSENSE_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ 641 #define CMU_CLKEN1_SMU (0x1UL << 15) /**< Enable Bus Clock */ 642 #define _CMU_CLKEN1_SMU_SHIFT 15 /**< Shift value for CMU_SMU */ 643 #define _CMU_CLKEN1_SMU_MASK 0x8000UL /**< Bit mask for CMU_SMU */ 644 #define _CMU_CLKEN1_SMU_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ 645 #define CMU_CLKEN1_SMU_DEFAULT (_CMU_CLKEN1_SMU_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ 646 #define CMU_CLKEN1_ICACHE0 (0x1UL << 16) /**< Enable Bus Clock */ 647 #define _CMU_CLKEN1_ICACHE0_SHIFT 16 /**< Shift value for CMU_ICACHE0 */ 648 #define _CMU_CLKEN1_ICACHE0_MASK 0x10000UL /**< Bit mask for CMU_ICACHE0 */ 649 #define _CMU_CLKEN1_ICACHE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ 650 #define CMU_CLKEN1_ICACHE0_DEFAULT (_CMU_CLKEN1_ICACHE0_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ 651 #define CMU_CLKEN1_MSC (0x1UL << 17) /**< Enable Bus Clock */ 652 #define _CMU_CLKEN1_MSC_SHIFT 17 /**< Shift value for CMU_MSC */ 653 #define _CMU_CLKEN1_MSC_MASK 0x20000UL /**< Bit mask for CMU_MSC */ 654 #define _CMU_CLKEN1_MSC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ 655 #define CMU_CLKEN1_MSC_DEFAULT (_CMU_CLKEN1_MSC_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ 656 #define CMU_CLKEN1_TIMER4 (0x1UL << 18) /**< Enable Bus Clock */ 657 #define _CMU_CLKEN1_TIMER4_SHIFT 18 /**< Shift value for CMU_TIMER4 */ 658 #define _CMU_CLKEN1_TIMER4_MASK 0x40000UL /**< Bit mask for CMU_TIMER4 */ 659 #define _CMU_CLKEN1_TIMER4_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CLKEN1 */ 660 #define CMU_CLKEN1_TIMER4_DEFAULT (_CMU_CLKEN1_TIMER4_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_CLKEN1 */ 661 662 /* Bit fields for CMU SYSCLKCTRL */ 663 #define _CMU_SYSCLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_SYSCLKCTRL */ 664 #define _CMU_SYSCLKCTRL_MASK 0x0001F507UL /**< Mask for CMU_SYSCLKCTRL */ 665 #define _CMU_SYSCLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ 666 #define _CMU_SYSCLKCTRL_CLKSEL_MASK 0x7UL /**< Bit mask for CMU_CLKSEL */ 667 #define _CMU_SYSCLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_SYSCLKCTRL */ 668 #define _CMU_SYSCLKCTRL_CLKSEL_FSRCO 0x00000001UL /**< Mode FSRCO for CMU_SYSCLKCTRL */ 669 #define _CMU_SYSCLKCTRL_CLKSEL_HFRCODPLL 0x00000002UL /**< Mode HFRCODPLL for CMU_SYSCLKCTRL */ 670 #define _CMU_SYSCLKCTRL_CLKSEL_HFXO 0x00000003UL /**< Mode HFXO for CMU_SYSCLKCTRL */ 671 #define _CMU_SYSCLKCTRL_CLKSEL_CLKIN0 0x00000004UL /**< Mode CLKIN0 for CMU_SYSCLKCTRL */ 672 #define CMU_SYSCLKCTRL_CLKSEL_DEFAULT (_CMU_SYSCLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_SYSCLKCTRL */ 673 #define CMU_SYSCLKCTRL_CLKSEL_FSRCO (_CMU_SYSCLKCTRL_CLKSEL_FSRCO << 0) /**< Shifted mode FSRCO for CMU_SYSCLKCTRL */ 674 #define CMU_SYSCLKCTRL_CLKSEL_HFRCODPLL (_CMU_SYSCLKCTRL_CLKSEL_HFRCODPLL << 0) /**< Shifted mode HFRCODPLL for CMU_SYSCLKCTRL */ 675 #define CMU_SYSCLKCTRL_CLKSEL_HFXO (_CMU_SYSCLKCTRL_CLKSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_SYSCLKCTRL */ 676 #define CMU_SYSCLKCTRL_CLKSEL_CLKIN0 (_CMU_SYSCLKCTRL_CLKSEL_CLKIN0 << 0) /**< Shifted mode CLKIN0 for CMU_SYSCLKCTRL */ 677 #define CMU_SYSCLKCTRL_PCLKPRESC (0x1UL << 10) /**< PCLK Prescaler */ 678 #define _CMU_SYSCLKCTRL_PCLKPRESC_SHIFT 10 /**< Shift value for CMU_PCLKPRESC */ 679 #define _CMU_SYSCLKCTRL_PCLKPRESC_MASK 0x400UL /**< Bit mask for CMU_PCLKPRESC */ 680 #define _CMU_SYSCLKCTRL_PCLKPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYSCLKCTRL */ 681 #define _CMU_SYSCLKCTRL_PCLKPRESC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_SYSCLKCTRL */ 682 #define _CMU_SYSCLKCTRL_PCLKPRESC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_SYSCLKCTRL */ 683 #define CMU_SYSCLKCTRL_PCLKPRESC_DEFAULT (_CMU_SYSCLKCTRL_PCLKPRESC_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_SYSCLKCTRL */ 684 #define CMU_SYSCLKCTRL_PCLKPRESC_DIV1 (_CMU_SYSCLKCTRL_PCLKPRESC_DIV1 << 10) /**< Shifted mode DIV1 for CMU_SYSCLKCTRL */ 685 #define CMU_SYSCLKCTRL_PCLKPRESC_DIV2 (_CMU_SYSCLKCTRL_PCLKPRESC_DIV2 << 10) /**< Shifted mode DIV2 for CMU_SYSCLKCTRL */ 686 #define _CMU_SYSCLKCTRL_HCLKPRESC_SHIFT 12 /**< Shift value for CMU_HCLKPRESC */ 687 #define _CMU_SYSCLKCTRL_HCLKPRESC_MASK 0xF000UL /**< Bit mask for CMU_HCLKPRESC */ 688 #define _CMU_SYSCLKCTRL_HCLKPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYSCLKCTRL */ 689 #define _CMU_SYSCLKCTRL_HCLKPRESC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_SYSCLKCTRL */ 690 #define _CMU_SYSCLKCTRL_HCLKPRESC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_SYSCLKCTRL */ 691 #define _CMU_SYSCLKCTRL_HCLKPRESC_DIV4 0x00000003UL /**< Mode DIV4 for CMU_SYSCLKCTRL */ 692 #define _CMU_SYSCLKCTRL_HCLKPRESC_DIV8 0x00000007UL /**< Mode DIV8 for CMU_SYSCLKCTRL */ 693 #define _CMU_SYSCLKCTRL_HCLKPRESC_DIV16 0x0000000FUL /**< Mode DIV16 for CMU_SYSCLKCTRL */ 694 #define CMU_SYSCLKCTRL_HCLKPRESC_DEFAULT (_CMU_SYSCLKCTRL_HCLKPRESC_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_SYSCLKCTRL */ 695 #define CMU_SYSCLKCTRL_HCLKPRESC_DIV1 (_CMU_SYSCLKCTRL_HCLKPRESC_DIV1 << 12) /**< Shifted mode DIV1 for CMU_SYSCLKCTRL */ 696 #define CMU_SYSCLKCTRL_HCLKPRESC_DIV2 (_CMU_SYSCLKCTRL_HCLKPRESC_DIV2 << 12) /**< Shifted mode DIV2 for CMU_SYSCLKCTRL */ 697 #define CMU_SYSCLKCTRL_HCLKPRESC_DIV4 (_CMU_SYSCLKCTRL_HCLKPRESC_DIV4 << 12) /**< Shifted mode DIV4 for CMU_SYSCLKCTRL */ 698 #define CMU_SYSCLKCTRL_HCLKPRESC_DIV8 (_CMU_SYSCLKCTRL_HCLKPRESC_DIV8 << 12) /**< Shifted mode DIV8 for CMU_SYSCLKCTRL */ 699 #define CMU_SYSCLKCTRL_HCLKPRESC_DIV16 (_CMU_SYSCLKCTRL_HCLKPRESC_DIV16 << 12) /**< Shifted mode DIV16 for CMU_SYSCLKCTRL */ 700 #define CMU_SYSCLKCTRL_RHCLKPRESC (0x1UL << 16) /**< Radio HCLK Prescaler */ 701 #define _CMU_SYSCLKCTRL_RHCLKPRESC_SHIFT 16 /**< Shift value for CMU_RHCLKPRESC */ 702 #define _CMU_SYSCLKCTRL_RHCLKPRESC_MASK 0x10000UL /**< Bit mask for CMU_RHCLKPRESC */ 703 #define _CMU_SYSCLKCTRL_RHCLKPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYSCLKCTRL */ 704 #define _CMU_SYSCLKCTRL_RHCLKPRESC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_SYSCLKCTRL */ 705 #define _CMU_SYSCLKCTRL_RHCLKPRESC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_SYSCLKCTRL */ 706 #define CMU_SYSCLKCTRL_RHCLKPRESC_DEFAULT (_CMU_SYSCLKCTRL_RHCLKPRESC_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_SYSCLKCTRL */ 707 #define CMU_SYSCLKCTRL_RHCLKPRESC_DIV1 (_CMU_SYSCLKCTRL_RHCLKPRESC_DIV1 << 16) /**< Shifted mode DIV1 for CMU_SYSCLKCTRL */ 708 #define CMU_SYSCLKCTRL_RHCLKPRESC_DIV2 (_CMU_SYSCLKCTRL_RHCLKPRESC_DIV2 << 16) /**< Shifted mode DIV2 for CMU_SYSCLKCTRL */ 709 710 /* Bit fields for CMU TRACECLKCTRL */ 711 #define _CMU_TRACECLKCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_TRACECLKCTRL */ 712 #define _CMU_TRACECLKCTRL_MASK 0x00000030UL /**< Mask for CMU_TRACECLKCTRL */ 713 #define _CMU_TRACECLKCTRL_PRESC_SHIFT 4 /**< Shift value for CMU_PRESC */ 714 #define _CMU_TRACECLKCTRL_PRESC_MASK 0x30UL /**< Bit mask for CMU_PRESC */ 715 #define _CMU_TRACECLKCTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_TRACECLKCTRL */ 716 #define _CMU_TRACECLKCTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_TRACECLKCTRL */ 717 #define _CMU_TRACECLKCTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_TRACECLKCTRL */ 718 #define _CMU_TRACECLKCTRL_PRESC_DIV4 0x00000003UL /**< Mode DIV4 for CMU_TRACECLKCTRL */ 719 #define CMU_TRACECLKCTRL_PRESC_DEFAULT (_CMU_TRACECLKCTRL_PRESC_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_TRACECLKCTRL */ 720 #define CMU_TRACECLKCTRL_PRESC_DIV1 (_CMU_TRACECLKCTRL_PRESC_DIV1 << 4) /**< Shifted mode DIV1 for CMU_TRACECLKCTRL */ 721 #define CMU_TRACECLKCTRL_PRESC_DIV2 (_CMU_TRACECLKCTRL_PRESC_DIV2 << 4) /**< Shifted mode DIV2 for CMU_TRACECLKCTRL */ 722 #define CMU_TRACECLKCTRL_PRESC_DIV4 (_CMU_TRACECLKCTRL_PRESC_DIV4 << 4) /**< Shifted mode DIV4 for CMU_TRACECLKCTRL */ 723 724 /* Bit fields for CMU EXPORTCLKCTRL */ 725 #define _CMU_EXPORTCLKCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_EXPORTCLKCTRL */ 726 #define _CMU_EXPORTCLKCTRL_MASK 0x1F0F0F0FUL /**< Mask for CMU_EXPORTCLKCTRL */ 727 #define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_SHIFT 0 /**< Shift value for CMU_CLKOUTSEL0 */ 728 #define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_MASK 0xFUL /**< Bit mask for CMU_CLKOUTSEL0 */ 729 #define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_EXPORTCLKCTRL */ 730 #define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_EXPORTCLKCTRL */ 731 #define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_HCLK 0x00000001UL /**< Mode HCLK for CMU_EXPORTCLKCTRL */ 732 #define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFEXPCLK 0x00000002UL /**< Mode HFEXPCLK for CMU_EXPORTCLKCTRL */ 733 #define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_EXPORTCLKCTRL */ 734 #define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_EXPORTCLKCTRL */ 735 #define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_LFXO 0x00000005UL /**< Mode LFXO for CMU_EXPORTCLKCTRL */ 736 #define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFRCODPLL 0x00000006UL /**< Mode HFRCODPLL for CMU_EXPORTCLKCTRL */ 737 #define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFXO 0x00000007UL /**< Mode HFXO for CMU_EXPORTCLKCTRL */ 738 #define _CMU_EXPORTCLKCTRL_CLKOUTSEL0_FSRCO 0x00000008UL /**< Mode FSRCO for CMU_EXPORTCLKCTRL */ 739 #define CMU_EXPORTCLKCTRL_CLKOUTSEL0_DEFAULT (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_EXPORTCLKCTRL */ 740 #define CMU_EXPORTCLKCTRL_CLKOUTSEL0_DISABLED (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_DISABLED << 0) /**< Shifted mode DISABLED for CMU_EXPORTCLKCTRL */ 741 #define CMU_EXPORTCLKCTRL_CLKOUTSEL0_HCLK (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_HCLK << 0) /**< Shifted mode HCLK for CMU_EXPORTCLKCTRL */ 742 #define CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFEXPCLK (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFEXPCLK << 0) /**< Shifted mode HFEXPCLK for CMU_EXPORTCLKCTRL */ 743 #define CMU_EXPORTCLKCTRL_CLKOUTSEL0_ULFRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_EXPORTCLKCTRL */ 744 #define CMU_EXPORTCLKCTRL_CLKOUTSEL0_LFRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_LFRCO << 0) /**< Shifted mode LFRCO for CMU_EXPORTCLKCTRL */ 745 #define CMU_EXPORTCLKCTRL_CLKOUTSEL0_LFXO (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_LFXO << 0) /**< Shifted mode LFXO for CMU_EXPORTCLKCTRL */ 746 #define CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFRCODPLL (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFRCODPLL << 0) /**< Shifted mode HFRCODPLL for CMU_EXPORTCLKCTRL*/ 747 #define CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFXO (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_HFXO << 0) /**< Shifted mode HFXO for CMU_EXPORTCLKCTRL */ 748 #define CMU_EXPORTCLKCTRL_CLKOUTSEL0_FSRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL0_FSRCO << 0) /**< Shifted mode FSRCO for CMU_EXPORTCLKCTRL */ 749 #define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_SHIFT 8 /**< Shift value for CMU_CLKOUTSEL1 */ 750 #define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_MASK 0xF00UL /**< Bit mask for CMU_CLKOUTSEL1 */ 751 #define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_EXPORTCLKCTRL */ 752 #define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_EXPORTCLKCTRL */ 753 #define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_HCLK 0x00000001UL /**< Mode HCLK for CMU_EXPORTCLKCTRL */ 754 #define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFEXPCLK 0x00000002UL /**< Mode HFEXPCLK for CMU_EXPORTCLKCTRL */ 755 #define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_EXPORTCLKCTRL */ 756 #define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_EXPORTCLKCTRL */ 757 #define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_LFXO 0x00000005UL /**< Mode LFXO for CMU_EXPORTCLKCTRL */ 758 #define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFRCODPLL 0x00000006UL /**< Mode HFRCODPLL for CMU_EXPORTCLKCTRL */ 759 #define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFXO 0x00000007UL /**< Mode HFXO for CMU_EXPORTCLKCTRL */ 760 #define _CMU_EXPORTCLKCTRL_CLKOUTSEL1_FSRCO 0x00000008UL /**< Mode FSRCO for CMU_EXPORTCLKCTRL */ 761 #define CMU_EXPORTCLKCTRL_CLKOUTSEL1_DEFAULT (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_EXPORTCLKCTRL */ 762 #define CMU_EXPORTCLKCTRL_CLKOUTSEL1_DISABLED (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_DISABLED << 8) /**< Shifted mode DISABLED for CMU_EXPORTCLKCTRL */ 763 #define CMU_EXPORTCLKCTRL_CLKOUTSEL1_HCLK (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_HCLK << 8) /**< Shifted mode HCLK for CMU_EXPORTCLKCTRL */ 764 #define CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFEXPCLK (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFEXPCLK << 8) /**< Shifted mode HFEXPCLK for CMU_EXPORTCLKCTRL */ 765 #define CMU_EXPORTCLKCTRL_CLKOUTSEL1_ULFRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_ULFRCO << 8) /**< Shifted mode ULFRCO for CMU_EXPORTCLKCTRL */ 766 #define CMU_EXPORTCLKCTRL_CLKOUTSEL1_LFRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_LFRCO << 8) /**< Shifted mode LFRCO for CMU_EXPORTCLKCTRL */ 767 #define CMU_EXPORTCLKCTRL_CLKOUTSEL1_LFXO (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_LFXO << 8) /**< Shifted mode LFXO for CMU_EXPORTCLKCTRL */ 768 #define CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFRCODPLL (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFRCODPLL << 8) /**< Shifted mode HFRCODPLL for CMU_EXPORTCLKCTRL*/ 769 #define CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFXO (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_HFXO << 8) /**< Shifted mode HFXO for CMU_EXPORTCLKCTRL */ 770 #define CMU_EXPORTCLKCTRL_CLKOUTSEL1_FSRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL1_FSRCO << 8) /**< Shifted mode FSRCO for CMU_EXPORTCLKCTRL */ 771 #define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_SHIFT 16 /**< Shift value for CMU_CLKOUTSEL2 */ 772 #define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_MASK 0xF0000UL /**< Bit mask for CMU_CLKOUTSEL2 */ 773 #define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_EXPORTCLKCTRL */ 774 #define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_EXPORTCLKCTRL */ 775 #define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_HCLK 0x00000001UL /**< Mode HCLK for CMU_EXPORTCLKCTRL */ 776 #define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFEXPCLK 0x00000002UL /**< Mode HFEXPCLK for CMU_EXPORTCLKCTRL */ 777 #define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_EXPORTCLKCTRL */ 778 #define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_EXPORTCLKCTRL */ 779 #define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_LFXO 0x00000005UL /**< Mode LFXO for CMU_EXPORTCLKCTRL */ 780 #define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFRCODPLL 0x00000006UL /**< Mode HFRCODPLL for CMU_EXPORTCLKCTRL */ 781 #define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFXO 0x00000007UL /**< Mode HFXO for CMU_EXPORTCLKCTRL */ 782 #define _CMU_EXPORTCLKCTRL_CLKOUTSEL2_FSRCO 0x00000008UL /**< Mode FSRCO for CMU_EXPORTCLKCTRL */ 783 #define CMU_EXPORTCLKCTRL_CLKOUTSEL2_DEFAULT (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_EXPORTCLKCTRL */ 784 #define CMU_EXPORTCLKCTRL_CLKOUTSEL2_DISABLED (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_DISABLED << 16) /**< Shifted mode DISABLED for CMU_EXPORTCLKCTRL */ 785 #define CMU_EXPORTCLKCTRL_CLKOUTSEL2_HCLK (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_HCLK << 16) /**< Shifted mode HCLK for CMU_EXPORTCLKCTRL */ 786 #define CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFEXPCLK (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFEXPCLK << 16) /**< Shifted mode HFEXPCLK for CMU_EXPORTCLKCTRL */ 787 #define CMU_EXPORTCLKCTRL_CLKOUTSEL2_ULFRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_ULFRCO << 16) /**< Shifted mode ULFRCO for CMU_EXPORTCLKCTRL */ 788 #define CMU_EXPORTCLKCTRL_CLKOUTSEL2_LFRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_LFRCO << 16) /**< Shifted mode LFRCO for CMU_EXPORTCLKCTRL */ 789 #define CMU_EXPORTCLKCTRL_CLKOUTSEL2_LFXO (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_LFXO << 16) /**< Shifted mode LFXO for CMU_EXPORTCLKCTRL */ 790 #define CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFRCODPLL (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFRCODPLL << 16) /**< Shifted mode HFRCODPLL for CMU_EXPORTCLKCTRL*/ 791 #define CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFXO (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_HFXO << 16) /**< Shifted mode HFXO for CMU_EXPORTCLKCTRL */ 792 #define CMU_EXPORTCLKCTRL_CLKOUTSEL2_FSRCO (_CMU_EXPORTCLKCTRL_CLKOUTSEL2_FSRCO << 16) /**< Shifted mode FSRCO for CMU_EXPORTCLKCTRL */ 793 #define _CMU_EXPORTCLKCTRL_PRESC_SHIFT 24 /**< Shift value for CMU_PRESC */ 794 #define _CMU_EXPORTCLKCTRL_PRESC_MASK 0x1F000000UL /**< Bit mask for CMU_PRESC */ 795 #define _CMU_EXPORTCLKCTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_EXPORTCLKCTRL */ 796 #define CMU_EXPORTCLKCTRL_PRESC_DEFAULT (_CMU_EXPORTCLKCTRL_PRESC_DEFAULT << 24) /**< Shifted mode DEFAULT for CMU_EXPORTCLKCTRL */ 797 798 /* Bit fields for CMU DPLLREFCLKCTRL */ 799 #define _CMU_DPLLREFCLKCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_DPLLREFCLKCTRL */ 800 #define _CMU_DPLLREFCLKCTRL_MASK 0x00000003UL /**< Mask for CMU_DPLLREFCLKCTRL */ 801 #define _CMU_DPLLREFCLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ 802 #define _CMU_DPLLREFCLKCTRL_CLKSEL_MASK 0x3UL /**< Bit mask for CMU_CLKSEL */ 803 #define _CMU_DPLLREFCLKCTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_DPLLREFCLKCTRL */ 804 #define _CMU_DPLLREFCLKCTRL_CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_DPLLREFCLKCTRL */ 805 #define _CMU_DPLLREFCLKCTRL_CLKSEL_HFXO 0x00000001UL /**< Mode HFXO for CMU_DPLLREFCLKCTRL */ 806 #define _CMU_DPLLREFCLKCTRL_CLKSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_DPLLREFCLKCTRL */ 807 #define _CMU_DPLLREFCLKCTRL_CLKSEL_CLKIN0 0x00000003UL /**< Mode CLKIN0 for CMU_DPLLREFCLKCTRL */ 808 #define CMU_DPLLREFCLKCTRL_CLKSEL_DEFAULT (_CMU_DPLLREFCLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_DPLLREFCLKCTRL */ 809 #define CMU_DPLLREFCLKCTRL_CLKSEL_DISABLED (_CMU_DPLLREFCLKCTRL_CLKSEL_DISABLED << 0) /**< Shifted mode DISABLED for CMU_DPLLREFCLKCTRL*/ 810 #define CMU_DPLLREFCLKCTRL_CLKSEL_HFXO (_CMU_DPLLREFCLKCTRL_CLKSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_DPLLREFCLKCTRL */ 811 #define CMU_DPLLREFCLKCTRL_CLKSEL_LFXO (_CMU_DPLLREFCLKCTRL_CLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_DPLLREFCLKCTRL */ 812 #define CMU_DPLLREFCLKCTRL_CLKSEL_CLKIN0 (_CMU_DPLLREFCLKCTRL_CLKSEL_CLKIN0 << 0) /**< Shifted mode CLKIN0 for CMU_DPLLREFCLKCTRL */ 813 814 /* Bit fields for CMU EM01GRPACLKCTRL */ 815 #define _CMU_EM01GRPACLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_EM01GRPACLKCTRL */ 816 #define _CMU_EM01GRPACLKCTRL_MASK 0x00000003UL /**< Mask for CMU_EM01GRPACLKCTRL */ 817 #define _CMU_EM01GRPACLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ 818 #define _CMU_EM01GRPACLKCTRL_CLKSEL_MASK 0x3UL /**< Bit mask for CMU_CLKSEL */ 819 #define _CMU_EM01GRPACLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_EM01GRPACLKCTRL */ 820 #define _CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLL 0x00000001UL /**< Mode HFRCODPLL for CMU_EM01GRPACLKCTRL */ 821 #define _CMU_EM01GRPACLKCTRL_CLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_EM01GRPACLKCTRL */ 822 #define _CMU_EM01GRPACLKCTRL_CLKSEL_FSRCO 0x00000003UL /**< Mode FSRCO for CMU_EM01GRPACLKCTRL */ 823 #define CMU_EM01GRPACLKCTRL_CLKSEL_DEFAULT (_CMU_EM01GRPACLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_EM01GRPACLKCTRL*/ 824 #define CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLL (_CMU_EM01GRPACLKCTRL_CLKSEL_HFRCODPLL << 0) /**< Shifted mode HFRCODPLL for CMU_EM01GRPACLKCTRL*/ 825 #define CMU_EM01GRPACLKCTRL_CLKSEL_HFXO (_CMU_EM01GRPACLKCTRL_CLKSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_EM01GRPACLKCTRL */ 826 #define CMU_EM01GRPACLKCTRL_CLKSEL_FSRCO (_CMU_EM01GRPACLKCTRL_CLKSEL_FSRCO << 0) /**< Shifted mode FSRCO for CMU_EM01GRPACLKCTRL */ 827 828 /* Bit fields for CMU EM01GRPBCLKCTRL */ 829 #define _CMU_EM01GRPBCLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_EM01GRPBCLKCTRL */ 830 #define _CMU_EM01GRPBCLKCTRL_MASK 0x00000007UL /**< Mask for CMU_EM01GRPBCLKCTRL */ 831 #define _CMU_EM01GRPBCLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ 832 #define _CMU_EM01GRPBCLKCTRL_CLKSEL_MASK 0x7UL /**< Bit mask for CMU_CLKSEL */ 833 #define _CMU_EM01GRPBCLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_EM01GRPBCLKCTRL */ 834 #define _CMU_EM01GRPBCLKCTRL_CLKSEL_HFRCODPLL 0x00000001UL /**< Mode HFRCODPLL for CMU_EM01GRPBCLKCTRL */ 835 #define _CMU_EM01GRPBCLKCTRL_CLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_EM01GRPBCLKCTRL */ 836 #define _CMU_EM01GRPBCLKCTRL_CLKSEL_FSRCO 0x00000003UL /**< Mode FSRCO for CMU_EM01GRPBCLKCTRL */ 837 #define _CMU_EM01GRPBCLKCTRL_CLKSEL_CLKIN0 0x00000004UL /**< Mode CLKIN0 for CMU_EM01GRPBCLKCTRL */ 838 #define _CMU_EM01GRPBCLKCTRL_CLKSEL_HFRCODPLLRT 0x00000005UL /**< Mode HFRCODPLLRT for CMU_EM01GRPBCLKCTRL */ 839 #define _CMU_EM01GRPBCLKCTRL_CLKSEL_HFXORT 0x00000006UL /**< Mode HFXORT for CMU_EM01GRPBCLKCTRL */ 840 #define CMU_EM01GRPBCLKCTRL_CLKSEL_DEFAULT (_CMU_EM01GRPBCLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_EM01GRPBCLKCTRL*/ 841 #define CMU_EM01GRPBCLKCTRL_CLKSEL_HFRCODPLL (_CMU_EM01GRPBCLKCTRL_CLKSEL_HFRCODPLL << 0) /**< Shifted mode HFRCODPLL for CMU_EM01GRPBCLKCTRL*/ 842 #define CMU_EM01GRPBCLKCTRL_CLKSEL_HFXO (_CMU_EM01GRPBCLKCTRL_CLKSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_EM01GRPBCLKCTRL */ 843 #define CMU_EM01GRPBCLKCTRL_CLKSEL_FSRCO (_CMU_EM01GRPBCLKCTRL_CLKSEL_FSRCO << 0) /**< Shifted mode FSRCO for CMU_EM01GRPBCLKCTRL */ 844 #define CMU_EM01GRPBCLKCTRL_CLKSEL_CLKIN0 (_CMU_EM01GRPBCLKCTRL_CLKSEL_CLKIN0 << 0) /**< Shifted mode CLKIN0 for CMU_EM01GRPBCLKCTRL */ 845 #define CMU_EM01GRPBCLKCTRL_CLKSEL_HFRCODPLLRT (_CMU_EM01GRPBCLKCTRL_CLKSEL_HFRCODPLLRT << 0) /**< Shifted mode HFRCODPLLRT for CMU_EM01GRPBCLKCTRL*/ 846 #define CMU_EM01GRPBCLKCTRL_CLKSEL_HFXORT (_CMU_EM01GRPBCLKCTRL_CLKSEL_HFXORT << 0) /**< Shifted mode HFXORT for CMU_EM01GRPBCLKCTRL */ 847 848 /* Bit fields for CMU EM23GRPACLKCTRL */ 849 #define _CMU_EM23GRPACLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_EM23GRPACLKCTRL */ 850 #define _CMU_EM23GRPACLKCTRL_MASK 0x00000003UL /**< Mask for CMU_EM23GRPACLKCTRL */ 851 #define _CMU_EM23GRPACLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ 852 #define _CMU_EM23GRPACLKCTRL_CLKSEL_MASK 0x3UL /**< Bit mask for CMU_CLKSEL */ 853 #define _CMU_EM23GRPACLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_EM23GRPACLKCTRL */ 854 #define _CMU_EM23GRPACLKCTRL_CLKSEL_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_EM23GRPACLKCTRL */ 855 #define _CMU_EM23GRPACLKCTRL_CLKSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_EM23GRPACLKCTRL */ 856 #define _CMU_EM23GRPACLKCTRL_CLKSEL_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_EM23GRPACLKCTRL */ 857 #define CMU_EM23GRPACLKCTRL_CLKSEL_DEFAULT (_CMU_EM23GRPACLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_EM23GRPACLKCTRL*/ 858 #define CMU_EM23GRPACLKCTRL_CLKSEL_LFRCO (_CMU_EM23GRPACLKCTRL_CLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_EM23GRPACLKCTRL */ 859 #define CMU_EM23GRPACLKCTRL_CLKSEL_LFXO (_CMU_EM23GRPACLKCTRL_CLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_EM23GRPACLKCTRL */ 860 #define CMU_EM23GRPACLKCTRL_CLKSEL_ULFRCO (_CMU_EM23GRPACLKCTRL_CLKSEL_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_EM23GRPACLKCTRL */ 861 862 /* Bit fields for CMU EM4GRPACLKCTRL */ 863 #define _CMU_EM4GRPACLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_EM4GRPACLKCTRL */ 864 #define _CMU_EM4GRPACLKCTRL_MASK 0x00000003UL /**< Mask for CMU_EM4GRPACLKCTRL */ 865 #define _CMU_EM4GRPACLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ 866 #define _CMU_EM4GRPACLKCTRL_CLKSEL_MASK 0x3UL /**< Bit mask for CMU_CLKSEL */ 867 #define _CMU_EM4GRPACLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_EM4GRPACLKCTRL */ 868 #define _CMU_EM4GRPACLKCTRL_CLKSEL_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_EM4GRPACLKCTRL */ 869 #define _CMU_EM4GRPACLKCTRL_CLKSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_EM4GRPACLKCTRL */ 870 #define _CMU_EM4GRPACLKCTRL_CLKSEL_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_EM4GRPACLKCTRL */ 871 #define CMU_EM4GRPACLKCTRL_CLKSEL_DEFAULT (_CMU_EM4GRPACLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_EM4GRPACLKCTRL */ 872 #define CMU_EM4GRPACLKCTRL_CLKSEL_LFRCO (_CMU_EM4GRPACLKCTRL_CLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_EM4GRPACLKCTRL */ 873 #define CMU_EM4GRPACLKCTRL_CLKSEL_LFXO (_CMU_EM4GRPACLKCTRL_CLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_EM4GRPACLKCTRL */ 874 #define CMU_EM4GRPACLKCTRL_CLKSEL_ULFRCO (_CMU_EM4GRPACLKCTRL_CLKSEL_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_EM4GRPACLKCTRL */ 875 876 /* Bit fields for CMU IADCCLKCTRL */ 877 #define _CMU_IADCCLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_IADCCLKCTRL */ 878 #define _CMU_IADCCLKCTRL_MASK 0x00000003UL /**< Mask for CMU_IADCCLKCTRL */ 879 #define _CMU_IADCCLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ 880 #define _CMU_IADCCLKCTRL_CLKSEL_MASK 0x3UL /**< Bit mask for CMU_CLKSEL */ 881 #define _CMU_IADCCLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_IADCCLKCTRL */ 882 #define _CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK 0x00000001UL /**< Mode EM01GRPACLK for CMU_IADCCLKCTRL */ 883 #define _CMU_IADCCLKCTRL_CLKSEL_FSRCO 0x00000002UL /**< Mode FSRCO for CMU_IADCCLKCTRL */ 884 #define CMU_IADCCLKCTRL_CLKSEL_DEFAULT (_CMU_IADCCLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IADCCLKCTRL */ 885 #define CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK (_CMU_IADCCLKCTRL_CLKSEL_EM01GRPACLK << 0) /**< Shifted mode EM01GRPACLK for CMU_IADCCLKCTRL*/ 886 #define CMU_IADCCLKCTRL_CLKSEL_FSRCO (_CMU_IADCCLKCTRL_CLKSEL_FSRCO << 0) /**< Shifted mode FSRCO for CMU_IADCCLKCTRL */ 887 888 /* Bit fields for CMU WDOG0CLKCTRL */ 889 #define _CMU_WDOG0CLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_WDOG0CLKCTRL */ 890 #define _CMU_WDOG0CLKCTRL_MASK 0x00000007UL /**< Mask for CMU_WDOG0CLKCTRL */ 891 #define _CMU_WDOG0CLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ 892 #define _CMU_WDOG0CLKCTRL_CLKSEL_MASK 0x7UL /**< Bit mask for CMU_CLKSEL */ 893 #define _CMU_WDOG0CLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_WDOG0CLKCTRL */ 894 #define _CMU_WDOG0CLKCTRL_CLKSEL_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_WDOG0CLKCTRL */ 895 #define _CMU_WDOG0CLKCTRL_CLKSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_WDOG0CLKCTRL */ 896 #define _CMU_WDOG0CLKCTRL_CLKSEL_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_WDOG0CLKCTRL */ 897 #define _CMU_WDOG0CLKCTRL_CLKSEL_HCLKDIV1024 0x00000004UL /**< Mode HCLKDIV1024 for CMU_WDOG0CLKCTRL */ 898 #define CMU_WDOG0CLKCTRL_CLKSEL_DEFAULT (_CMU_WDOG0CLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_WDOG0CLKCTRL */ 899 #define CMU_WDOG0CLKCTRL_CLKSEL_LFRCO (_CMU_WDOG0CLKCTRL_CLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_WDOG0CLKCTRL */ 900 #define CMU_WDOG0CLKCTRL_CLKSEL_LFXO (_CMU_WDOG0CLKCTRL_CLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_WDOG0CLKCTRL */ 901 #define CMU_WDOG0CLKCTRL_CLKSEL_ULFRCO (_CMU_WDOG0CLKCTRL_CLKSEL_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_WDOG0CLKCTRL */ 902 #define CMU_WDOG0CLKCTRL_CLKSEL_HCLKDIV1024 (_CMU_WDOG0CLKCTRL_CLKSEL_HCLKDIV1024 << 0) /**< Shifted mode HCLKDIV1024 for CMU_WDOG0CLKCTRL*/ 903 904 /* Bit fields for CMU EUART0CLKCTRL */ 905 #define _CMU_EUART0CLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_EUART0CLKCTRL */ 906 #define _CMU_EUART0CLKCTRL_MASK 0x00000003UL /**< Mask for CMU_EUART0CLKCTRL */ 907 #define _CMU_EUART0CLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ 908 #define _CMU_EUART0CLKCTRL_CLKSEL_MASK 0x3UL /**< Bit mask for CMU_CLKSEL */ 909 #define _CMU_EUART0CLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_EUART0CLKCTRL */ 910 #define _CMU_EUART0CLKCTRL_CLKSEL_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_EUART0CLKCTRL */ 911 #define _CMU_EUART0CLKCTRL_CLKSEL_EM01GRPACLK 0x00000001UL /**< Mode EM01GRPACLK for CMU_EUART0CLKCTRL */ 912 #define _CMU_EUART0CLKCTRL_CLKSEL_EM23GRPACLK 0x00000002UL /**< Mode EM23GRPACLK for CMU_EUART0CLKCTRL */ 913 #define CMU_EUART0CLKCTRL_CLKSEL_DEFAULT (_CMU_EUART0CLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_EUART0CLKCTRL */ 914 #define CMU_EUART0CLKCTRL_CLKSEL_DISABLED (_CMU_EUART0CLKCTRL_CLKSEL_DISABLED << 0) /**< Shifted mode DISABLED for CMU_EUART0CLKCTRL */ 915 #define CMU_EUART0CLKCTRL_CLKSEL_EM01GRPACLK (_CMU_EUART0CLKCTRL_CLKSEL_EM01GRPACLK << 0) /**< Shifted mode EM01GRPACLK for CMU_EUART0CLKCTRL*/ 916 #define CMU_EUART0CLKCTRL_CLKSEL_EM23GRPACLK (_CMU_EUART0CLKCTRL_CLKSEL_EM23GRPACLK << 0) /**< Shifted mode EM23GRPACLK for CMU_EUART0CLKCTRL*/ 917 918 /* Bit fields for CMU RTCCCLKCTRL */ 919 #define _CMU_RTCCCLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_RTCCCLKCTRL */ 920 #define _CMU_RTCCCLKCTRL_MASK 0x00000003UL /**< Mask for CMU_RTCCCLKCTRL */ 921 #define _CMU_RTCCCLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ 922 #define _CMU_RTCCCLKCTRL_CLKSEL_MASK 0x3UL /**< Bit mask for CMU_CLKSEL */ 923 #define _CMU_RTCCCLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_RTCCCLKCTRL */ 924 #define _CMU_RTCCCLKCTRL_CLKSEL_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_RTCCCLKCTRL */ 925 #define _CMU_RTCCCLKCTRL_CLKSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_RTCCCLKCTRL */ 926 #define _CMU_RTCCCLKCTRL_CLKSEL_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_RTCCCLKCTRL */ 927 #define CMU_RTCCCLKCTRL_CLKSEL_DEFAULT (_CMU_RTCCCLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_RTCCCLKCTRL */ 928 #define CMU_RTCCCLKCTRL_CLKSEL_LFRCO (_CMU_RTCCCLKCTRL_CLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_RTCCCLKCTRL */ 929 #define CMU_RTCCCLKCTRL_CLKSEL_LFXO (_CMU_RTCCCLKCTRL_CLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_RTCCCLKCTRL */ 930 #define CMU_RTCCCLKCTRL_CLKSEL_ULFRCO (_CMU_RTCCCLKCTRL_CLKSEL_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_RTCCCLKCTRL */ 931 932 /* Bit fields for CMU PRORTCCLKCTRL */ 933 #define _CMU_PRORTCCLKCTRL_RESETVALUE 0x00000001UL /**< Default value for CMU_PRORTCCLKCTRL */ 934 #define _CMU_PRORTCCLKCTRL_MASK 0x00000003UL /**< Mask for CMU_PRORTCCLKCTRL */ 935 #define _CMU_PRORTCCLKCTRL_CLKSEL_SHIFT 0 /**< Shift value for CMU_CLKSEL */ 936 #define _CMU_PRORTCCLKCTRL_CLKSEL_MASK 0x3UL /**< Bit mask for CMU_CLKSEL */ 937 #define _CMU_PRORTCCLKCTRL_CLKSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_PRORTCCLKCTRL */ 938 #define _CMU_PRORTCCLKCTRL_CLKSEL_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_PRORTCCLKCTRL */ 939 #define _CMU_PRORTCCLKCTRL_CLKSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_PRORTCCLKCTRL */ 940 #define _CMU_PRORTCCLKCTRL_CLKSEL_ULFRCO 0x00000003UL /**< Mode ULFRCO for CMU_PRORTCCLKCTRL */ 941 #define CMU_PRORTCCLKCTRL_CLKSEL_DEFAULT (_CMU_PRORTCCLKCTRL_CLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_PRORTCCLKCTRL */ 942 #define CMU_PRORTCCLKCTRL_CLKSEL_LFRCO (_CMU_PRORTCCLKCTRL_CLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_PRORTCCLKCTRL */ 943 #define CMU_PRORTCCLKCTRL_CLKSEL_LFXO (_CMU_PRORTCCLKCTRL_CLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_PRORTCCLKCTRL */ 944 #define CMU_PRORTCCLKCTRL_CLKSEL_ULFRCO (_CMU_PRORTCCLKCTRL_CLKSEL_ULFRCO << 0) /**< Shifted mode ULFRCO for CMU_PRORTCCLKCTRL */ 945 946 /* Bit fields for CMU CRYPTOACCCLKCTRL */ 947 #define _CMU_CRYPTOACCCLKCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_CRYPTOACCCLKCTRL */ 948 #define _CMU_CRYPTOACCCLKCTRL_MASK 0x00000003UL /**< Mask for CMU_CRYPTOACCCLKCTRL */ 949 #define CMU_CRYPTOACCCLKCTRL_PKEN (0x1UL << 0) /**< PK Enable */ 950 #define _CMU_CRYPTOACCCLKCTRL_PKEN_SHIFT 0 /**< Shift value for CMU_PKEN */ 951 #define _CMU_CRYPTOACCCLKCTRL_PKEN_MASK 0x1UL /**< Bit mask for CMU_PKEN */ 952 #define _CMU_CRYPTOACCCLKCTRL_PKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CRYPTOACCCLKCTRL */ 953 #define CMU_CRYPTOACCCLKCTRL_PKEN_DEFAULT (_CMU_CRYPTOACCCLKCTRL_PKEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CRYPTOACCCLKCTRL*/ 954 #define CMU_CRYPTOACCCLKCTRL_AESEN (0x1UL << 1) /**< AES Enable */ 955 #define _CMU_CRYPTOACCCLKCTRL_AESEN_SHIFT 1 /**< Shift value for CMU_AESEN */ 956 #define _CMU_CRYPTOACCCLKCTRL_AESEN_MASK 0x2UL /**< Bit mask for CMU_AESEN */ 957 #define _CMU_CRYPTOACCCLKCTRL_AESEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CRYPTOACCCLKCTRL */ 958 #define CMU_CRYPTOACCCLKCTRL_AESEN_DEFAULT (_CMU_CRYPTOACCCLKCTRL_AESEN_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_CRYPTOACCCLKCTRL*/ 959 960 /* Bit fields for CMU RADIOCLKCTRL */ 961 #define _CMU_RADIOCLKCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_RADIOCLKCTRL */ 962 #define _CMU_RADIOCLKCTRL_MASK 0x80000001UL /**< Mask for CMU_RADIOCLKCTRL */ 963 #define CMU_RADIOCLKCTRL_EN (0x1UL << 0) /**< Enable */ 964 #define _CMU_RADIOCLKCTRL_EN_SHIFT 0 /**< Shift value for CMU_EN */ 965 #define _CMU_RADIOCLKCTRL_EN_MASK 0x1UL /**< Bit mask for CMU_EN */ 966 #define _CMU_RADIOCLKCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_RADIOCLKCTRL */ 967 #define CMU_RADIOCLKCTRL_EN_DEFAULT (_CMU_RADIOCLKCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_RADIOCLKCTRL */ 968 #define CMU_RADIOCLKCTRL_DBGCLK (0x1UL << 31) /**< Enable Clock for Debugger */ 969 #define _CMU_RADIOCLKCTRL_DBGCLK_SHIFT 31 /**< Shift value for CMU_DBGCLK */ 970 #define _CMU_RADIOCLKCTRL_DBGCLK_MASK 0x80000000UL /**< Bit mask for CMU_DBGCLK */ 971 #define _CMU_RADIOCLKCTRL_DBGCLK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_RADIOCLKCTRL */ 972 #define CMU_RADIOCLKCTRL_DBGCLK_DEFAULT (_CMU_RADIOCLKCTRL_DBGCLK_DEFAULT << 31) /**< Shifted mode DEFAULT for CMU_RADIOCLKCTRL */ 973 974 /** @} End of group EFR32BG22_CMU_BitFields */ 975 /** @} End of group EFR32BG22_CMU */ 976 /** @} End of group Parts */ 977 978 #endif /* EFR32BG22_CMU_H */ 979
