1 /* 2 * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef _SOC_PERIPH_DEFS_H_ 8 #define _SOC_PERIPH_DEFS_H_ 9 10 #ifdef __cplusplus 11 extern "C" { 12 #endif 13 14 typedef enum { 15 PERIPH_LEDC_MODULE = 0, 16 PERIPH_UART0_MODULE, 17 PERIPH_UART1_MODULE, 18 PERIPH_USB_MODULE, 19 PERIPH_I2C0_MODULE, 20 PERIPH_I2C1_MODULE, 21 PERIPH_I2S0_MODULE, 22 PERIPH_TIMG0_MODULE, 23 PERIPH_TIMG1_MODULE, 24 PERIPH_UHCI0_MODULE, 25 PERIPH_UHCI1_MODULE, 26 PERIPH_RMT_MODULE, 27 PERIPH_PCNT_MODULE, 28 PERIPH_SPI_MODULE, //SPI1 29 PERIPH_FSPI_MODULE, //SPI2 30 PERIPH_HSPI_MODULE, //SPI3 31 PERIPH_SPI2_DMA_MODULE, 32 PERIPH_SPI3_DMA_MODULE, 33 PERIPH_TWAI_MODULE, 34 PERIPH_RNG_MODULE, 35 PERIPH_WIFI_MODULE, 36 PERIPH_WIFI_BT_COMMON_MODULE, 37 PERIPH_SYSTIMER_MODULE, 38 PERIPH_AES_MODULE, 39 PERIPH_SHA_MODULE, 40 PERIPH_RSA_MODULE, 41 PERIPH_CRYPTO_DMA_MODULE, //this DMA is shared between AES and SHA 42 PERIPH_AES_DMA_MODULE, 43 PERIPH_SHA_DMA_MODULE, 44 PERIPH_DEDIC_GPIO_MODULE, 45 PERIPH_SARADC_MODULE, 46 PERIPH_MODULE_MAX 47 } periph_module_t; 48 49 typedef enum { 50 ETS_WIFI_MAC_INTR_SOURCE = 0, /**< interrupt of WiFi MAC, level*/ 51 ETS_WIFI_MAC_NMI_SOURCE, /**< interrupt of WiFi MAC, NMI, use if MAC have bug to fix in NMI*/ 52 ETS_WIFI_PWR_INTR_SOURCE, /**< */ 53 ETS_WIFI_BB_INTR_SOURCE, /**< interrupt of WiFi BB, level, we can do some calibartion*/ 54 ETS_BT_MAC_INTR_SOURCE, /**< will be cancelled*/ 55 ETS_BT_BB_INTR_SOURCE, /**< interrupt of BT BB, level*/ 56 ETS_BT_BB_NMI_SOURCE, /**< interrupt of BT BB, NMI, use if BB have bug to fix in NMI*/ 57 ETS_RWBT_INTR_SOURCE, /**< interrupt of RWBT, level*/ 58 ETS_RWBLE_INTR_SOURCE, /**< interrupt of RWBLE, level*/ 59 ETS_RWBT_NMI_SOURCE, /**< interrupt of RWBT, NMI, use if RWBT have bug to fix in NMI*/ 60 ETS_RWBLE_NMI_SOURCE, /**< interrupt of RWBLE, NMI, use if RWBT have bug to fix in NMI*/ 61 ETS_SLC0_INTR_SOURCE, /**< interrupt of SLC0, level*/ 62 ETS_SLC1_INTR_SOURCE, /**< interrupt of SLC1, level*/ 63 ETS_UHCI0_INTR_SOURCE, /**< interrupt of UHCI0, level*/ 64 ETS_UHCI1_INTR_SOURCE, /**< interrupt of UHCI1, level*/ 65 ETS_TG0_T0_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, TIMER0, level, we would like use EDGE for timer if permission*/ 66 67 ETS_TG0_T1_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, TIMER1, level, we would like use EDGE for timer if permission*/ 68 ETS_TG0_WDT_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, WATCHDOG, level*/ 69 ETS_TG0_LACT_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, LACT, level*/ 70 ETS_TG1_T0_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, TIMER0, level, we would like use EDGE for timer if permission*/ 71 ETS_TG1_T1_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, TIMER1, level, we would like use EDGE for timer if permission*/ 72 ETS_TG1_WDT_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, WATCHDOG, level*/ 73 ETS_TG1_LACT_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, LACT, level*/ 74 ETS_GPIO_INTR_SOURCE, /**< interrupt of GPIO, level*/ 75 ETS_GPIO_NMI_SOURCE, /**< interrupt of GPIO, NMI*/ 76 ETS_GPIO_INTR_SOURCE2, /**< interrupt of GPIO, level*/ 77 ETS_GPIO_NMI_SOURCE2, /**< interrupt of GPIO, NMI*/ 78 ETS_DEDICATED_GPIO_INTR_SOURCE, /**< interrupt of dedicated GPIO, level*/ 79 ETS_FROM_CPU_INTR0_SOURCE, /**< interrupt0 generated from a CPU, level*/ /* Used for FreeRTOS */ 80 ETS_FROM_CPU_INTR1_SOURCE, /**< interrupt1 generated from a CPU, level*/ /* Used for FreeRTOS */ 81 ETS_FROM_CPU_INTR2_SOURCE, /**< interrupt2 generated from a CPU, level*/ 82 ETS_FROM_CPU_INTR3_SOURCE, /**< interrupt3 generated from a CPU, level*/ 83 84 ETS_SPI1_INTR_SOURCE = 32, /**< interrupt of SPI1, level, SPI1 is for flash read/write, do not use this*/ 85 ETS_SPI2_INTR_SOURCE, /**< interrupt of SPI2, level*/ 86 ETS_SPI3_INTR_SOURCE, /**< interrupt of SPI3, level*/ 87 ETS_I2S0_INTR_SOURCE, /**< interrupt of I2S0, level*/ 88 ETS_UART0_INTR_SOURCE = 37, /**< interrupt of UART0, level*/ 89 ETS_UART1_INTR_SOURCE, /**< interrupt of UART1, level*/ 90 ETS_UART2_INTR_SOURCE, /**< interrupt of UART2, level*/ 91 ETS_SDIO_HOST_INTR_SOURCE, /**< interrupt of SD/SDIO/MMC HOST, level*/ 92 ETS_LEDC_INTR_SOURCE = 45, /**< interrupt of LED PWM, level*/ 93 ETS_EFUSE_INTR_SOURCE, /**< interrupt of efuse, level, not likely to use*/ 94 ETS_TWAI_INTR_SOURCE , /**< interrupt of twai, level*/ 95 96 ETS_USB_INTR_SOURCE = 48, /**< interrupt of USB, level*/ 97 ETS_RTC_CORE_INTR_SOURCE, /**< interrupt of rtc core, level, include rtc watchdog*/ 98 ETS_RMT_INTR_SOURCE, /**< interrupt of remote controller, level*/ 99 ETS_PCNT_INTR_SOURCE, /**< interrupt of pluse count, level*/ 100 ETS_I2C_EXT0_INTR_SOURCE, /**< interrupt of I2C controller1, level*/ 101 ETS_I2C_EXT1_INTR_SOURCE, /**< interrupt of I2C controller0, level*/ 102 ETS_RSA_INTR_SOURCE, /**< interrupt of RSA accelerator, level*/ 103 ETS_SHA_INTR_SOURCE, /**< interrupt of SHA accelerator, level*/ 104 ETS_AES_INTR_SOURCE, /**< interrupt of AES accelerator, level*/ 105 ETS_SPI2_DMA_INTR_SOURCE, /**< interrupt of SPI2 DMA, level*/ 106 ETS_SPI3_DMA_INTR_SOURCE, /**< interrupt of SPI3 DMA, level*/ 107 ETS_WDT_INTR_SOURCE, /**< will be cancelled*/ 108 ETS_TIMER1_INTR_SOURCE, /**< will be cancelled*/ 109 ETS_TIMER2_INTR_SOURCE, /**< will be cancelled*/ 110 ETS_TG0_T0_EDGE_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, TIMER0, EDGE*/ 111 ETS_TG0_T1_EDGE_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, TIMER1, EDGE*/ 112 113 ETS_TG0_WDT_EDGE_INTR_SOURCE = 64, /**< interrupt of TIMER_GROUP0, WATCH DOG, EDGE*/ 114 ETS_TG0_LACT_EDGE_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, LACT, EDGE*/ 115 ETS_TG1_T0_EDGE_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, TIMER0, EDGE*/ 116 ETS_TG1_T1_EDGE_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, TIMER1, EDGE*/ 117 ETS_TG1_WDT_EDGE_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, WATCHDOG, EDGE*/ 118 ETS_TG1_LACT_EDGE_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, LACT, EDGE*/ 119 ETS_CACHE_IA_INTR_SOURCE, /**< interrupt of Cache Invalied Access, LEVEL*/ 120 ETS_SYSTIMER_TARGET0_EDGE_INTR_SOURCE, /**< interrupt of system timer 0, EDGE*/ 121 ETS_SYSTIMER_TARGET1_EDGE_INTR_SOURCE, /**< interrupt of system timer 1, EDGE*/ 122 ETS_SYSTIMER_TARGET2_EDGE_INTR_SOURCE, /**< interrupt of system timer 2, EDGE*/ 123 ETS_ASSIST_DEBUG_INTR_SOURCE, /**< interrupt of Assist debug module, LEVEL*/ 124 ETS_PMS_PRO_IRAM0_ILG_INTR_SOURCE, /**< interrupt of illegal IRAM1 access, LEVEL*/ 125 ETS_PMS_PRO_DRAM0_ILG_INTR_SOURCE, /**< interrupt of illegal DRAM0 access, LEVEL*/ 126 ETS_PMS_PRO_DPORT_ILG_INTR_SOURCE, /**< interrupt of illegal DPORT access, LEVEL*/ 127 ETS_PMS_PRO_AHB_ILG_INTR_SOURCE, /**< interrupt of illegal AHB access, LEVEL*/ 128 ETS_PMS_PRO_CACHE_ILG_INTR_SOURCE, /**< interrupt of illegal CACHE access, LEVEL*/ 129 130 ETS_PMS_DMA_APB_I_ILG_INTR_SOURCE = 80, /**< interrupt of illegal APB access, LEVEL*/ 131 ETS_PMS_DMA_RX_I_ILG_INTR_SOURCE, /**< interrupt of illegal DMA RX access, LEVEL*/ 132 ETS_PMS_DMA_TX_I_ILG_INTR_SOURCE, /**< interrupt of illegal DMA TX access, LEVEL*/ 133 ETS_SPI_MEM_REJECT_CACHE_INTR_SOURCE, /**< interrupt of SPI0 Cache access and SPI1 access rejected, LEVEL*/ 134 ETS_DMA_COPY_INTR_SOURCE, /**< interrupt of DMA copy, LEVEL*/ 135 ETS_SPI4_DMA_INTR_SOURCE, /**< interrupt of SPI4 DMA, LEVEL*/ 136 ETS_SPI4_INTR_SOURCE, /**< interrupt of SPI4, LEVEL*/ 137 ETS_ICACHE_PRELOAD_INTR_SOURCE, /**< interrupt of ICache perload operation, LEVEL*/ 138 ETS_DCACHE_PRELOAD_INTR_SOURCE, /**< interrupt of DCache preload operation, LEVEL*/ 139 ETS_APB_ADC_INTR_SOURCE, /**< interrupt of APB ADC, LEVEL*/ 140 ETS_CRYPTO_DMA_INTR_SOURCE, /**< interrupt of encrypted DMA, LEVEL*/ 141 ETS_CPU_PERI_ERROR_INTR_SOURCE, /**< interrupt of CPU peripherals error, LEVEL*/ 142 ETS_APB_PERI_ERROR_INTR_SOURCE, /**< interrupt of APB peripherals error, LEVEL*/ 143 ETS_DCACHE_SYNC_INTR_SOURCE, /**< interrupt of data cache sync done, LEVEL*/ 144 ETS_ICACHE_SYNC_INTR_SOURCE, /**< interrupt of instruction cache sync done, LEVEL*/ 145 ETS_MAX_INTR_SOURCE, /**< number of interrupt sources */ 146 147 } periph_interrput_t; 148 149 #ifdef __cplusplus 150 } 151 #endif 152 153 #endif /* _SOC_PERIPH_DEFS_H_ */ 154
