1 /*
2  * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 
7 #pragma once
8 
9 #ifdef __cplusplus
10 extern "C" {
11 #endif
12 
13 typedef enum {
14     PERIPH_LEDC_MODULE = 0,
15     PERIPH_UART0_MODULE,
16     PERIPH_UART1_MODULE,
17     PERIPH_USB_DEVICE_MODULE,
18     PERIPH_I2C0_MODULE,
19     PERIPH_I2S1_MODULE,
20     PERIPH_TIMG0_MODULE,
21     PERIPH_TIMG1_MODULE,
22     PERIPH_UHCI0_MODULE,
23     PERIPH_RMT_MODULE,
24     PERIPH_SPI_MODULE,  //SPI1
25     PERIPH_SPI2_MODULE, //SPI2
26     PERIPH_TWAI_MODULE,
27     PERIPH_RNG_MODULE,
28     PERIPH_WIFI_MODULE,
29     PERIPH_BT_MODULE,
30     PERIPH_WIFI_BT_COMMON_MODULE,
31     PERIPH_BT_BASEBAND_MODULE,
32     PERIPH_BT_LC_MODULE,
33     PERIPH_RSA_MODULE,
34     PERIPH_AES_MODULE,
35     PERIPH_SHA_MODULE,
36     PERIPH_HMAC_MODULE,
37     PERIPH_DS_MODULE,
38     PERIPH_GDMA_MODULE,
39     PERIPH_SYSTIMER_MODULE,
40     PERIPH_SARADC_MODULE,
41     PERIPH_TEMPSENSOR_MODULE,
42     PERIPH_MODULE_MAX
43 } periph_module_t;
44 
45 typedef enum {
46     ETS_WIFI_MAC_INTR_SOURCE = 0,               /**< interrupt of WiFi MAC, level*/
47     ETS_WIFI_MAC_NMI_SOURCE,                    /**< interrupt of WiFi MAC, NMI, use if MAC have bug to fix in NMI*/
48     ETS_WIFI_PWR_INTR_SOURCE,                   /**< */
49     ETS_WIFI_BB_INTR_SOURCE,                    /**< interrupt of WiFi BB, level, we can do some calibartion*/
50     ETS_BT_MAC_INTR_SOURCE,                     /**< will be cancelled*/
51     ETS_BT_BB_INTR_SOURCE,                      /**< interrupt of BT BB, level*/
52     ETS_BT_BB_NMI_SOURCE,                       /**< interrupt of BT BB, NMI, use if BB have bug to fix in NMI*/
53     ETS_RWBT_INTR_SOURCE,                       /**< interrupt of RWBT, level*/
54     ETS_RWBLE_INTR_SOURCE,                      /**< interrupt of RWBLE, level*/
55     ETS_RWBT_NMI_SOURCE,                        /**< interrupt of RWBT, NMI, use if RWBT have bug to fix in NMI*/
56     ETS_RWBLE_NMI_SOURCE,                       /**< interrupt of RWBLE, NMI, use if RWBT have bug to fix in NMI*/
57     ETS_I2C_MASTER_SOURCE,                      /**< interrupt of I2C Master, level*/
58     ETS_SLC0_INTR_SOURCE,                       /**< interrupt of SLC0, level*/
59     ETS_SLC1_INTR_SOURCE,                       /**< interrupt of SLC1, level*/
60     ETS_APB_CTRL_INTR_SOURCE,                   /**< interrupt of APB ctrl, ?*/
61     ETS_UHCI0_INTR_SOURCE,                      /**< interrupt of UHCI0, level*/
62     ETS_GPIO_INTR_SOURCE,                       /**< interrupt of GPIO, level*/
63     ETS_GPIO_NMI_SOURCE,                        /**< interrupt of GPIO, NMI*/
64     ETS_SPI1_INTR_SOURCE,                       /**< interrupt of SPI1, level, SPI1 is for flash read/write, do not use this*/
65     ETS_SPI2_INTR_SOURCE,                       /**< interrupt of SPI2, level*/
66     ETS_I2S1_INTR_SOURCE,                       /**< interrupt of I2S1, level*/
67     ETS_UART0_INTR_SOURCE,                      /**< interrupt of UART0, level*/
68     ETS_UART1_INTR_SOURCE,                      /**< interrupt of UART1, level*/
69     ETS_LEDC_INTR_SOURCE,                       /**< interrupt of LED PWM, level*/
70     ETS_EFUSE_INTR_SOURCE,                      /**< interrupt of efuse, level, not likely to use*/
71     ETS_TWAI_INTR_SOURCE,                       /**< interrupt of can, level*/
72     ETS_USB_SERIAL_JTAG_INTR_SOURCE,            /**< interrupt of USJ, level*/
73     ETS_RTC_CORE_INTR_SOURCE,                   /**< interrupt of rtc core, level, include rtc watchdog*/
74     ETS_RMT_INTR_SOURCE,                        /**< interrupt of remote controller, level*/
75     ETS_I2C_EXT0_INTR_SOURCE,                   /**< interrupt of I2C controller1, level*/
76     ETS_TIMER1_INTR_SOURCE,
77     ETS_TIMER2_INTR_SOURCE,
78     ETS_TG0_T0_LEVEL_INTR_SOURCE,               /**< interrupt of TIMER_GROUP0, TIMER0, level*/
79     ETS_TG0_WDT_LEVEL_INTR_SOURCE,              /**< interrupt of TIMER_GROUP0, WATCH DOG, level*/
80     ETS_TG1_T0_LEVEL_INTR_SOURCE,               /**< interrupt of TIMER_GROUP1, TIMER0, level*/
81     ETS_TG1_WDT_LEVEL_INTR_SOURCE,              /**< interrupt of TIMER_GROUP1, WATCHDOG, level*/
82     ETS_CACHE_IA_INTR_SOURCE,                   /**< interrupt of Cache Invalied Access, LEVEL*/
83     ETS_SYSTIMER_TARGET0_EDGE_INTR_SOURCE,      /**< interrupt of system timer 0, EDGE*/
84     ETS_SYSTIMER_TARGET1_EDGE_INTR_SOURCE,      /**< interrupt of system timer 1, EDGE*/
85     ETS_SYSTIMER_TARGET2_EDGE_INTR_SOURCE,      /**< interrupt of system timer 2, EDGE*/
86     ETS_SPI_MEM_REJECT_CACHE_INTR_SOURCE,       /**< interrupt of SPI0 Cache access and SPI1 access rejected, LEVEL*/
87     ETS_ICACHE_PRELOAD0_INTR_SOURCE,            /**< interrupt of ICache perload operation, LEVEL*/
88     ETS_ICACHE_SYNC0_INTR_SOURCE,               /**< interrupt of instruction cache sync done, LEVEL*/
89     ETS_APB_ADC_INTR_SOURCE,                    /**< interrupt of APB ADC, LEVEL*/
90     ETS_DMA_CH0_INTR_SOURCE,                    /**< interrupt of general DMA channel 0, LEVEL*/
91     ETS_DMA_CH1_INTR_SOURCE,                    /**< interrupt of general DMA channel 1, LEVEL*/
92     ETS_DMA_CH2_INTR_SOURCE,                    /**< interrupt of general DMA channel 2, LEVEL*/
93     ETS_RSA_INTR_SOURCE,                        /**< interrupt of RSA accelerator, level*/
94     ETS_AES_INTR_SOURCE,                        /**< interrupt of AES accelerator, level*/
95     ETS_SHA_INTR_SOURCE,                        /**< interrupt of SHA accelerator, level*/
96     ETS_FROM_CPU_INTR0_SOURCE,                  /**< interrupt0 generated from a CPU, level*/ /* Used for FreeRTOS */
97     ETS_FROM_CPU_INTR1_SOURCE,                  /**< interrupt1 generated from a CPU, level*/ /* Used for FreeRTOS */
98     ETS_FROM_CPU_INTR2_SOURCE,                  /**< interrupt2 generated from a CPU, level*/
99     ETS_FROM_CPU_INTR3_SOURCE,                  /**< interrupt3 generated from a CPU, level*/
100     ETS_ASSIST_DEBUG_INTR_SOURCE,               /**< interrupt of Assist debug module, LEVEL*/
101     ETS_DMA_APBPERI_PMS_INTR_SOURCE,
102     ETS_CORE0_IRAM0_PMS_INTR_SOURCE,
103     ETS_CORE0_DRAM0_PMS_INTR_SOURCE,
104     ETS_CORE0_PIF_PMS_INTR_SOURCE,
105     ETS_CORE0_PIF_PMS_SIZE_INTR_SOURCE,
106     ETS_BAK_PMS_VIOLATE_INTR_SOURCE,
107     ETS_CACHE_CORE0_ACS_INTR_SOURCE,
108     ETS_MAX_INTR_SOURCE,
109 } periph_interrput_t;
110 
111 #ifdef __cplusplus
112 }
113 #endif
114