1 /**
2 ******************************************************************************
3 * @file stm32n6xx_ll_rcc.c
4 * @author MCD Application Team
5 * @brief RCC LL module driver.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2023 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Includes ------------------------------------------------------------------*/
20 #include "stm32n6xx_ll_rcc.h"
21 #include "stm32n6xx_ll_bus.h"
22 #ifdef USE_FULL_ASSERT
23 #include "stm32_assert.h"
24 #else
25 #define assert_param(expr) ((void)0U)
26 #endif /* USE_FULL_ASSERT */
27
28 /** @addtogroup STM32N6xx_LL_Driver
29 * @{
30 */
31
32 #if defined(RCC)
33
34 /** @addtogroup RCC_LL
35 * @{
36 */
37
38 /* Private types -------------------------------------------------------------*/
39 /* Private variables ---------------------------------------------------------*/
40 /* Private constants ---------------------------------------------------------*/
41 /** @addtogroup RCC_LL_Private_Constants
42 * @{
43 */
44 #if defined(USE_FPGA)
45 /* ***** FPGA values ******/
46 #define FREF_FREQ 32000000UL /* FREF forced to 32MHz */
47 #define PLL_SOURCE_FREQ 32000000UL /* PLL source forced to 32MHz */
48 #endif /* USE_FPGA */
49 /**
50 * @}
51 */
52
53 /* Private macros ------------------------------------------------------------*/
54 /** @addtogroup RCC_LL_Private_Macros
55 * @{
56 */
57 #define IS_LL_RCC_ADC_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_ADC_CLKSOURCE)
58
59 #define IS_LL_RCC_ADF_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_ADF1_CLKSOURCE)
60
61 #define IS_LL_RCC_DCMIPP_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_DCMIPP_CLKSOURCE)
62
63 #define IS_LL_RCC_ETH_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_ETH1_CLKSOURCE)
64
65 #define IS_LL_RCC_ETHPTP_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_ETH1PTP_CLKSOURCE)
66
67 #define IS_LL_RCC_FDCAN_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_FDCAN_CLKSOURCE)
68
69 #define IS_LL_RCC_FMC_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_FMC_CLKSOURCE)
70
71 #define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) \
72 || ((__VALUE__) == LL_RCC_I2C2_CLKSOURCE) \
73 || ((__VALUE__) == LL_RCC_I2C3_CLKSOURCE) \
74 || ((__VALUE__) == LL_RCC_I2C4_CLKSOURCE))
75
76 #define IS_LL_RCC_I3C_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I3C1_CLKSOURCE) \
77 || ((__VALUE__) == LL_RCC_I3C2_CLKSOURCE))
78
79 #define IS_LL_RCC_LPTIM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LPTIM1_CLKSOURCE) \
80 || ((__VALUE__) == LL_RCC_LPTIM2_CLKSOURCE) \
81 || ((__VALUE__) == LL_RCC_LPTIM3_CLKSOURCE) \
82 || ((__VALUE__) == LL_RCC_LPTIM4_CLKSOURCE) \
83 || ((__VALUE__) == LL_RCC_LPTIM5_CLKSOURCE))
84
85 #define IS_LL_RCC_LTDC_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_LTDC_CLKSOURCE)
86
87 #define IS_LL_RCC_MDF_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_MDF1_CLKSOURCE)
88
89 #define IS_LL_RCC_OTGPHY_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_OTGPHY1_CLKSOURCE) \
90 || ((__VALUE__) == LL_RCC_OTGPHY2_CLKSOURCE))
91
92 #define IS_LL_RCC_OTGPHYCKREF_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_OTGPHY1CKREF_CLKSOURCE) \
93 || ((__VALUE__) == LL_RCC_OTGPHY2CKREF_CLKSOURCE))
94
95 #define IS_LL_RCC_PSSI_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_PSSI_CLKSOURCE)
96
97 #define IS_LL_RCC_SAI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SAI1_CLKSOURCE) \
98 || ((__VALUE__) == LL_RCC_SAI2_CLKSOURCE))
99
100 #define IS_LL_RCC_SDMMC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SDMMC1_CLKSOURCE) \
101 || ((__VALUE__) == LL_RCC_SDMMC2_CLKSOURCE))
102
103 #define IS_LL_RCC_SPDIFRX_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_SPDIFRX1_CLKSOURCE)
104
105 #define IS_LL_RCC_SPI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SPI1_CLKSOURCE) \
106 || ((__VALUE__) == LL_RCC_SPI2_CLKSOURCE) \
107 || ((__VALUE__) == LL_RCC_SPI3_CLKSOURCE) \
108 || ((__VALUE__) == LL_RCC_SPI4_CLKSOURCE) \
109 || ((__VALUE__) == LL_RCC_SPI5_CLKSOURCE) \
110 || ((__VALUE__) == LL_RCC_SPI6_CLKSOURCE))
111
112 #define IS_LL_RCC_UART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_UART4_CLKSOURCE) \
113 || ((__VALUE__) == LL_RCC_UART5_CLKSOURCE) \
114 || ((__VALUE__) == LL_RCC_UART7_CLKSOURCE) \
115 || ((__VALUE__) == LL_RCC_UART8_CLKSOURCE) \
116 || ((__VALUE__) == LL_RCC_UART9_CLKSOURCE))
117
118 #define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \
119 || ((__VALUE__) == LL_RCC_USART2_CLKSOURCE) \
120 || ((__VALUE__) == LL_RCC_USART3_CLKSOURCE) \
121 || ((__VALUE__) == LL_RCC_USART6_CLKSOURCE) \
122 || ((__VALUE__) == LL_RCC_USART10_CLKSOURCE))
123
124 #define IS_LL_RCC_XSPI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_XSPI1_CLKSOURCE) \
125 || ((__VALUE__) == LL_RCC_XSPI2_CLKSOURCE) \
126 || ((__VALUE__) == LL_RCC_XSPI3_CLKSOURCE))
127
128 /**
129 * @}
130 */
131
132 /* Private function prototypes -----------------------------------------------*/
133 /** @defgroup RCC_LL_Private_Functions RCC Private functions
134 * @{
135 */
136 static uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency);
137 static uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency);
138 static uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency);
139 static uint32_t RCC_GetPCLK4ClockFreq(uint32_t HCLK_Frequency);
140 static uint32_t RCC_GetPCLK5ClockFreq(uint32_t HCLK_Frequency);
141
142 /**
143 * @}
144 */
145
146
147 /* Exported functions --------------------------------------------------------*/
148 /** @addtogroup RCC_LL_Exported_Functions
149 * @{
150 */
151
152 /** @addtogroup RCC_LL_EF_Init
153 * @{
154 */
155
156 /**
157 * @brief Resets the RCC clock configuration to the default reset state.
158 * @note The default reset state of the clock configuration is given below:
159 * - HSI ON and used as system clock source
160 * - HSE, PLL1, PLL2 and PLL3 OFF
161 * - AHB, APB Bus pre-scaler set to 1.
162 * - CSS, MCO1 and MCO2 OFF
163 * - All interrupts disabled
164 * @note This function doesn't modify the configuration of the
165 * - Peripheral clocks
166 * - LSI, LSE and RTC clocks
167 * @retval None
168 */
LL_RCC_DeInit(void)169 void LL_RCC_DeInit(void)
170 {
171 /* Disable all interrupts except default one */
172 WRITE_REG(RCC->CIER, RCC_CIER_HSECSSIE);
173
174 /* Clear all interrupts flags */
175 WRITE_REG(RCC->CICR, RCC_CICR_LSIRDYC | RCC_CICR_LSERDYC | RCC_CICR_MSIRDYC | RCC_CICR_HSIRDYC | RCC_CICR_HSERDYC | \
176 RCC_CICR_PLL1RDYC | RCC_CICR_PLL2RDYC | RCC_CICR_PLL3RDYC | RCC_CICR_PLL4RDYC | \
177 RCC_CICR_LSECSSC | RCC_CICR_HSECSSC | RCC_CICR_WKUPFC);
178
179 /* Clear reset source flags */
180 SET_BIT(RCC->RSR, RCC_RSR_RMVF);
181
182 /* Restore default HSI */
183 LL_RCC_HSI_SetDivider(LL_RCC_HSI_DIV_1);
184 LL_RCC_HSI_Enable();
185
186 /* Wait for HSI READY bit */
187 while (LL_RCC_HSI_IsReady() == 0U)
188 {}
189
190 /* Reset CFGR1 register to select HSI as system clock */
191 CLEAR_REG(RCC->CFGR1);
192
193 /* Reset MSION, HSEON, PLL1ON, PLL2ON, PLL3ON and PLL4ON bits */
194 WRITE_REG(RCC->CCR, RCC_CCR_MSIONC | RCC_CCR_HSEONC | \
195 RCC_CCR_PLL1ONC | RCC_CCR_PLL2ONC | RCC_CCR_PLL3ONC | RCC_CCR_PLL4ONC);
196
197 /* Wait for PLL1 READY bit to be reset */
198 while (LL_RCC_PLL1_IsReady() != 0U)
199 {}
200
201 /* Wait for PLL2 READY bit to be reset */
202 while (LL_RCC_PLL2_IsReady() != 0U)
203 {}
204
205 /* Wait for PLL3 READY bit to be reset */
206 while (LL_RCC_PLL3_IsReady() != 0U)
207 {}
208
209 /* Wait for PLL4 READY bit to be reset */
210 while (LL_RCC_PLL4_IsReady() != 0U)
211 {}
212
213 /* Reset prescalers in CFGR2 register */
214 CLEAR_REG(RCC->CFGR2);
215
216 /* Reset LSECFGR register */
217 CLEAR_REG(RCC->LSECFGR);
218
219 /* Reset MSICFGR register */
220 CLEAR_REG(RCC->MSICFGR);
221
222 /* Reset HSIMCR register to default value */
223 WRITE_REG(RCC->HSIMCR, 0x001F07A1U);
224
225 /* Reset HSECFGR register to default value */
226 WRITE_REG(RCC->HSECFGR, 0x00000800U);
227
228 /* Reset STOPCR register to default value */
229 WRITE_REG(RCC->STOPCR, 0x00000008U);
230
231 /* Reset PLL1 registers to default value */
232 WRITE_REG(RCC->PLL1CFGR1, 0x08202500U);
233 WRITE_REG(RCC->PLL1CFGR2, 0x00800000U);
234 WRITE_REG(RCC->PLL1CFGR3, 0x4900000DU);
235 /* Reset PLL2 registers to default value */
236 WRITE_REG(RCC->PLL2CFGR1, 0x08000000U);
237 WRITE_REG(RCC->PLL2CFGR2, 0x00000000U);
238 WRITE_REG(RCC->PLL2CFGR3, 0x49000005U);
239 /* Reset PLL3 registers to default value */
240 WRITE_REG(RCC->PLL3CFGR1, 0x08000000U);
241 WRITE_REG(RCC->PLL3CFGR2, 0x00000000U);
242 WRITE_REG(RCC->PLL3CFGR3, 0x49000005U);
243 /* Reset PLL4 registers to default value */
244 WRITE_REG(RCC->PLL4CFGR1, 0x08000000U);
245 WRITE_REG(RCC->PLL4CFGR2, 0x00000000U);
246 WRITE_REG(RCC->PLL4CFGR3, 0x49000005U);
247
248 /* Disable DIVENR register to set ICx state to default value */
249 WRITE_REG(RCC->DIVENCR, 0x00FFFFFFU);
250
251 /* ICxCFGR reset value */
252 WRITE_REG(RCC->IC1CFGR, 0x00020000U);
253 WRITE_REG(RCC->IC2CFGR, 0x00030000U);
254 WRITE_REG(RCC->IC3CFGR, 0x00000000U);
255 WRITE_REG(RCC->IC4CFGR, 0x00000000U);
256 WRITE_REG(RCC->IC5CFGR, 0x00000000U);
257 WRITE_REG(RCC->IC6CFGR, 0x00030000U);
258 WRITE_REG(RCC->IC7CFGR, 0x10000000U);
259 WRITE_REG(RCC->IC8CFGR, 0x10000000U);
260 WRITE_REG(RCC->IC9CFGR, 0x10000000U);
261 WRITE_REG(RCC->IC10CFGR, 0x10000000U);
262 WRITE_REG(RCC->IC11CFGR, 0x00030000U);
263 WRITE_REG(RCC->IC12CFGR, 0x20000000U);
264 WRITE_REG(RCC->IC13CFGR, 0x20000000U);
265 WRITE_REG(RCC->IC14CFGR, 0x20000000U);
266 WRITE_REG(RCC->IC15CFGR, 0x20000000U);
267 WRITE_REG(RCC->IC16CFGR, 0x30000000U);
268 WRITE_REG(RCC->IC17CFGR, 0x30000000U);
269 WRITE_REG(RCC->IC18CFGR, 0x30000000U);
270 WRITE_REG(RCC->IC19CFGR, 0x30000000U);
271 WRITE_REG(RCC->IC20CFGR, 0x30000000U);
272
273 /* CCIPRx reset value except RTCSEL/RTCPRE preserved */
274 WRITE_REG(RCC->CCIPR1, 0x00000000U);
275 WRITE_REG(RCC->CCIPR2, 0x00000000U);
276 WRITE_REG(RCC->CCIPR3, 0x00000001U);
277 WRITE_REG(RCC->CCIPR4, 0x00000000U);
278 WRITE_REG(RCC->CCIPR5, 0x0000F0F0U);
279 WRITE_REG(RCC->CCIPR6, 0x00000000U);
280 MODIFY_REG(RCC->CCIPR7, RCC_CCIPR7_PERSEL | RCC_CCIPR7_PSSISEL | \
281 RCC_CCIPR7_SAI1SEL | RCC_CCIPR7_SAI2SEL, 0x00000000U);
282 WRITE_REG(RCC->CCIPR8, 0x00000000U);
283 WRITE_REG(RCC->CCIPR9, 0x00000000U);
284 WRITE_REG(RCC->CCIPR12, 0x00000000U);
285 WRITE_REG(RCC->CCIPR13, 0x00000000U);
286 WRITE_REG(RCC->CCIPR14, 0x00000000U);
287
288 /* Reset MEMENR register to default value */
289 WRITE_REG(RCC->MEMENR, 0x000013FFU);
290
291 /* Reset MISCENR register */
292 CLEAR_REG(RCC->MISCENR);
293 }
294
295 /**
296 * @}
297 */
298
299 /** @addtogroup RCC_LL_EF_Get_Freq
300 * @brief Return the frequencies of different on chip clocks; System, AHB, APB1, APB2, APB3 and APB4 buses clocks.
301 * and different peripheral clocks available on the device.
302 * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
303 * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)
304 * @note If SYSCLK source is MSI, function returns values based on MSI_VALUE(***)
305 * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(**)
306 * or HSI_VALUE(*) multiplied/divided by the PLL factors.
307 * @note (*) HSI_VALUE is a constant defined in header file (default value
308 * 64 MHz) divider by HSIDIV, but the real value may vary depending on
309 * on the variations in voltage and temperature.
310 * @note (**) HSE_VALUE is a constant defined in header file (default value
311 * 25 MHz), user has to ensure that HSE_VALUE is same as the real
312 * frequency of the crystal used. Otherwise, this function may
313 * have wrong result.
314 * @note (***) MSI_VALUE is a constant defined in header file (default value
315 * 4 MHz) but the real value may vary depending on the variations
316 * in voltage and temperature.
317 * @note The result of this function could be incorrect when using fractional
318 * value for HSE crystal.
319 * @note This function can be used by the user application to compute the
320 * baud-rate for the communication peripherals or configure other parameters.
321 * @{
322 */
323
324 /**
325 * @brief Return the frequencies of different on chip clocks; CPU, System bus, AHB, APB1, APB2, APB4
326 * and APB5 buses clocks.
327 * @note Each time CPUCLK, SYSCLK, HCLK, PCLK1, PCLK2, PCLK4 and/or PCLK5 clock changes, this function
328 * must be called to update application structure fields. Otherwise, any configuration based on this
329 * function will be incorrect.
330 * @param RCC_Clocks pointer to a @ref LL_RCC_ClocksTypeDef structure which will hold the clocks frequencies
331 * @retval None
332 */
LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef * RCC_Clocks)333 void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks)
334 {
335 /* Get CPU frequency */
336 RCC_Clocks->CPUCLK_Frequency = LL_RCC_GetCpuClockFreq();
337
338 /* Get SYSCLK frequency */
339 RCC_Clocks->SYSCLK_Frequency = LL_RCC_GetSystemClockFreq();
340
341 /* HCLK clock frequency */
342 RCC_Clocks->HCLK_Frequency = RCC_GetHCLKClockFreq(RCC_Clocks->SYSCLK_Frequency);
343
344 /* PCLK1 clock frequency */
345 RCC_Clocks->PCLK1_Frequency = RCC_GetPCLK1ClockFreq(RCC_Clocks->HCLK_Frequency);
346
347 /* PCLK2 clock frequency */
348 RCC_Clocks->PCLK2_Frequency = RCC_GetPCLK2ClockFreq(RCC_Clocks->HCLK_Frequency);
349
350 /* PCLK4 clock frequency */
351 RCC_Clocks->PCLK4_Frequency = RCC_GetPCLK4ClockFreq(RCC_Clocks->HCLK_Frequency);
352
353 /* PCLK5 clock frequency */
354 RCC_Clocks->PCLK5_Frequency = RCC_GetPCLK5ClockFreq(RCC_Clocks->HCLK_Frequency);
355 }
356
357 /**
358 * @brief Return CPU clock frequency
359 * @retval CPU clock frequency (in Hz)
360 */
LL_RCC_GetCpuClockFreq(void)361 uint32_t LL_RCC_GetCpuClockFreq(void)
362 {
363 uint32_t frequency = 0U;
364 uint32_t ic_divider;
365
366 /* Get CPU clock source ----------------------------------------------------*/
367 switch (LL_RCC_GetCpuClkSource())
368 {
369 /* No check on Ready: Won't be selected by hardware if not */
370 case LL_RCC_CPU_CLKSOURCE_STATUS_HSI:
371 frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_HSICFGR_HSIDIV_Pos);
372 break;
373
374 case LL_RCC_CPU_CLKSOURCE_STATUS_MSI:
375 frequency = MSI_VALUE;
376 break;
377
378 case LL_RCC_CPU_CLKSOURCE_STATUS_HSE:
379 frequency = HSE_VALUE;
380 break;
381
382 case LL_RCC_CPU_CLKSOURCE_STATUS_IC1:
383 ic_divider = LL_RCC_IC1_GetDivider();
384 switch (LL_RCC_IC1_GetSource())
385 {
386 case LL_RCC_ICCLKSOURCE_PLL1:
387 frequency = LL_RCC_GetPLL1ClockFreq();
388 frequency = frequency / ic_divider;
389 break;
390 case LL_RCC_ICCLKSOURCE_PLL2:
391 frequency = LL_RCC_GetPLL2ClockFreq();
392 frequency = frequency / ic_divider;
393 break;
394 case LL_RCC_ICCLKSOURCE_PLL3:
395 frequency = LL_RCC_GetPLL3ClockFreq();
396 frequency = frequency / ic_divider;
397 break;
398 case LL_RCC_ICCLKSOURCE_PLL4:
399 frequency = LL_RCC_GetPLL4ClockFreq();
400 frequency = frequency / ic_divider;
401 break;
402 default:
403 /* Unexpected case */
404 break;
405 }
406 break;
407
408 default:
409 /* Unexpected case */
410 break;
411 }
412
413 return frequency;
414 }
415
416 /**
417 * @brief Return SYSTEM bus clock frequency
418 * @retval SYSTEM bus clock frequency (in Hz)
419 */
LL_RCC_GetSystemClockFreq(void)420 uint32_t LL_RCC_GetSystemClockFreq(void)
421 {
422 uint32_t frequency = 0U;
423 uint32_t ic_divider;
424
425 /* Get SYSCLK source -------------------------------------------------------*/
426 switch (LL_RCC_GetSysClkSource())
427 {
428 /* No check on Ready: Won't be selected by hardware if not */
429 case LL_RCC_SYS_CLKSOURCE_STATUS_HSI:
430 frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_HSICFGR_HSIDIV_Pos);
431 break;
432
433 case LL_RCC_SYS_CLKSOURCE_STATUS_MSI:
434 frequency = MSI_VALUE;
435 break;
436
437 case LL_RCC_SYS_CLKSOURCE_STATUS_HSE:
438 frequency = HSE_VALUE;
439 break;
440
441 case LL_RCC_SYS_CLKSOURCE_STATUS_IC2_IC6_IC11:
442 ic_divider = LL_RCC_IC2_GetDivider();
443 switch (LL_RCC_IC2_GetSource())
444 {
445 case LL_RCC_ICCLKSOURCE_PLL1:
446 frequency = LL_RCC_GetPLL1ClockFreq();
447 frequency = frequency / ic_divider;
448 break;
449 case LL_RCC_ICCLKSOURCE_PLL2:
450 frequency = LL_RCC_GetPLL2ClockFreq();
451 frequency = frequency / ic_divider;
452 break;
453 case LL_RCC_ICCLKSOURCE_PLL3:
454 frequency = LL_RCC_GetPLL3ClockFreq();
455 frequency = frequency / ic_divider;
456 break;
457 case LL_RCC_ICCLKSOURCE_PLL4:
458 frequency = LL_RCC_GetPLL4ClockFreq();
459 frequency = frequency / ic_divider;
460 break;
461 default:
462 /* Unexpected case */
463 break;
464 }
465 break;
466
467 default:
468 /* Unexpected case */
469 break;
470 }
471
472 return frequency;
473 }
474
475 /**
476 * @brief Return PLL1 clock frequency
477 * @note LL_RCC_PERIPH_FREQUENCY_NO returned for non activated output or oscillator not ready
478 * @retval PLL1 output clock frequency
479 */
LL_RCC_GetPLL1ClockFreq(void)480 uint32_t LL_RCC_GetPLL1ClockFreq(void)
481 {
482 uint32_t pllinputfreq = LL_RCC_PERIPH_FREQUENCY_NO;
483 uint32_t plloutputfreq = LL_RCC_PERIPH_FREQUENCY_NO;
484 uint32_t pllsource;
485 uint32_t divm;
486
487 /* PLL_VCO = (HSE_VALUE, MSI_VALUE or HSI_VALUE/HSIDIV) / PLLM * (PLLN + FRACN)
488 SYSCLK = PLL_VCO / PLLP1 / PLLP2
489 */
490 if (LL_RCC_PLL1_IsReady() != 0U)
491 {
492 if (LL_RCC_PLL1P_IsEnabled() != 0U)
493 {
494 pllsource = LL_RCC_PLL1_GetSource();
495
496 switch (pllsource)
497 {
498 case LL_RCC_PLLSOURCE_HSI:
499 if (LL_RCC_HSI_IsReady() != 0U)
500 {
501 pllinputfreq = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_HSICFGR_HSIDIV_Pos);
502 }
503 break;
504
505 case LL_RCC_PLLSOURCE_MSI:
506 if (LL_RCC_MSI_IsReady() != 0U)
507 {
508 pllinputfreq = MSI_VALUE;
509 }
510 break;
511
512 case LL_RCC_PLLSOURCE_HSE:
513 if (LL_RCC_HSE_IsReady() != 0U)
514 {
515 pllinputfreq = HSE_VALUE;
516 }
517 break;
518
519 case LL_RCC_PLLSOURCE_I2S_CKIN:
520 pllinputfreq = EXTERNAL_CLOCK_VALUE;
521 break;
522
523 default:
524 /* unexpected case */
525 break;
526 }
527
528 if (pllinputfreq != LL_RCC_PERIPH_FREQUENCY_NO)
529 {
530 #if defined(USE_FPGA)
531 /**** FPGA PLL input forced to 32MHz *****/
532 pllinputfreq = PLL_SOURCE_FREQ;
533 #endif /* USE_FPGA */
534 /* INTEGER mode only - others TO DO */
535 divm = LL_RCC_PLL1_GetM();
536
537 if (divm != 0U)
538 {
539 plloutputfreq = LL_RCC_CalcPLLClockFreq(pllinputfreq, divm, LL_RCC_PLL1_GetN(), LL_RCC_PLL1_GetFRACN(), \
540 LL_RCC_PLL1_GetP1(), LL_RCC_PLL1_GetP2());
541 }
542 }
543 }
544 }
545
546 return plloutputfreq;
547 }
548
549 /**
550 * @brief Return PLL2 clock frequency
551 * @note LL_RCC_PERIPH_FREQUENCY_NO returned for non activated output or oscillator not ready
552 * @retval PLL2 output clock frequency
553 */
LL_RCC_GetPLL2ClockFreq(void)554 uint32_t LL_RCC_GetPLL2ClockFreq(void)
555 {
556 uint32_t pllinputfreq = LL_RCC_PERIPH_FREQUENCY_NO;
557 uint32_t plloutputfreq = LL_RCC_PERIPH_FREQUENCY_NO;
558 uint32_t pllsource;
559 uint32_t divm;
560
561 /* PLL_VCO = (HSE_VALUE, MSI_VALUE or HSI_VALUE/HSIDIV) / PLLM * (PLLN + FRACN)
562 SYSCLK = PLL_VCO / PLLP1 / PLLP2
563 */
564 if (LL_RCC_PLL2_IsReady() != 0U)
565 {
566 if (LL_RCC_PLL2P_IsEnabled() != 0U)
567 {
568 pllsource = LL_RCC_PLL2_GetSource();
569
570 switch (pllsource)
571 {
572 case LL_RCC_PLLSOURCE_HSI:
573 if (LL_RCC_HSI_IsReady() != 0U)
574 {
575 pllinputfreq = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_HSICFGR_HSIDIV_Pos);
576 }
577 break;
578
579 case LL_RCC_PLLSOURCE_MSI:
580 if (LL_RCC_MSI_IsReady() != 0U)
581 {
582 pllinputfreq = MSI_VALUE;
583 }
584 break;
585
586 case LL_RCC_PLLSOURCE_HSE:
587 if (LL_RCC_HSE_IsReady() != 0U)
588 {
589 pllinputfreq = HSE_VALUE;
590 }
591 break;
592
593 case LL_RCC_PLLSOURCE_I2S_CKIN:
594 pllinputfreq = EXTERNAL_CLOCK_VALUE;
595 break;
596
597 default:
598 /* unexpected case */
599 break;
600 }
601
602 if (pllinputfreq != LL_RCC_PERIPH_FREQUENCY_NO)
603 {
604 #if defined(USE_FPGA)
605 /**** FPGA PLL input forced to 32MHz *****/
606 pllinputfreq = PLL_SOURCE_FREQ;
607 #endif /* USE_FPGA */
608 /* INTEGER mode only - others TO DO */
609 divm = LL_RCC_PLL2_GetM();
610
611 if (divm != 0U)
612 {
613 plloutputfreq = LL_RCC_CalcPLLClockFreq(pllinputfreq, divm, LL_RCC_PLL2_GetN(), LL_RCC_PLL2_GetFRACN(), \
614 LL_RCC_PLL2_GetP1(), LL_RCC_PLL2_GetP2());
615 }
616 }
617 }
618 }
619
620 return plloutputfreq;
621 }
622
623 /**
624 * @brief Return PLL3 clock frequency
625 * @note LL_RCC_PERIPH_FREQUENCY_NO returned for non activated output or oscillator not ready
626 * @retval PLL3 output clock frequency
627 */
LL_RCC_GetPLL3ClockFreq(void)628 uint32_t LL_RCC_GetPLL3ClockFreq(void)
629 {
630 uint32_t pllinputfreq = LL_RCC_PERIPH_FREQUENCY_NO;
631 uint32_t plloutputfreq = LL_RCC_PERIPH_FREQUENCY_NO;
632 uint32_t pllsource;
633 uint32_t divm;
634
635 /* PLL_VCO = (HSE_VALUE, MSI_VALUE or HSI_VALUE/HSIDIV) / PLLM * (PLLN + FRACN)
636 SYSCLK = PLL_VCO / PLLP1 / PLLP2
637 */
638 if (LL_RCC_PLL3_IsReady() != 0U)
639 {
640 if (LL_RCC_PLL3P_IsEnabled() != 0U)
641 {
642 pllsource = LL_RCC_PLL3_GetSource();
643
644 switch (pllsource)
645 {
646 case LL_RCC_PLLSOURCE_HSI:
647 if (LL_RCC_HSI_IsReady() != 0U)
648 {
649 pllinputfreq = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_HSICFGR_HSIDIV_Pos);
650 }
651 break;
652
653 case LL_RCC_PLLSOURCE_MSI:
654 if (LL_RCC_MSI_IsReady() != 0U)
655 {
656 pllinputfreq = MSI_VALUE;
657 }
658 break;
659
660 case LL_RCC_PLLSOURCE_HSE:
661 if (LL_RCC_HSE_IsReady() != 0U)
662 {
663 pllinputfreq = HSE_VALUE;
664 }
665 break;
666
667 case LL_RCC_PLLSOURCE_I2S_CKIN:
668 pllinputfreq = EXTERNAL_CLOCK_VALUE;
669 break;
670
671 default:
672 /* unexpected case */
673 break;
674 }
675
676 if (pllinputfreq != LL_RCC_PERIPH_FREQUENCY_NO)
677 {
678 #if defined(USE_FPGA)
679 /**** FPGA PLL input forced to 32MHz *****/
680 pllinputfreq = PLL_SOURCE_FREQ;
681 #endif /* USE_FPGA */
682 /* INTEGER mode only - others TO DO */
683 divm = LL_RCC_PLL3_GetM();
684
685 if (divm != 0U)
686 {
687 plloutputfreq = LL_RCC_CalcPLLClockFreq(pllinputfreq, divm, LL_RCC_PLL3_GetN(), LL_RCC_PLL3_GetFRACN(), \
688 LL_RCC_PLL3_GetP1(), LL_RCC_PLL3_GetP2());
689 }
690 }
691 }
692 }
693
694 return plloutputfreq;
695 }
696
697 /**
698 * @brief Return PLL4 clock frequency
699 * @note LL_RCC_PERIPH_FREQUENCY_NO returned for non activated output or oscillator not ready
700 * @retval PLL4 output clock frequency
701 */
LL_RCC_GetPLL4ClockFreq(void)702 uint32_t LL_RCC_GetPLL4ClockFreq(void)
703 {
704 uint32_t pllinputfreq = LL_RCC_PERIPH_FREQUENCY_NO;
705 uint32_t plloutputfreq = LL_RCC_PERIPH_FREQUENCY_NO;
706 uint32_t pllsource;
707 uint32_t divm;
708
709 /* PLL_VCO = (HSE_VALUE, MSI_VALUE or HSI_VALUE/HSIDIV) / PLLM * (PLLN + FRACN)
710 SYSCLK = PLL_VCO / PLLP1 / PLLP2
711 */
712 if (LL_RCC_PLL4_IsReady() != 0U)
713 {
714 if (LL_RCC_PLL4P_IsEnabled() != 0U)
715 {
716 pllsource = LL_RCC_PLL4_GetSource();
717
718 switch (pllsource)
719 {
720 case LL_RCC_PLLSOURCE_HSI:
721 if (LL_RCC_HSI_IsReady() != 0U)
722 {
723 pllinputfreq = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_HSICFGR_HSIDIV_Pos);
724 }
725 break;
726
727 case LL_RCC_PLLSOURCE_MSI:
728 if (LL_RCC_MSI_IsReady() != 0U)
729 {
730 pllinputfreq = MSI_VALUE;
731 }
732 break;
733
734 case LL_RCC_PLLSOURCE_HSE:
735 if (LL_RCC_HSE_IsReady() != 0U)
736 {
737 pllinputfreq = HSE_VALUE;
738 }
739 break;
740
741 case LL_RCC_PLLSOURCE_I2S_CKIN:
742 pllinputfreq = EXTERNAL_CLOCK_VALUE;
743 break;
744
745 default:
746 /* unexpected case */
747 break;
748 }
749
750 if (pllinputfreq != LL_RCC_PERIPH_FREQUENCY_NO)
751 {
752 #if defined(USE_FPGA)
753 /**** FPGA PLL input forced to 32MHz *****/
754 pllinputfreq = PLL_SOURCE_FREQ;
755 #endif /* USE_FPGA */
756 /* INTEGER mode only - others TO DO */
757 divm = LL_RCC_PLL4_GetM();
758
759 if (divm != 0U)
760 {
761 plloutputfreq = LL_RCC_CalcPLLClockFreq(pllinputfreq, divm, LL_RCC_PLL4_GetN(), LL_RCC_PLL4_GetFRACN(), \
762 LL_RCC_PLL4_GetP1(), LL_RCC_PLL4_GetP2());
763 }
764 }
765 }
766 }
767
768 return plloutputfreq;
769 }
770
771 /**
772 * @brief Helper function to calculate the PLL frequency output when used in integer or fractional mode
773 * @note ex: @ref LL_RCC_CalcPLLClockFreq (HSE_VALUE, @ref LL_RCC_PLL1_GetM (), @ref LL_RCC_PLL1_GetN (),
774 * @ref LL_RCC_PLL1_GetFRACN (), @ref LL_RCC_PLL1_GetP1 (), @ref LL_RCC_PLL1_GetP2 ());
775 * @param PLLInputFreq PLL Input frequency (based on HSE/(HSI/HSIDIV)/MSI)
776 * @param M Between 1 and 63
777 * @param N Between 16 and 640 in integer mode, 20 to 320 in fractional mode
778 * @param FRACN 0 in integer mode, between 0 and 0xFFFFFF in fractional mode
779 * @param P1 VCO output divider P1 between 1 and 7
780 * @param P2 VCO output divider P2 between 1 and 7
781 * @retval PLL clock frequency (in Hz)
782 */
LL_RCC_CalcPLLClockFreq(uint32_t PLLInputFreq,uint32_t M,uint32_t N,uint32_t FRACN,uint32_t P1,uint32_t P2)783 uint32_t LL_RCC_CalcPLLClockFreq(uint32_t PLLInputFreq, uint32_t M, uint32_t N, uint32_t FRACN, uint32_t P1,
784 uint32_t P2)
785 {
786 float_t freq;
787
788 freq = ((float_t)PLLInputFreq * ((float_t)N + ((float_t)FRACN / (float_t)0x1000000))) / (float_t)M;
789
790 freq = freq / (float_t)P1;
791 freq = freq / (float_t)P2;
792
793 return (uint32_t)freq;
794 }
795
796 /**
797 * @brief Return ADC clock frequency
798 * @param ADCxSource This parameter can be one of the following values:
799 * @arg @ref LL_RCC_ADC_CLKSOURCE
800 * @retval ADC clock frequency (in Hz)
801 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
802 */
LL_RCC_GetADCClockFreq(uint32_t ADCxSource)803 uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource)
804 {
805 uint32_t frequency = LL_RCC_PERIPH_FREQUENCY_NO;
806 uint32_t ic_divider;
807
808 /* Check parameter */
809 assert_param(IS_LL_RCC_ADC_CLKSOURCE(ADCxSource));
810
811 switch (LL_RCC_GetADCClockSource(ADCxSource))
812 {
813 case LL_RCC_ADC_CLKSOURCE_HCLK:
814 frequency = RCC_GetHCLKClockFreq(LL_RCC_GetSystemClockFreq());
815 break;
816
817 case LL_RCC_ADC_CLKSOURCE_CLKP:
818 frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_CLKP_CLKSOURCE);
819 break;
820
821 case LL_RCC_ADC_CLKSOURCE_IC7:
822 if (LL_RCC_IC7_IsEnabled() != 0U)
823 {
824 ic_divider = LL_RCC_IC7_GetDivider();
825 switch (LL_RCC_IC7_GetSource())
826 {
827 case LL_RCC_ICCLKSOURCE_PLL1:
828 frequency = LL_RCC_GetPLL1ClockFreq();
829 frequency = frequency / ic_divider;
830 break;
831 case LL_RCC_ICCLKSOURCE_PLL2:
832 frequency = LL_RCC_GetPLL2ClockFreq();
833 frequency = frequency / ic_divider;
834 break;
835 case LL_RCC_ICCLKSOURCE_PLL3:
836 frequency = LL_RCC_GetPLL3ClockFreq();
837 frequency = frequency / ic_divider;
838 break;
839 case LL_RCC_ICCLKSOURCE_PLL4:
840 frequency = LL_RCC_GetPLL4ClockFreq();
841 frequency = frequency / ic_divider;
842 break;
843 default:
844 /* Unexpected case */
845 break;
846 }
847 }
848 break;
849
850 case LL_RCC_ADC_CLKSOURCE_IC8:
851 if (LL_RCC_IC8_IsEnabled() != 0U)
852 {
853 ic_divider = LL_RCC_IC8_GetDivider();
854 switch (LL_RCC_IC8_GetSource())
855 {
856 case LL_RCC_ICCLKSOURCE_PLL1:
857 frequency = LL_RCC_GetPLL1ClockFreq();
858 frequency = frequency / ic_divider;
859 break;
860 case LL_RCC_ICCLKSOURCE_PLL2:
861 frequency = LL_RCC_GetPLL2ClockFreq();
862 frequency = frequency / ic_divider;
863 break;
864 case LL_RCC_ICCLKSOURCE_PLL3:
865 frequency = LL_RCC_GetPLL3ClockFreq();
866 frequency = frequency / ic_divider;
867 break;
868 case LL_RCC_ICCLKSOURCE_PLL4:
869 frequency = LL_RCC_GetPLL4ClockFreq();
870 frequency = frequency / ic_divider;
871 break;
872 default:
873 /* Unexpected case */
874 break;
875 }
876 }
877 break;
878
879 case LL_RCC_ADC_CLKSOURCE_HSI:
880 if (LL_RCC_HSI_IsReady() != 0U)
881 {
882 frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_HSICFGR_HSIDIV_Pos);
883 }
884 break;
885
886 case LL_RCC_ADC_CLKSOURCE_MSI:
887 if (LL_RCC_MSI_IsReady() != 0U)
888 {
889 frequency = MSI_VALUE;
890 }
891 break;
892
893 case LL_RCC_ADC_CLKSOURCE_I2S_CKIN:
894 frequency = EXTERNAL_CLOCK_VALUE;
895 break;
896
897 case LL_RCC_ADC_CLKSOURCE_TIMG:
898 frequency = LL_RCC_GetSystemClockFreq() / (1UL << LL_RCC_GetTIMPrescaler());
899 break;
900
901 default:
902 /* Unexpected case */
903 break;
904 }
905
906 return frequency;
907 }
908
909 /**
910 * @brief Return ADFx clock frequency
911 * @param ADFxSource This parameter can be one of the following values:
912 * @arg @ref LL_RCC_ADF1_CLKSOURCE
913 * @retval ADF clock frequency (in Hz)
914 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
915 */
LL_RCC_GetADFClockFreq(uint32_t ADFxSource)916 uint32_t LL_RCC_GetADFClockFreq(uint32_t ADFxSource)
917 {
918 uint32_t frequency = LL_RCC_PERIPH_FREQUENCY_NO;
919 uint32_t ic_divider;
920
921 /* Check parameter */
922 assert_param(IS_LL_RCC_ADF_CLKSOURCE(ADFxSource));
923
924 switch (LL_RCC_GetADFClockSource(ADFxSource))
925 {
926 case LL_RCC_ADF1_CLKSOURCE_HCLK:
927 frequency = RCC_GetHCLKClockFreq(LL_RCC_GetSystemClockFreq());
928 break;
929
930 case LL_RCC_ADF1_CLKSOURCE_CLKP:
931 frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_CLKP_CLKSOURCE);
932 break;
933
934 case LL_RCC_ADF1_CLKSOURCE_IC7:
935 if (LL_RCC_IC7_IsEnabled() != 0U)
936 {
937 ic_divider = LL_RCC_IC7_GetDivider();
938 switch (LL_RCC_IC7_GetSource())
939 {
940 case LL_RCC_ICCLKSOURCE_PLL1:
941 frequency = LL_RCC_GetPLL1ClockFreq();
942 frequency = frequency / ic_divider;
943 break;
944 case LL_RCC_ICCLKSOURCE_PLL2:
945 frequency = LL_RCC_GetPLL2ClockFreq();
946 frequency = frequency / ic_divider;
947 break;
948 case LL_RCC_ICCLKSOURCE_PLL3:
949 frequency = LL_RCC_GetPLL3ClockFreq();
950 frequency = frequency / ic_divider;
951 break;
952 case LL_RCC_ICCLKSOURCE_PLL4:
953 frequency = LL_RCC_GetPLL4ClockFreq();
954 frequency = frequency / ic_divider;
955 break;
956 default:
957 /* Unexpected case */
958 break;
959 }
960 }
961 break;
962
963 case LL_RCC_ADF1_CLKSOURCE_IC8:
964 if (LL_RCC_IC8_IsEnabled() != 0U)
965 {
966 ic_divider = LL_RCC_IC8_GetDivider();
967 switch (LL_RCC_IC8_GetSource())
968 {
969 case LL_RCC_ICCLKSOURCE_PLL1:
970 frequency = LL_RCC_GetPLL1ClockFreq();
971 frequency = frequency / ic_divider;
972 break;
973 case LL_RCC_ICCLKSOURCE_PLL2:
974 frequency = LL_RCC_GetPLL2ClockFreq();
975 frequency = frequency / ic_divider;
976 break;
977 case LL_RCC_ICCLKSOURCE_PLL3:
978 frequency = LL_RCC_GetPLL3ClockFreq();
979 frequency = frequency / ic_divider;
980 break;
981 case LL_RCC_ICCLKSOURCE_PLL4:
982 frequency = LL_RCC_GetPLL4ClockFreq();
983 frequency = frequency / ic_divider;
984 break;
985 default:
986 /* Unexpected case */
987 break;
988 }
989 }
990 break;
991
992 case LL_RCC_ADF1_CLKSOURCE_HSI:
993 if (LL_RCC_HSI_IsReady() != 0U)
994 {
995 frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_HSICFGR_HSIDIV_Pos);
996 }
997 break;
998
999 case LL_RCC_ADF1_CLKSOURCE_MSI:
1000 if (LL_RCC_MSI_IsReady() != 0U)
1001 {
1002 frequency = MSI_VALUE;
1003 }
1004 break;
1005
1006 case LL_RCC_ADF1_CLKSOURCE_I2S_CKIN:
1007 frequency = EXTERNAL_CLOCK_VALUE;
1008 break;
1009
1010 case LL_RCC_ADF1_CLKSOURCE_TIMG:
1011 frequency = LL_RCC_GetSystemClockFreq() / (1UL << LL_RCC_GetTIMPrescaler());
1012 break;
1013
1014 default:
1015 /* Unexpected case */
1016 break;
1017 }
1018
1019 return frequency;
1020 }
1021
1022 /**
1023 * @brief Return CLKP clock frequency
1024 * @param CLKPxSource This parameter can be one of the following values:
1025 * @arg @ref LL_RCC_CLKP_CLKSOURCE
1026 * @retval CLKP clock frequency (in Hz)
1027 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
1028 */
LL_RCC_GetCLKPClockFreq(uint32_t CLKPxSource)1029 uint32_t LL_RCC_GetCLKPClockFreq(uint32_t CLKPxSource)
1030 {
1031 uint32_t frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1032 uint32_t ic_divider;
1033
1034 switch (LL_RCC_GetCLKPClockSource(CLKPxSource))
1035 {
1036 case LL_RCC_CLKP_CLKSOURCE_HSI:
1037 if (LL_RCC_HSI_IsReady() != 0U)
1038 {
1039 frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_HSICFGR_HSIDIV_Pos);
1040 }
1041 break;
1042
1043 case LL_RCC_CLKP_CLKSOURCE_MSI:
1044 if (LL_RCC_MSI_IsReady() != 0U)
1045 {
1046 frequency = MSI_VALUE;
1047 }
1048 break;
1049
1050 case LL_RCC_CLKP_CLKSOURCE_HSE:
1051 if (LL_RCC_HSE_IsReady() != 0U)
1052 {
1053 frequency = HSE_VALUE;
1054 }
1055 break;
1056
1057 case LL_RCC_CLKP_CLKSOURCE_IC5:
1058 if (LL_RCC_IC5_IsEnabled() != 0U)
1059 {
1060 ic_divider = LL_RCC_IC5_GetDivider();
1061 switch (LL_RCC_IC5_GetSource())
1062 {
1063 case LL_RCC_ICCLKSOURCE_PLL1:
1064 frequency = LL_RCC_GetPLL1ClockFreq();
1065 frequency = frequency / ic_divider;
1066 break;
1067 case LL_RCC_ICCLKSOURCE_PLL2:
1068 frequency = LL_RCC_GetPLL2ClockFreq();
1069 frequency = frequency / ic_divider;
1070 break;
1071 case LL_RCC_ICCLKSOURCE_PLL3:
1072 frequency = LL_RCC_GetPLL3ClockFreq();
1073 frequency = frequency / ic_divider;
1074 break;
1075 case LL_RCC_ICCLKSOURCE_PLL4:
1076 frequency = LL_RCC_GetPLL4ClockFreq();
1077 frequency = frequency / ic_divider;
1078 break;
1079 default:
1080 /* Unexpected case */
1081 break;
1082 }
1083 }
1084 break;
1085
1086 case LL_RCC_CLKP_CLKSOURCE_IC10:
1087 if (LL_RCC_IC10_IsEnabled() != 0U)
1088 {
1089 ic_divider = LL_RCC_IC10_GetDivider();
1090 switch (LL_RCC_IC10_GetSource())
1091 {
1092 case LL_RCC_ICCLKSOURCE_PLL1:
1093 frequency = LL_RCC_GetPLL1ClockFreq();
1094 frequency = frequency / ic_divider;
1095 break;
1096 case LL_RCC_ICCLKSOURCE_PLL2:
1097 frequency = LL_RCC_GetPLL2ClockFreq();
1098 frequency = frequency / ic_divider;
1099 break;
1100 case LL_RCC_ICCLKSOURCE_PLL3:
1101 frequency = LL_RCC_GetPLL3ClockFreq();
1102 frequency = frequency / ic_divider;
1103 break;
1104 case LL_RCC_ICCLKSOURCE_PLL4:
1105 frequency = LL_RCC_GetPLL4ClockFreq();
1106 frequency = frequency / ic_divider;
1107 break;
1108 default:
1109 /* Unexpected case */
1110 break;
1111 }
1112 }
1113 break;
1114
1115 case LL_RCC_CLKP_CLKSOURCE_IC15:
1116 if (LL_RCC_IC15_IsEnabled() != 0U)
1117 {
1118 ic_divider = LL_RCC_IC15_GetDivider();
1119 switch (LL_RCC_IC15_GetSource())
1120 {
1121 case LL_RCC_ICCLKSOURCE_PLL1:
1122 frequency = LL_RCC_GetPLL1ClockFreq();
1123 frequency = frequency / ic_divider;
1124 break;
1125 case LL_RCC_ICCLKSOURCE_PLL2:
1126 frequency = LL_RCC_GetPLL2ClockFreq();
1127 frequency = frequency / ic_divider;
1128 break;
1129 case LL_RCC_ICCLKSOURCE_PLL3:
1130 frequency = LL_RCC_GetPLL3ClockFreq();
1131 frequency = frequency / ic_divider;
1132 break;
1133 case LL_RCC_ICCLKSOURCE_PLL4:
1134 frequency = LL_RCC_GetPLL4ClockFreq();
1135 frequency = frequency / ic_divider;
1136 break;
1137 default:
1138 /* Unexpected case */
1139 break;
1140 }
1141 }
1142 break;
1143
1144 case LL_RCC_CLKP_CLKSOURCE_IC19:
1145 if (LL_RCC_IC19_IsEnabled() != 0U)
1146 {
1147 ic_divider = LL_RCC_IC19_GetDivider();
1148 switch (LL_RCC_IC19_GetSource())
1149 {
1150 case LL_RCC_ICCLKSOURCE_PLL1:
1151 frequency = LL_RCC_GetPLL1ClockFreq();
1152 frequency = frequency / ic_divider;
1153 break;
1154 case LL_RCC_ICCLKSOURCE_PLL2:
1155 frequency = LL_RCC_GetPLL2ClockFreq();
1156 frequency = frequency / ic_divider;
1157 break;
1158 case LL_RCC_ICCLKSOURCE_PLL3:
1159 frequency = LL_RCC_GetPLL3ClockFreq();
1160 frequency = frequency / ic_divider;
1161 break;
1162 case LL_RCC_ICCLKSOURCE_PLL4:
1163 frequency = LL_RCC_GetPLL4ClockFreq();
1164 frequency = frequency / ic_divider;
1165 break;
1166 default:
1167 /* Unexpected case */
1168 break;
1169 }
1170 }
1171 break;
1172
1173 case LL_RCC_CLKP_CLKSOURCE_IC20:
1174 if (LL_RCC_IC20_IsEnabled() != 0U)
1175 {
1176 ic_divider = LL_RCC_IC20_GetDivider();
1177 switch (LL_RCC_IC20_GetSource())
1178 {
1179 case LL_RCC_ICCLKSOURCE_PLL1:
1180 frequency = LL_RCC_GetPLL1ClockFreq();
1181 frequency = frequency / ic_divider;
1182 break;
1183 case LL_RCC_ICCLKSOURCE_PLL2:
1184 frequency = LL_RCC_GetPLL2ClockFreq();
1185 frequency = frequency / ic_divider;
1186 break;
1187 case LL_RCC_ICCLKSOURCE_PLL3:
1188 frequency = LL_RCC_GetPLL3ClockFreq();
1189 frequency = frequency / ic_divider;
1190 break;
1191 case LL_RCC_ICCLKSOURCE_PLL4:
1192 frequency = LL_RCC_GetPLL4ClockFreq();
1193 frequency = frequency / ic_divider;
1194 break;
1195 default:
1196 /* Unexpected case */
1197 break;
1198 }
1199 }
1200 break;
1201
1202 default:
1203 /* Unexpected case */
1204 break;
1205 }
1206
1207 return frequency;
1208 }
1209
1210 /**
1211 * @brief Return DCMIPP clock frequency
1212 * @param DCMIPPxSource This parameter can be one of the following values:
1213 * @arg @ref LL_RCC_DCMIPP_CLKSOURCE
1214 * @retval DCMIPP clock frequency (in Hz)
1215 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
1216 */
LL_RCC_GetDCMIPPClockFreq(uint32_t DCMIPPxSource)1217 uint32_t LL_RCC_GetDCMIPPClockFreq(uint32_t DCMIPPxSource)
1218 {
1219 uint32_t frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1220 uint32_t ic_divider;
1221
1222 /* Check parameter */
1223 assert_param(IS_LL_RCC_DCMIPP_CLKSOURCE(DCMIPPxSource));
1224
1225 switch (LL_RCC_GetDCMIPPClockSource(DCMIPPxSource))
1226 {
1227 case LL_RCC_DCMIPP_CLKSOURCE_PCLK5:
1228 frequency = RCC_GetPCLK5ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_GetSystemClockFreq()));
1229 break;
1230
1231 case LL_RCC_DCMIPP_CLKSOURCE_CLKP:
1232 frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_CLKP_CLKSOURCE);
1233 break;
1234
1235 case LL_RCC_DCMIPP_CLKSOURCE_IC17:
1236 if (LL_RCC_IC17_IsEnabled() != 0U)
1237 {
1238 ic_divider = LL_RCC_IC17_GetDivider();
1239 switch (LL_RCC_IC17_GetSource())
1240 {
1241 case LL_RCC_ICCLKSOURCE_PLL1:
1242 frequency = LL_RCC_GetPLL1ClockFreq();
1243 frequency = frequency / ic_divider;
1244 break;
1245 case LL_RCC_ICCLKSOURCE_PLL2:
1246 frequency = LL_RCC_GetPLL2ClockFreq();
1247 frequency = frequency / ic_divider;
1248 break;
1249 case LL_RCC_ICCLKSOURCE_PLL3:
1250 frequency = LL_RCC_GetPLL3ClockFreq();
1251 frequency = frequency / ic_divider;
1252 break;
1253 case LL_RCC_ICCLKSOURCE_PLL4:
1254 frequency = LL_RCC_GetPLL4ClockFreq();
1255 frequency = frequency / ic_divider;
1256 break;
1257 default:
1258 /* Unexpected case */
1259 break;
1260 }
1261 }
1262 break;
1263
1264 case LL_RCC_DCMIPP_CLKSOURCE_HSI:
1265 if (LL_RCC_HSI_IsReady() != 0U)
1266 {
1267 frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_HSICFGR_HSIDIV_Pos);
1268 }
1269 break;
1270
1271 default:
1272 /* Unexpected case */
1273 break;
1274 }
1275
1276 return frequency;
1277 }
1278
1279 /**
1280 * @brief Return ETH clock frequency
1281 * @param ETHxSource This parameter can be one of the following values:
1282 * @arg @ref LL_RCC_ETH1_CLKSOURCE
1283 * @retval ETH1 clock frequency (in Hz)
1284 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
1285 */
LL_RCC_GetETHClockFreq(uint32_t ETHxSource)1286 uint32_t LL_RCC_GetETHClockFreq(uint32_t ETHxSource)
1287 {
1288 uint32_t frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1289 uint32_t ic_divider;
1290
1291 /* Check parameter */
1292 assert_param(IS_LL_RCC_ETH_CLKSOURCE(ETHxSource));
1293
1294 switch (LL_RCC_GetETHClockSource(ETHxSource))
1295 {
1296 case LL_RCC_ETH1_CLKSOURCE_HCLK:
1297 frequency = RCC_GetHCLKClockFreq(LL_RCC_GetSystemClockFreq());
1298 break;
1299
1300 case LL_RCC_ETH1_CLKSOURCE_CLKP:
1301 frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_CLKP_CLKSOURCE);
1302 break;
1303
1304 case LL_RCC_ETH1_CLKSOURCE_IC12:
1305 if (LL_RCC_IC12_IsEnabled() != 0U)
1306 {
1307 ic_divider = LL_RCC_IC12_GetDivider();
1308 switch (LL_RCC_IC12_GetSource())
1309 {
1310 case LL_RCC_ICCLKSOURCE_PLL1:
1311 frequency = LL_RCC_GetPLL1ClockFreq();
1312 frequency = frequency / ic_divider;
1313 break;
1314 case LL_RCC_ICCLKSOURCE_PLL2:
1315 frequency = LL_RCC_GetPLL2ClockFreq();
1316 frequency = frequency / ic_divider;
1317 break;
1318 case LL_RCC_ICCLKSOURCE_PLL3:
1319 frequency = LL_RCC_GetPLL3ClockFreq();
1320 frequency = frequency / ic_divider;
1321 break;
1322 case LL_RCC_ICCLKSOURCE_PLL4:
1323 frequency = LL_RCC_GetPLL4ClockFreq();
1324 frequency = frequency / ic_divider;
1325 break;
1326 default:
1327 /* Unexpected case */
1328 break;
1329 }
1330 }
1331 break;
1332
1333 case LL_RCC_ETH1_CLKSOURCE_HSE:
1334 if (LL_RCC_HSE_IsReady() != 0U)
1335 {
1336 frequency = HSE_VALUE;
1337 }
1338 break;
1339
1340 default:
1341 /* Unexpected case */
1342 break;
1343 }
1344
1345 return frequency;
1346 }
1347
1348 /**
1349 * @brief Return ETH PTP clock frequency
1350 * @param ETHxPTPSource This parameter can be one of the following values:
1351 * @arg @ref LL_RCC_ETH1PTP_CLKSOURCE
1352 * @retval ETH1 PTP clock frequency with divider (in Hz)
1353 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
1354 */
LL_RCC_GetETHPTPClockFreq(uint32_t ETHxPTPSource)1355 uint32_t LL_RCC_GetETHPTPClockFreq(uint32_t ETHxPTPSource)
1356 {
1357 uint32_t frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1358 uint32_t ic_divider;
1359
1360 /* Check parameter */
1361 assert_param(IS_LL_RCC_ETHPTP_CLKSOURCE(ETHxPTPSource));
1362
1363 switch (LL_RCC_GetETHPTPClockSource(ETHxPTPSource))
1364 {
1365 case LL_RCC_ETH1PTP_CLKSOURCE_HCLK:
1366 frequency = RCC_GetHCLKClockFreq(LL_RCC_GetSystemClockFreq());
1367 break;
1368
1369 case LL_RCC_ETH1PTP_CLKSOURCE_CLKP:
1370 frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_CLKP_CLKSOURCE);
1371 break;
1372
1373 case LL_RCC_ETH1PTP_CLKSOURCE_IC13:
1374 if (LL_RCC_IC13_IsEnabled() != 0U)
1375 {
1376 ic_divider = LL_RCC_IC13_GetDivider();
1377 switch (LL_RCC_IC13_GetSource())
1378 {
1379 case LL_RCC_ICCLKSOURCE_PLL1:
1380 frequency = LL_RCC_GetPLL1ClockFreq();
1381 frequency = frequency / ic_divider;
1382 break;
1383 case LL_RCC_ICCLKSOURCE_PLL2:
1384 frequency = LL_RCC_GetPLL2ClockFreq();
1385 frequency = frequency / ic_divider;
1386 break;
1387 case LL_RCC_ICCLKSOURCE_PLL3:
1388 frequency = LL_RCC_GetPLL3ClockFreq();
1389 frequency = frequency / ic_divider;
1390 break;
1391 case LL_RCC_ICCLKSOURCE_PLL4:
1392 frequency = LL_RCC_GetPLL4ClockFreq();
1393 frequency = frequency / ic_divider;
1394 break;
1395 default:
1396 /* Unexpected case */
1397 break;
1398 }
1399 }
1400 break;
1401
1402 case LL_RCC_ETH1PTP_CLKSOURCE_HSE:
1403 if (LL_RCC_HSE_IsReady() != 0U)
1404 {
1405 frequency = HSE_VALUE;
1406 }
1407 break;
1408
1409 default:
1410 /* Unexpected case */
1411 break;
1412 }
1413
1414 /* Apply divider */
1415 if (frequency != LL_RCC_PERIPH_FREQUENCY_NO)
1416 {
1417 frequency = frequency / ((LL_RCC_GetETH1PTPDivider() >> RCC_CCIPR2_ETH1PTPDIV_Pos) + 1U);
1418 }
1419
1420 return frequency;
1421 }
1422
1423 /**
1424 * @brief Return FDCAN clock frequency
1425 * @param FDCANxSource This parameter can be one of the following values:
1426 * @arg @ref LL_RCC_FDCAN_CLKSOURCE
1427 * @retval FDCAN clock frequency (in Hz)
1428 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
1429 */
LL_RCC_GetFDCANClockFreq(uint32_t FDCANxSource)1430 uint32_t LL_RCC_GetFDCANClockFreq(uint32_t FDCANxSource)
1431 {
1432 uint32_t frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1433 uint32_t ic_divider;
1434
1435 switch (LL_RCC_GetFDCANClockSource(FDCANxSource))
1436 {
1437 case LL_RCC_FDCAN_CLKSOURCE_PCLK1:
1438 frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_GetSystemClockFreq()));
1439 break;
1440
1441 case LL_RCC_FDCAN_CLKSOURCE_CLKP:
1442 frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_CLKP_CLKSOURCE);
1443 break;
1444
1445 case LL_RCC_FDCAN_CLKSOURCE_IC19:
1446 if (LL_RCC_IC19_IsEnabled() != 0U)
1447 {
1448 ic_divider = LL_RCC_IC19_GetDivider();
1449 switch (LL_RCC_IC19_GetSource())
1450 {
1451 case LL_RCC_ICCLKSOURCE_PLL1:
1452 frequency = LL_RCC_GetPLL1ClockFreq();
1453 frequency = frequency / ic_divider;
1454 break;
1455 case LL_RCC_ICCLKSOURCE_PLL2:
1456 frequency = LL_RCC_GetPLL2ClockFreq();
1457 frequency = frequency / ic_divider;
1458 break;
1459 case LL_RCC_ICCLKSOURCE_PLL3:
1460 frequency = LL_RCC_GetPLL3ClockFreq();
1461 frequency = frequency / ic_divider;
1462 break;
1463 case LL_RCC_ICCLKSOURCE_PLL4:
1464 frequency = LL_RCC_GetPLL4ClockFreq();
1465 frequency = frequency / ic_divider;
1466 break;
1467 default:
1468 /* Unexpected case */
1469 break;
1470 }
1471 }
1472 break;
1473
1474 case LL_RCC_FDCAN_CLKSOURCE_HSE:
1475 if (LL_RCC_HSE_IsReady() != 0U)
1476 {
1477 frequency = HSE_VALUE;
1478 }
1479 break;
1480
1481 default:
1482 /* Unexpected case */
1483 break;
1484 }
1485
1486 return frequency;
1487 }
1488
1489 /**
1490 * @brief Return FMC clock frequency
1491 * @param FMCxSource This parameter can be one of the following values:
1492 * @arg @ref LL_RCC_FMC_CLKSOURCE
1493 * @retval FMC clock frequency (in Hz)
1494 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
1495 */
LL_RCC_GetFMCClockFreq(uint32_t FMCxSource)1496 uint32_t LL_RCC_GetFMCClockFreq(uint32_t FMCxSource)
1497 {
1498 uint32_t frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1499 uint32_t ic_divider;
1500
1501 switch (LL_RCC_GetFMCClockSource(FMCxSource))
1502 {
1503 case LL_RCC_FMC_CLKSOURCE_HCLK:
1504 frequency = RCC_GetHCLKClockFreq(LL_RCC_GetSystemClockFreq());
1505 break;
1506
1507 case LL_RCC_FMC_CLKSOURCE_CLKP:
1508 frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_CLKP_CLKSOURCE);
1509 break;
1510
1511 case LL_RCC_FMC_CLKSOURCE_IC3:
1512 if (LL_RCC_IC3_IsEnabled() != 0U)
1513 {
1514 ic_divider = LL_RCC_IC3_GetDivider();
1515 switch (LL_RCC_IC3_GetSource())
1516 {
1517 case LL_RCC_ICCLKSOURCE_PLL1:
1518 frequency = LL_RCC_GetPLL1ClockFreq();
1519 frequency = frequency / ic_divider;
1520 break;
1521 case LL_RCC_ICCLKSOURCE_PLL2:
1522 frequency = LL_RCC_GetPLL2ClockFreq();
1523 frequency = frequency / ic_divider;
1524 break;
1525 case LL_RCC_ICCLKSOURCE_PLL3:
1526 frequency = LL_RCC_GetPLL3ClockFreq();
1527 frequency = frequency / ic_divider;
1528 break;
1529 case LL_RCC_ICCLKSOURCE_PLL4:
1530 frequency = LL_RCC_GetPLL4ClockFreq();
1531 frequency = frequency / ic_divider;
1532 break;
1533 default:
1534 /* Unexpected case */
1535 break;
1536 }
1537 }
1538 break;
1539
1540 case LL_RCC_FMC_CLKSOURCE_IC4:
1541 if (LL_RCC_IC4_IsEnabled() != 0U)
1542 {
1543 ic_divider = LL_RCC_IC4_GetDivider();
1544 switch (LL_RCC_IC4_GetSource())
1545 {
1546 case LL_RCC_ICCLKSOURCE_PLL1:
1547 frequency = LL_RCC_GetPLL1ClockFreq();
1548 frequency = frequency / ic_divider;
1549 break;
1550 case LL_RCC_ICCLKSOURCE_PLL2:
1551 frequency = LL_RCC_GetPLL2ClockFreq();
1552 frequency = frequency / ic_divider;
1553 break;
1554 case LL_RCC_ICCLKSOURCE_PLL3:
1555 frequency = LL_RCC_GetPLL3ClockFreq();
1556 frequency = frequency / ic_divider;
1557 break;
1558 case LL_RCC_ICCLKSOURCE_PLL4:
1559 frequency = LL_RCC_GetPLL4ClockFreq();
1560 frequency = frequency / ic_divider;
1561 break;
1562 default:
1563 /* Unexpected case */
1564 break;
1565 }
1566 }
1567 break;
1568
1569 default:
1570 /* Unexpected case */
1571 break;
1572 }
1573
1574 return frequency;
1575 }
1576
1577 /**
1578 * @brief Return I2Cx clock frequency
1579 * @param I2CxSource This parameter can be one of the following values:
1580 * @arg @ref LL_RCC_I2C1_CLKSOURCE
1581 * @arg @ref LL_RCC_I2C2_CLKSOURCE
1582 * @arg @ref LL_RCC_I2C3_CLKSOURCE
1583 * @arg @ref LL_RCC_I2C4_CLKSOURCE
1584 * @retval I2C clock frequency (in Hz)
1585 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
1586 */
LL_RCC_GetI2CClockFreq(uint32_t I2CxSource)1587 uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource)
1588 {
1589 uint32_t frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1590 uint32_t ic_divider;
1591
1592 /* Check parameter */
1593 assert_param(IS_LL_RCC_I2C_CLKSOURCE(I2CxSource));
1594
1595 switch (LL_RCC_GetI2CClockSource(I2CxSource))
1596 {
1597 case LL_RCC_I2C1_CLKSOURCE_PCLK1:
1598 case LL_RCC_I2C2_CLKSOURCE_PCLK1:
1599 case LL_RCC_I2C3_CLKSOURCE_PCLK1:
1600 case LL_RCC_I2C4_CLKSOURCE_PCLK1:
1601 frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_GetSystemClockFreq()));
1602 break;
1603
1604 case LL_RCC_I2C1_CLKSOURCE_CLKP:
1605 case LL_RCC_I2C2_CLKSOURCE_CLKP:
1606 case LL_RCC_I2C3_CLKSOURCE_CLKP:
1607 case LL_RCC_I2C4_CLKSOURCE_CLKP:
1608 frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_CLKP_CLKSOURCE);
1609 break;
1610
1611 case LL_RCC_I2C1_CLKSOURCE_IC10:
1612 case LL_RCC_I2C2_CLKSOURCE_IC10:
1613 case LL_RCC_I2C3_CLKSOURCE_IC10:
1614 case LL_RCC_I2C4_CLKSOURCE_IC10:
1615 if (LL_RCC_IC10_IsEnabled() != 0U)
1616 {
1617 ic_divider = LL_RCC_IC10_GetDivider();
1618 switch (LL_RCC_IC10_GetSource())
1619 {
1620 case LL_RCC_ICCLKSOURCE_PLL1:
1621 frequency = LL_RCC_GetPLL1ClockFreq();
1622 frequency = frequency / ic_divider;
1623 break;
1624 case LL_RCC_ICCLKSOURCE_PLL2:
1625 frequency = LL_RCC_GetPLL2ClockFreq();
1626 frequency = frequency / ic_divider;
1627 break;
1628 case LL_RCC_ICCLKSOURCE_PLL3:
1629 frequency = LL_RCC_GetPLL3ClockFreq();
1630 frequency = frequency / ic_divider;
1631 break;
1632 case LL_RCC_ICCLKSOURCE_PLL4:
1633 frequency = LL_RCC_GetPLL4ClockFreq();
1634 frequency = frequency / ic_divider;
1635 break;
1636 default:
1637 /* Unexpected case */
1638 break;
1639 }
1640 }
1641 break;
1642
1643 case LL_RCC_I2C1_CLKSOURCE_IC15:
1644 case LL_RCC_I2C2_CLKSOURCE_IC15:
1645 case LL_RCC_I2C3_CLKSOURCE_IC15:
1646 case LL_RCC_I2C4_CLKSOURCE_IC15:
1647 if (LL_RCC_IC15_IsEnabled() != 0U)
1648 {
1649 ic_divider = LL_RCC_IC15_GetDivider();
1650 switch (LL_RCC_IC15_GetSource())
1651 {
1652 case LL_RCC_ICCLKSOURCE_PLL1:
1653 frequency = LL_RCC_GetPLL1ClockFreq();
1654 frequency = frequency / ic_divider;
1655 break;
1656 case LL_RCC_ICCLKSOURCE_PLL2:
1657 frequency = LL_RCC_GetPLL2ClockFreq();
1658 frequency = frequency / ic_divider;
1659 break;
1660 case LL_RCC_ICCLKSOURCE_PLL3:
1661 frequency = LL_RCC_GetPLL3ClockFreq();
1662 frequency = frequency / ic_divider;
1663 break;
1664 case LL_RCC_ICCLKSOURCE_PLL4:
1665 frequency = LL_RCC_GetPLL4ClockFreq();
1666 frequency = frequency / ic_divider;
1667 break;
1668 default:
1669 /* Unexpected case */
1670 break;
1671 }
1672 }
1673 break;
1674
1675 case LL_RCC_I2C1_CLKSOURCE_HSI:
1676 case LL_RCC_I2C2_CLKSOURCE_HSI:
1677 case LL_RCC_I2C3_CLKSOURCE_HSI:
1678 case LL_RCC_I2C4_CLKSOURCE_HSI:
1679 if (LL_RCC_HSI_IsReady() != 0U)
1680 {
1681 frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_HSICFGR_HSIDIV_Pos);
1682 }
1683 break;
1684
1685 case LL_RCC_I2C1_CLKSOURCE_MSI:
1686 case LL_RCC_I2C2_CLKSOURCE_MSI:
1687 case LL_RCC_I2C3_CLKSOURCE_MSI:
1688 case LL_RCC_I2C4_CLKSOURCE_MSI:
1689 if (LL_RCC_MSI_IsReady() != 0U)
1690 {
1691 frequency = MSI_VALUE;
1692 }
1693 break;
1694
1695 default:
1696 /* Unexpected case */
1697 break;
1698 }
1699
1700 return frequency;
1701 }
1702
1703 /**
1704 * @brief Return I3Cx clock frequency
1705 * @param I3CxSource This parameter can be one of the following values:
1706 * @arg @ref LL_RCC_I3C1_CLKSOURCE
1707 * @arg @ref LL_RCC_I3C2_CLKSOURCE
1708 * @retval I3C clock frequency (in Hz)
1709 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
1710 */
LL_RCC_GetI3CClockFreq(uint32_t I3CxSource)1711 uint32_t LL_RCC_GetI3CClockFreq(uint32_t I3CxSource)
1712 {
1713 uint32_t frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1714 uint32_t ic_divider;
1715
1716 /* Check parameter */
1717 assert_param(IS_LL_RCC_I3C_CLKSOURCE(I3CxSource));
1718
1719 switch (LL_RCC_GetI3CClockSource(I3CxSource))
1720 {
1721 case LL_RCC_I3C1_CLKSOURCE_PCLK1:
1722 case LL_RCC_I3C2_CLKSOURCE_PCLK1:
1723 frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_GetSystemClockFreq()));
1724 break;
1725
1726 case LL_RCC_I3C1_CLKSOURCE_CLKP:
1727 case LL_RCC_I3C2_CLKSOURCE_CLKP:
1728 frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_CLKP_CLKSOURCE);
1729 break;
1730
1731 case LL_RCC_I3C1_CLKSOURCE_IC10:
1732 case LL_RCC_I3C2_CLKSOURCE_IC10:
1733 if (LL_RCC_IC10_IsEnabled() != 0U)
1734 {
1735 ic_divider = LL_RCC_IC10_GetDivider();
1736 switch (LL_RCC_IC10_GetSource())
1737 {
1738 case LL_RCC_ICCLKSOURCE_PLL1:
1739 frequency = LL_RCC_GetPLL1ClockFreq();
1740 frequency = frequency / ic_divider;
1741 break;
1742 case LL_RCC_ICCLKSOURCE_PLL2:
1743 frequency = LL_RCC_GetPLL2ClockFreq();
1744 frequency = frequency / ic_divider;
1745 break;
1746 case LL_RCC_ICCLKSOURCE_PLL3:
1747 frequency = LL_RCC_GetPLL3ClockFreq();
1748 frequency = frequency / ic_divider;
1749 break;
1750 case LL_RCC_ICCLKSOURCE_PLL4:
1751 frequency = LL_RCC_GetPLL4ClockFreq();
1752 frequency = frequency / ic_divider;
1753 break;
1754 default:
1755 /* Unexpected case */
1756 break;
1757 }
1758 }
1759 break;
1760
1761 case LL_RCC_I3C1_CLKSOURCE_IC15:
1762 case LL_RCC_I3C2_CLKSOURCE_IC15:
1763 if (LL_RCC_IC15_IsEnabled() != 0U)
1764 {
1765 ic_divider = LL_RCC_IC15_GetDivider();
1766 switch (LL_RCC_IC15_GetSource())
1767 {
1768 case LL_RCC_ICCLKSOURCE_PLL1:
1769 frequency = LL_RCC_GetPLL1ClockFreq();
1770 frequency = frequency / ic_divider;
1771 break;
1772 case LL_RCC_ICCLKSOURCE_PLL2:
1773 frequency = LL_RCC_GetPLL2ClockFreq();
1774 frequency = frequency / ic_divider;
1775 break;
1776 case LL_RCC_ICCLKSOURCE_PLL3:
1777 frequency = LL_RCC_GetPLL3ClockFreq();
1778 frequency = frequency / ic_divider;
1779 break;
1780 case LL_RCC_ICCLKSOURCE_PLL4:
1781 frequency = LL_RCC_GetPLL4ClockFreq();
1782 frequency = frequency / ic_divider;
1783 break;
1784 default:
1785 /* Unexpected case */
1786 break;
1787 }
1788 }
1789 break;
1790
1791 case LL_RCC_I3C1_CLKSOURCE_HSI:
1792 case LL_RCC_I3C2_CLKSOURCE_HSI:
1793 if (LL_RCC_HSI_IsReady() != 0U)
1794 {
1795 frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_HSICFGR_HSIDIV_Pos);
1796 }
1797 break;
1798
1799 case LL_RCC_I3C1_CLKSOURCE_MSI:
1800 case LL_RCC_I3C2_CLKSOURCE_MSI:
1801 if (LL_RCC_MSI_IsReady() != 0U)
1802 {
1803 frequency = MSI_VALUE;
1804 }
1805 break;
1806
1807 default:
1808 /* Unexpected case */
1809 break;
1810 }
1811
1812 return frequency;
1813 }
1814
1815 /**
1816 * @brief Return LPTIMx clock frequency
1817 * @param LPTIMxSource This parameter can be one of the following values:
1818 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE
1819 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE
1820 * @arg @ref LL_RCC_LPTIM3_CLKSOURCE
1821 * @arg @ref LL_RCC_LPTIM4_CLKSOURCE
1822 * @arg @ref LL_RCC_LPTIM5_CLKSOURCE
1823 * @retval LPTIM clock frequency (in Hz)
1824 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
1825 */
LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource)1826 uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource)
1827 {
1828 uint32_t frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1829 uint32_t ic_divider;
1830
1831 /* Check parameter */
1832 assert_param(IS_LL_RCC_LPTIM_CLKSOURCE(LPTIMxSource));
1833
1834 switch (LL_RCC_GetLPTIMClockSource(LPTIMxSource))
1835 {
1836 case LL_RCC_LPTIM1_CLKSOURCE_PCLK1:
1837 frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_GetSystemClockFreq()));
1838 break;
1839
1840 case LL_RCC_LPTIM2_CLKSOURCE_PCLK4:
1841 case LL_RCC_LPTIM3_CLKSOURCE_PCLK4:
1842 case LL_RCC_LPTIM4_CLKSOURCE_PCLK4:
1843 case LL_RCC_LPTIM5_CLKSOURCE_PCLK4:
1844 frequency = RCC_GetPCLK4ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_GetSystemClockFreq()));
1845 break;
1846
1847 case LL_RCC_LPTIM1_CLKSOURCE_CLKP:
1848 case LL_RCC_LPTIM2_CLKSOURCE_CLKP:
1849 case LL_RCC_LPTIM3_CLKSOURCE_CLKP:
1850 case LL_RCC_LPTIM4_CLKSOURCE_CLKP:
1851 case LL_RCC_LPTIM5_CLKSOURCE_CLKP:
1852 frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_CLKP_CLKSOURCE);
1853 break;
1854
1855 case LL_RCC_LPTIM1_CLKSOURCE_IC15:
1856 case LL_RCC_LPTIM2_CLKSOURCE_IC15:
1857 case LL_RCC_LPTIM3_CLKSOURCE_IC15:
1858 case LL_RCC_LPTIM4_CLKSOURCE_IC15:
1859 case LL_RCC_LPTIM5_CLKSOURCE_IC15:
1860 if (LL_RCC_IC15_IsEnabled() != 0U)
1861 {
1862 ic_divider = LL_RCC_IC15_GetDivider();
1863 switch (LL_RCC_IC15_GetSource())
1864 {
1865 case LL_RCC_ICCLKSOURCE_PLL1:
1866 frequency = LL_RCC_GetPLL1ClockFreq();
1867 frequency = frequency / ic_divider;
1868 break;
1869 case LL_RCC_ICCLKSOURCE_PLL2:
1870 frequency = LL_RCC_GetPLL2ClockFreq();
1871 frequency = frequency / ic_divider;
1872 break;
1873 case LL_RCC_ICCLKSOURCE_PLL3:
1874 frequency = LL_RCC_GetPLL3ClockFreq();
1875 frequency = frequency / ic_divider;
1876 break;
1877 case LL_RCC_ICCLKSOURCE_PLL4:
1878 frequency = LL_RCC_GetPLL4ClockFreq();
1879 frequency = frequency / ic_divider;
1880 break;
1881 default:
1882 /* Unexpected case */
1883 break;
1884 }
1885 }
1886 break;
1887
1888 case LL_RCC_LPTIM1_CLKSOURCE_LSE:
1889 case LL_RCC_LPTIM2_CLKSOURCE_LSE:
1890 case LL_RCC_LPTIM3_CLKSOURCE_LSE:
1891 case LL_RCC_LPTIM4_CLKSOURCE_LSE:
1892 case LL_RCC_LPTIM5_CLKSOURCE_LSE:
1893 if (LL_RCC_LSE_IsReady() != 0U)
1894 {
1895 frequency = LSE_VALUE;
1896 }
1897 break;
1898
1899 case LL_RCC_LPTIM1_CLKSOURCE_LSI:
1900 case LL_RCC_LPTIM2_CLKSOURCE_LSI:
1901 case LL_RCC_LPTIM3_CLKSOURCE_LSI:
1902 case LL_RCC_LPTIM4_CLKSOURCE_LSI:
1903 case LL_RCC_LPTIM5_CLKSOURCE_LSI:
1904 if (LL_RCC_LSI_IsReady() != 0U)
1905 {
1906 frequency = LSI_VALUE;
1907 }
1908 break;
1909
1910 case LL_RCC_LPTIM1_CLKSOURCE_TIMG:
1911 case LL_RCC_LPTIM2_CLKSOURCE_TIMG:
1912 case LL_RCC_LPTIM3_CLKSOURCE_TIMG:
1913 case LL_RCC_LPTIM4_CLKSOURCE_TIMG:
1914 case LL_RCC_LPTIM5_CLKSOURCE_TIMG:
1915 frequency = LL_RCC_GetSystemClockFreq() / (1UL << LL_RCC_GetTIMPrescaler());
1916 break;
1917
1918 default:
1919 /* Unexpected case */
1920 break;
1921 }
1922
1923 return frequency;
1924 }
1925
1926 /**
1927 * @brief Return LPUART clock frequency
1928 * @param LPUARTxSource This parameter can be one of the following values:
1929 * @arg @ref LL_RCC_LPUART1_CLKSOURCE
1930 * @retval LPUART clock frequency (in Hz)
1931 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
1932 */
LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource)1933 uint32_t LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource)
1934 {
1935 uint32_t frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1936 uint32_t ic_divider;
1937
1938 switch (LL_RCC_GetLPUARTClockSource(LPUARTxSource))
1939 {
1940 case LL_RCC_LPUART1_CLKSOURCE_PCLK4:
1941 frequency = RCC_GetPCLK4ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_GetSystemClockFreq()));
1942 break;
1943
1944 case LL_RCC_LPUART1_CLKSOURCE_CLKP:
1945 frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_CLKP_CLKSOURCE);
1946 break;
1947
1948 case LL_RCC_LPUART1_CLKSOURCE_IC9:
1949 if (LL_RCC_IC9_IsEnabled() != 0U)
1950 {
1951 ic_divider = LL_RCC_IC9_GetDivider();
1952 switch (LL_RCC_IC9_GetSource())
1953 {
1954 case LL_RCC_ICCLKSOURCE_PLL1:
1955 frequency = LL_RCC_GetPLL1ClockFreq();
1956 frequency = frequency / ic_divider;
1957 break;
1958 case LL_RCC_ICCLKSOURCE_PLL2:
1959 frequency = LL_RCC_GetPLL2ClockFreq();
1960 frequency = frequency / ic_divider;
1961 break;
1962 case LL_RCC_ICCLKSOURCE_PLL3:
1963 frequency = LL_RCC_GetPLL3ClockFreq();
1964 frequency = frequency / ic_divider;
1965 break;
1966 case LL_RCC_ICCLKSOURCE_PLL4:
1967 frequency = LL_RCC_GetPLL4ClockFreq();
1968 frequency = frequency / ic_divider;
1969 break;
1970 default:
1971 /* Unexpected case */
1972 break;
1973 }
1974 }
1975 break;
1976
1977 case LL_RCC_LPUART1_CLKSOURCE_IC14:
1978 if (LL_RCC_IC14_IsEnabled() != 0U)
1979 {
1980 ic_divider = LL_RCC_IC14_GetDivider();
1981 switch (LL_RCC_IC14_GetSource())
1982 {
1983 case LL_RCC_ICCLKSOURCE_PLL1:
1984 frequency = LL_RCC_GetPLL1ClockFreq();
1985 frequency = frequency / ic_divider;
1986 break;
1987 case LL_RCC_ICCLKSOURCE_PLL2:
1988 frequency = LL_RCC_GetPLL2ClockFreq();
1989 frequency = frequency / ic_divider;
1990 break;
1991 case LL_RCC_ICCLKSOURCE_PLL3:
1992 frequency = LL_RCC_GetPLL3ClockFreq();
1993 frequency = frequency / ic_divider;
1994 break;
1995 case LL_RCC_ICCLKSOURCE_PLL4:
1996 frequency = LL_RCC_GetPLL4ClockFreq();
1997 frequency = frequency / ic_divider;
1998 break;
1999 default:
2000 /* Unexpected case */
2001 break;
2002 }
2003 }
2004 break;
2005
2006 case LL_RCC_LPUART1_CLKSOURCE_HSI:
2007 if (LL_RCC_HSI_IsReady() != 0U)
2008 {
2009 frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_HSICFGR_HSIDIV_Pos);
2010 }
2011 break;
2012
2013 case LL_RCC_LPUART1_CLKSOURCE_MSI:
2014 if (LL_RCC_MSI_IsReady() != 0U)
2015 {
2016 frequency = MSI_VALUE;
2017 }
2018 break;
2019
2020 case LL_RCC_LPUART1_CLKSOURCE_LSE:
2021 if (LL_RCC_LSE_IsReady() != 0U)
2022 {
2023 frequency = LSE_VALUE;
2024 }
2025 break;
2026
2027 default:
2028 /* Unexpected case */
2029 break;
2030 }
2031
2032 return frequency;
2033 }
2034
2035 /**
2036 * @brief Return LTDC clock frequency
2037 * @param LTDCxSource This parameter can be one of the following values:
2038 * @arg @ref LL_RCC_LTDC_CLKSOURCE
2039 * @retval LTDC clock frequency (in Hz)
2040 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
2041 */
LL_RCC_GetLTDCClockFreq(uint32_t LTDCxSource)2042 uint32_t LL_RCC_GetLTDCClockFreq(uint32_t LTDCxSource)
2043 {
2044 uint32_t frequency = LL_RCC_PERIPH_FREQUENCY_NO;
2045 uint32_t ic_divider;
2046
2047 /* Check parameter */
2048 assert_param(IS_LL_RCC_LTDC_CLKSOURCE(LTDCxSource));
2049
2050 switch (LL_RCC_GetLTDCClockSource(LTDCxSource))
2051 {
2052 case LL_RCC_LTDC_CLKSOURCE_PCLK5:
2053 frequency = RCC_GetPCLK5ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_GetSystemClockFreq()));
2054 break;
2055
2056 case LL_RCC_LTDC_CLKSOURCE_CLKP:
2057 frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_CLKP_CLKSOURCE);
2058 break;
2059
2060 case LL_RCC_LTDC_CLKSOURCE_IC16:
2061 if (LL_RCC_IC16_IsEnabled() != 0U)
2062 {
2063 ic_divider = LL_RCC_IC16_GetDivider();
2064 switch (LL_RCC_IC16_GetSource())
2065 {
2066 case LL_RCC_ICCLKSOURCE_PLL1:
2067 frequency = LL_RCC_GetPLL1ClockFreq();
2068 frequency = frequency / ic_divider;
2069 break;
2070 case LL_RCC_ICCLKSOURCE_PLL2:
2071 frequency = LL_RCC_GetPLL2ClockFreq();
2072 frequency = frequency / ic_divider;
2073 break;
2074 case LL_RCC_ICCLKSOURCE_PLL3:
2075 frequency = LL_RCC_GetPLL3ClockFreq();
2076 frequency = frequency / ic_divider;
2077 break;
2078 case LL_RCC_ICCLKSOURCE_PLL4:
2079 frequency = LL_RCC_GetPLL4ClockFreq();
2080 frequency = frequency / ic_divider;
2081 break;
2082 default:
2083 /* Unexpected case */
2084 break;
2085 }
2086 }
2087 break;
2088
2089 case LL_RCC_LTDC_CLKSOURCE_HSI:
2090 if (LL_RCC_HSI_IsReady() != 0U)
2091 {
2092 frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_HSICFGR_HSIDIV_Pos);
2093 }
2094 break;
2095
2096 default:
2097 /* Unexpected case */
2098 break;
2099 }
2100
2101 return frequency;
2102 }
2103
2104 /**
2105 * @brief Return MDFx clock frequency
2106 * @param MDFxSource This parameter can be one of the following values:
2107 * @arg @ref LL_RCC_MDF1_CLKSOURCE
2108 * @retval MDF clock frequency (in Hz)
2109 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
2110 */
LL_RCC_GetMDFClockFreq(uint32_t MDFxSource)2111 uint32_t LL_RCC_GetMDFClockFreq(uint32_t MDFxSource)
2112 {
2113 uint32_t frequency = LL_RCC_PERIPH_FREQUENCY_NO;
2114 uint32_t ic_divider;
2115
2116 /* Check parameter */
2117 assert_param(IS_LL_RCC_MDF_CLKSOURCE(MDFxSource));
2118
2119 switch (LL_RCC_GetMDFClockSource(MDFxSource))
2120 {
2121 case LL_RCC_MDF1_CLKSOURCE_HCLK:
2122 frequency = RCC_GetHCLKClockFreq(LL_RCC_GetSystemClockFreq());
2123 break;
2124
2125 case LL_RCC_MDF1_CLKSOURCE_CLKP:
2126 frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_CLKP_CLKSOURCE);
2127 break;
2128
2129 case LL_RCC_MDF1_CLKSOURCE_IC7:
2130 if (LL_RCC_IC7_IsEnabled() != 0U)
2131 {
2132 ic_divider = LL_RCC_IC7_GetDivider();
2133 switch (LL_RCC_IC7_GetSource())
2134 {
2135 case LL_RCC_ICCLKSOURCE_PLL1:
2136 frequency = LL_RCC_GetPLL1ClockFreq();
2137 frequency = frequency / ic_divider;
2138 break;
2139 case LL_RCC_ICCLKSOURCE_PLL2:
2140 frequency = LL_RCC_GetPLL2ClockFreq();
2141 frequency = frequency / ic_divider;
2142 break;
2143 case LL_RCC_ICCLKSOURCE_PLL3:
2144 frequency = LL_RCC_GetPLL3ClockFreq();
2145 frequency = frequency / ic_divider;
2146 break;
2147 case LL_RCC_ICCLKSOURCE_PLL4:
2148 frequency = LL_RCC_GetPLL4ClockFreq();
2149 frequency = frequency / ic_divider;
2150 break;
2151 default:
2152 /* Unexpected case */
2153 break;
2154 }
2155 }
2156 break;
2157
2158 case LL_RCC_MDF1_CLKSOURCE_IC8:
2159 if (LL_RCC_IC8_IsEnabled() != 0U)
2160 {
2161 ic_divider = LL_RCC_IC8_GetDivider();
2162 switch (LL_RCC_IC8_GetSource())
2163 {
2164 case LL_RCC_ICCLKSOURCE_PLL1:
2165 frequency = LL_RCC_GetPLL1ClockFreq();
2166 frequency = frequency / ic_divider;
2167 break;
2168 case LL_RCC_ICCLKSOURCE_PLL2:
2169 frequency = LL_RCC_GetPLL2ClockFreq();
2170 frequency = frequency / ic_divider;
2171 break;
2172 case LL_RCC_ICCLKSOURCE_PLL3:
2173 frequency = LL_RCC_GetPLL3ClockFreq();
2174 frequency = frequency / ic_divider;
2175 break;
2176 case LL_RCC_ICCLKSOURCE_PLL4:
2177 frequency = LL_RCC_GetPLL4ClockFreq();
2178 frequency = frequency / ic_divider;
2179 break;
2180 default:
2181 /* Unexpected case */
2182 break;
2183 }
2184 }
2185 break;
2186
2187 case LL_RCC_MDF1_CLKSOURCE_HSI:
2188 if (LL_RCC_HSI_IsReady() != 0U)
2189 {
2190 frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_HSICFGR_HSIDIV_Pos);
2191 }
2192 break;
2193
2194 case LL_RCC_MDF1_CLKSOURCE_MSI:
2195 if (LL_RCC_MSI_IsReady() != 0U)
2196 {
2197 frequency = MSI_VALUE;
2198 }
2199 break;
2200
2201 case LL_RCC_MDF1_CLKSOURCE_I2S_CKIN:
2202 frequency = EXTERNAL_CLOCK_VALUE;
2203 break;
2204
2205 case LL_RCC_MDF1_CLKSOURCE_TIMG:
2206 frequency = LL_RCC_GetSystemClockFreq() / (1UL << LL_RCC_GetTIMPrescaler());
2207 break;
2208
2209 default:
2210 /* Unexpected case */
2211 break;
2212 }
2213
2214 return frequency;
2215 }
2216
2217 /**
2218 * @brief Return OTGPHYx clock frequency
2219 * @param OTGPHYxSource This parameter can be one of the following values:
2220 * @arg @ref LL_RCC_OTGPHY1_CLKSOURCE
2221 * @arg @ref LL_RCC_OTGPHY2_CLKSOURCE
2222 * @retval OTGPHY clock frequency (in Hz)
2223 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
2224 */
LL_RCC_GetOTGPHYClockFreq(uint32_t OTGPHYxSource)2225 uint32_t LL_RCC_GetOTGPHYClockFreq(uint32_t OTGPHYxSource)
2226 {
2227 uint32_t frequency = LL_RCC_PERIPH_FREQUENCY_NO;
2228 uint32_t ic_divider;
2229
2230 /* Check parameter */
2231 assert_param(IS_LL_RCC_OTGPHY_CLKSOURCE(OTGPHYxSource));
2232
2233 switch (LL_RCC_GetOTGPHYClockSource(OTGPHYxSource))
2234 {
2235 case LL_RCC_OTGPHY1_CLKSOURCE_CLKP:
2236 case LL_RCC_OTGPHY2_CLKSOURCE_CLKP:
2237 frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_CLKP_CLKSOURCE);
2238 break;
2239
2240 case LL_RCC_OTGPHY1_CLKSOURCE_IC15:
2241 case LL_RCC_OTGPHY2_CLKSOURCE_IC15:
2242 if (LL_RCC_IC15_IsEnabled() != 0U)
2243 {
2244 ic_divider = LL_RCC_IC15_GetDivider();
2245 switch (LL_RCC_IC15_GetSource())
2246 {
2247 case LL_RCC_ICCLKSOURCE_PLL1:
2248 frequency = LL_RCC_GetPLL1ClockFreq();
2249 frequency = frequency / ic_divider;
2250 break;
2251 case LL_RCC_ICCLKSOURCE_PLL2:
2252 frequency = LL_RCC_GetPLL2ClockFreq();
2253 frequency = frequency / ic_divider;
2254 break;
2255 case LL_RCC_ICCLKSOURCE_PLL3:
2256 frequency = LL_RCC_GetPLL3ClockFreq();
2257 frequency = frequency / ic_divider;
2258 break;
2259 case LL_RCC_ICCLKSOURCE_PLL4:
2260 frequency = LL_RCC_GetPLL4ClockFreq();
2261 frequency = frequency / ic_divider;
2262 break;
2263 default:
2264 /* Unexpected case */
2265 break;
2266 }
2267 }
2268 break;
2269
2270 case LL_RCC_OTGPHY1_CLKSOURCE_HSE_DIV_2:
2271 case LL_RCC_OTGPHY2_CLKSOURCE_HSE_DIV_2:
2272 if (LL_RCC_HSE_IsReady() != 0U)
2273 {
2274 frequency = HSE_VALUE >> 1U;
2275 }
2276 break;
2277
2278 case LL_RCC_OTGPHY1_CLKSOURCE_HSE_DIV_2_OSC:
2279 case LL_RCC_OTGPHY2_CLKSOURCE_HSE_DIV_2_OSC:
2280 if (LL_RCC_HSE_IsReady() != 0U)
2281 {
2282 if (LL_RCC_HSE_IsSelectedHSEDiv2AsDiv2Clock() == 0UL)
2283 {
2284 frequency = HSE_VALUE;
2285 }
2286 else
2287 {
2288 frequency = HSE_VALUE >> 1U;
2289 }
2290 }
2291 break;
2292
2293 default:
2294 /* Unexpected case */
2295 break;
2296 }
2297
2298 return frequency;
2299 }
2300
2301 /**
2302 * @brief Return OTGPHYxCKREF clock frequency
2303 * @param OTGPHYxCKREFSource This parameter can be one of the following values:
2304 * @arg @ref LL_RCC_OTGPHY1CKREF_CLKSOURCE
2305 * @arg @ref LL_RCC_OTGPHY2CKREF_CLKSOURCE
2306 * @retval OTGPHYCKREF clock frequency (in Hz)
2307 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
2308 */
LL_RCC_GetOTGPHYCKREFClockFreq(uint32_t OTGPHYxCKREFSource)2309 uint32_t LL_RCC_GetOTGPHYCKREFClockFreq(uint32_t OTGPHYxCKREFSource)
2310 {
2311 uint32_t frequency = LL_RCC_PERIPH_FREQUENCY_NO;
2312
2313 /* Check parameter */
2314 assert_param(IS_LL_RCC_OTGPHYCKREF_CLKSOURCE(OTGPHYxCKREFSource));
2315
2316 switch (LL_RCC_GetOTGPHYCKREFClockSource(OTGPHYxCKREFSource))
2317 {
2318 case LL_RCC_OTGPHY1CKREF_CLKSOURCE_OTGPHY1:
2319 frequency = LL_RCC_GetOTGPHYClockFreq(LL_RCC_OTGPHY1_CLKSOURCE);
2320 break;
2321
2322 case LL_RCC_OTGPHY2CKREF_CLKSOURCE_OTGPHY2:
2323 frequency = LL_RCC_GetOTGPHYClockFreq(LL_RCC_OTGPHY2_CLKSOURCE);
2324 break;
2325
2326 case LL_RCC_OTGPHY1CKREF_CLKSOURCE_HSE_DIV_2_OSC:
2327 case LL_RCC_OTGPHY2CKREF_CLKSOURCE_HSE_DIV_2_OSC:
2328 if (LL_RCC_HSE_IsReady() != 0U)
2329 {
2330 if (LL_RCC_HSE_IsSelectedHSEDiv2AsDiv2Clock() == 0UL)
2331 {
2332 frequency = HSE_VALUE;
2333 }
2334 else
2335 {
2336 frequency = HSE_VALUE >> 1U;
2337 }
2338 }
2339 break;
2340
2341 default:
2342 /* Unexpected case */
2343 break;
2344 }
2345
2346 return frequency;
2347 }
2348
2349 /**
2350 * @brief Return PSSI clock frequency
2351 * @param PSSIxSource This parameter can be one of the following values:
2352 * @arg @ref LL_RCC_PSSI_CLKSOURCE
2353 * @retval PSSI clock frequency (in Hz)
2354 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
2355 */
LL_RCC_GetPSSIClockFreq(uint32_t PSSIxSource)2356 uint32_t LL_RCC_GetPSSIClockFreq(uint32_t PSSIxSource)
2357 {
2358 uint32_t frequency = LL_RCC_PERIPH_FREQUENCY_NO;
2359 uint32_t ic_divider;
2360
2361 /* Check parameter */
2362 assert_param(IS_LL_RCC_PSSI_CLKSOURCE(PSSIxSource));
2363
2364 switch (LL_RCC_GetPSSIClockSource(PSSIxSource))
2365 {
2366 case LL_RCC_PSSI_CLKSOURCE_HCLK:
2367 frequency = RCC_GetHCLKClockFreq(LL_RCC_GetSystemClockFreq());
2368 break;
2369
2370 case LL_RCC_PSSI_CLKSOURCE_CLKP:
2371 frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_CLKP_CLKSOURCE);
2372 break;
2373
2374 case LL_RCC_PSSI_CLKSOURCE_IC20:
2375 if (LL_RCC_IC20_IsEnabled() != 0U)
2376 {
2377 ic_divider = LL_RCC_IC20_GetDivider();
2378 switch (LL_RCC_IC20_GetSource())
2379 {
2380 case LL_RCC_ICCLKSOURCE_PLL1:
2381 frequency = LL_RCC_GetPLL1ClockFreq();
2382 frequency = frequency / ic_divider;
2383 break;
2384 case LL_RCC_ICCLKSOURCE_PLL2:
2385 frequency = LL_RCC_GetPLL2ClockFreq();
2386 frequency = frequency / ic_divider;
2387 break;
2388 case LL_RCC_ICCLKSOURCE_PLL3:
2389 frequency = LL_RCC_GetPLL3ClockFreq();
2390 frequency = frequency / ic_divider;
2391 break;
2392 case LL_RCC_ICCLKSOURCE_PLL4:
2393 frequency = LL_RCC_GetPLL4ClockFreq();
2394 frequency = frequency / ic_divider;
2395 break;
2396 default:
2397 /* Unexpected case */
2398 break;
2399 }
2400 }
2401 break;
2402
2403 case LL_RCC_PSSI_CLKSOURCE_HSI:
2404 if (LL_RCC_HSI_IsReady() != 0U)
2405 {
2406 frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_HSICFGR_HSIDIV_Pos);
2407 }
2408 break;
2409
2410 default:
2411 /* Unexpected case */
2412 break;
2413 }
2414
2415 return frequency;
2416 }
2417
2418 /**
2419 * @brief Return SAIx clock frequency
2420 * @param SAIxSource This parameter can be one of the following values:
2421 * @arg @ref LL_RCC_SAI1_CLKSOURCE
2422 * @arg @ref LL_RCC_SAI2_CLKSOURCE
2423 * @retval SAI clock frequency (in Hz)
2424 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
2425 */
LL_RCC_GetSAIClockFreq(uint32_t SAIxSource)2426 uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource)
2427 {
2428 uint32_t frequency = LL_RCC_PERIPH_FREQUENCY_NO;
2429 uint32_t ic_divider;
2430
2431 /* Check parameter */
2432 assert_param(IS_LL_RCC_SAI_CLKSOURCE(SAIxSource));
2433
2434 switch (LL_RCC_GetSAIClockSource(SAIxSource))
2435 {
2436 case LL_RCC_SAI1_CLKSOURCE_PCLK2:
2437 case LL_RCC_SAI2_CLKSOURCE_PCLK2:
2438 frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_GetSystemClockFreq()));
2439 break;
2440
2441 case LL_RCC_SAI1_CLKSOURCE_CLKP:
2442 case LL_RCC_SAI2_CLKSOURCE_CLKP:
2443 frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_CLKP_CLKSOURCE);
2444 break;
2445
2446 case LL_RCC_SAI1_CLKSOURCE_IC7:
2447 case LL_RCC_SAI2_CLKSOURCE_IC7:
2448 if (LL_RCC_IC7_IsEnabled() != 0U)
2449 {
2450 ic_divider = LL_RCC_IC7_GetDivider();
2451 switch (LL_RCC_IC7_GetSource())
2452 {
2453 case LL_RCC_ICCLKSOURCE_PLL1:
2454 frequency = LL_RCC_GetPLL1ClockFreq();
2455 frequency = frequency / ic_divider;
2456 break;
2457 case LL_RCC_ICCLKSOURCE_PLL2:
2458 frequency = LL_RCC_GetPLL2ClockFreq();
2459 frequency = frequency / ic_divider;
2460 break;
2461 case LL_RCC_ICCLKSOURCE_PLL3:
2462 frequency = LL_RCC_GetPLL3ClockFreq();
2463 frequency = frequency / ic_divider;
2464 break;
2465 case LL_RCC_ICCLKSOURCE_PLL4:
2466 frequency = LL_RCC_GetPLL4ClockFreq();
2467 frequency = frequency / ic_divider;
2468 break;
2469 default:
2470 /* Unexpected case */
2471 break;
2472 }
2473 }
2474 break;
2475
2476 case LL_RCC_SAI1_CLKSOURCE_IC8:
2477 case LL_RCC_SAI2_CLKSOURCE_IC8:
2478 if (LL_RCC_IC8_IsEnabled() != 0U)
2479 {
2480 ic_divider = LL_RCC_IC8_GetDivider();
2481 switch (LL_RCC_IC8_GetSource())
2482 {
2483 case LL_RCC_ICCLKSOURCE_PLL1:
2484 frequency = LL_RCC_GetPLL1ClockFreq();
2485 frequency = frequency / ic_divider;
2486 break;
2487 case LL_RCC_ICCLKSOURCE_PLL2:
2488 frequency = LL_RCC_GetPLL2ClockFreq();
2489 frequency = frequency / ic_divider;
2490 break;
2491 case LL_RCC_ICCLKSOURCE_PLL3:
2492 frequency = LL_RCC_GetPLL3ClockFreq();
2493 frequency = frequency / ic_divider;
2494 break;
2495 case LL_RCC_ICCLKSOURCE_PLL4:
2496 frequency = LL_RCC_GetPLL4ClockFreq();
2497 frequency = frequency / ic_divider;
2498 break;
2499 default:
2500 /* Unexpected case */
2501 break;
2502 }
2503 }
2504 break;
2505
2506 case LL_RCC_SAI1_CLKSOURCE_HSI:
2507 case LL_RCC_SAI2_CLKSOURCE_HSI:
2508 if (LL_RCC_HSI_IsReady() != 0U)
2509 {
2510 frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_HSICFGR_HSIDIV_Pos);
2511 }
2512 break;
2513
2514 case LL_RCC_SAI1_CLKSOURCE_MSI:
2515 case LL_RCC_SAI2_CLKSOURCE_MSI:
2516 if (LL_RCC_MSI_IsReady() != 0U)
2517 {
2518 frequency = MSI_VALUE;
2519 }
2520 break;
2521
2522 case LL_RCC_SAI1_CLKSOURCE_I2S_CKIN:
2523 case LL_RCC_SAI2_CLKSOURCE_I2S_CKIN:
2524 frequency = EXTERNAL_CLOCK_VALUE;
2525 break;
2526
2527 case LL_RCC_SAI1_CLKSOURCE_SPDIFRX1:
2528 case LL_RCC_SAI2_CLKSOURCE_SPDIFRX1:
2529 frequency = LL_RCC_GetSPDIFRXClockFreq(LL_RCC_SPDIFRX1_CLKSOURCE);
2530 break;
2531
2532 default:
2533 /* Unexpected case */
2534 break;
2535 }
2536
2537 return frequency;
2538 }
2539
2540 /**
2541 * @brief Return SDMMC clock frequency
2542 * @param SDMMCxSource This parameter can be one of the following values:
2543 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE
2544 * @arg @ref LL_RCC_SDMMC2_CLKSOURCE
2545 * @retval SDMMC clock frequency (in Hz)
2546 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
2547 */
LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource)2548 uint32_t LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource)
2549 {
2550 uint32_t frequency = LL_RCC_PERIPH_FREQUENCY_NO;
2551 uint32_t ic_divider;
2552
2553 /* Check parameter */
2554 assert_param(IS_LL_RCC_SDMMC_CLKSOURCE(SDMMCxSource));
2555
2556 switch (LL_RCC_GetSDMMCClockSource(SDMMCxSource))
2557 {
2558 case LL_RCC_SDMMC1_CLKSOURCE_HCLK:
2559 case LL_RCC_SDMMC2_CLKSOURCE_HCLK:
2560 frequency = RCC_GetHCLKClockFreq(LL_RCC_GetSystemClockFreq());
2561 break;
2562
2563 case LL_RCC_SDMMC1_CLKSOURCE_CLKP:
2564 case LL_RCC_SDMMC2_CLKSOURCE_CLKP:
2565 frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_CLKP_CLKSOURCE);
2566 break;
2567
2568 case LL_RCC_SDMMC1_CLKSOURCE_IC4:
2569 case LL_RCC_SDMMC2_CLKSOURCE_IC4:
2570 if (LL_RCC_IC4_IsEnabled() != 0U)
2571 {
2572 ic_divider = LL_RCC_IC4_GetDivider();
2573 switch (LL_RCC_IC4_GetSource())
2574 {
2575 case LL_RCC_ICCLKSOURCE_PLL1:
2576 frequency = LL_RCC_GetPLL1ClockFreq();
2577 frequency = frequency / ic_divider;
2578 break;
2579 case LL_RCC_ICCLKSOURCE_PLL2:
2580 frequency = LL_RCC_GetPLL2ClockFreq();
2581 frequency = frequency / ic_divider;
2582 break;
2583 case LL_RCC_ICCLKSOURCE_PLL3:
2584 frequency = LL_RCC_GetPLL3ClockFreq();
2585 frequency = frequency / ic_divider;
2586 break;
2587 case LL_RCC_ICCLKSOURCE_PLL4:
2588 frequency = LL_RCC_GetPLL4ClockFreq();
2589 frequency = frequency / ic_divider;
2590 break;
2591 default:
2592 /* Unexpected case */
2593 break;
2594 }
2595 }
2596 break;
2597
2598 case LL_RCC_SDMMC1_CLKSOURCE_IC5:
2599 case LL_RCC_SDMMC2_CLKSOURCE_IC5:
2600 if (LL_RCC_IC5_IsEnabled() != 0U)
2601 {
2602 ic_divider = LL_RCC_IC5_GetDivider();
2603 switch (LL_RCC_IC5_GetSource())
2604 {
2605 case LL_RCC_ICCLKSOURCE_PLL1:
2606 frequency = LL_RCC_GetPLL1ClockFreq();
2607 frequency = frequency / ic_divider;
2608 break;
2609 case LL_RCC_ICCLKSOURCE_PLL2:
2610 frequency = LL_RCC_GetPLL2ClockFreq();
2611 frequency = frequency / ic_divider;
2612 break;
2613 case LL_RCC_ICCLKSOURCE_PLL3:
2614 frequency = LL_RCC_GetPLL3ClockFreq();
2615 frequency = frequency / ic_divider;
2616 break;
2617 case LL_RCC_ICCLKSOURCE_PLL4:
2618 frequency = LL_RCC_GetPLL4ClockFreq();
2619 frequency = frequency / ic_divider;
2620 break;
2621 default:
2622 /* Unexpected case */
2623 break;
2624 }
2625 }
2626 break;
2627
2628 default:
2629 /* Unexpected case */
2630 break;
2631 }
2632
2633 return frequency;
2634 }
2635
2636 /**
2637 * @brief Return SPDIFRX clock frequency
2638 * @param SPDIFRXxSource This parameter can be one of the following values:
2639 * @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE
2640 * @retval SPDIF clock frequency (in Hz)
2641 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
2642 */
LL_RCC_GetSPDIFRXClockFreq(uint32_t SPDIFRXxSource)2643 uint32_t LL_RCC_GetSPDIFRXClockFreq(uint32_t SPDIFRXxSource)
2644 {
2645 uint32_t frequency = LL_RCC_PERIPH_FREQUENCY_NO;
2646 uint32_t ic_divider;
2647
2648 /* Check parameter */
2649 assert_param(IS_LL_RCC_SPDIFRX_CLKSOURCE(SPDIFRXxSource));
2650
2651 switch (LL_RCC_GetSPDIFRXClockSource(SPDIFRXxSource))
2652 {
2653 case LL_RCC_SPDIFRX1_CLKSOURCE_PCLK1:
2654 frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_GetSystemClockFreq()));
2655 break;
2656
2657 case LL_RCC_SPDIFRX1_CLKSOURCE_CLKP:
2658 frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_CLKP_CLKSOURCE);
2659 break;
2660
2661 case LL_RCC_SPDIFRX1_CLKSOURCE_IC7:
2662 if (LL_RCC_IC7_IsEnabled() != 0U)
2663 {
2664 ic_divider = LL_RCC_IC7_GetDivider();
2665 switch (LL_RCC_IC7_GetSource())
2666 {
2667 case LL_RCC_ICCLKSOURCE_PLL1:
2668 frequency = LL_RCC_GetPLL1ClockFreq();
2669 frequency = frequency / ic_divider;
2670 break;
2671 case LL_RCC_ICCLKSOURCE_PLL2:
2672 frequency = LL_RCC_GetPLL2ClockFreq();
2673 frequency = frequency / ic_divider;
2674 break;
2675 case LL_RCC_ICCLKSOURCE_PLL3:
2676 frequency = LL_RCC_GetPLL3ClockFreq();
2677 frequency = frequency / ic_divider;
2678 break;
2679 case LL_RCC_ICCLKSOURCE_PLL4:
2680 frequency = LL_RCC_GetPLL4ClockFreq();
2681 frequency = frequency / ic_divider;
2682 break;
2683 default:
2684 /* Unexpected case */
2685 break;
2686 }
2687 }
2688 break;
2689
2690 case LL_RCC_SPDIFRX1_CLKSOURCE_IC8:
2691 if (LL_RCC_IC8_IsEnabled() != 0U)
2692 {
2693 ic_divider = LL_RCC_IC8_GetDivider();
2694 switch (LL_RCC_IC8_GetSource())
2695 {
2696 case LL_RCC_ICCLKSOURCE_PLL1:
2697 frequency = LL_RCC_GetPLL1ClockFreq();
2698 frequency = frequency / ic_divider;
2699 break;
2700 case LL_RCC_ICCLKSOURCE_PLL2:
2701 frequency = LL_RCC_GetPLL2ClockFreq();
2702 frequency = frequency / ic_divider;
2703 break;
2704 case LL_RCC_ICCLKSOURCE_PLL3:
2705 frequency = LL_RCC_GetPLL3ClockFreq();
2706 frequency = frequency / ic_divider;
2707 break;
2708 case LL_RCC_ICCLKSOURCE_PLL4:
2709 frequency = LL_RCC_GetPLL4ClockFreq();
2710 frequency = frequency / ic_divider;
2711 break;
2712 default:
2713 /* Unexpected case */
2714 break;
2715 }
2716 }
2717 break;
2718
2719 case LL_RCC_SPDIFRX1_CLKSOURCE_HSI:
2720 if (LL_RCC_HSI_IsReady() != 0U)
2721 {
2722 frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_HSICFGR_HSIDIV_Pos);
2723 }
2724 break;
2725
2726 case LL_RCC_SPDIFRX1_CLKSOURCE_MSI:
2727 if (LL_RCC_MSI_IsReady() != 0U)
2728 {
2729 frequency = MSI_VALUE;
2730 }
2731 break;
2732
2733 case LL_RCC_SPDIFRX1_CLKSOURCE_I2S_CKIN:
2734 frequency = EXTERNAL_CLOCK_VALUE;
2735 break;
2736
2737 default:
2738 /* Unexpected case */
2739 break;
2740 }
2741
2742 return frequency;
2743 }
2744
2745 /**
2746 * @brief Return SPIx clock frequency
2747 * @param SPIxSource This parameter can be one of the following values:
2748 * @arg @ref LL_RCC_SPI1_CLKSOURCE
2749 * @arg @ref LL_RCC_SPI2_CLKSOURCE
2750 * @arg @ref LL_RCC_SPI3_CLKSOURCE
2751 * @arg @ref LL_RCC_SPI4_CLKSOURCE
2752 * @arg @ref LL_RCC_SPI5_CLKSOURCE
2753 * @arg @ref LL_RCC_SPI6_CLKSOURCE
2754 * @retval SPI clock frequency (in Hz)
2755 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
2756 */
LL_RCC_GetSPIClockFreq(uint32_t SPIxSource)2757 uint32_t LL_RCC_GetSPIClockFreq(uint32_t SPIxSource)
2758 {
2759 uint32_t frequency = LL_RCC_PERIPH_FREQUENCY_NO;
2760 uint32_t ic_divider;
2761
2762 /* Check parameter */
2763 assert_param(IS_LL_RCC_SPI_CLKSOURCE(SPIxSource));
2764
2765 switch (LL_RCC_GetSPIClockSource(SPIxSource))
2766 {
2767 case LL_RCC_SPI2_CLKSOURCE_PCLK1:
2768 case LL_RCC_SPI3_CLKSOURCE_PCLK1:
2769 frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_GetSystemClockFreq()));
2770 break;
2771
2772 case LL_RCC_SPI1_CLKSOURCE_PCLK2:
2773 case LL_RCC_SPI4_CLKSOURCE_PCLK2:
2774 case LL_RCC_SPI5_CLKSOURCE_PCLK2:
2775 frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_GetSystemClockFreq()));
2776 break;
2777
2778 case LL_RCC_SPI6_CLKSOURCE_PCLK4:
2779 frequency = RCC_GetPCLK4ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_GetSystemClockFreq()));
2780 break;
2781
2782 case LL_RCC_SPI1_CLKSOURCE_CLKP:
2783 case LL_RCC_SPI2_CLKSOURCE_CLKP:
2784 case LL_RCC_SPI3_CLKSOURCE_CLKP:
2785 case LL_RCC_SPI4_CLKSOURCE_CLKP:
2786 case LL_RCC_SPI5_CLKSOURCE_CLKP:
2787 case LL_RCC_SPI6_CLKSOURCE_CLKP:
2788 frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_CLKP_CLKSOURCE);
2789 break;
2790
2791 case LL_RCC_SPI1_CLKSOURCE_IC8:
2792 case LL_RCC_SPI2_CLKSOURCE_IC8:
2793 case LL_RCC_SPI3_CLKSOURCE_IC8:
2794 case LL_RCC_SPI6_CLKSOURCE_IC8:
2795 if (LL_RCC_IC8_IsEnabled() != 0U)
2796 {
2797 ic_divider = LL_RCC_IC8_GetDivider();
2798 switch (LL_RCC_IC8_GetSource())
2799 {
2800 case LL_RCC_ICCLKSOURCE_PLL1:
2801 frequency = LL_RCC_GetPLL1ClockFreq();
2802 frequency = frequency / ic_divider;
2803 break;
2804 case LL_RCC_ICCLKSOURCE_PLL2:
2805 frequency = LL_RCC_GetPLL2ClockFreq();
2806 frequency = frequency / ic_divider;
2807 break;
2808 case LL_RCC_ICCLKSOURCE_PLL3:
2809 frequency = LL_RCC_GetPLL3ClockFreq();
2810 frequency = frequency / ic_divider;
2811 break;
2812 case LL_RCC_ICCLKSOURCE_PLL4:
2813 frequency = LL_RCC_GetPLL4ClockFreq();
2814 frequency = frequency / ic_divider;
2815 break;
2816 default:
2817 /* Unexpected case */
2818 break;
2819 }
2820 }
2821 break;
2822
2823 case LL_RCC_SPI1_CLKSOURCE_IC9:
2824 case LL_RCC_SPI2_CLKSOURCE_IC9:
2825 case LL_RCC_SPI3_CLKSOURCE_IC9:
2826 case LL_RCC_SPI4_CLKSOURCE_IC9:
2827 case LL_RCC_SPI5_CLKSOURCE_IC9:
2828 case LL_RCC_SPI6_CLKSOURCE_IC9:
2829 if (LL_RCC_IC9_IsEnabled() != 0U)
2830 {
2831 ic_divider = LL_RCC_IC9_GetDivider();
2832 switch (LL_RCC_IC9_GetSource())
2833 {
2834 case LL_RCC_ICCLKSOURCE_PLL1:
2835 frequency = LL_RCC_GetPLL1ClockFreq();
2836 frequency = frequency / ic_divider;
2837 break;
2838 case LL_RCC_ICCLKSOURCE_PLL2:
2839 frequency = LL_RCC_GetPLL2ClockFreq();
2840 frequency = frequency / ic_divider;
2841 break;
2842 case LL_RCC_ICCLKSOURCE_PLL3:
2843 frequency = LL_RCC_GetPLL3ClockFreq();
2844 frequency = frequency / ic_divider;
2845 break;
2846 case LL_RCC_ICCLKSOURCE_PLL4:
2847 frequency = LL_RCC_GetPLL4ClockFreq();
2848 frequency = frequency / ic_divider;
2849 break;
2850 default:
2851 /* Unexpected case */
2852 break;
2853 }
2854 }
2855 break;
2856
2857 case LL_RCC_SPI4_CLKSOURCE_IC14:
2858 case LL_RCC_SPI5_CLKSOURCE_IC14:
2859 if (LL_RCC_IC14_IsEnabled() != 0U)
2860 {
2861 ic_divider = LL_RCC_IC14_GetDivider();
2862 switch (LL_RCC_IC14_GetSource())
2863 {
2864 case LL_RCC_ICCLKSOURCE_PLL1:
2865 frequency = LL_RCC_GetPLL1ClockFreq();
2866 frequency = frequency / ic_divider;
2867 break;
2868 case LL_RCC_ICCLKSOURCE_PLL2:
2869 frequency = LL_RCC_GetPLL2ClockFreq();
2870 frequency = frequency / ic_divider;
2871 break;
2872 case LL_RCC_ICCLKSOURCE_PLL3:
2873 frequency = LL_RCC_GetPLL3ClockFreq();
2874 frequency = frequency / ic_divider;
2875 break;
2876 case LL_RCC_ICCLKSOURCE_PLL4:
2877 frequency = LL_RCC_GetPLL4ClockFreq();
2878 frequency = frequency / ic_divider;
2879 break;
2880 default:
2881 /* Unexpected case */
2882 break;
2883 }
2884 }
2885 break;
2886
2887 case LL_RCC_SPI1_CLKSOURCE_HSI:
2888 case LL_RCC_SPI2_CLKSOURCE_HSI:
2889 case LL_RCC_SPI3_CLKSOURCE_HSI:
2890 case LL_RCC_SPI4_CLKSOURCE_HSI:
2891 case LL_RCC_SPI5_CLKSOURCE_HSI:
2892 case LL_RCC_SPI6_CLKSOURCE_HSI:
2893 if (LL_RCC_HSI_IsReady() != 0U)
2894 {
2895 frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_HSICFGR_HSIDIV_Pos);
2896 }
2897 break;
2898
2899 case LL_RCC_SPI1_CLKSOURCE_MSI:
2900 case LL_RCC_SPI2_CLKSOURCE_MSI:
2901 case LL_RCC_SPI3_CLKSOURCE_MSI:
2902 case LL_RCC_SPI4_CLKSOURCE_MSI:
2903 case LL_RCC_SPI5_CLKSOURCE_MSI:
2904 case LL_RCC_SPI6_CLKSOURCE_MSI:
2905 if (LL_RCC_MSI_IsReady() != 0U)
2906 {
2907 frequency = MSI_VALUE;
2908 }
2909 break;
2910
2911 case LL_RCC_SPI1_CLKSOURCE_I2S_CKIN:
2912 case LL_RCC_SPI2_CLKSOURCE_I2S_CKIN:
2913 case LL_RCC_SPI3_CLKSOURCE_I2S_CKIN:
2914 case LL_RCC_SPI6_CLKSOURCE_I2S_CKIN:
2915 frequency = EXTERNAL_CLOCK_VALUE;
2916 break;
2917
2918 case LL_RCC_SPI4_CLKSOURCE_HSE:
2919 case LL_RCC_SPI5_CLKSOURCE_HSE:
2920 if (LL_RCC_HSE_IsReady() != 0U)
2921 {
2922 frequency = HSE_VALUE;
2923 }
2924 break;
2925
2926 default:
2927 /* Unexpected case */
2928 break;
2929 }
2930
2931 return frequency;
2932 }
2933
2934 /**
2935 * @brief Return UARTx clock frequency
2936 * @param UARTxSource This parameter can be one of the following values:
2937 * @arg @ref LL_RCC_UART4_CLKSOURCE
2938 * @arg @ref LL_RCC_UART5_CLKSOURCE
2939 * @arg @ref LL_RCC_UART7_CLKSOURCE
2940 * @arg @ref LL_RCC_UART8_CLKSOURCE
2941 * @arg @ref LL_RCC_UART9_CLKSOURCE
2942 * @retval USART clock frequency (in Hz)
2943 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
2944 */
LL_RCC_GetUARTClockFreq(uint32_t UARTxSource)2945 uint32_t LL_RCC_GetUARTClockFreq(uint32_t UARTxSource)
2946 {
2947 uint32_t frequency = LL_RCC_PERIPH_FREQUENCY_NO;
2948 uint32_t ic_divider;
2949
2950 /* Check parameter */
2951 assert_param(IS_LL_RCC_UART_CLKSOURCE(UARTxSource));
2952
2953 switch (LL_RCC_GetUARTClockSource(UARTxSource))
2954 {
2955 case LL_RCC_UART4_CLKSOURCE_PCLK1:
2956 case LL_RCC_UART5_CLKSOURCE_PCLK1:
2957 case LL_RCC_UART7_CLKSOURCE_PCLK1:
2958 case LL_RCC_UART8_CLKSOURCE_PCLK1:
2959 frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_GetSystemClockFreq()));
2960 break;
2961
2962 case LL_RCC_UART9_CLKSOURCE_PCLK2:
2963 frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_GetSystemClockFreq()));
2964 break;
2965
2966 case LL_RCC_UART4_CLKSOURCE_CLKP:
2967 case LL_RCC_UART5_CLKSOURCE_CLKP:
2968 case LL_RCC_UART7_CLKSOURCE_CLKP:
2969 case LL_RCC_UART8_CLKSOURCE_CLKP:
2970 case LL_RCC_UART9_CLKSOURCE_CLKP:
2971 frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_CLKP_CLKSOURCE);
2972 break;
2973
2974 case LL_RCC_UART4_CLKSOURCE_IC9:
2975 case LL_RCC_UART5_CLKSOURCE_IC9:
2976 case LL_RCC_UART7_CLKSOURCE_IC9:
2977 case LL_RCC_UART8_CLKSOURCE_IC9:
2978 case LL_RCC_UART9_CLKSOURCE_IC9:
2979 if (LL_RCC_IC9_IsEnabled() != 0U)
2980 {
2981 ic_divider = LL_RCC_IC9_GetDivider();
2982 switch (LL_RCC_IC9_GetSource())
2983 {
2984 case LL_RCC_ICCLKSOURCE_PLL1:
2985 frequency = LL_RCC_GetPLL1ClockFreq();
2986 frequency = frequency / ic_divider;
2987 break;
2988 case LL_RCC_ICCLKSOURCE_PLL2:
2989 frequency = LL_RCC_GetPLL2ClockFreq();
2990 frequency = frequency / ic_divider;
2991 break;
2992 case LL_RCC_ICCLKSOURCE_PLL3:
2993 frequency = LL_RCC_GetPLL3ClockFreq();
2994 frequency = frequency / ic_divider;
2995 break;
2996 case LL_RCC_ICCLKSOURCE_PLL4:
2997 frequency = LL_RCC_GetPLL4ClockFreq();
2998 frequency = frequency / ic_divider;
2999 break;
3000 default:
3001 /* Unexpected case */
3002 break;
3003 }
3004 }
3005 break;
3006
3007 case LL_RCC_UART4_CLKSOURCE_IC14:
3008 case LL_RCC_UART5_CLKSOURCE_IC14:
3009 case LL_RCC_UART7_CLKSOURCE_IC14:
3010 case LL_RCC_UART8_CLKSOURCE_IC14:
3011 case LL_RCC_UART9_CLKSOURCE_IC14:
3012 if (LL_RCC_IC14_IsEnabled() != 0U)
3013 {
3014 ic_divider = LL_RCC_IC14_GetDivider();
3015 switch (LL_RCC_IC14_GetSource())
3016 {
3017 case LL_RCC_ICCLKSOURCE_PLL1:
3018 frequency = LL_RCC_GetPLL1ClockFreq();
3019 frequency = frequency / ic_divider;
3020 break;
3021 case LL_RCC_ICCLKSOURCE_PLL2:
3022 frequency = LL_RCC_GetPLL2ClockFreq();
3023 frequency = frequency / ic_divider;
3024 break;
3025 case LL_RCC_ICCLKSOURCE_PLL3:
3026 frequency = LL_RCC_GetPLL3ClockFreq();
3027 frequency = frequency / ic_divider;
3028 break;
3029 case LL_RCC_ICCLKSOURCE_PLL4:
3030 frequency = LL_RCC_GetPLL4ClockFreq();
3031 frequency = frequency / ic_divider;
3032 break;
3033 default:
3034 /* Unexpected case */
3035 break;
3036 }
3037 }
3038 break;
3039
3040 case LL_RCC_UART4_CLKSOURCE_HSI:
3041 case LL_RCC_UART5_CLKSOURCE_HSI:
3042 case LL_RCC_UART7_CLKSOURCE_HSI:
3043 case LL_RCC_UART8_CLKSOURCE_HSI:
3044 case LL_RCC_UART9_CLKSOURCE_HSI:
3045 if (LL_RCC_HSI_IsReady() != 0U)
3046 {
3047 frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_HSICFGR_HSIDIV_Pos);
3048 }
3049 break;
3050
3051 case LL_RCC_UART4_CLKSOURCE_MSI:
3052 case LL_RCC_UART5_CLKSOURCE_MSI:
3053 case LL_RCC_UART7_CLKSOURCE_MSI:
3054 case LL_RCC_UART8_CLKSOURCE_MSI:
3055 case LL_RCC_UART9_CLKSOURCE_MSI:
3056 if (LL_RCC_MSI_IsReady() != 0U)
3057 {
3058 frequency = MSI_VALUE;
3059 }
3060 break;
3061
3062 case LL_RCC_UART4_CLKSOURCE_LSE:
3063 case LL_RCC_UART5_CLKSOURCE_LSE:
3064 case LL_RCC_UART7_CLKSOURCE_LSE:
3065 case LL_RCC_UART8_CLKSOURCE_LSE:
3066 case LL_RCC_UART9_CLKSOURCE_LSE:
3067 if (LL_RCC_LSE_IsReady() != 0U)
3068 {
3069 frequency = LSE_VALUE;
3070 }
3071 break;
3072
3073 default:
3074 /* Unexpected case */
3075 break;
3076 }
3077
3078 return frequency;
3079 }
3080
3081 /**
3082 * @brief Return USARTx clock frequency
3083 * @param USARTxSource This parameter can be one of the following values:
3084 * @arg @ref LL_RCC_USART1_CLKSOURCE
3085 * @arg @ref LL_RCC_USART2_CLKSOURCE
3086 * @arg @ref LL_RCC_USART3_CLKSOURCE
3087 * @arg @ref LL_RCC_USART6_CLKSOURCE
3088 * @arg @ref LL_RCC_USART10_CLKSOURCE
3089 * @retval USART clock frequency (in Hz)
3090 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
3091 */
LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource)3092 uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource)
3093 {
3094 uint32_t frequency = LL_RCC_PERIPH_FREQUENCY_NO;
3095 uint32_t ic_divider;
3096
3097 /* Check parameter */
3098 assert_param(IS_LL_RCC_USART_CLKSOURCE(USARTxSource));
3099
3100 switch (LL_RCC_GetUSARTClockSource(USARTxSource))
3101 {
3102 case LL_RCC_USART1_CLKSOURCE_PCLK2:
3103 case LL_RCC_USART6_CLKSOURCE_PCLK2:
3104 case LL_RCC_USART10_CLKSOURCE_PCLK2:
3105 frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_GetSystemClockFreq()));
3106 break;
3107
3108 case LL_RCC_USART2_CLKSOURCE_PCLK1:
3109 case LL_RCC_USART3_CLKSOURCE_PCLK1:
3110 frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(LL_RCC_GetSystemClockFreq()));
3111 break;
3112
3113 case LL_RCC_USART1_CLKSOURCE_CLKP:
3114 case LL_RCC_USART2_CLKSOURCE_CLKP:
3115 case LL_RCC_USART3_CLKSOURCE_CLKP:
3116 case LL_RCC_USART6_CLKSOURCE_CLKP:
3117 case LL_RCC_USART10_CLKSOURCE_CLKP:
3118 frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_CLKP_CLKSOURCE);
3119 break;
3120
3121 case LL_RCC_USART1_CLKSOURCE_IC9:
3122 case LL_RCC_USART2_CLKSOURCE_IC9:
3123 case LL_RCC_USART3_CLKSOURCE_IC9:
3124 case LL_RCC_USART6_CLKSOURCE_IC9:
3125 case LL_RCC_USART10_CLKSOURCE_IC9:
3126 if (LL_RCC_IC9_IsEnabled() != 0U)
3127 {
3128 ic_divider = LL_RCC_IC9_GetDivider();
3129 switch (LL_RCC_IC9_GetSource())
3130 {
3131 case LL_RCC_ICCLKSOURCE_PLL1:
3132 frequency = LL_RCC_GetPLL1ClockFreq();
3133 frequency = frequency / ic_divider;
3134 break;
3135 case LL_RCC_ICCLKSOURCE_PLL2:
3136 frequency = LL_RCC_GetPLL2ClockFreq();
3137 frequency = frequency / ic_divider;
3138 break;
3139 case LL_RCC_ICCLKSOURCE_PLL3:
3140 frequency = LL_RCC_GetPLL3ClockFreq();
3141 frequency = frequency / ic_divider;
3142 break;
3143 case LL_RCC_ICCLKSOURCE_PLL4:
3144 frequency = LL_RCC_GetPLL4ClockFreq();
3145 frequency = frequency / ic_divider;
3146 break;
3147 default:
3148 /* Unexpected case */
3149 break;
3150 }
3151 }
3152 break;
3153
3154 case LL_RCC_USART1_CLKSOURCE_IC14:
3155 case LL_RCC_USART2_CLKSOURCE_IC14:
3156 case LL_RCC_USART3_CLKSOURCE_IC14:
3157 case LL_RCC_USART6_CLKSOURCE_IC14:
3158 case LL_RCC_USART10_CLKSOURCE_IC14:
3159 if (LL_RCC_IC14_IsEnabled() != 0U)
3160 {
3161 ic_divider = LL_RCC_IC14_GetDivider();
3162 switch (LL_RCC_IC14_GetSource())
3163 {
3164 case LL_RCC_ICCLKSOURCE_PLL1:
3165 frequency = LL_RCC_GetPLL1ClockFreq();
3166 frequency = frequency / ic_divider;
3167 break;
3168 case LL_RCC_ICCLKSOURCE_PLL2:
3169 frequency = LL_RCC_GetPLL2ClockFreq();
3170 frequency = frequency / ic_divider;
3171 break;
3172 case LL_RCC_ICCLKSOURCE_PLL3:
3173 frequency = LL_RCC_GetPLL3ClockFreq();
3174 frequency = frequency / ic_divider;
3175 break;
3176 case LL_RCC_ICCLKSOURCE_PLL4:
3177 frequency = LL_RCC_GetPLL4ClockFreq();
3178 frequency = frequency / ic_divider;
3179 break;
3180 default:
3181 /* Unexpected case */
3182 break;
3183 }
3184 }
3185 break;
3186
3187 case LL_RCC_USART1_CLKSOURCE_HSI:
3188 case LL_RCC_USART2_CLKSOURCE_HSI:
3189 case LL_RCC_USART3_CLKSOURCE_HSI:
3190 case LL_RCC_USART6_CLKSOURCE_HSI:
3191 case LL_RCC_USART10_CLKSOURCE_HSI:
3192 if (LL_RCC_HSI_IsReady() != 0U)
3193 {
3194 frequency = HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_HSICFGR_HSIDIV_Pos);
3195 }
3196 break;
3197
3198 case LL_RCC_USART1_CLKSOURCE_MSI:
3199 case LL_RCC_USART2_CLKSOURCE_MSI:
3200 case LL_RCC_USART3_CLKSOURCE_MSI:
3201 case LL_RCC_USART6_CLKSOURCE_MSI:
3202 case LL_RCC_USART10_CLKSOURCE_MSI:
3203 if (LL_RCC_MSI_IsReady() != 0U)
3204 {
3205 frequency = MSI_VALUE;
3206 }
3207 break;
3208
3209 case LL_RCC_USART1_CLKSOURCE_LSE:
3210 case LL_RCC_USART2_CLKSOURCE_LSE:
3211 case LL_RCC_USART3_CLKSOURCE_LSE:
3212 case LL_RCC_USART6_CLKSOURCE_LSE:
3213 case LL_RCC_USART10_CLKSOURCE_LSE:
3214 if (LL_RCC_LSE_IsReady() != 0U)
3215 {
3216 frequency = LSE_VALUE;
3217 }
3218 break;
3219
3220 default:
3221 /* Unexpected case */
3222 break;
3223 }
3224
3225 return frequency;
3226 }
3227
3228 /**
3229 * @brief Return XSPI clock frequency
3230 * @param XSPIxSource This parameter can be one of the following values:
3231 * @arg @ref LL_RCC_XSPI1_CLKSOURCE
3232 * @arg @ref LL_RCC_XSPI2_CLKSOURCE
3233 * @arg @ref LL_RCC_XSPI3_CLKSOURCE
3234 * @retval XSPI clock frequency (in Hz)
3235 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
3236 */
3237
LL_RCC_GetXSPIClockFreq(uint32_t XSPIxSource)3238 uint32_t LL_RCC_GetXSPIClockFreq(uint32_t XSPIxSource)
3239 {
3240 uint32_t frequency = LL_RCC_PERIPH_FREQUENCY_NO;
3241 uint32_t ic_divider;
3242
3243 switch (LL_RCC_GetXSPIClockSource(XSPIxSource))
3244 {
3245 case LL_RCC_XSPI1_CLKSOURCE_HCLK:
3246 case LL_RCC_XSPI2_CLKSOURCE_HCLK:
3247 case LL_RCC_XSPI3_CLKSOURCE_HCLK:
3248 frequency = RCC_GetHCLKClockFreq(LL_RCC_GetSystemClockFreq());
3249 break;
3250
3251 case LL_RCC_XSPI1_CLKSOURCE_CLKP:
3252 case LL_RCC_XSPI2_CLKSOURCE_CLKP:
3253 case LL_RCC_XSPI3_CLKSOURCE_CLKP:
3254 frequency = LL_RCC_GetCLKPClockFreq(LL_RCC_CLKP_CLKSOURCE);
3255 break;
3256
3257 case LL_RCC_XSPI1_CLKSOURCE_IC3:
3258 case LL_RCC_XSPI2_CLKSOURCE_IC3:
3259 case LL_RCC_XSPI3_CLKSOURCE_IC3:
3260 if (LL_RCC_IC3_IsEnabled() != 0U)
3261 {
3262 ic_divider = LL_RCC_IC3_GetDivider();
3263 switch (LL_RCC_IC3_GetSource())
3264 {
3265 case LL_RCC_ICCLKSOURCE_PLL1:
3266 frequency = LL_RCC_GetPLL1ClockFreq();
3267 frequency = frequency / ic_divider;
3268 break;
3269 case LL_RCC_ICCLKSOURCE_PLL2:
3270 frequency = LL_RCC_GetPLL2ClockFreq();
3271 frequency = frequency / ic_divider;
3272 break;
3273 case LL_RCC_ICCLKSOURCE_PLL3:
3274 frequency = LL_RCC_GetPLL3ClockFreq();
3275 frequency = frequency / ic_divider;
3276 break;
3277 case LL_RCC_ICCLKSOURCE_PLL4:
3278 frequency = LL_RCC_GetPLL4ClockFreq();
3279 frequency = frequency / ic_divider;
3280 break;
3281 default:
3282 /* Unexpected case */
3283 break;
3284 }
3285 }
3286 break;
3287
3288 case LL_RCC_XSPI1_CLKSOURCE_IC4:
3289 case LL_RCC_XSPI2_CLKSOURCE_IC4:
3290 case LL_RCC_XSPI3_CLKSOURCE_IC4:
3291 if (LL_RCC_IC4_IsEnabled() != 0U)
3292 {
3293 ic_divider = LL_RCC_IC4_GetDivider();
3294 switch (LL_RCC_IC4_GetSource())
3295 {
3296 case LL_RCC_ICCLKSOURCE_PLL1:
3297 frequency = LL_RCC_GetPLL1ClockFreq();
3298 frequency = frequency / ic_divider;
3299 break;
3300 case LL_RCC_ICCLKSOURCE_PLL2:
3301 frequency = LL_RCC_GetPLL2ClockFreq();
3302 frequency = frequency / ic_divider;
3303 break;
3304 case LL_RCC_ICCLKSOURCE_PLL3:
3305 frequency = LL_RCC_GetPLL3ClockFreq();
3306 frequency = frequency / ic_divider;
3307 break;
3308 case LL_RCC_ICCLKSOURCE_PLL4:
3309 frequency = LL_RCC_GetPLL4ClockFreq();
3310 frequency = frequency / ic_divider;
3311 break;
3312 default:
3313 /* Unexpected case */
3314 break;
3315 }
3316 }
3317 break;
3318
3319 default:
3320 /* Nothing to do */
3321 break;
3322 }
3323
3324 return frequency;
3325 }
3326
3327 /**
3328 * @}
3329 */
3330
3331 /**
3332 * @}
3333 */
3334
3335 /** @addtogroup RCC_LL_Private_Functions
3336 * @{
3337 */
3338
3339 /**
3340 * @brief Return HCLK clock frequency
3341 * @param SYSCLK_Frequency SYSCLK clock frequency
3342 * @retval HCLK clock frequency (in Hz)
3343 */
RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency)3344 static uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency)
3345 {
3346 /* HCLK clock frequency */
3347 return LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, LL_RCC_GetAHBPrescaler());
3348 }
3349
3350 /**
3351 * @brief Return PCLK1 clock frequency
3352 * @param HCLK_Frequency HCLK clock frequency
3353 * @retval PCLK1 clock frequency (in Hz)
3354 */
RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency)3355 static uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency)
3356 {
3357 /* PCLK1 clock frequency */
3358 return LL_RCC_CALC_PCLK1_FREQ(HCLK_Frequency, LL_RCC_GetAPB1Prescaler());
3359 }
3360
3361 /**
3362 * @brief Return PCLK2 clock frequency
3363 * @param HCLK_Frequency HCLK clock frequency
3364 * @retval PCLK2 clock frequency (in Hz)
3365 */
RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency)3366 static uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency)
3367 {
3368 /* PCLK2 clock frequency */
3369 return LL_RCC_CALC_PCLK2_FREQ(HCLK_Frequency, LL_RCC_GetAPB2Prescaler());
3370 }
3371
3372 /**
3373 * @brief Return PCLK4 clock frequency
3374 * @param HCLK_Frequency HCLK clock frequency
3375 * @retval PCLK4 clock frequency (in Hz)
3376 */
RCC_GetPCLK4ClockFreq(uint32_t HCLK_Frequency)3377 static uint32_t RCC_GetPCLK4ClockFreq(uint32_t HCLK_Frequency)
3378 {
3379 /* PCLK4 clock frequency */
3380 return LL_RCC_CALC_PCLK4_FREQ(HCLK_Frequency, LL_RCC_GetAPB4Prescaler());
3381 }
3382
3383 /**
3384 * @brief Return PCLK5 clock frequency
3385 * @param HCLK_Frequency HCLK clock frequency
3386 * @retval PCLK5 clock frequency (in Hz)
3387 */
RCC_GetPCLK5ClockFreq(uint32_t HCLK_Frequency)3388 static uint32_t RCC_GetPCLK5ClockFreq(uint32_t HCLK_Frequency)
3389 {
3390 /* PCLK5 clock frequency */
3391 return LL_RCC_CALC_PCLK5_FREQ(HCLK_Frequency, LL_RCC_GetAPB5Prescaler());
3392 }
3393
3394 /**
3395 * @}
3396 */
3397
3398 /**
3399 * @}
3400 */
3401
3402 #endif /* defined(RCC) */
3403
3404 /**
3405 * @}
3406 */
3407
