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Searched defs:ETH_MACMDIOAR_CR_DIV42 (Results 1 – 25 of 50) sorted by relevance

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/hal_stm32-latest/stm32cube/stm32h7rsxx/soc/
Dstm32h7s7xx.h6854 #define ETH_MACMDIOAR_CR_DIV42 ((uint32_t)0x00000000) /* CSR clock/42 */ macro
Dstm32h7s3xx.h6775 #define ETH_MACMDIOAR_CR_DIV42 ((uint32_t)0x00000000) /* CSR clock/42 */ macro
Dstm32h7r3xx.h6330 #define ETH_MACMDIOAR_CR_DIV42 ((uint32_t)0x00000000) /* CSR clock/42 */ macro
Dstm32h7r7xx.h6407 #define ETH_MACMDIOAR_CR_DIV42 ((uint32_t)0x00000000) /* CSR clock/42 */ macro
/hal_stm32-latest/stm32cube/stm32h7xx/soc/
Dstm32h730xxq.h7912 #define ETH_MACMDIOAR_CR_DIV42 (0U) /* CSR clock/42 */ macro
Dstm32h733xx.h7911 #define ETH_MACMDIOAR_CR_DIV42 (0U) /* CSR clock/42 */ macro
Dstm32h725xx.h7658 #define ETH_MACMDIOAR_CR_DIV42 (0U) /* CSR clock/42 */ macro
Dstm32h730xx.h7911 #define ETH_MACMDIOAR_CR_DIV42 (0U) /* CSR clock/42 */ macro
Dstm32h735xx.h7912 #define ETH_MACMDIOAR_CR_DIV42 (0U) /* CSR clock/42 */ macro
Dstm32h723xx.h7657 #define ETH_MACMDIOAR_CR_DIV42 (0U) /* CSR clock/42 */ macro
Dstm32h750xx.h7672 #define ETH_MACMDIOAR_CR_DIV42 (0U) /* CSR clock/42 */ macro
Dstm32h753xx.h7672 #define ETH_MACMDIOAR_CR_DIV42 (0U) /* CSR clock/42 */ macro
Dstm32h745xx.h7586 #define ETH_MACMDIOAR_CR_DIV42 (0U) /* CSR clock/42 */ macro
Dstm32h745xg.h7586 #define ETH_MACMDIOAR_CR_DIV42 (0U) /* CSR clock/42 */ macro
Dstm32h742xx.h7384 #define ETH_MACMDIOAR_CR_DIV42 (0U) /* CSR clock/42 */ macro
Dstm32h743xx.h7479 #define ETH_MACMDIOAR_CR_DIV42 (0U) /* CSR clock/42 */ macro
Dstm32h755xx.h7779 #define ETH_MACMDIOAR_CR_DIV42 (0U) /* CSR clock/42 */ macro
Dstm32h757xx.h7862 #define ETH_MACMDIOAR_CR_DIV42 (0U) /* CSR clock/42 */ macro
Dstm32h747xg.h7669 #define ETH_MACMDIOAR_CR_DIV42 (0U) /* CSR clock/42 */ macro
Dstm32h747xx.h7669 #define ETH_MACMDIOAR_CR_DIV42 (0U) /* CSR clock/42 */ macro
/hal_stm32-latest/stm32cube/stm32h5xx/soc/
Dstm32h573xx.h6803 #define ETH_MACMDIOAR_CR_DIV42 ((uint32_t)0x00000000) /* CSR clock/42 */ macro
Dstm32h563xx.h6394 #define ETH_MACMDIOAR_CR_DIV42 ((uint32_t)0x00000000) /* CSR clock/42 */ macro
/hal_stm32-latest/stm32cube/stm32mp1xx/soc/
Dstm32mp151dxx_ca7.h11720 #define ETH_MACMDIOAR_CR_DIV42 (0x0UL << ETH_MACMDIOAR_CR_Pos) /*!<… macro
Dstm32mp153axx_ca7.h13271 #define ETH_MACMDIOAR_CR_DIV42 (0x0UL << ETH_MACMDIOAR_CR_Pos) /*!<… macro
Dstm32mp151fxx_cm4.h11883 #define ETH_MACMDIOAR_CR_DIV42 (0x0UL << ETH_MACMDIOAR_CR_Pos) /*!<… macro

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