1 /**
2   ******************************************************************************
3   * @file    stm32n6xx_hal_eth.h
4   * @author  MCD Application Team
5   * @brief   Header file of ETH HAL module.
6   ******************************************************************************
7   * @attention
8   *
9   * Copyright (c) 2023 STMicroelectronics.
10   * All rights reserved.
11   *
12   * This software is licensed under terms that can be found in the LICENSE file
13   * in the root directory of this software component.
14   * If no LICENSE file comes with this software, it is provided AS-IS.
15   *
16   ******************************************************************************
17   */
18 
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32N6xx_HAL_ETH_H
21 #define STM32N6xx_HAL_ETH_H
22 
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26 
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32n6xx_hal_def.h"
29 
30 #if defined(ETH1)
31 
32 /** @addtogroup STM32N6xx_HAL_Driver
33   * @{
34   */
35 
36 /** @addtogroup ETH
37   * @{
38   */
39 
40 /* Exported types ------------------------------------------------------------*/
41 /* ETH Multi-Queue feature is supported by HW */
42 #define ETH_MULTIQUEUE_SUPPORTED
43 
44 #ifndef ETH_MTL_TX_Q_CNT
45 #define ETH_MTL_TX_Q_CNT         2U
46 #endif /* ETH_MTL_TX_Q_CNT */
47 
48 #ifndef ETH_MTL_RX_Q_CNT
49 #define ETH_MTL_RX_Q_CNT         2U
50 #endif /* ETH_MTL_RX_Q_CNT */
51 
52 #ifndef ETH_DMA_CH_CNT
53 #define ETH_DMA_CH_CNT         ETH_MTL_TX_Q_CNT
54 #endif /* ETH_DMA_CH_CNT */
55 
56 #ifndef ETH_DMA_TX_CH_CNT
57 #define ETH_DMA_TX_CH_CNT         2U
58 #endif /* ETH_DMA_TX_CH_CNT */
59 
60 #ifndef ETH_DMA_RX_CH_CNT
61 #define ETH_DMA_RX_CH_CNT         2U
62 #endif /* ETH_DMA_RX_CH_CNT */
63 
64 #ifndef ETH_TX_DESC_CNT
65 #define ETH_TX_DESC_CNT         4U
66 #endif /* ETH_TX_DESC_CNT */
67 
68 #ifndef ETH_RX_DESC_CNT
69 #define ETH_RX_DESC_CNT         4U
70 #endif /* ETH_RX_DESC_CNT */
71 
72 #ifndef ETH_SWRESET_TIMEOUT
73 #define ETH_SWRESET_TIMEOUT     500U
74 #endif /* ETH_SWRESET_TIMEOUT */
75 
76 #ifndef ETH_MDIO_BUS_TIMEOUT
77 #define ETH_MDIO_BUS_TIMEOUT    1000U
78 #endif /* ETH_MDIO_BUS_TIMEOUT */
79 
80 #ifndef ETH_MAC_US_TICK
81 #define ETH_MAC_US_TICK         1000000U
82 #endif /* ETH_MAC_US_TICK */
83 
84 /*********************** Descriptors struct def section ************************/
85 /** @defgroup ETH_Exported_Types ETH Exported Types
86   * @{
87   */
88 
89 /**
90   * @brief  ETH DMA Descriptor structure definition
91   */
92 typedef struct
93 {
94   __IO uint32_t DESC0;
95   __IO uint32_t DESC1;
96   __IO uint32_t DESC2;
97   __IO uint32_t DESC3;
98   uint32_t BackupAddr0; /* used to store rx buffer 1 address */
99   uint32_t BackupAddr1; /* used to store rx buffer 2 address */
100 } ETH_DMADescTypeDef;
101 /**
102   *
103   */
104 
105 /**
106   * @brief  ETH Buffers List structure definition
107   */
108 typedef struct __ETH_BufferTypeDef
109 {
110   uint8_t *buffer;                /*<! buffer address */
111 
112   uint32_t len;                   /*<! buffer length */
113 
114   struct __ETH_BufferTypeDef *next; /*<! Pointer to the next buffer in the list */
115 } ETH_BufferTypeDef;
116 /**
117   *
118   */
119 
120 /**
121   * @brief  DMA Transmit Descriptors Wrapper structure definition
122   */
123 typedef struct
124 {
125   uint32_t  TxDesc[ETH_TX_DESC_CNT];        /*<! Tx DMA descriptors addresses */
126 
127   uint32_t  CurTxDesc;                      /*<! Current Tx descriptor index for packet transmission */
128 
129   uint32_t *PacketAddress[ETH_TX_DESC_CNT];  /*<! Ethernet packet addresses array */
130 
131   uint32_t *CurrentPacketAddress;           /*<! Current transmit packet addresses */
132 
133   uint32_t BuffersInUse;                   /*<! Buffers in Use */
134 
135   uint32_t releaseIndex;                  /*<! Release index */
136 } ETH_TxDescListTypeDef;
137 /**
138   *
139   */
140 
141 /**
142   * @brief  Transmit Packet Configuration structure definition
143   */
144 typedef struct
145 {
146   uint32_t TxDMACh;                 /*!< Sets the Tx Queue/Channel which will transmit the packet */
147 
148   uint32_t Attributes;              /*!< Tx packet HW features capabilities.
149                                          This parameter can be a combination of @ref ETH_Tx_Packet_Attributes*/
150 
151   uint32_t Length;                  /*!< Total packet length   */
152 
153   ETH_BufferTypeDef *TxBuffer;      /*!< Tx buffers pointers */
154 
155   uint32_t SrcAddrCtrl;             /*!< Specifies the source address insertion control.
156                                          This parameter can be a value of @ref ETH_Tx_Packet_Source_Addr_Control */
157 
158   uint32_t CRCPadCtrl;             /*!< Specifies the CRC and Pad insertion and replacement control.
159                                         This parameter can be a value of @ref ETH_Tx_Packet_CRC_Pad_Control  */
160 
161   uint32_t ChecksumCtrl;           /*!< Specifies the checksum insertion control.
162                                         This parameter can be a value of @ref ETH_Tx_Packet_Checksum_Control  */
163 
164   uint32_t MaxSegmentSize;         /*!< Sets TCP maximum segment size only when TCP segmentation is enabled.
165                                         This parameter can be a value from 0x0 to 0x3FFF */
166 
167   uint32_t PayloadLen;             /*!< Sets Total payload length only when TCP segmentation is enabled.
168                                         This parameter can be a value from 0x0 to 0x3FFFF */
169 
170   uint32_t TCPHeaderLen;           /*!< Sets TCP header length only when TCP segmentation is enabled.
171                                         This parameter can be a value from 0x5 to 0xF */
172 
173   uint32_t VlanTag;                /*!< Sets VLAN Tag only when VLAN is enabled.
174                                         This parameter can be a value from 0x0 to 0xFFFF*/
175 
176   uint32_t VlanCtrl;               /*!< Specifies VLAN Tag insertion control only when VLAN is enabled.
177                                         This parameter can be a value of @ref ETH_Tx_Packet_VLAN_Control */
178 
179   uint32_t InnerVlanTag;           /*!< Sets Inner VLAN Tag only when Inner VLAN is enabled.
180                                         This parameter can be a value from 0x0 to 0x3FFFF */
181 
182   uint32_t InnerVlanCtrl;          /*!< Specifies Inner VLAN Tag insertion control only when Inner VLAN is enabled.
183                                         This parameter can be a value of @ref ETH_Tx_Packet_Inner_VLAN_Control   */
184 
185   void *pData;                     /*!< Specifies Application packet pointer to save   */
186 
187 } ETH_TxPacketConfigTypeDef;
188 /**
189   *
190   */
191 
192 /**
193   * @brief  ETH Timestamp structure definition
194   */
195 typedef struct
196 {
197   uint32_t TimeStampLow;
198   uint32_t TimeStampHigh;
199 
200 } ETH_TimeStampTypeDef;
201 /**
202   *
203   */
204 
205 #ifdef HAL_ETH_USE_PTP
206 /**
207   * @brief  ETH Timeupdate structure definition
208   */
209 typedef struct
210 {
211   uint32_t Seconds;
212   uint32_t NanoSeconds;
213 } ETH_TimeTypeDef;
214 /**
215   *
216   */
217 #endif  /* HAL_ETH_USE_PTP */
218 
219 /**
220   * @brief  DMA Receive Descriptors Wrapper structure definition
221   */
222 typedef struct
223 {
224   uint32_t RxDesc[ETH_RX_DESC_CNT];     /*<! Rx DMA descriptors addresses. */
225 
226   uint32_t ItMode;                      /*<! If 1, DMA will generate the Rx complete interrupt.
227                                              If 0, DMA will not generate the Rx complete interrupt. */
228 
229   uint32_t RxDescIdx;                 /*<! Current Rx descriptor. */
230 
231   uint32_t RxDescCnt;                 /*<! Number of descriptors . */
232 
233   uint32_t RxDataLength;              /*<! Received Data Length. */
234 
235   uint32_t RxBuildDescIdx;            /*<! Current Rx Descriptor for building descriptors. */
236 
237   uint32_t RxBuildDescCnt;            /*<! Number of Rx Descriptors awaiting building. */
238 
239   uint32_t pRxLastRxDesc;             /*<! Last received descriptor. */
240 
241   ETH_TimeStampTypeDef TimeStamp;     /*<! Time Stamp Low value for receive. */
242 
243   void *pRxStart;                     /*<! Pointer to the first buff. */
244 
245   void *pRxEnd;                       /*<! Pointer to the last buff. */
246 
247 } ETH_RxDescListTypeDef;
248 /**
249   *
250   */
251 
252 /**
253   * @brief  ETH MAC Configuration Structure definition
254   */
255 typedef struct
256 {
257   uint32_t
258   SourceAddrControl;           /*!< Selects the Source Address Insertion or Replacement Control.
259                                                      This parameter can be a value of @ref ETH_Source_Addr_Control */
260 
261   FunctionalState
262   ChecksumOffload;             /*!< Enables or Disable the checksum checking for received packet payloads TCP, UDP or ICMP headers */
263 
264   uint32_t         InterPacketGapVal;           /*!< Sets the minimum IPG between Packet during transmission.
265                                                      This parameter can be a value of @ref ETH_Inter_Packet_Gap */
266 
267   FunctionalState  GiantPacketSizeLimitControl; /*!< Enables or disables the Giant Packet Size Limit Control. */
268 
269   FunctionalState  Support2KPacket;             /*!< Enables or disables the IEEE 802.3as Support for 2K length Packets */
270 
271   FunctionalState  CRCStripTypePacket;          /*!< Enables or disables the CRC stripping for Type packets.*/
272 
273   FunctionalState  AutomaticPadCRCStrip;        /*!< Enables or disables  the Automatic MAC Pad/CRC Stripping.*/
274 
275   FunctionalState  Watchdog;                    /*!< Enables or disables the Watchdog timer on Rx path.*/
276 
277   FunctionalState  Jabber;                      /*!< Enables or disables Jabber timer on Tx path.*/
278 
279   FunctionalState  JumboPacket;                 /*!< Enables or disables receiving Jumbo Packet
280                                                            When enabled, the MAC allows jumbo packets of 9,018 bytes
281                                                            without reporting a giant packet error */
282 
283   FunctionalState  PortSelect;                  /*!< Sets the Port Select
284                                                             When disabled, the line speed is for 1000Mbps operations
285                                                             When enabled, it is for 10 or 100Mbps operations*/
286 
287   uint32_t         Speed;                       /*!< Sets the Ethernet speed: 10/100 Mbps.
288                                                            This parameter can be a value of @ref ETH_Speed */
289 
290   uint32_t         DuplexMode;                  /*!< Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode
291                                                            This parameter can be a value of @ref ETH_Duplex_Mode */
292 
293   FunctionalState  LoopbackMode;                /*!< Enables or disables the loopback mode */
294 
295   FunctionalState
296   CarrierSenseBeforeTransmit;  /*!< Enables or disables the Carrier Sense Before Transmission in Full Duplex Mode. */
297 
298   FunctionalState  ReceiveOwn;                  /*!< Enables or disables the Receive Own in Half Duplex mode. */
299 
300   FunctionalState
301   CarrierSenseDuringTransmit;  /*!< Enables or disables the Carrier Sense During Transmission in the Half Duplex mode */
302 
303   FunctionalState
304   RetryTransmission;           /*!< Enables or disables the MAC retry transmission, when a collision occurs in Half Duplex mode.*/
305 
306   uint32_t         BackOffLimit;                /*!< Selects the BackOff limit value.
307                                                         This parameter can be a value of @ref ETH_Back_Off_Limit */
308 
309   FunctionalState
310   DeferralCheck;               /*!< Enables or disables the deferral check function in Half Duplex mode. */
311 
312   uint32_t
313   PreambleLength;              /*!< Selects or not the Preamble Length for Transmit packets (Full Duplex mode).
314                                                            This parameter can be a value of @ref ETH_Preamble_Length */
315 
316   FunctionalState
317   UnicastSlowProtocolPacketDetect;   /*!< Enable or disables the Detection of Slow Protocol Packets with unicast address. */
318 
319   FunctionalState  SlowProtocolDetect;          /*!< Enable or disables the Slow Protocol Detection. */
320 
321   FunctionalState  CRCCheckingRxPackets;        /*!< Enable or disables the CRC Checking for Received Packets. */
322 
323   uint32_t
324   GiantPacketSizeLimit;        /*!< Specifies the packet size that the MAC will declare it as Giant, If it's size is
325                                                     greater than the value programmed in this field in units of bytes
326                                                     This parameter must be a number between
327                                                     Min_Data = 0x618 (1518 byte) and Max_Data = 0x3FFF (32 Kbyte). */
328 
329   FunctionalState  ExtendedInterPacketGap;      /*!< Enable or disables the extended inter packet gap. */
330 
331   uint32_t         ExtendedInterPacketGapVal;   /*!< Sets the Extended IPG between Packet during transmission.
332                                                            This parameter can be a value from 0x0 to 0xFF */
333 
334   FunctionalState  ProgrammableWatchdog;        /*!< Enable or disables the Programmable Watchdog.*/
335 
336   uint32_t         WatchdogTimeout;             /*!< This field is used as watchdog timeout for a received packet
337                                                         This parameter can be a value of @ref ETH_Watchdog_Timeout */
338 
339   uint32_t
340   PauseTime;                   /*!< This field holds the value to be used in the Pause Time field in the transmit control packet.
341                                                    This parameter must be a number between
342                                                    Min_Data = 0x0 and Max_Data = 0xFFFF.*/
343 
344   FunctionalState
345   ZeroQuantaPause;             /*!< Enable or disables the automatic generation of Zero Quanta Pause Control packets.*/
346 
347   uint32_t
348   PauseLowThreshold;           /*!< This field configures the threshold of the PAUSE to be checked for automatic retransmission of PAUSE Packet.
349                                                    This parameter can be a value of @ref ETH_Pause_Low_Threshold */
350 
351   FunctionalState
352   TransmitFlowControl;         /*!< Enables or disables the MAC to transmit Pause packets in Full Duplex mode
353                                                    or the MAC back pressure operation in Half Duplex mode */
354 
355   FunctionalState
356   UnicastPausePacketDetect;    /*!< Enables or disables the MAC to detect Pause packets with unicast address of the station */
357 
358   FunctionalState  ReceiveFlowControl;          /*!< Enables or disables the MAC to decodes the received Pause packet
359                                                   and disables its transmitter for a specified (Pause) time */
360 
361   FunctionalState  PacketBurst;                 /*!< Enables or disables the MAC to allow packet bursting during transmission
362                                                       in the GMII Halfduplex mode */
363 
364 } ETH_MACConfigTypeDef;
365 /**
366   *
367   */
368 
369 /**
370   * @brief  ETH DMA Configuration Structure definition
371   */
372 typedef struct
373 {
374   FunctionalState         PBLx8Mode;                    /*!< Enables or disables the PBL multiplication by eight. */
375 
376   uint32_t
377   TxDMABurstLength;        /*!< Indicates the maximum number of beats to be transferred in one Tx DMA transaction.
378                                                      This parameter can be a value of @ref ETH_Tx_DMA_Burst_Length */
379   FunctionalState
380   SecondPacketOperate;     /*!< Enables or disables the Operate on second Packet mode, which allows the DMA to process a second
381                                  Packet of Transmit data even before obtaining the status for the first one. */
382   FunctionalState         TCPSegmentation;              /*!< Enables or disables the TCP Segmentation */
383 
384   uint32_t                DescriptorSkipLength;         /*!< Sets the Descriptor Skip Length */
385 
386   FunctionalState         FlushRxPacket;                /*!< Enables or disables the Rx Packet Flush */
387 
388   uint32_t
389   RxDMABurstLength;        /*!< Indicates the maximum number of beats to be transferred in one Rx DMA transaction.
390                                                     This parameter can be a value of @ref ETH_Rx_DMA_Burst_Length */
391   uint32_t                MaximumSegmentSize;           /*!< Sets the maximum segment size that should be used while segmenting the packet
392                                                              This parameter can be a value from 0x40 to 0x3FFF */
393 } DMAChannelInstanceTypeDef;
394 /**
395   *
396   */
397 
398 /**
399   * @brief  ETH DMA Configuration Structure definition
400   */
401 typedef struct
402 {
403   DMAChannelInstanceTypeDef DMACh[ETH_DMA_CH_CNT];          /*!< DMA Channel x Configuration */
404 
405   uint32_t                  TransmitArbitrationAlgorithm;  /*!< Speicifies the arbitration algorithm for the Transmit side */
406 
407   FunctionalState           AddressAlignedBeats;           /*!< Enables or disables the AHB Master interface address aligned
408                                                               burst transfers on Read and Write channels  */
409   uint32_t                  BurstMode;                     /*!< Sets the AHB Master interface burst transfers.
410                                                                This parameter can be a value of @ref ETH_Burst_Mode */
411   uint32_t                  RxOSRLimit;                    /*!< Sets the maximum outstanding request on the AXI read interface. */
412 
413   uint32_t                  TxOSRLimit;                    /*!< Sets the maximum outstanding request on the AXI write interface. */
414 
415   uint32_t                  AXIBLENMaxSize;                 /*!< Sets the maximum BLEN max size that should be used on th AXI interface to initiate burst transfers of specified lengths */
416 
417   FunctionalState           TransmitPriority;               /*!< Sets Transmit priority over Receive */
418 
419 } ETH_DMAConfigTypeDef;
420 /**
421   *
422   */
423 
424 /**
425   * @brief  HAL ETH Media Interfaces enum definition
426   */
427 typedef enum
428 {
429   HAL_ETH_MII_MODE             = 0x00U,   /*!<  Media Independent Interface               */
430   HAL_ETH_RMII_MODE            = 0x01U,   /*!<   Reduced Media Independent Interface       */
431   HAL_ETH_GMII_MODE            = 0x02U,   /*!<  Giga Media Independent Interface       */
432   HAL_ETH_RGMII_MODE           = 0x03U    /*!<  Reduced Giga Media Independent Interface       */
433 } ETH_MediaInterfaceTypeDef;
434 /**
435   *
436   */
437 
438 #ifdef HAL_ETH_USE_PTP
439 /**
440   * @brief  HAL ETH PTP Update type enum definition
441   */
442 typedef enum
443 {
444   HAL_ETH_PTP_POSITIVE_UPDATE   = 0x00000000U,   /*!<  PTP positive time update       */
445   HAL_ETH_PTP_NEGATIVE_UPDATE   = 0x00000001U   /*!<  PTP negative time update       */
446 } ETH_PtpUpdateTypeDef;
447 /**
448   *
449   */
450 #endif  /* HAL_ETH_USE_PTP */
451 
452 /**
453   * @brief  ETH Init Structure definition
454   */
455 typedef struct
456 {
457   uint8_t
458   *MACAddr;                                     /*!< MAC Address of used Hardware: must be pointer on an array of 6 bytes */
459 
460   ETH_MediaInterfaceTypeDef   MediaInterface;   /*!< Selects the MII/RMII/RGMII interface. */
461 
462   ETH_DMADescTypeDef
463   *TxDesc[ETH_DMA_TX_CH_CNT];                   /*!< Provides the address of the first DMA CH Tx descriptor in the list */
464 
465   ETH_DMADescTypeDef
466   *RxDesc[ETH_DMA_RX_CH_CNT];                   /*!< Provides the address of the first DMA Rx CH descriptor in the list */
467 
468   uint32_t                    RxBuffLen;        /*!< Provides the length of Rx buffers size */
469 
470 } ETH_InitTypeDef;
471 /**
472   *
473   */
474 
475 #ifdef HAL_ETH_USE_PTP
476 /**
477   * @brief  ETH PTP Init Structure definition
478   */
479 typedef struct
480 {
481   uint32_t                    AV8021ASMEN;                  /*!< Enable AV 802.1AS Mode */
482   uint32_t                    Timestamp;                    /*!< Enable Timestamp */
483   uint32_t                    TimestampUpdateMode;          /*!< Fine or Coarse Timestamp Update */
484   uint32_t                    TimestampInitialize;          /*!< Initialize Timestamp */
485   uint32_t                    TimestampUpdate;              /*!< Timestamp Update */
486   uint32_t                    TimestampAddendUpdate;        /*!< Timestamp Addend Update */
487   uint32_t                    TimestampAll;                 /*!< Enable Timestamp for All Packets */
488   uint32_t                    TimestampRolloverMode;        /*!< Timestamp Digital or Binary Rollover Control */
489   uint32_t                    TimestampV2;                  /*!< Enable PTP Packet Processing for Version 2 Format */
490   uint32_t                    TimestampEthernet;            /*!< Enable Processing of PTP over Ethernet Packets */
491   uint32_t                    TimestampIPv6;                /*!< Enable Processing of PTP Packets Sent over IPv6-UDP */
492   uint32_t                    TimestampIPv4;                /*!< Enable Processing of PTP Packets Sent over IPv4-UDP */
493   uint32_t                    TimestampEvent;               /*!< Enable Timestamp Snapshot for Event Messages */
494   uint32_t                    TimestampMaster;              /*!< Enable Timestamp Snapshot for Event Messages */
495   uint32_t                    TimestampSnapshots;           /*!< Select PTP packets for Taking Snapshots */
496   uint32_t                    TimestampFilter;              /*!< Enable MAC Address for PTP Packet Filtering */
497   uint32_t
498   TimestampChecksumCorrection;  /*!< Enable checksum correction during OST for PTP over UDP/IPv4 packets */
499   uint32_t                    TimestampExternalSystemTime;  /*!< External System Time Input */
500   uint32_t                    TimestampStatusMode;          /*!< Transmit Timestamp Status Mode */
501   uint32_t                    TimestampAddend;              /*!< Timestamp addend value */
502   uint32_t                    TimestampSubsecondInc;        /*!< Subsecond Increment */
503 
504 } ETH_PTP_ConfigTypeDef;
505 /**
506   *
507   */
508 #endif  /* HAL_ETH_USE_PTP */
509 
510 /**
511   * @brief  HAL State structures definition
512   */
513 typedef uint32_t HAL_ETH_StateTypeDef;
514 /**
515   *
516   */
517 
518 /**
519   * @brief  HAL ETH Rx Get Buffer Function definition
520   */
521 typedef  void (*pETH_rxAllocateCallbackTypeDef)(uint8_t **buffer);  /*!< pointer to an ETH Rx Get Buffer Function */
522 /**
523   *
524   */
525 
526 /**
527   * @brief  HAL ETH Rx Set App Data Function definition
528   */
529 typedef  void (*pETH_rxLinkCallbackTypeDef)(void **pStart, void **pEnd, uint8_t *buff,
530                                             uint16_t Length); /*!< pointer to an ETH Rx Set App Data Function */
531 /**
532   *
533   */
534 
535 /**
536   * @brief  HAL ETH Tx Free Function definition
537   */
538 typedef  void (*pETH_txFreeCallbackTypeDef)(uint32_t *buffer);  /*!< pointer to an ETH Tx Free function */
539 /**
540   *
541   */
542 
543 /**
544   * @brief  HAL ETH Tx Free Function definition
545   */
546 typedef  void (*pETH_txPtpCallbackTypeDef)(uint32_t *buffer,
547                                            ETH_TimeStampTypeDef *timestamp);  /*!< pointer to an ETH Tx Free function */
548 /**
549   *
550   */
551 
552 /**
553   * @brief  ETH Handle Structure definition
554   */
555 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
556 typedef struct __ETH_HandleTypeDef
557 #else
558 typedef struct
559 #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
560 {
561   ETH_TypeDef                *Instance;                           /*!< Register base address       */
562 
563   ETH_InitTypeDef            Init;                                /*!< Ethernet Init Configuration */
564 
565   ETH_TxDescListTypeDef      TxDescList[ETH_DMA_TX_CH_CNT];       /*!< DMA Channel Tx descriptor wrapper: holds all Tx descriptors
566                                                                        list addresses and current descriptor index  */
567 
568   ETH_RxDescListTypeDef      RxDescList[ETH_DMA_RX_CH_CNT];       /*!< DMA Channel Rx descriptor wrapper: holds all Rx descriptors
569                                                                        list addresses and current descriptor index  */
570 #ifdef HAL_ETH_USE_PTP
571   ETH_TimeStampTypeDef       TxTimestamp;               /*!< Tx Timestamp */
572 #endif /* HAL_ETH_USE_PTP */
573 
574   __IO HAL_ETH_StateTypeDef  gState;                   /*!< ETH state information related to global Handle management
575                                                               and also related to Tx operations. This parameter can
576                                                               be a value of @ref ETH_State_Codes */
577 
578   __IO uint32_t              ErrorCode;                 /*!< Holds the global Error code of the ETH HAL status machine
579                                                              This parameter can be a value of @ref ETH_Error_Code.*/
580 
581   __IO uint32_t
582   DMAErrorCode;              /*!< Holds the DMA CH0/CH1 Rx Tx Error code when a DMA AIS interrupt occurs
583                                                              This parameter can be a combination of
584                                                              @ref ETH_DMA_Status_Flags */
585 
586   __IO uint32_t
587   MACErrorCode;              /*!< Holds the MAC Rx Tx Error code when a MAC Rx or Tx status interrupt occurs
588                                                              This parameter can be a combination of
589                                                              @ref ETH_MAC_Rx_Tx_Status */
590 
591   __IO uint32_t              MACWakeUpEvent;            /*!< Holds the Wake Up event when the MAC exit the power down mode
592                                                              This parameter can be a value of
593                                                              @ref ETH_MAC_Wake_Up_Event */
594 
595   __IO uint32_t              MACLPIEvent;               /*!< Holds the LPI event when the an LPI status interrupt occurs.
596                                                              This parameter can be a value of @ref ETHEx_LPI_Event */
597 
598   __IO uint32_t              IsPtpConfigured;           /*!< Holds the PTP configuration status.
599                                                              This parameter can be a value of
600                                                              @ref ETH_PTP_Config_Status */
601 
602   __IO uint32_t              TxCH;                      /*!< Holds the Tx DMA Channels Number events.
603                                                              This parameter can be a value of
604                                                              @ref ETH_DMA_Channel_Number_Tx_Rx_Selection */
605 
606   __IO uint32_t              RxCH;                      /*!< Holds the Rx DMA Channels Number events.
607                                                              This parameter can be a value of
608                                                              @ref ETH_DMA_Channel_Number_Tx_Rx_Selection */
609   __IO uint32_t              TxOpCH;                    /*!< Holds the Tx DMA Channel Index which transfer data.
610                                                              This parameter can be a value of
611                                                              @ref ETH_DMA_Channel_Number_TxOp_RxOp_Selection */
612   __IO uint32_t              RxOpCH;                    /*!< Holds the Rx DMA Channel Index which receive data.
613                                                              This parameter can be a value of
614                                                              @ref ETH_DMA_Channel_Number_TxOp_RxOp_Selection */
615 
616 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
617 
618   void (* TxCpltCallback)(struct __ETH_HandleTypeDef *heth);             /*!< ETH Tx Complete Callback */
619   void (* RxCpltCallback)(struct __ETH_HandleTypeDef *heth);            /*!< ETH Rx  Complete Callback     */
620   void (* ErrorCallback)(struct __ETH_HandleTypeDef *heth);             /*!< ETH Error Callback   */
621   void (* PMTCallback)(struct __ETH_HandleTypeDef *heth);               /*!< ETH Power Management Callback            */
622   void (* EEECallback)(struct __ETH_HandleTypeDef *heth);               /*!< ETH EEE Callback   */
623   void (* WakeUpCallback)(struct __ETH_HandleTypeDef *heth);            /*!< ETH Wake UP Callback   */
624 
625   void (* MspInitCallback)(struct __ETH_HandleTypeDef *heth);             /*!< ETH Msp Init callback              */
626   void (* MspDeInitCallback)(struct __ETH_HandleTypeDef *heth);           /*!< ETH Msp DeInit callback            */
627 
628 #endif  /* USE_HAL_ETH_REGISTER_CALLBACKS */
629 
630   pETH_rxAllocateCallbackTypeDef  rxAllocateCallback;  /*!< ETH Rx Get Buffer Function   */
631   pETH_rxLinkCallbackTypeDef      rxLinkCallback; /*!< ETH Rx Set App Data Function */
632   pETH_txFreeCallbackTypeDef      txFreeCallback;       /*!< ETH Tx Free Function         */
633   pETH_txPtpCallbackTypeDef       txPtpCallback;  /*!< ETH Tx Handle Ptp Function */
634 
635 }
636 ETH_HandleTypeDef;
637 /**
638   *
639   */
640 
641 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
642 /**
643   * @brief  HAL ETH Callback ID enumeration definition
644   */
645 typedef enum
646 {
647   HAL_ETH_MSPINIT_CB_ID            = 0x00U,    /*!< ETH MspInit callback ID           */
648   HAL_ETH_MSPDEINIT_CB_ID          = 0x01U,    /*!< ETH MspDeInit callback ID         */
649   HAL_ETH_TX_COMPLETE_CB_ID        = 0x02U,    /*!< ETH Tx Complete Callback ID       */
650   HAL_ETH_RX_COMPLETE_CB_ID        = 0x03U,    /*!< ETH Rx Complete Callback ID       */
651   HAL_ETH_ERROR_CB_ID              = 0x04U,    /*!< ETH Error Callback ID             */
652   HAL_ETH_PMT_CB_ID                = 0x06U,    /*!< ETH Power Management Callback ID  */
653   HAL_ETH_EEE_CB_ID                = 0x07U,    /*!< ETH EEE Callback ID               */
654   HAL_ETH_WAKEUP_CB_ID             = 0x08U     /*!< ETH Wake UP Callback ID           */
655 
656 } HAL_ETH_CallbackIDTypeDef;
657 
658 /**
659   * @brief  HAL ETH Callback pointer definition
660   */
661 typedef  void (*pETH_CallbackTypeDef)(ETH_HandleTypeDef *heth);  /*!< pointer to an ETH callback function */
662 
663 #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
664 
665 /**
666   * @brief  ETH MAC filter structure definition
667   */
668 typedef struct
669 {
670   FunctionalState PromiscuousMode;          /*!< Enable or Disable Promiscuous Mode */
671 
672   FunctionalState ReceiveAllMode;           /*!< Enable or Disable Receive All Mode */
673 
674   FunctionalState HachOrPerfectFilter;      /*!< Enable or Disable Perfect filtering in addition to Hash filtering */
675 
676   FunctionalState HashUnicast;              /*!< Enable or Disable Hash filtering on unicast packets */
677 
678   FunctionalState HashMulticast;            /*!< Enable or Disable Hash filtering on multicast packets */
679 
680   FunctionalState PassAllMulticast;         /*!< Enable or Disable passing all multicast packets */
681 
682   FunctionalState SrcAddrFiltering;         /*!< Enable or Disable source address filtering module */
683 
684   FunctionalState SrcAddrInverseFiltering;  /*!< Enable or Disable source address inverse filtering */
685 
686   FunctionalState DestAddrInverseFiltering; /*!< Enable or Disable destination address inverse filtering */
687 
688   FunctionalState BroadcastFilter;          /*!< Enable or Disable broadcast filter */
689 
690   uint32_t        ControlPacketsFilter;     /*!< Set the control packets filter
691                                                  This parameter can be a value of @ref ETH_Control_Packets_Filter */
692 } ETH_MACFilterConfigTypeDef;
693 /**
694   *
695   */
696 
697 /**
698   * @brief  ETH Power Down structure definition
699   */
700 typedef struct
701 {
702   FunctionalState WakeUpPacket;    /*!< Enable or Disable Wake up packet detection in power down mode */
703 
704   FunctionalState MagicPacket;     /*!< Enable or Disable Magic packet detection in power down mode */
705 
706   FunctionalState GlobalUnicast;    /*!< Enable or Disable Global unicast packet detection in power down mode */
707 
708   FunctionalState WakeUpForward;    /*!< Enable or Disable Forwarding Wake up packets */
709 
710 } ETH_PowerDownConfigTypeDef;
711 /**
712   *
713   */
714 
715 /**
716   * @}
717   */
718 
719 /* Exported constants --------------------------------------------------------*/
720 /** @defgroup ETH_Exported_Constants ETH Exported Constants
721   * @{
722   */
723 
724 /** @defgroup ETH_DMA_Tx_Descriptor_Bit_Definition ETH DMA Tx Descriptor Bit Definition
725   * @{
726   */
727 
728 /*
729    DMA Tx Normal Descriptor Read Format
730   -----------------------------------------------------------------------------------------------------------
731   TDES0 |                           Buffer1 or Header Address  [31:0]                                        |
732   -----------------------------------------------------------------------------------------------------------
733   TDES1 |                           Buffer2 Address [31:0] / Next Descriptor Address [31:0]                  |
734   -----------------------------------------------------------------------------------------------------------
735   TDES2 | IOC(31) |   TTSE(30) |    Buff2 Length[29:16] |    VTIR[15:14]  |    Header or Buff1 Length[13:0]  |
736   -----------------------------------------------------------------------------------------------------------
737   TDES3 | OWN(31)|CTXT(28)|FD(29)|LD(28)|CPC[27:26]|SAIC[25:23]|SLOTNUM[22:19]|TTSE(18)|TPL[17:16]|FT/L[15:0]|
738   -----------------------------------------------------------------------------------------------
739 */
740 
741 /**
742   * @brief  Bit definition of TDES0 RF register
743   */
744 #define ETH_DMATXNDESCRF_B1AP         0xFFFFFFFFU  /*!< Transmit Packet Timestamp Low */
745 
746 /**
747   * @brief  Bit definition of TDES1 RF register
748   */
749 #define ETH_DMATXNDESCRF_B2AP         0xFFFFFFFFU  /*!< Transmit Packet Timestamp High */
750 
751 /**
752   * @brief  Bit definition of TDES2 RF register
753   */
754 #define ETH_DMATXNDESCRF_IOC          0x80000000U  /*!< Interrupt on Completion */
755 #define ETH_DMATXNDESCRF_TTSE         0x40000000U  /*!< Transmit Timestamp Enable */
756 #define ETH_DMATXNDESCRF_B2L          0x3FFF0000U  /*!< Buffer 2 Length */
757 #define ETH_DMATXNDESCRF_VTIR         0x0000C000U  /*!< VLAN Tag Insertion or Replacement mask */
758 #define ETH_DMATXNDESCRF_VTIR_DISABLE 0x00000000U  /*!< Do not add a VLAN tag. */
759 #define ETH_DMATXNDESCRF_VTIR_REMOVE  0x00004000U  /*!< Remove the VLAN tag from the packets before transmission. */
760 #define ETH_DMATXNDESCRF_VTIR_INSERT  0x00008000U  /*!< Insert a VLAN tag. */
761 #define ETH_DMATXNDESCRF_VTIR_REPLACE 0x0000C000U  /*!< Replace the VLAN tag. */
762 #define ETH_DMATXNDESCRF_B1L          0x00003FFFU  /*!< Buffer 1 Length */
763 #define ETH_DMATXNDESCRF_HL           0x000003FFU  /*!< Header Length */
764 
765 /**
766   * @brief  Bit definition of TDES3 RF register
767   */
768 #define ETH_DMATXNDESCRF_OWN                                 0x80000000U  /*!< OWN bit: descriptor is owned by DMA engine */
769 #define ETH_DMATXNDESCRF_CTXT                                0x40000000U  /*!< Context Type */
770 #define ETH_DMATXNDESCRF_FD                                  0x20000000U  /*!< First Descriptor */
771 #define ETH_DMATXNDESCRF_LD                                  0x10000000U  /*!< Last Descriptor */
772 #define ETH_DMATXNDESCRF_CPC                                 0x0C000000U  /*!< CRC Pad Control mask */
773 #define ETH_DMATXNDESCRF_CPC_CRCPAD_INSERT                   0x00000000U  /*!< CRC Pad Control: CRC and Pad Insertion */
774 #define ETH_DMATXNDESCRF_CPC_CRC_INSERT                      0x04000000U  /*!< CRC Pad Control: CRC Insertion (Disable Pad Insertion) */
775 #define ETH_DMATXNDESCRF_CPC_DISABLE                         0x08000000U  /*!< CRC Pad Control: Disable CRC Insertion */
776 #define ETH_DMATXNDESCRF_CPC_CRC_REPLACE                     0x0C000000U  /*!< CRC Pad Control: CRC Replacement */
777 #define ETH_DMATXNDESCRF_SAIC                                0x03800000U  /*!< SA Insertion Control mask*/
778 #define ETH_DMATXNDESCRF_SAIC_DISABLE                        0x00000000U  /*!< SA Insertion Control: Do not include the source address */
779 #define ETH_DMATXNDESCRF_SAIC_INSERT                         0x00800000U  /*!< SA Insertion Control: Include or insert the source address */
780 #define ETH_DMATXNDESCRF_SAIC_REPLACE                        0x01000000U  /*!< SA Insertion Control: Replace the source address */
781 #define ETH_DMATXNDESCRF_THL                                 0x00780000U  /*!< TCP Header Length */
782 #define ETH_DMATXNDESCRF_SLOTNUM                             0x00780000U  /*!< Slot Number Control */
783 #define ETH_DMATXNDESCRF_TSE                                 0x00040000U  /*!< TCP segmentation enable */
784 #define ETH_DMATXNDESCRF_CIC                                 0x00030000U  /*!< Checksum Insertion Control: 4 cases */
785 #define ETH_DMATXNDESCRF_CIC_DISABLE                         0x00000000U  /*!< Do Nothing: Checksum Engine is disabled */
786 #define ETH_DMATXNDESCRF_CIC_IPHDR_INSERT                    0x00010000U  /*!< Only IP header checksum calculation and insertion are enabled. */
787 #define ETH_DMATXNDESCRF_CIC_IPHDR_PAYLOAD_INSERT            0x00020000U  /*!< IP header checksum and payload checksum calculation and insertion are
788                                                                                         enabled, but pseudo header
789                                                                                         checksum is not
790                                                                                         calculated in hardware */
791 #define ETH_DMATXNDESCRF_CIC_IPHDR_PAYLOAD_INSERT_PHDR_CALC  0x00030000U  /*!< IP Header checksum and payload checksum calculation and insertion are
792                                                                                         enabled, and pseudo header
793                                                                                         checksum is
794                                                                                         calculated in hardware. */
795 #define ETH_DMATXNDESCRF_TPL                                 0x0003FFFFU  /*!< TCP Payload Length */
796 #define ETH_DMATXNDESCRF_FL                                  0x00007FFFU  /*!< Transmit End of Ring */
797 
798 /*
799    DMA Tx Normal Descriptor Write Back Format
800   -----------------------------------------------------------------------------------------------
801   TDES0 |                         Timestamp Low                                                  |
802   -----------------------------------------------------------------------------------------------
803   TDES1 |                         Timestamp High                                                 |
804   -----------------------------------------------------------------------------------------------
805   TDES2 |                         Reserved[31:0]                                                 |
806   -----------------------------------------------------------------------------------------------
807   TDES3 | OWN(31) |    Status[30:28]  |       Reserved[27:18] |         Status[17:0]             |
808   -----------------------------------------------------------------------------------------------
809 */
810 
811 /**
812   * @brief  Bit definition of TDES0 WBF register
813   */
814 #define ETH_DMATXNDESCWBF_TTSL                    0xFFFFFFFFU  /*!< Buffer1 Address Pointer or TSO Header Address Pointer */
815 
816 /**
817   * @brief  Bit definition of TDES1 WBF register
818   */
819 #define ETH_DMATXNDESCWBF_TTSH                    0xFFFFFFFFU  /*!< Buffer2 Address Pointer */
820 
821 /**
822   * @brief  Bit definition of TDES3 WBF register
823   */
824 #define ETH_DMATXNDESCWBF_OWN                     0x80000000U  /*!< OWN bit: descriptor is owned by DMA engine */
825 #define ETH_DMATXNDESCWBF_CTXT                    0x40000000U  /*!< Context Type */
826 #define ETH_DMATXNDESCWBF_FD                      0x20000000U  /*!< First Descriptor */
827 #define ETH_DMATXNDESCWBF_LD                      0x10000000U  /*!< Last Descriptor */
828 #define ETH_DMATXNDESCWBF_TTSS                    0x00020000U  /*!< Tx Timestamp Status */
829 #define ETH_DMATXNDESCWBF_DP                      0x04000000U  /*!< Disable Padding */
830 #define ETH_DMATXNDESCWBF_TTSE                    0x02000000U  /*!< Transmit Timestamp Enable */
831 #define ETH_DMATXNDESCWBF_ES                      0x00008000U  /*!< Error summary: OR of the following bits: IHE || UF || ED || EC || LCO || PCE || NC || LCA || FF || JT */
832 #define ETH_DMATXNDESCWBF_JT                      0x00004000U  /*!< Jabber Timeout */
833 #define ETH_DMATXNDESCWBF_FF                      0x00002000U  /*!< Packet Flushed: DMA/MTL flushed the packet due to SW flush */
834 #define ETH_DMATXNDESCWBF_PCE                     0x00001000U  /*!< Payload Checksum Error */
835 #define ETH_DMATXNDESCWBF_LCA                     0x00000800U  /*!< Loss of Carrier: carrier lost during transmission */
836 #define ETH_DMATXNDESCWBF_NC                      0x00000400U  /*!< No Carrier: no carrier signal from the transceiver */
837 #define ETH_DMATXNDESCWBF_LCO                     0x00000200U  /*!< Late Collision: transmission aborted due to collision */
838 #define ETH_DMATXNDESCWBF_EC                      0x00000100U  /*!< Excessive Collision: transmission aborted after 16 collisions */
839 #define ETH_DMATXNDESCWBF_CC                      0x000000F0U  /*!< Collision Count */
840 #define ETH_DMATXNDESCWBF_ED                      0x00000008U  /*!< Excessive Deferral */
841 #define ETH_DMATXNDESCWBF_UF                      0x00000004U  /*!< Underflow Error: late data arrival from the memory */
842 #define ETH_DMATXNDESCWBF_DB                      0x00000002U  /*!< Deferred Bit */
843 #define ETH_DMATXNDESCWBF_IHE                     0x00000004U  /*!< IP Header Error */
844 
845 /*
846    DMA Tx Context Descriptor
847   -----------------------------------------------------------------------------------------------
848   TDES0 |                               Timestamp Low                                            |
849   -----------------------------------------------------------------------------------------------
850   TDES1 |                               Timestamp High                                           |
851   -----------------------------------------------------------------------------------------------
852   TDES2 |      Inner VLAN Tag[31:16]    | Reserved(15) |     Maximum Segment Size [14:0]         |
853   -----------------------------------------------------------------------------------------------
854   TDES3 | OWN(31) |                          Status[30:0]                                        |
855   -----------------------------------------------------------------------------------------------
856 */
857 
858 /**
859   * @brief  Bit definition of Tx context descriptor register 0
860   */
861 #define ETH_DMATXCDESC_TTSL                    0xFFFFFFFFU  /*!< Transmit Packet Timestamp Low */
862 
863 /**
864   * @brief  Bit definition of Tx context descriptor register 1
865   */
866 #define ETH_DMATXCDESC_TTSH                    0xFFFFFFFFU  /*!< Transmit Packet Timestamp High */
867 
868 /**
869   * @brief  Bit definition of Tx context descriptor register 2
870   */
871 #define ETH_DMATXCDESC_IVT                     0xFFFF0000U  /*!< Inner VLAN Tag */
872 #define ETH_DMATXCDESC_MSS                     0x00003FFFU  /*!< Maximum Segment Size */
873 
874 /**
875   * @brief  Bit definition of Tx context descriptor register 3
876   */
877 #define ETH_DMATXCDESC_OWN                     0x80000000U     /*!< OWN bit: descriptor is owned by DMA engine */
878 #define ETH_DMATXCDESC_CTXT                    0x40000000U     /*!< Context Type */
879 #define ETH_DMATXCDESC_OSTC                    0x08000000U     /*!< One-Step Timestamp Correction Enable */
880 #define ETH_DMATXCDESC_TCMSSV                  0x04000000U     /*!< One-Step Timestamp Correction Input or MSS Valid */
881 #define ETH_DMATXCDESC_CDE                     0x00800000U     /*!< Context Descriptor Error */
882 #define ETH_DMATXCDESC_IVTIR                   0x000C0000U     /*!< Inner VLAN Tag Insert or Replace Mask */
883 #define ETH_DMATXCDESC_IVTIR_DISABLE           0x00000000U     /*!< Do not add the inner VLAN tag. */
884 #define ETH_DMATXCDESC_IVTIR_REMOVE            0x00040000U     /*!< Remove the inner VLAN tag from the packets before transmission. */
885 #define ETH_DMATXCDESC_IVTIR_INSERT            0x00080000U     /*!< Insert the inner VLAN tag. */
886 #define ETH_DMATXCDESC_IVTIR_REPLACE           0x000C0000U     /*!< Replace the inner VLAN tag. */
887 #define ETH_DMATXCDESC_IVLTV                   0x00020000U     /*!< Inner VLAN Tag Valid */
888 #define ETH_DMATXCDESC_VLTV                    0x00010000U     /*!< VLAN Tag Valid */
889 #define ETH_DMATXCDESC_VT                      0x0000FFFFU     /*!< VLAN Tag */
890 
891 /**
892   * @}
893   */
894 
895 /** @defgroup ETH_DMA_Rx_Descriptor_Bit_Definition ETH DMA Rx Descriptor Bit Definition
896   * @{
897   */
898 
899 /*
900   DMA Rx Normal Descriptor read format
901   -----------------------------------------------------------------------------------------------------------
902   RDES0 |                                  Buffer1 or Header Address [31:0]                                 |
903   -----------------------------------------------------------------------------------------------------------
904   RDES1 |                                            Reserved                                               |
905   -----------------------------------------------------------------------------------------------------------
906   RDES2 |                                      Payload or Buffer2 Address[31:0]                             |
907   -----------------------------------------------------------------------------------------------------------
908   RDES3 | OWN(31) | IOC(30) | Reserved [29:26] | BUF2V(25) | BUF1V(24) |           Reserved [23:0]          |
909   -----------------------------------------------------------------------------------------------------------
910 */
911 
912 /**
913   * @brief  Bit definition of Rx normal descriptor register 0 read format
914   */
915 #define ETH_DMARXNDESCRF_BUF1AP           0xFFFFFFFFU  /*!< Header or Buffer 1 Address Pointer  */
916 
917 /**
918   * @brief  Bit definition of Rx normal descriptor register 2 read format
919   */
920 #define ETH_DMARXNDESCRF_BUF2AP           0xFFFFFFFFU  /*!< Buffer 2 Address Pointer  */
921 
922 /**
923   * @brief  Bit definition of Rx normal descriptor register 3 read format
924   */
925 #define ETH_DMARXNDESCRF_OWN              0x80000000U  /*!< OWN bit: descriptor is owned by DMA engine  */
926 #define ETH_DMARXNDESCRF_IOC              0x40000000U  /*!< Interrupt Enabled on Completion  */
927 #define ETH_DMARXNDESCRF_BUF2V            0x02000000U  /*!< Buffer 2 Address Valid */
928 #define ETH_DMARXNDESCRF_BUF1V            0x01000000U  /*!< Buffer 1 Address Valid */
929 
930 /*
931   DMA Rx Normal Descriptor write back format
932   ---------------------------------------------------------------------------------------------------------------------
933   RDES0 |                 Inner VLAN Tag[31:16]                 |                 Outer VLAN Tag[15:0]                |
934   ---------------------------------------------------------------------------------------------------------------------
935   RDES1 |       OAM code, or MAC Control Opcode [31:16]         |               Extended Status                       |
936   ---------------------------------------------------------------------------------------------------------------------
937   RDES2 |      MAC Filter Status[31:16]        | VF(15) | Reserved [14:12] | ARP Status [11:10] | Header Length [9:0] |
938   ---------------------------------------------------------------------------------------------------------------------
939   RDES3 | OWN(31) | CTXT(30) |  FD(29) | LD(28) |   Status[27:16]     | ES(15) |        Packet Length[14:0]           |
940   ---------------------------------------------------------------------------------------------------------------------
941 */
942 
943 /**
944   * @brief  Bit definition of Rx normal descriptor register 0 write back format
945   */
946 #define ETH_DMARXNDESCWBF_IVT             0xFFFF0000U  /*!< Inner VLAN Tag  */
947 #define ETH_DMARXNDESCWBF_OVT             0x0000FFFFU  /*!< Outer VLAN Tag  */
948 
949 /**
950   * @brief  Bit definition of Rx normal descriptor register 1 write back format
951   */
952 #define ETH_DMARXNDESCWBF_OPC             0xFFFF0000U  /*!< OAM Sub-Type Code, or MAC Control Packet opcode  */
953 #define ETH_DMARXNDESCWBF_TD              0x00008000U  /*!< Timestamp Dropped  */
954 #define ETH_DMARXNDESCWBF_TSA             0x00004000U  /*!< Timestamp Available  */
955 #define ETH_DMARXNDESCWBF_PV              0x00002000U  /*!< PTP Version  */
956 #define ETH_DMARXNDESCWBF_PFT             0x00001000U  /*!< PTP Packet Type  */
957 #define ETH_DMARXNDESCWBF_PMT_NO          0x00000000U  /*!< PTP Message Type: No PTP message received  */
958 #define ETH_DMARXNDESCWBF_PMT_SYNC        0x00000100U  /*!< PTP Message Type: SYNC (all clock types)  */
959 #define ETH_DMARXNDESCWBF_PMT_FUP         0x00000200U  /*!< PTP Message Type: Follow_Up (all clock types)  */
960 #define ETH_DMARXNDESCWBF_PMT_DREQ        0x00000300U  /*!< PTP Message Type: Delay_Req (all clock types)  */
961 #define ETH_DMARXNDESCWBF_PMT_DRESP       0x00000400U  /*!< PTP Message Type: Delay_Resp (all clock types)  */
962 #define ETH_DMARXNDESCWBF_PMT_PDREQ       0x00000500U  /*!< PTP Message Type: Pdelay_Req (in peer-to-peer transparent clock)  */
963 #define ETH_DMARXNDESCWBF_PMT_PDRESP      0x00000600U  /*!< PTP Message Type: Pdelay_Resp (in peer-to-peer transparent clock)  */
964 #define ETH_DMARXNDESCWBF_PMT_PDRESPFUP   0x00000700U  /*!< PTP Message Type: Pdelay_Resp_Follow_Up (in peer-to-peer transparent clock)  */
965 #define ETH_DMARXNDESCWBF_PMT_ANNOUNCE    0x00000800U  /*!< PTP Message Type: Announce  */
966 #define ETH_DMARXNDESCWBF_PMT_MANAG       0x00000900U  /*!< PTP Message Type: Management  */
967 #define ETH_DMARXNDESCWBF_PMT_SIGN        0x00000A00U  /*!< PTP Message Type: Signaling  */
968 #define ETH_DMARXNDESCWBF_PMT_RESERVED    0x00000F00U  /*!< PTP Message Type: PTP packet with Reserved message type  */
969 #define ETH_DMARXNDESCWBF_IPCE            0x00000080U  /*!< IP Payload Error */
970 #define ETH_DMARXNDESCWBF_IPCB            0x00000040U  /*!< IP Checksum Bypassed */
971 #define ETH_DMARXNDESCWBF_IPV6            0x00000020U  /*!< IPv6 header Present */
972 #define ETH_DMARXNDESCWBF_IPV4            0x00000010U  /*!< IPv4 header Present */
973 #define ETH_DMARXNDESCWBF_IPHE            0x00000008U  /*!< IP Header Error */
974 #define ETH_DMARXNDESCWBF_PT              0x00000003U  /*!< Payload Type mask */
975 #define ETH_DMARXNDESCWBF_PT_UNKNOWN      0x00000000U  /*!< Payload Type: Unknown type or IP/AV payload not processed */
976 #define ETH_DMARXNDESCWBF_PT_UDP          0x00000001U  /*!< Payload Type: UDP */
977 #define ETH_DMARXNDESCWBF_PT_TCP          0x00000002U  /*!< Payload Type: TCP  */
978 #define ETH_DMARXNDESCWBF_PT_ICMP         0x00000003U  /*!< Payload Type: ICMP */
979 
980 /**
981   * @brief  Bit definition of Rx normal descriptor register 2 write back format
982   */
983 #define ETH_DMARXNDESCWBF_L3L4FM          0x20000000U  /*!< L3 and L4 Filter Number Matched: if reset filter 0 is matched , if set filter 1 is matched */
984 #define ETH_DMARXNDESCWBF_L4FM            0x10000000U  /*!< Layer 4 Filter Match                  */
985 #define ETH_DMARXNDESCWBF_L3FM            0x08000000U  /*!< Layer 3 Filter Match                  */
986 #define ETH_DMARXNDESCWBF_MADRM           0x07F80000U  /*!< MAC Address Match or Hash Value       */
987 #define ETH_DMARXNDESCWBF_HF              0x00040000U  /*!< Hash Filter Status                    */
988 #define ETH_DMARXNDESCWBF_DAF             0x00020000U  /*!< Destination Address Filter Fail       */
989 #define ETH_DMARXNDESCWBF_SAF             0x00010000U  /*!< SA Address Filter Fail                */
990 #define ETH_DMARXNDESCWBF_VF              0x00008000U  /*!< VLAN Filter Status                    */
991 #define ETH_DMARXNDESCWBF_ARPNR           0x00000400U  /*!< ARP Reply Not Generated               */
992 
993 /**
994   * @brief  Bit definition of Rx normal descriptor register 3 write back format
995   */
996 #define ETH_DMARXNDESCWBF_OWN             0x80000000U  /*!< Own Bit */
997 #define ETH_DMARXNDESCWBF_CTXT            0x40000000U  /*!< Receive Context Descriptor */
998 #define ETH_DMARXNDESCWBF_FD              0x20000000U  /*!< First Descriptor */
999 #define ETH_DMARXNDESCWBF_LD              0x10000000U  /*!< Last Descriptor */
1000 #define ETH_DMARXNDESCWBF_RS2V            0x08000000U  /*!< Receive Status RDES2 Valid */
1001 #define ETH_DMARXNDESCWBF_RS1V            0x04000000U  /*!< Receive Status RDES1 Valid */
1002 #define ETH_DMARXNDESCWBF_RS0V            0x02000000U  /*!< Receive Status RDES0 Valid */
1003 #define ETH_DMARXNDESCWBF_CE              0x01000000U  /*!< CRC Error */
1004 #define ETH_DMARXNDESCWBF_GP              0x00800000U  /*!< Giant Packet */
1005 #define ETH_DMARXNDESCWBF_RWT             0x00400000U  /*!< Receive Watchdog Timeout */
1006 #define ETH_DMARXNDESCWBF_OE              0x00200000U  /*!< Overflow Error */
1007 #define ETH_DMARXNDESCWBF_RE              0x00100000U  /*!< Receive Error */
1008 #define ETH_DMARXNDESCWBF_DE              0x00080000U  /*!< Dribble Bit Error */
1009 #define ETH_DMARXNDESCWBF_LT              0x00070000U  /*!< Length/Type Field */
1010 #define ETH_DMARXNDESCWBF_LT_LP           0x00000000U  /*!< The packet is a length packet */
1011 #define ETH_DMARXNDESCWBF_LT_TP           0x00010000U  /*!< The packet is a type packet */
1012 #define ETH_DMARXNDESCWBF_LT_ARP          0x00030000U  /*!< The packet is a ARP Request packet type */
1013 #define ETH_DMARXNDESCWBF_LT_VLAN         0x00040000U  /*!< The packet is a type packet with VLAN Tag */
1014 #define ETH_DMARXNDESCWBF_LT_DVLAN        0x00050000U  /*!< The packet is a type packet with Double VLAN Tag */
1015 #define ETH_DMARXNDESCWBF_LT_MAC          0x00060000U  /*!< The packet is a MAC Control packet type */
1016 #define ETH_DMARXNDESCWBF_LT_OAM          0x00070000U  /*!< The packet is a OAM packet type */
1017 #define ETH_DMARXNDESCWBF_ES              0x00008000U  /*!< Error Summary */
1018 #define ETH_DMARXNDESCWBF_PL              0x00007FFFU  /*!< Packet Length */
1019 
1020 /*
1021   DMA Rx context Descriptor
1022   ---------------------------------------------------------------------------------------------------------------------
1023   RDES0 |                                     Timestamp Low[31:0]                                                     |
1024   ---------------------------------------------------------------------------------------------------------------------
1025   RDES1 |                                     Timestamp High[31:0]                                                    |
1026   ---------------------------------------------------------------------------------------------------------------------
1027   RDES2 |                                          Reserved                                                           |
1028   ---------------------------------------------------------------------------------------------------------------------
1029   RDES3 | OWN(31) | CTXT(30) |                                Reserved[29:0]                                          |
1030   ---------------------------------------------------------------------------------------------------------------------
1031 */
1032 
1033 /**
1034   * @brief  Bit definition of Rx context descriptor register 0
1035   */
1036 #define ETH_DMARXCDESC_RTSL                   0xFFFFFFFFU  /*!< Receive Packet Timestamp Low  */
1037 
1038 /**
1039   * @brief  Bit definition of Rx context descriptor register 1
1040   */
1041 #define ETH_DMARXCDESC_RTSH                   0xFFFFFFFFU  /*!< Receive Packet Timestamp High  */
1042 
1043 /**
1044   * @brief  Bit definition of Rx context descriptor register 3
1045   */
1046 #define ETH_DMARXCDESC_OWN                    0x80000000U  /*!< Own Bit  */
1047 #define ETH_DMARXCDESC_CTXT                   0x40000000U  /*!< Receive Context Descriptor  */
1048 
1049 /**
1050   * @}
1051   */
1052 
1053 /** @defgroup ETH_Frame_settings ETH frame settings
1054   * @{
1055   */
1056 #define ETH_MAX_PACKET_SIZE                   1528U    /*!< ETH_HEADER + 2*VLAN_TAG + MAX_ETH_PAYLOAD + ETH_CRC */
1057 #define ETH_HEADER                            14U    /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */
1058 #define ETH_CRC                               4U    /*!< Ethernet CRC */
1059 #define ETH_VLAN_TAG                          4U    /*!< optional 802.1q VLAN Tag */
1060 #define ETH_MIN_PAYLOAD                       46U    /*!< Minimum Ethernet payload size */
1061 #define ETH_MAX_PAYLOAD                       1500U    /*!< Maximum Ethernet payload size */
1062 #define ETH_JUMBO_FRAME_PAYLOAD               9000U    /*!< Jumbo frame payload size */
1063 /**
1064   * @}
1065   */
1066 
1067 /** @defgroup ETH_Error_Code ETH Error Code
1068   * @{
1069   */
1070 #define HAL_ETH_ERROR_NONE                    0x00000000U   /*!< No error            */
1071 #define HAL_ETH_ERROR_PARAM                   0x00000001U   /*!< Busy error          */
1072 #define HAL_ETH_ERROR_BUSY                    0x00000002U   /*!< Parameter error     */
1073 #define HAL_ETH_ERROR_TIMEOUT                 0x00000004U   /*!< Timeout error       */
1074 #define HAL_ETH_ERROR_MTL_Q0                  0x00000020U   /*!< MTL Q0 error  */
1075 #define HAL_ETH_ERROR_MTL_Q1                  0x00000040U   /*!< MTL Q1 error  */
1076 #define HAL_ETH_ERROR_MAC                     0x00000080U   /*!< MAC transfer error  */
1077 
1078 typedef enum
1079 {
1080   HAL_ETH_ERROR_DMA = 0x00000008U,
1081   HAL_ETH_ERROR_DMA_CH0 = 0x00000010U,
1082   HAL_ETH_ERROR_DMA_CH1 = 0x00000020U
1083 } ETH_DMAChannelErrorTypeDef;
1084 
1085 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
1086 #define HAL_ETH_ERROR_INVALID_CALLBACK        0x00000020U    /*!< Invalid Callback error  */
1087 #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
1088 /**
1089   * @}
1090   */
1091 
1092 /** @defgroup ETH_Tx_Packet_Attributes ETH Tx Packet Attributes
1093   * @{
1094   */
1095 #define ETH_TX_PACKETS_FEATURES_CSUM          0x00000001U
1096 #define ETH_TX_PACKETS_FEATURES_SAIC          0x00000002U
1097 #define ETH_TX_PACKETS_FEATURES_VLANTAG       0x00000004U
1098 #define ETH_TX_PACKETS_FEATURES_INNERVLANTAG  0x00000008U
1099 #define ETH_TX_PACKETS_FEATURES_TSO           0x00000010U
1100 #define ETH_TX_PACKETS_FEATURES_CRCPAD        0x00000020U
1101 /**
1102   * @}
1103   */
1104 
1105 /** @defgroup ETH_Tx_Packet_Source_Addr_Control ETH Tx Packet Source Addr Control
1106   * @{
1107   */
1108 #define ETH_SRC_ADDR_CONTROL_DISABLE          ETH_DMATXNDESCRF_SAIC_DISABLE
1109 #define ETH_SRC_ADDR_INSERT                   ETH_DMATXNDESCRF_SAIC_INSERT
1110 #define ETH_SRC_ADDR_REPLACE                  ETH_DMATXNDESCRF_SAIC_REPLACE
1111 /**
1112   * @}
1113   */
1114 
1115 /** @defgroup ETH_Tx_Packet_CRC_Pad_Control ETH Tx Packet CRC Pad Control
1116   * @{
1117   */
1118 #define ETH_CRC_PAD_DISABLE      ETH_DMATXNDESCRF_CPC_DISABLE
1119 #define ETH_CRC_PAD_INSERT       ETH_DMATXNDESCRF_CPC_CRCPAD_INSERT
1120 #define ETH_CRC_INSERT           ETH_DMATXNDESCRF_CPC_CRC_INSERT
1121 #define ETH_CRC_REPLACE          ETH_DMATXNDESCRF_CPC_CRC_REPLACE
1122 /**
1123   * @}
1124   */
1125 
1126 /** @defgroup ETH_Tx_Packet_Checksum_Control ETH Tx Packet Checksum Control
1127   * @{
1128   */
1129 #define ETH_CHECKSUM_DISABLE                         ETH_DMATXNDESCRF_CIC_DISABLE
1130 #define ETH_CHECKSUM_IPHDR_INSERT                    ETH_DMATXNDESCRF_CIC_IPHDR_INSERT
1131 #define ETH_CHECKSUM_IPHDR_PAYLOAD_INSERT            ETH_DMATXNDESCRF_CIC_IPHDR_PAYLOAD_INSERT
1132 #define ETH_CHECKSUM_IPHDR_PAYLOAD_INSERT_PHDR_CALC  ETH_DMATXNDESCRF_CIC_IPHDR_PAYLOAD_INSERT_PHDR_CALC
1133 /**
1134   * @}
1135   */
1136 
1137 /** @defgroup ETH_Tx_Packet_VLAN_Control ETH Tx Packet VLAN Control
1138   * @{
1139   */
1140 #define ETH_VLAN_DISABLE  ETH_DMATXNDESCRF_VTIR_DISABLE
1141 #define ETH_VLAN_REMOVE   ETH_DMATXNDESCRF_VTIR_REMOVE
1142 #define ETH_VLAN_INSERT   ETH_DMATXNDESCRF_VTIR_INSERT
1143 #define ETH_VLAN_REPLACE  ETH_DMATXNDESCRF_VTIR_REPLACE
1144 /**
1145   * @}
1146   */
1147 
1148 /** @defgroup ETH_Tx_Packet_Inner_VLAN_Control ETH Tx Packet Inner VLAN Control
1149   * @{
1150   */
1151 #define ETH_INNER_VLAN_DISABLE  ETH_DMATXCDESC_IVTIR_DISABLE
1152 #define ETH_INNER_VLAN_REMOVE   ETH_DMATXCDESC_IVTIR_REMOVE
1153 #define ETH_INNER_VLAN_INSERT   ETH_DMATXCDESC_IVTIR_INSERT
1154 #define ETH_INNER_VLAN_REPLACE  ETH_DMATXCDESC_IVTIR_REPLACE
1155 /**
1156   * @}
1157   */
1158 
1159 /** @defgroup ETH_Rx_Checksum_Status ETH Rx Checksum Status
1160   * @{
1161   */
1162 #define ETH_CHECKSUM_BYPASSED           ETH_DMARXNDESCWBF_IPCB
1163 #define ETH_CHECKSUM_IP_HEADER_ERROR    ETH_DMARXNDESCWBF_IPHE
1164 #define ETH_CHECKSUM_IP_PAYLOAD_ERROR   ETH_DMARXNDESCWBF_IPCE
1165 /**
1166   * @}
1167   */
1168 
1169 /** @defgroup ETH_Rx_IP_Header_Type ETH Rx IP Header Type
1170   * @{
1171   */
1172 #define ETH_IP_HEADER_IPV4   ETH_DMARXNDESCWBF_IPV4
1173 #define ETH_IP_HEADER_IPV6   ETH_DMARXNDESCWBF_IPV6
1174 /**
1175   * @}
1176   */
1177 
1178 /** @defgroup ETH_Rx_Payload_Type ETH Rx Payload Type
1179   * @{
1180   */
1181 #define ETH_IP_PAYLOAD_UNKNOWN   ETH_DMARXNDESCWBF_PT_UNKNOWN
1182 #define ETH_IP_PAYLOAD_UDP       ETH_DMARXNDESCWBF_PT_UDP
1183 #define ETH_IP_PAYLOAD_TCP       ETH_DMARXNDESCWBF_PT_TCP
1184 #define ETH_IP_PAYLOAD_ICMPN     ETH_DMARXNDESCWBF_PT_ICMP
1185 /**
1186   * @}
1187   */
1188 
1189 /** @defgroup ETH_Rx_MAC_Filter_Status ETH Rx MAC Filter Status
1190   * @{
1191   */
1192 #define ETH_HASH_FILTER_PASS        ETH_DMARXNDESCWBF_HF
1193 #define ETH_VLAN_FILTER_PASS        ETH_DMARXNDESCWBF_VF
1194 #define ETH_DEST_ADDRESS_FAIL       ETH_DMARXNDESCWBF_DAF
1195 #define ETH_SOURCE_ADDRESS_FAIL     ETH_DMARXNDESCWBF_SAF
1196 /**
1197   * @}
1198   */
1199 /** @defgroup ETH_Rx_L3_Filter_Status ETH Rx L3 Filter Status
1200   * @{
1201   */
1202 #define ETH_L3_FILTER0_MATCH        ETH_DMARXNDESCWBF_L3FM
1203 #define ETH_L3_FILTER1_MATCH        (ETH_DMARXNDESCWBF_L3FM | ETH_DMARXNDESCWBF_L3L4FM)
1204 /**
1205   * @}
1206   */
1207 
1208 /** @defgroup ETH_Rx_L4_Filter_Status ETH Rx L4 Filter Status
1209   * @{
1210   */
1211 #define ETH_L4_FILTER0_MATCH        ETH_DMARXNDESCWBF_L4FM
1212 #define ETH_L4_FILTER1_MATCH        (ETH_DMARXNDESCWBF_L4FM | ETH_DMARXNDESCWBF_L3L4FM)
1213 /**
1214   * @}
1215   */
1216 
1217 /** @defgroup ETH_Rx_Error_Code ETH Rx Error Code
1218   * @{
1219   */
1220 #define ETH_DRIBBLE_BIT_ERROR   ETH_DMARXNDESCWBF_DE
1221 #define ETH_RECEIVE_ERROR       ETH_DMARXNDESCWBF_RE
1222 #define ETH_RECEIVE_OVERFLOW    ETH_DMARXNDESCWBF_OE
1223 #define ETH_WATCHDOG_TIMEOUT    ETH_DMARXNDESCWBF_RWT
1224 #define ETH_GIANT_PACKET        ETH_DMARXNDESCWBF_GP
1225 #define ETH_CRC_ERROR           ETH_DMARXNDESCWBF_CE
1226 /**
1227   * @}
1228   */
1229 
1230 /** @defgroup ETH_DMA_Arbitration ETH DMA Arbitration
1231   * @{
1232   */
1233 #define ETH_DMAARBITRATION_TX        (ETH_DMAMR_TXPR)
1234 /**
1235   * @}
1236   */
1237 
1238 /** @defgroup ETH_DMA_Transmit_Arbitration_Algorithm ETH DMA Transmit Arbitration Algorithm
1239   * @{
1240   */
1241 #define ETH_DMATXARBITRATION_FIXED_PRIO      (ETH_DMAMR_TAA_FP)
1242 #define ETH_DMATXARBITRATION_WEIGHTED_SP     (ETH_DMAMR_TAA_WSP)
1243 #define ETH_DMATXARBITRATION_WEIGHTED_RR     (ETH_DMAMR_TAA_WRR)
1244 /**
1245   * @}
1246   */
1247 
1248 /** @defgroup ETH_Burst_Mode ETH Burst Mode
1249   * @{
1250   */
1251 #define ETH_BURSTLENGTH_FIXED           ETH_DMASBMR_FB
1252 #define ETH_BURSTLENGTH_UNSPECIFIED     0x00000000U
1253 /**
1254   * @}
1255   */
1256 
1257 /** @defgroup ETH_BLEN_Size ETH Blen size
1258   * @{
1259   */
1260 #define ETH_BLEN_MAX_SIZE_256             (ETH_DMASBMR_BLEN256 | ETH_BLEN_MAX_SIZE_128)
1261 #define ETH_BLEN_MAX_SIZE_128             (ETH_DMASBMR_BLEN128 | ETH_BLEN_MAX_SIZE_64)
1262 #define ETH_BLEN_MAX_SIZE_64              (ETH_DMASBMR_BLEN64 | ETH_BLEN_MAX_SIZE_32)
1263 #define ETH_BLEN_MAX_SIZE_32              (ETH_DMASBMR_BLEN32 | ETH_BLEN_MAX_SIZE_16)
1264 #define ETH_BLEN_MAX_SIZE_16              (ETH_DMASBMR_BLEN16 | ETH_BLEN_MAX_SIZE_8)
1265 #define ETH_BLEN_MAX_SIZE_8               (ETH_DMASBMR_BLEN8 | ETH_BLEN_MAX_SIZE_4)
1266 #define ETH_BLEN_MAX_SIZE_4               ETH_DMASBMR_BLEN4
1267 
1268 /**
1269   * @}
1270   */
1271 
1272 /** @defgroup ETH_RX_OSR_LIMIT ETH Rx maximum read outstanding request limit
1273   * @{
1274   */
1275 #define ETH_RX_OSR_LIMIT_1 ETH_DMASBMR_RD_OSR_LMT_0
1276 #define ETH_RX_OSR_LIMIT_2 ETH_DMASBMR_RD_OSR_LMT_1
1277 #define ETH_RX_OSR_LIMIT_3 (ETH_DMASBMR_RD_OSR_LMT_1 | ETH_DMASBMR_RD_OSR_LMT_0)
1278 
1279 /**
1280   * @}
1281   */
1282 
1283 /** @defgroup ETH_TX_OSR_LIMIT ETH Tx maximum write outstanding request limit
1284   * @{
1285   */
1286 #define ETH_TX_OSR_LIMIT_1 ETH_DMASBMR_WR_OSR_LMT_0
1287 #define ETH_TX_OSR_LIMIT_2 ETH_DMASBMR_WR_OSR_LMT_1
1288 #define ETH_TX_OSR_LIMIT_3 (ETH_DMASBMR_WR_OSR_LMT_1 | ETH_DMASBMR_WR_OSR_LMT_0)
1289 /**
1290   * @}
1291   */
1292 
1293 /** @defgroup ETH_Tx_DMA_Burst_Length ETH Tx DMA Burst Length
1294   * @{
1295   */
1296 #define ETH_TXDMABURSTLENGTH_1BEAT          ETH_DMACxTXCR_TXPBL_1PBL
1297 #define ETH_TXDMABURSTLENGTH_2BEAT          ETH_DMACxTXCR_TXPBL_2PBL
1298 #define ETH_TXDMABURSTLENGTH_4BEAT          ETH_DMACxTXCR_TXPBL_4PBL
1299 #define ETH_TXDMABURSTLENGTH_8BEAT          ETH_DMACxTXCR_TXPBL_8PBL
1300 #define ETH_TXDMABURSTLENGTH_16BEAT         ETH_DMACxTXCR_TXPBL_16PBL
1301 #define ETH_TXDMABURSTLENGTH_32BEAT         ETH_DMACxTXCR_TXPBL_32PBL
1302 /**
1303   * @}
1304   */
1305 
1306 /** @defgroup ETH_Tx_DMA_Channel_Weight ETH Tx DMA Channel Weight
1307   * @{
1308   */
1309 #define ETH_TXCHANNELWEIGHT_1               ETH_DMACxTXCR_TCW_1
1310 #define ETH_TXCHANNELWEIGHT_2               ETH_DMACxTXCR_TCW_2
1311 #define ETH_TXCHANNELWEIGHT_3               ETH_DMACxTXCR_TCW_3
1312 #define ETH_TXCHANNELWEIGHT_4               ETH_DMACxTXCR_TCW_4
1313 #define ETH_TXCHANNELWEIGHT_5               ETH_DMACxTXCR_TCW_5
1314 #define ETH_TXCHANNELWEIGHT_6               ETH_DMACxTXCR_TCW_6
1315 #define ETH_TXCHANNELWEIGHT_7               ETH_DMACxTXCR_TCW_7
1316 /**
1317   * @}
1318   */
1319 
1320 /** @defgroup ETH_Rx_DMA_Burst_Length ETH Rx DMA Burst Length
1321   * @{
1322   */
1323 #define ETH_RXDMABURSTLENGTH_1BEAT          ETH_DMACxRXCR_RXPBL_1PBL
1324 #define ETH_RXDMABURSTLENGTH_2BEAT          ETH_DMACxRXCR_RXPBL_2PBL
1325 #define ETH_RXDMABURSTLENGTH_4BEAT          ETH_DMACxRXCR_RXPBL_4PBL
1326 #define ETH_RXDMABURSTLENGTH_8BEAT          ETH_DMACxRXCR_RXPBL_8PBL
1327 #define ETH_RXDMABURSTLENGTH_16BEAT         ETH_DMACxRXCR_RXPBL_16PBL
1328 #define ETH_RXDMABURSTLENGTH_32BEAT         ETH_DMACxRXCR_RXPBL_32PBL
1329 /**
1330   * @}
1331   */
1332 
1333 /** @defgroup ETH_DMA_Descriptor_Skip_Length ETH DMA Descriptor Skip Length
1334   * @{
1335   */
1336 #define ETH_DMA_DESC_SKIP_LENGTH_0       ETH_DMACxCR_DSL_0BIT
1337 #define ETH_DMA_DESC_SKIP_LENGTH_32      ETH_DMACxCR_DSL_32BIT
1338 #define ETH_DMA_DESC_SKIP_LENGTH_64      ETH_DMACxCR_DSL_64BIT
1339 #define ETH_DMA_DESC_SKIP_LENGTH_128     ETH_DMACxCR_DSL_128BIT
1340 
1341 /**
1342   * @}
1343   */
1344 
1345 /** @defgroup ETH_Queue_Operation_Mode ETH Queue Operation Mode
1346   * @{
1347   */
1348 #define ETH_TX_QUEUE_ENABLED     ETH_MTLTXQxOMR_TXQEN_EN
1349 #define ETH_TX_QUEUE_DISABLED    ETH_MTLTXQxOMR_TXQEN_NOT
1350 #define ETH_TX_QUEUE_AV_ENABLED  ETH_MTLTXQxOMR_TXQEN_AVMODE
1351 
1352 #define ETH_RX_QUEUE0_ENABLED     ETH_MACRXQC0R_RXQ0EN_GT
1353 #define ETH_RX_QUEUE0_DISABLED    ETH_MACRXQC0R_RXQ0EN_NOT
1354 #define ETH_RX_QUEUE0_AV_ENABLED  ETH_MACRXQC0R_RXQ0EN_AV
1355 
1356 #define ETH_RX_QUEUE1_ENABLED     ETH_MACRXQC0R_RXQ1EN_GT
1357 #define ETH_RX_QUEUE1_DISABLED    ETH_MACRXQC0R_RXQ1EN_NOT
1358 #define ETH_RX_QUEUE1_AV_ENABLED  ETH_MACRXQC0R_RXQ1EN_AV
1359 /**
1360   * @}
1361   */
1362 
1363 /** @defgroup ETH_Transmit_Queue_Size ETH Transmit Queue Size
1364   * @{
1365   */
1366 #define ETH_TRANSMIT_QUEUE_SIZE_256      0x00000000U
1367 #define ETH_TRANSMIT_QUEUE_SIZE_2048     (ETH_MTLTXQxOMR_TQS_0 | ETH_MTLTXQxOMR_TQS_1 | ETH_MTLTXQxOMR_TQS_2)
1368 #define ETH_TRANSMIT_QUEUE_SIZE_4096     (ETH_TRANSMIT_QUEUE_SIZE_2048 | ETH_MTLTXQxOMR_TQS_3)
1369 
1370 /**
1371   * @}
1372   */
1373 
1374 /** @defgroup ETH_Receive_Queue_Size ETH Receive Queue Size
1375   * @{
1376   */
1377 #define ETH_RECEIVE_QUEUE_SIZE_256      0x00000000U
1378 #define ETH_RECEIVE_QUEUE_SIZE_2048     (ETH_MTLRXQxOMR_RQS_0 | ETH_MTLRXQxOMR_RQS_1 | ETH_MTLRXQxOMR_RQS_2)
1379 #define ETH_RECEIVE_QUEUE_SIZE_4096     (ETH_RECEIVE_QUEUE_SIZE_2048 | ETH_MTLRXQxOMR_RQS_3)
1380 
1381 /**
1382   * @}
1383   */
1384 
1385 /** @defgroup ETH_DMA_Interrupts ETH DMA Interrupts
1386   * @{
1387   */
1388 #define ETH_DMA_NORMAL_IT                 ETH_DMACxIER_NIE
1389 #define ETH_DMA_ABNORMAL_IT               ETH_DMACxIER_AIE
1390 #define ETH_DMA_CONTEXT_DESC_ERROR_IT     ETH_DMACxIER_CDEE
1391 #define ETH_DMA_FATAL_BUS_ERROR_IT        ETH_DMACxIER_FBEE
1392 #define ETH_DMA_EARLY_RX_IT               ETH_DMACxIER_ERIE
1393 #define ETH_DMA_EARLY_TX_IT               ETH_DMACxIER_ETIE
1394 #define ETH_DMA_RX_WATCHDOG_TIMEOUT_IT    ETH_DMACxIER_RWTE
1395 #define ETH_DMA_RX_PROCESS_STOPPED_IT     ETH_DMACxIER_RSE
1396 #define ETH_DMA_RX_BUFFER_UNAVAILABLE_IT  ETH_DMACxIER_RBUE
1397 #define ETH_DMA_RX_IT                     ETH_DMACxIER_RIE
1398 #define ETH_DMA_TX_BUFFER_UNAVAILABLE_IT  ETH_DMACxIER_TBUE
1399 #define ETH_DMA_TX_PROCESS_STOPPED_IT     ETH_DMACxIER_TXSE
1400 #define ETH_DMA_TX_IT                     ETH_DMACxIER_TIE
1401 /**
1402   * @}
1403   */
1404 
1405 /** @defgroup ETH_DMA_Status_Flags ETH DMA Status Flags
1406   * @{
1407   */
1408 #define ETH_DMA_RX_NO_ERROR_FLAG                 0x00000000U
1409 #define ETH_DMA_TX_NO_ERROR_FLAG                 0x00000000U
1410 #define ETH_DMA_CONTEXT_DESC_ERROR_FLAG          ETH_DMACxSR_CDE
1411 #define ETH_DMA_FATAL_BUS_ERROR_FLAG             ETH_DMACxSR_FBE
1412 #define ETH_DMA_EARLY_TX_IT_FLAG                 ETH_DMACxSR_ERI
1413 #define ETH_DMA_RX_WATCHDOG_TIMEOUT_FLAG         ETH_DMACxSR_RWT
1414 #define ETH_DMA_RX_PROCESS_STOPPED_FLAG          ETH_DMACxSR_RPS
1415 #define ETH_DMA_RX_BUFFER_UNAVAILABLE_FLAG       ETH_DMACxSR_RBU
1416 #define ETH_DMA_TX_PROCESS_STOPPED_FLAG          ETH_DMACxSR_TPS
1417 /**
1418   * @}
1419   */
1420 
1421 /** @defgroup ETH_Transmit_Mode ETH Transmit Mode
1422   * @{
1423   */
1424 #define ETH_TRANSMITSTOREFORWARD       ETH_MTLTXQxOMR_TSF
1425 #define ETH_TRANSMITTHRESHOLD_32       ETH_MTLTXQxOMR_TTC_32BITS
1426 #define ETH_TRANSMITTHRESHOLD_64       ETH_MTLTXQxOMR_TTC_64BITS
1427 #define ETH_TRANSMITTHRESHOLD_96       ETH_MTLTXQxOMR_TTC_96BITS
1428 #define ETH_TRANSMITTHRESHOLD_128      ETH_MTLTXQxOMR_TTC_128BITS
1429 #define ETH_TRANSMITTHRESHOLD_192      ETH_MTLTXQxOMR_TTC_192BITS
1430 #define ETH_TRANSMITTHRESHOLD_256      ETH_MTLTXQxOMR_TTC_256BITS
1431 #define ETH_TRANSMITTHRESHOLD_384      ETH_MTLTXQxOMR_TTC_384BITS
1432 #define ETH_TRANSMITTHRESHOLD_512      ETH_MTLTXQxOMR_TTC_512BITS
1433 /**
1434   * @}
1435   */
1436 
1437 /** @defgroup ETH_Receive_Mode ETH Receive Mode
1438   * @{
1439   */
1440 #define ETH_RECEIVESTOREFORWARD        ETH_MTLRXQxOMR_RSF
1441 #define ETH_RECEIVETHRESHOLD8_64       ETH_MTLRXQxOMR_RTC_64BITS
1442 #define ETH_RECEIVETHRESHOLD8_32       ETH_MTLRXQxOMR_RTC_32BITS
1443 #define ETH_RECEIVETHRESHOLD8_96       ETH_MTLRXQxOMR_RTC_96BITS
1444 #define ETH_RECEIVETHRESHOLD8_128      ETH_MTLRXQxOMR_RTC_128BITS
1445 /**
1446   * @}
1447   */
1448 
1449 /** @defgroup ETH_Queue_Mapped_DMA_Channel ETH Queue Mapped DMA Channel
1450   * @{
1451   */
1452 #define ETH_MTL_Q0_MAPPED_TO_DMA_CH0   ETH_MTLRXQDMAMR_Q0MDMACH_DMACH0
1453 #define ETH_MTL_Q0_MAPPED_TO_DMA_CH1   ETH_MTLRXQDMAMR_Q0MDMACH_DMACH1
1454 #define ETH_MTL_Q1_MAPPED_TO_DMA_CH0   ETH_MTLRXQDMAMR_Q1MDMACH_DMACH0
1455 #define ETH_MTL_Q1_MAPPED_TO_DMA_CH1   ETH_MTLRXQDMAMR_Q1MDMACH_DMACH1
1456 /**
1457   * @}
1458   */
1459 
1460 /** @defgroup ETH_Queue1_AV_Algo ETH Queue1 AV Algo
1461   * @{
1462   */
1463 #define ETH_TX_QUEUE_AV_ALGO_CBS    ETH_MTLTXQ1ECR_AVALG
1464 #define ETH_TX_QUEUE_AV_ALGO_SP     0x00000000U
1465 /**
1466   * @}
1467   */
1468 
1469 /** @defgroup ETH_RX_Queue ETH RX Queue
1470   * @{
1471   */
1472 #define ETH_RX_QUEUE0              0x00000000U
1473 #define ETH_RX_QUEUE1              0x00000001U
1474 /**
1475   * @}
1476   */
1477 
1478 /** @defgroup ETH_MTL_Interrupts ETH MTL Interrupts
1479   * @{
1480   */
1481 #define ETH_RX_QUEUE_OVERFLOW_IT       ETH_MTLQxICSR_RXOIE
1482 #define ETH_AVERAGE_BITS_PER_SLOT_IT   ETH_MTLQxICSR_ABPSIE
1483 #define ETH_TX_QUEUE_UNDERFLOW_IT      ETH_MTLQxICSR_TXUIE
1484 /**
1485   * @}
1486   */
1487 
1488 /** @defgroup ETH_Pause_Low_Threshold  ETH Pause Low Threshold
1489   * @{
1490   */
1491 #define ETH_PAUSELOWTHRESHOLD_MINUS_4        ETH_MACQ0TXFCR_PLT_MINUS4
1492 #define ETH_PAUSELOWTHRESHOLD_MINUS_28       ETH_MACQ0TXFCR_PLT_MINUS28
1493 #define ETH_PAUSELOWTHRESHOLD_MINUS_36       ETH_MACQ0TXFCR_PLT_MINUS36
1494 #define ETH_PAUSELOWTHRESHOLD_MINUS_144      ETH_MACQ0TXFCR_PLT_MINUS144
1495 #define ETH_PAUSELOWTHRESHOLD_MINUS_256      ETH_MACQ0TXFCR_PLT_MINUS256
1496 #define ETH_PAUSELOWTHRESHOLD_MINUS_512      ETH_MACQ0TXFCR_PLT_MINUS512
1497 /**
1498   * @}
1499   */
1500 
1501 /** @defgroup ETH_Watchdog_Timeout ETH Watchdog Timeout
1502   * @{
1503   */
1504 #define ETH_WATCHDOGTIMEOUT_2KB      ETH_MACWTR_WTO_2KB
1505 #define ETH_WATCHDOGTIMEOUT_3KB      ETH_MACWTR_WTO_3KB
1506 #define ETH_WATCHDOGTIMEOUT_4KB      ETH_MACWTR_WTO_4KB
1507 #define ETH_WATCHDOGTIMEOUT_5KB      ETH_MACWTR_WTO_5KB
1508 #define ETH_WATCHDOGTIMEOUT_6KB      ETH_MACWTR_WTO_6KB
1509 #define ETH_WATCHDOGTIMEOUT_7KB      ETH_MACWTR_WTO_7KB
1510 #define ETH_WATCHDOGTIMEOUT_8KB      ETH_MACWTR_WTO_8KB
1511 #define ETH_WATCHDOGTIMEOUT_9KB      ETH_MACWTR_WTO_9KB
1512 #define ETH_WATCHDOGTIMEOUT_10KB     ETH_MACWTR_WTO_10KB
1513 #define ETH_WATCHDOGTIMEOUT_11KB     ETH_MACWTR_WTO_12KB
1514 #define ETH_WATCHDOGTIMEOUT_12KB     ETH_MACWTR_WTO_12KB
1515 #define ETH_WATCHDOGTIMEOUT_13KB     ETH_MACWTR_WTO_13KB
1516 #define ETH_WATCHDOGTIMEOUT_14KB     ETH_MACWTR_WTO_14KB
1517 #define ETH_WATCHDOGTIMEOUT_15KB     ETH_MACWTR_WTO_15KB
1518 #define ETH_WATCHDOGTIMEOUT_16KB     ETH_MACWTR_WTO_16KB
1519 /**
1520   * @}
1521   */
1522 
1523 /** @defgroup ETH_Inter_Packet_Gap ETH Inter Packet Gap
1524   * @{
1525   */
1526 #define ETH_INTERPACKETGAP_96BIT   ETH_MACCR_IPG_96BIT
1527 #define ETH_INTERPACKETGAP_88BIT   ETH_MACCR_IPG_88BIT
1528 #define ETH_INTERPACKETGAP_80BIT   ETH_MACCR_IPG_80BIT
1529 #define ETH_INTERPACKETGAP_72BIT   ETH_MACCR_IPG_72BIT
1530 #define ETH_INTERPACKETGAP_64BIT   ETH_MACCR_IPG_64BIT
1531 #define ETH_INTERPACKETGAP_56BIT   ETH_MACCR_IPG_56BIT
1532 #define ETH_INTERPACKETGAP_48BIT   ETH_MACCR_IPG_48BIT
1533 #define ETH_INTERPACKETGAP_40BIT   ETH_MACCR_IPG_40BIT
1534 /**
1535   * @}
1536   */
1537 
1538 /** @defgroup ETH_Speed  ETH Speed
1539   * @{
1540   */
1541 #define ETH_SPEED_10M        0x00000000U
1542 #define ETH_SPEED_100M       ETH_MACCR_FES
1543 #define ETH_SPEED_1000M      0x00000000U
1544 /**
1545   * @}
1546   */
1547 
1548 /** @defgroup ETH_Duplex_Mode ETH Duplex Mode
1549   * @{
1550   */
1551 #define ETH_FULLDUPLEX_MODE       ETH_MACCR_DM
1552 #define ETH_HALFDUPLEX_MODE       0x00000000U
1553 /**
1554   * @}
1555   */
1556 
1557 /** @defgroup ETH_Back_Off_Limit ETH Back Off Limit
1558   * @{
1559   */
1560 #define ETH_BACKOFFLIMIT_10  ETH_MACCR_BL_10
1561 #define ETH_BACKOFFLIMIT_8   ETH_MACCR_BL_8
1562 #define ETH_BACKOFFLIMIT_4   ETH_MACCR_BL_4
1563 #define ETH_BACKOFFLIMIT_1   ETH_MACCR_BL_1
1564 /**
1565   * @}
1566   */
1567 
1568 /** @defgroup ETH_Preamble_Length ETH Preamble Length
1569   * @{
1570   */
1571 #define ETH_PREAMBLELENGTH_7      ETH_MACCR_PRELEN_7
1572 #define ETH_PREAMBLELENGTH_5      ETH_MACCR_PRELEN_5
1573 #define ETH_PREAMBLELENGTH_3      ETH_MACCR_PRELEN_3
1574 /**
1575   * @}
1576   */
1577 
1578 /** @defgroup ETH_Source_Addr_Control ETH Source Addr Control
1579   * @{
1580   */
1581 #define ETH_SOURCEADDRESS_DISABLE           0x00000000U
1582 #define ETH_SOURCEADDRESS_INSERT_ADDR0      ETH_MACCR_SARC_1
1583 #define ETH_SOURCEADDRESS_INSERT_ADDR1      (ETH_MACCR_SARC_2 | ETH_MACCR_SARC_1)
1584 #define ETH_SOURCEADDRESS_REPLACE_ADDR0     (ETH_MACCR_SARC_1 | ETH_MACCR_SARC_0)
1585 #define ETH_SOURCEADDRESS_REPLACE_ADDR1     (ETH_MACCR_SARC_2 | ETH_MACCR_SARC_1 | ETH_MACCR_SARC_0)
1586 /**
1587   * @}
1588   */
1589 
1590 /** @defgroup ETH_Control_Packets_Filter ETH Control Packets Filter
1591   * @{
1592   */
1593 #define ETH_CTRLPACKETS_BLOCK_ALL                      ETH_MACPFR_PCF_BLOCKALL
1594 #define ETH_CTRLPACKETS_FORWARD_ALL_EXCEPT_PA          ETH_MACPFR_PCF_FORWARDALLEXCEPTPA
1595 #define ETH_CTRLPACKETS_FORWARD_ALL                    ETH_MACPFR_PCF_FORWARDALL
1596 #define ETH_CTRLPACKETS_FORWARD_PASSED_ADDR_FILTER     ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER
1597 /**
1598   * @}
1599   */
1600 
1601 /** @defgroup ETH_VLAN_Tag_Comparison ETH VLAN Tag Comparison
1602   * @{
1603   */
1604 #define ETH_VLANTAGCOMPARISON_16BIT          0x00000000U
1605 #define ETH_VLANTAGCOMPARISON_12BIT          ETH_MACVTCR_ETV
1606 /**
1607   * @}
1608   */
1609 
1610 /** @defgroup ETH_MAC_addresses ETH MAC addresses
1611   * @{
1612   */
1613 #define ETH_MAC_ADDRESS0     0x00000000U
1614 #define ETH_MAC_ADDRESS1     0x00000008U
1615 #define ETH_MAC_ADDRESS2     0x00000010U
1616 #define ETH_MAC_ADDRESS3     0x00000018U
1617 /**
1618   * @}
1619   */
1620 
1621 /** @defgroup ETH_MAC_Interrupts ETH MAC Interrupts
1622   * @{
1623   */
1624 #define ETH_MAC_RX_STATUS_IT     ETH_MACIER_RXSTSIE
1625 #define ETH_MAC_TX_STATUS_IT     ETH_MACIER_TXSTSIE
1626 #define ETH_MAC_TIMESTAMP_IT     ETH_MACIER_TSIE
1627 #define ETH_MAC_LPI_IT           ETH_MACIER_LPIIE
1628 #define ETH_MAC_PMT_IT           ETH_MACIER_PMTIE
1629 #define ETH_MAC_PHY_IT           ETH_MACIER_PHYIE
1630 /**
1631   * @}
1632   */
1633 
1634 /** @defgroup ETH_MAC_Wake_Up_Event ETH MAC Wake Up Event
1635   * @{
1636   */
1637 #define ETH_WAKEUP_PACKET_RECIEVED    ETH_MACPCSR_RWKPRCVD
1638 #define ETH_MAGIC_PACKET_RECIEVED     ETH_MACPCSR_MGKPRCVD
1639 /**
1640   * @}
1641   */
1642 
1643 /** @defgroup ETH_MAC_Rx_Tx_Status ETH MAC Rx Tx Status
1644   * @{
1645   */
1646 #define ETH_RECEIVE_WATCHDOG_TIMEOUT        ETH_MACRXTXSR_RWT
1647 #define ETH_EXECESSIVE_COLLISIONS           ETH_MACRXTXSR_EXCOL
1648 #define ETH_LATE_COLLISIONS                 ETH_MACRXTXSR_LCOL
1649 #define ETH_EXECESSIVE_DEFERRAL             ETH_MACRXTXSR_EXDEF
1650 #define ETH_LOSS_OF_CARRIER                 ETH_MACRXTXSR_LCARR
1651 #define ETH_NO_CARRIER                      ETH_MACRXTXSR_NCARR
1652 #define ETH_TRANSMIT_JABBR_TIMEOUT          ETH_MACRXTXSR_TJT
1653 /**
1654   * @}
1655   */
1656 
1657 /** @defgroup ETH_State_Codes ETH States
1658   * @{
1659   */
1660 #define HAL_ETH_STATE_RESET                0x00000000U    /*!< Peripheral not yet Initialized or disabled */
1661 #define HAL_ETH_STATE_READY                0x00000010U    /*!< Peripheral Communication started           */
1662 #define HAL_ETH_STATE_BUSY                 0x00000020U    /*!< an internal process is ongoing             */
1663 #define HAL_ETH_STATE_STARTED              0x00000040U    /*!< an internal process is started             */
1664 #define HAL_ETH_STATE_ERROR                0x000000E0U    /*!< Error State                                */
1665 /**
1666   * @}
1667   */
1668 
1669 /** @defgroup ETH_PTP_Config_Status ETH PTP Config Status
1670   * @{
1671   */
1672 #define HAL_ETH_PTP_NOT_CONFIGURED        0x00000000U    /*!< ETH PTP Configuration not done */
1673 #define HAL_ETH_PTP_CONFIGURED            0x00000001U    /*!< ETH PTP Configuration done     */
1674 /**
1675   * @}
1676   */
1677 #ifdef HAL_ETH_USE_PTP
1678 /** @defgroup ETH_PTP_Update_Method ETH PTP Update Method
1679   * @{
1680   */
1681 #define HAL_ETH_PTP_COARSE_TS_UPDATE  0x00000000U    /*!< Coarse method is used to update the system timestamp */
1682 #define HAL_ETH_PTP_FINE_TS_UPDATE    0x00000002U    /*!< Fine method is used to update system timestamp     */
1683 /**
1684   * @}
1685   */
1686 /** @defgroup ETH_PTP_Snap_Type_Selection ETH PTP Snap Type Selection
1687   * @{
1688   */
1689 #define HAL_ETH_PTP_SNAPTYPSEL_0      0x00000000U    /*!< SNAPTYPSEL 00 */
1690 #define HAL_ETH_PTP_SNAPTYPSEL_1      0x00010000U    /*!< SNAPTYPSEL 01 */
1691 #define HAL_ETH_PTP_SNAPTYPSEL_2      0x00020000U    /*!< SNAPTYPSEL 10 */
1692 #define HAL_ETH_PTP_SNAPTYPSEL_3      0x00030000U    /*!< SNAPTYPSEL 11 */
1693 /**
1694   * @}
1695   */
1696 #endif /* HAL_ETH_USE_PTP */
1697 
1698 /** @defgroup ETH_DMA_Channel_Number_Tx_Rx_Selection ETH DMA Channel Number Tx Rx Selection
1699   * @{
1700   */
1701 #define ETH_DMA_CH0                 0x00000001U
1702 #define ETH_DMA_CH1                 0x00000002U
1703 /**
1704   * @}
1705   */
1706 /** @defgroup ETH_DMA_Channel_Number_TxOp_RxOp_Selection ETH DMA Channel Number Tx Rx Selection Index
1707   * @{
1708   */
1709 #define ETH_DMA_CH0_IDX             (0U)
1710 #define ETH_DMA_CH1_IDX             (1U)
1711 /**
1712   * @}
1713   */
1714 
1715 
1716 
1717 /* Exported macro ------------------------------------------------------------*/
1718 /** @defgroup ETH_Exported_Macros ETH Exported Macros
1719   * @{
1720   */
1721 
1722 /** @brief Reset ETH handle state
1723   * @param  __HANDLE__: specifies the ETH handle.
1724   * @retval None
1725   */
1726 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
1727 #define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__)  do{                                                   \
1728                                                       (__HANDLE__)->gState = HAL_ETH_STATE_RESET;      \
1729                                                       (__HANDLE__)->MspInitCallback = NULL;             \
1730                                                       (__HANDLE__)->MspDeInitCallback = NULL;           \
1731                                                     } while(0)
1732 #else
1733 #define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__)  do{                                                   \
1734                                                       (__HANDLE__)->gState = HAL_ETH_STATE_RESET;      \
1735                                                     } while(0)
1736 #endif /*USE_HAL_ETH_REGISTER_CALLBACKS */
1737 
1738 /**
1739   * @brief  Enables the specified ETHERNET DMA interrupts.
1740   * @param  __HANDLE__   : ETH Handle
1741   * @param  __CH__   : DMA Channel
1742   * @param  __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be
1743   *   enabled @ref ETH_DMA_Interrupts
1744   * @retval None
1745   */
1746 #define __HAL_ETH_DMA_CH_ENABLE_IT(__HANDLE__, __INTERRUPT__,__CH__) ((__HANDLE__)->Instance->DMA_CH[__CH__].DMACIER \
1747                                                                       |= (__INTERRUPT__))
1748 
1749 /**
1750   * @brief  Disables the specified ETHERNET DMA interrupts.
1751   * @param  __HANDLE__   : ETH Handle
1752   * @param  __CH__   : DMA Channel
1753   * @param  __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be
1754   *   disabled. @ref ETH_DMA_Interrupts
1755   * @retval None
1756   */
1757 #define __HAL_ETH_DMA_CH_DISABLE_IT(__HANDLE__, __INTERRUPT__, __CH__) ((__HANDLE__)->Instance->DMA_CH[__CH__].DMACIER \
1758                                                                         &= ~(__INTERRUPT__))
1759 
1760 /**
1761   * @brief  Gets the ETHERNET DMA IT source enabled or disabled.
1762   * @param  __HANDLE__   : ETH Handle
1763   * @param  __CH__   : DMA Channel
1764   * @param  __INTERRUPT__: specifies the interrupt source to get . @ref ETH_DMA_Interrupts
1765   * @retval The ETH DMA IT Source enabled or disabled
1766   */
1767 #define __HAL_ETH_DMA_CH_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__, __CH__) \
1768   (((__HANDLE__)->Instance->DMA_CH[__CH__].DMACIER &  (__INTERRUPT__)) == (__INTERRUPT__))
1769 
1770 /**
1771   * @brief  Gets the ETHERNET DMA IT pending bit.
1772   * @param  __HANDLE__   : ETH Handle
1773   * @param  __CH__   : DMA Channel
1774   * @param  __INTERRUPT__: specifies the interrupt source to get . @ref ETH_DMA_Interrupts
1775   * @retval The state of ETH DMA IT (SET or RESET)
1776   */
1777 #define __HAL_ETH_DMA_CH_GET_IT(__HANDLE__, __INTERRUPT__, __CH__) \
1778   (((__HANDLE__)->Instance->DMA_CH[__CH__].DMACSR &  (__INTERRUPT__)) == (__INTERRUPT__))
1779 
1780 /**
1781   * @brief  Clears the ETHERNET DMA IT pending bit.
1782   * @param  __HANDLE__   : ETH Handle
1783   * @param  __CH__   : DMA Channel
1784   * @param  __INTERRUPT__: specifies the interrupt pending bit to clear. @ref ETH_DMA_Interrupts
1785   * @retval None
1786   */
1787 #define __HAL_ETH_DMA_CH_CLEAR_IT(__HANDLE__, __INTERRUPT__, __CH__) ((__HANDLE__)->Instance->DMA_CH[__CH__].DMACSR \
1788                                                                       = (__INTERRUPT__))
1789 
1790 /**
1791   * @brief  Checks whether the specified ETHERNET DMA flag is set or not.
1792   * @param  __HANDLE__: ETH Handle
1793   * @param  __CH__   : DMA Channel
1794   * @param  __FLAG__: specifies the flag to check. @ref ETH_DMA_Status_Flags
1795   * @retval The state of ETH DMA FLAG (SET or RESET).
1796   */
1797 #define __HAL_ETH_DMA_GET_FLAG(__HANDLE__, __FLAG__, __CH__) (((__HANDLE__)->Instance->DMA_CH[__CH__].DMACSR &\
1798                                                                ( __FLAG__)) == ( __FLAG__))
1799 
1800 /**
1801   * @brief  Clears the specified ETHERNET DMA flag.
1802   * @param  __HANDLE__: ETH Handle
1803   * @param  __CH__   : DMA Channel
1804   * @param  __FLAG__: specifies the flag to check. @ref ETH_DMA_Status_Flags
1805   * @retval The state of ETH DMA FLAG (SET or RESET).
1806   */
1807 #define __HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__, __CH__) ((__HANDLE__)->Instance->DMA_CH[__CH__].DMACSR\
1808                                                                 = ( __FLAG__))
1809 
1810 /**
1811   * @brief  Enables the specified ETHERNET MTL interrupts.
1812   * @param  __HANDLE__   : ETH Handle
1813   * @param  __Q__   : MTL Queue
1814   * @param  __INTERRUPT__: specifies the ETHERNET MTL interrupt sources to be
1815   *   enabled @ref ETH_MTL_Interrupts
1816   * @retval None
1817   */
1818 
1819 #define __HAL_ETH_MTL_Q_ENABLE_IT(__HANDLE__, __INTERRUPT__, __Q__) ((__HANDLE__)->Instance->MTL_QUEUE[__Q__].MTLQICSR \
1820                                                                      |= (__INTERRUPT__))
1821 
1822 /**
1823   * @brief  Gets the ETHERNET MTL IT source enabled or disabled.
1824   * @param  __HANDLE__   : ETH Handle
1825   * @param  __INTERRUPT__: specifies the interrupt source to get . @ref ETH_MTL_Interrupts
1826   * @retval The ETH MTL IT Source enabled or disabled
1827   */
1828 #define __HAL_ETH_MTL_GET_IT(__HANDLE__, __INTERRUPT__) \
1829   (((__HANDLE__)->Instance->MTLISR &  (__INTERRUPT__)) == (__INTERRUPT__))
1830 
1831 /**
1832   * @brief  Gets the ETHERNET MTL IT pending bit.
1833   * @param  __HANDLE__   : ETH Handle
1834   * @param  __Q__   : MTL Queue
1835   * @param  __INTERRUPT__: specifies the interrupt source to get . @ref ETH_MTL_Interrupts
1836   * @retval The state of ETH MTL IT (SET or RESET)
1837   */
1838 #define __HAL_ETH_MTL_Q_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__, __Q__) \
1839   (((__HANDLE__)->Instance->MTL_QUEUE[__Q__].MTLQICSR &  (__INTERRUPT__)) == (__INTERRUPT__))
1840 /**
1841   * @brief  Disables the specified ETHERNET MTL interrupts.
1842   * @param  __HANDLE__   : ETH Handle
1843   * @param  __Q__   : MTL Queue
1844   * @param  __INTERRUPT__: specifies the ETHERNET MTL interrupt sources to be
1845   *   disabled @ref ETH_MTL_Interrupts
1846   * @retval None
1847   */
1848 
1849 #define __HAL_ETH_MTL_Q_DISABLE_IT(__HANDLE__, __INTERRUPT__, __Q__) \
1850   ((__HANDLE__)->Instance->MTL_QUEUE[__Q__].MTLQICSR &= ~(__INTERRUPT__))
1851 
1852 /**
1853   * @brief  Enables the specified ETHERNET MAC interrupts.
1854   * @param  __HANDLE__   : ETH Handle
1855   * @param  __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be
1856   *   enabled @ref ETH_MAC_Interrupts
1857   * @retval None
1858   */
1859 
1860 #define __HAL_ETH_MAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIER |= (__INTERRUPT__))
1861 
1862 /**
1863   * @brief  Disables the specified ETHERNET MAC interrupts.
1864   * @param  __HANDLE__   : ETH Handle
1865   * @param  __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be
1866   *   enabled @ref ETH_MAC_Interrupts
1867   * @retval None
1868   */
1869 #define __HAL_ETH_MAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIER &= ~(__INTERRUPT__))
1870 
1871 /**
1872   * @brief  Checks whether the specified ETHERNET MAC flag is set or not.
1873   * @param  __HANDLE__: ETH Handle
1874   * @param  __INTERRUPT__: specifies the flag to check. @ref ETH_MAC_Interrupts
1875   * @retval The state of ETH MAC IT (SET or RESET).
1876   */
1877 #define __HAL_ETH_MAC_GET_IT(__HANDLE__, __INTERRUPT__)                     (((__HANDLE__)->Instance->MACISR &\
1878                                                                               ( __INTERRUPT__)) == ( __INTERRUPT__))
1879 
1880 /*!< External interrupt line 51 Connected to the ETH wakeup EXTI Line */
1881 #define ETH_WAKEUP_EXTI_LINE  0x00080000U  /* !<  IM51 in EXTI IMR2 register is bit 19 */
1882 
1883 /**
1884   * @brief Enable the ETH WAKEUP Exti Line.
1885   * @param  __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be enabled.
1886   *   @arg ETH_WAKEUP_EXTI_LINE
1887   * @retval None.
1888   */
1889 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_IT(__EXTI_LINE__)   (EXTI_D1->IMR3 |= (__EXTI_LINE__))
1890 
1891 /**
1892   * @brief checks whether the specified ETH WAKEUP Exti interrupt flag is set or not.
1893   * @param  __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be cleared.
1894   *   @arg ETH_WAKEUP_EXTI_LINE
1895   * @retval EXTI ETH WAKEUP Line Status.
1896   */
1897 #define __HAL_ETH_WAKEUP_EXTI_GET_FLAG(__EXTI_LINE__)  (EXTI->IMR2 & (__EXTI_LINE__))
1898 
1899 /**
1900   * @brief Clear the ETH WAKEUP Exti flag.
1901   * @param  __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be cleared.
1902   *   @arg ETH_WAKEUP_EXTI_LINE
1903   * @retval None.
1904   */
1905 #define __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->IMR2 = (__EXTI_LINE__))
1906 
1907 /**
1908   * @brief  enable rising edge interrupt on selected EXTI line.
1909   * @param  __EXTI_LINE__: specifies the ETH WAKEUP EXTI sources to be disabled.
1910   *  @arg ETH_WAKEUP_EXTI_LINE
1911   * @retval None
1912   */
1913 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE(__EXTI_LINE__) (EXTI->FTSR3 &= ~(__EXTI_LINE__)); \
1914   (EXTI->RTSR3 |= (__EXTI_LINE__))
1915 
1916 /**
1917   * @brief  enable falling edge interrupt on selected EXTI line.
1918   * @param  __EXTI_LINE__: specifies the ETH WAKEUP EXTI sources to be disabled.
1919   *  @arg ETH_WAKEUP_EXTI_LINE
1920   * @retval None
1921   */
1922 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE(__EXTI_LINE__) (EXTI->RTSR3 &= ~(__EXTI_LINE__));\
1923   (EXTI->FTSR3 |= (__EXTI_LINE__))
1924 
1925 /**
1926   * @brief  enable falling edge interrupt on selected EXTI line.
1927   * @param  __EXTI_LINE__: specifies the ETH WAKEUP EXTI sources to be disabled.
1928   *  @arg ETH_WAKEUP_EXTI_LINE
1929   * @retval None
1930   */
1931 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE(__EXTI_LINE__) (EXTI->RTSR3 |= (__EXTI_LINE__));\
1932   (EXTI->FTSR3 |= (__EXTI_LINE__))
1933 
1934 /**
1935   * @brief  Generates a Software interrupt on selected EXTI line.
1936   * @param  __EXTI_LINE__: specifies the ETH WAKEUP EXTI sources to be disabled.
1937   *  @arg ETH_WAKEUP_EXTI_LINE
1938   * @retval None
1939   */
1940 #define __HAL_ETH_WAKEUP_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER3 |= (__EXTI_LINE__))
1941 #define __HAL_ETH_GET_PTP_CONTROL(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->MACTSCR) & \
1942                                                            (__FLAG__)) == (__FLAG__)) ? SET : RESET)
1943 #define __HAL_ETH_SET_PTP_CONTROL(__HANDLE__, __FLAG__)   ((__HANDLE__)->Instance->MACTSCR |= (__FLAG__))
1944 
1945 /**
1946   * @}
1947   */
1948 
1949 /* Include ETH HAL Extension module */
1950 #include "stm32n6xx_hal_eth_ex.h"
1951 
1952 /* Exported functions --------------------------------------------------------*/
1953 
1954 /** @addtogroup ETH_Exported_Functions
1955   * @{
1956   */
1957 
1958 /** @addtogroup ETH_Exported_Functions_Group1
1959   * @{
1960   */
1961 /* Initialization and de initialization functions  **********************************/
1962 HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth);
1963 HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth);
1964 void              HAL_ETH_MspInit(ETH_HandleTypeDef *heth);
1965 void              HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth);
1966 
1967 /* Callbacks Register/UnRegister functions  ***********************************/
1968 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
1969 HAL_StatusTypeDef HAL_ETH_RegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID,
1970                                            pETH_CallbackTypeDef pCallback);
1971 HAL_StatusTypeDef HAL_ETH_UnRegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID);
1972 #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
1973 
1974 /**
1975   * @}
1976   */
1977 
1978 /** @addtogroup ETH_Exported_Functions_Group2
1979   * @{
1980   */
1981 /* IO operation functions *******************************************************/
1982 HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth);
1983 HAL_StatusTypeDef HAL_ETH_Start_IT(ETH_HandleTypeDef *heth);
1984 HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth);
1985 HAL_StatusTypeDef HAL_ETH_Stop_IT(ETH_HandleTypeDef *heth);
1986 
1987 HAL_StatusTypeDef HAL_ETH_ReadData(ETH_HandleTypeDef *heth, void **pAppBuff);
1988 HAL_StatusTypeDef HAL_ETH_RegisterRxAllocateCallback(ETH_HandleTypeDef *heth,
1989                                                      pETH_rxAllocateCallbackTypeDef rxAllocateCallback);
1990 HAL_StatusTypeDef HAL_ETH_UnRegisterRxAllocateCallback(ETH_HandleTypeDef *heth);
1991 HAL_StatusTypeDef HAL_ETH_RegisterRxLinkCallback(ETH_HandleTypeDef *heth, pETH_rxLinkCallbackTypeDef rxLinkCallback);
1992 HAL_StatusTypeDef HAL_ETH_UnRegisterRxLinkCallback(ETH_HandleTypeDef *heth);
1993 HAL_StatusTypeDef HAL_ETH_GetRxDataErrorCode(const ETH_HandleTypeDef *heth, uint32_t *pErrorCode);
1994 HAL_StatusTypeDef HAL_ETH_RegisterTxFreeCallback(ETH_HandleTypeDef *heth, pETH_txFreeCallbackTypeDef txFreeCallback);
1995 HAL_StatusTypeDef HAL_ETH_UnRegisterTxFreeCallback(ETH_HandleTypeDef *heth);
1996 HAL_StatusTypeDef HAL_ETH_ReleaseTxPacket(ETH_HandleTypeDef *heth);
1997 
1998 #ifdef HAL_ETH_USE_PTP
1999 HAL_StatusTypeDef HAL_ETH_PTP_SetConfig(ETH_HandleTypeDef *heth, ETH_PTP_ConfigTypeDef *ptpconfig);
2000 HAL_StatusTypeDef HAL_ETH_PTP_GetConfig(ETH_HandleTypeDef *heth, ETH_PTP_ConfigTypeDef *ptpconfig);
2001 HAL_StatusTypeDef HAL_ETH_PTP_SetTime(ETH_HandleTypeDef *heth, ETH_TimeTypeDef *time);
2002 HAL_StatusTypeDef HAL_ETH_PTP_GetTime(ETH_HandleTypeDef *heth, ETH_TimeTypeDef *time);
2003 HAL_StatusTypeDef HAL_ETH_PTP_AddTimeOffset(ETH_HandleTypeDef *heth, ETH_PtpUpdateTypeDef ptpoffsettype,
2004                                             ETH_TimeTypeDef *timeoffset);
2005 HAL_StatusTypeDef HAL_ETH_PTP_InsertTxTimestamp(ETH_HandleTypeDef *heth);
2006 HAL_StatusTypeDef HAL_ETH_PTP_GetTxTimestamp(ETH_HandleTypeDef *heth, ETH_TimeStampTypeDef *timestamp);
2007 HAL_StatusTypeDef HAL_ETH_PTP_GetRxTimestamp(ETH_HandleTypeDef *heth, ETH_TimeStampTypeDef *timestamp);
2008 HAL_StatusTypeDef HAL_ETH_RegisterTxPtpCallback(ETH_HandleTypeDef *heth, pETH_txPtpCallbackTypeDef txPtpCallback);
2009 HAL_StatusTypeDef HAL_ETH_UnRegisterTxPtpCallback(ETH_HandleTypeDef *heth);
2010 #endif /* HAL_ETH_USE_PTP */
2011 
2012 HAL_StatusTypeDef HAL_ETH_Transmit(ETH_HandleTypeDef *heth, ETH_TxPacketConfigTypeDef *pTxConfig, uint32_t Timeout);
2013 HAL_StatusTypeDef HAL_ETH_Transmit_IT(ETH_HandleTypeDef *heth, ETH_TxPacketConfigTypeDef *pTxConfig);
2014 
2015 HAL_StatusTypeDef HAL_ETH_WritePHYRegister(const ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg,
2016                                            uint32_t RegValue);
2017 HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg,
2018                                           uint32_t *pRegValue);
2019 
2020 void              HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth);
2021 void              HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth);
2022 void              HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth);
2023 void              HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth);
2024 void              HAL_ETH_PMTCallback(ETH_HandleTypeDef *heth);
2025 void              HAL_ETH_EEECallback(ETH_HandleTypeDef *heth);
2026 void              HAL_ETH_WakeUpCallback(ETH_HandleTypeDef *heth);
2027 void              HAL_ETH_RxAllocateCallback(uint8_t **buff);
2028 void              HAL_ETH_RxLinkCallback(void **pStart, void **pEnd, uint8_t *buff, uint16_t Length);
2029 void              HAL_ETH_TxFreeCallback(uint32_t *buff);
2030 void              HAL_ETH_TxPtpCallback(uint32_t *buff, ETH_TimeStampTypeDef *timestamp);
2031 /**
2032   * @}
2033   */
2034 
2035 /** @addtogroup ETH_Exported_Functions_Group3
2036   * @{
2037   */
2038 /* Peripheral Control functions  **********************************************/
2039 /* MAC & DMA Configuration APIs  **********************************************/
2040 HAL_StatusTypeDef HAL_ETH_GetMACConfig(const ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf);
2041 HAL_StatusTypeDef HAL_ETH_GetDMAConfig(const ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf);
2042 HAL_StatusTypeDef HAL_ETH_SetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf);
2043 HAL_StatusTypeDef HAL_ETH_SetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf);
2044 void              HAL_ETH_SetMDIOClockRange(ETH_HandleTypeDef *heth);
2045 
2046 /* MAC VLAN Processing APIs    ************************************************/
2047 void              HAL_ETH_SetRxVLANIdentifier(ETH_HandleTypeDef *heth, uint32_t ComparisonBits,
2048                                               uint32_t VLANIdentifier);
2049 
2050 /* MAC L2 Packet Filtering APIs  **********************************************/
2051 HAL_StatusTypeDef HAL_ETH_GetMACFilterConfig(const ETH_HandleTypeDef *heth, ETH_MACFilterConfigTypeDef *pFilterConfig);
2052 HAL_StatusTypeDef HAL_ETH_SetMACFilterConfig(ETH_HandleTypeDef *heth, const ETH_MACFilterConfigTypeDef *pFilterConfig);
2053 HAL_StatusTypeDef HAL_ETH_SetHashTable(ETH_HandleTypeDef *heth, uint32_t *pHashTable);
2054 HAL_StatusTypeDef HAL_ETH_SetSourceMACAddrMatch(const ETH_HandleTypeDef *heth, uint32_t AddrNbr,
2055                                                 const uint8_t *pMACAddr);
2056 
2057 /* MAC Power Down APIs    *****************************************************/
2058 void              HAL_ETH_EnterPowerDownMode(ETH_HandleTypeDef *heth,
2059                                              const ETH_PowerDownConfigTypeDef *pPowerDownConfig);
2060 void              HAL_ETH_ExitPowerDownMode(ETH_HandleTypeDef *heth);
2061 HAL_StatusTypeDef HAL_ETH_SetWakeUpFilter(ETH_HandleTypeDef *heth, uint32_t *pFilter, uint32_t Count);
2062 
2063 /**
2064   * @}
2065   */
2066 
2067 /** @addtogroup ETH_Exported_Functions_Group4
2068   * @{
2069   */
2070 /* Peripheral State functions  **************************************************/
2071 HAL_ETH_StateTypeDef HAL_ETH_GetState(const ETH_HandleTypeDef *heth);
2072 uint32_t             HAL_ETH_GetError(const ETH_HandleTypeDef *heth);
2073 uint32_t             HAL_ETH_GetDMAError(const ETH_HandleTypeDef *heth);
2074 uint32_t             HAL_ETH_GetMACError(const ETH_HandleTypeDef *heth);
2075 uint32_t             HAL_ETH_GetMACWakeUpSource(const ETH_HandleTypeDef *heth);
2076 uint32_t             HAL_ETH_GetTxBuffersNumber(const ETH_HandleTypeDef *heth);
2077 /**
2078   * @}
2079   */
2080 
2081 /**
2082   * @}
2083   */
2084 
2085 /**
2086   * @}
2087   */
2088 
2089 /**
2090   * @}
2091   */
2092 
2093 /**
2094   * @}
2095   */
2096 
2097 #endif /* ETH1 */
2098 
2099 #ifdef __cplusplus
2100 }
2101 #endif
2102 
2103 #endif /* STM32N6xx_HAL_ETH_H */
2104