1 /* 2 * Copyright (c) 2014-2023, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <drivers/arm/tzc400.h> 11 #if TRUSTED_BOARD_BOOT 12 #include MBEDTLS_CONFIG_FILE 13 #endif 14 #include <plat/arm/board/common/board_css_def.h> 15 #include <plat/arm/board/common/v2m_def.h> 16 #include <plat/arm/common/arm_def.h> 17 #include <plat/arm/css/common/css_def.h> 18 #include <plat/arm/soc/common/soc_css_def.h> 19 #include <plat/common/common_def.h> 20 21 #include "../juno_def.h" 22 #ifdef JUNO_ETHOSN_TZMP1 23 #include "../juno_ethosn_tzmp1_def.h" 24 #endif 25 26 /* Required platform porting definitions */ 27 /* Juno supports system power domain */ 28 #define PLAT_MAX_PWR_LVL ARM_PWR_LVL2 29 #define PLAT_NUM_PWR_DOMAINS (ARM_SYSTEM_COUNT + \ 30 JUNO_CLUSTER_COUNT + \ 31 PLATFORM_CORE_COUNT) 32 #define PLATFORM_CORE_COUNT (JUNO_CLUSTER0_CORE_COUNT + \ 33 JUNO_CLUSTER1_CORE_COUNT) 34 35 /* 36 * Other platform porting definitions are provided by included headers 37 */ 38 39 /* 40 * Required ARM standard platform porting definitions 41 */ 42 #define PLAT_ARM_CLUSTER_COUNT JUNO_CLUSTER_COUNT 43 44 #define PLAT_ARM_TRUSTED_SRAM_SIZE UL(0x00040000) /* 256 KB */ 45 46 /* Use the bypass address */ 47 #define PLAT_ARM_TRUSTED_ROM_BASE (V2M_FLASH0_BASE + \ 48 BL1_ROM_BYPASS_OFFSET) 49 50 #define NSRAM_BASE UL(0x2e000000) 51 #define NSRAM_SIZE UL(0x00008000) /* 32KB */ 52 53 #define PLAT_ARM_DRAM2_BASE ULL(0x880000000) 54 #define PLAT_ARM_DRAM2_SIZE ULL(0x180000000) 55 56 /* Range of kernel DTB load address */ 57 #define JUNO_DTB_DRAM_MAP_START ULL(0x82000000) 58 #define JUNO_DTB_DRAM_MAP_SIZE ULL(0x00008000) /* 32KB */ 59 60 #define ARM_DTB_DRAM_NS MAP_REGION_FLAT( \ 61 JUNO_DTB_DRAM_MAP_START, \ 62 JUNO_DTB_DRAM_MAP_SIZE, \ 63 MT_MEMORY | MT_RO | MT_NS) 64 65 #ifdef JUNO_ETHOSN_TZMP1 66 #define JUNO_ETHOSN_PROT_FW_RO MAP_REGION_FLAT( \ 67 JUNO_ETHOSN_FW_TZC_PROT_DRAM2_BASE, \ 68 JUNO_ETHOSN_FW_TZC_PROT_DRAM2_SIZE, \ 69 MT_RO_DATA | MT_SECURE) 70 71 #define JUNO_ETHOSN_PROT_FW_RW MAP_REGION_FLAT( \ 72 JUNO_ETHOSN_FW_TZC_PROT_DRAM2_BASE, \ 73 JUNO_ETHOSN_FW_TZC_PROT_DRAM2_SIZE, \ 74 MT_MEMORY | MT_RW | MT_SECURE) 75 #endif 76 77 /* virtual address used by dynamic mem_protect for chunk_base */ 78 #define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xc0000000) 79 80 /* 81 * PLAT_ARM_MAX_ROMLIB_RW_SIZE is define to use a full page 82 */ 83 84 #if USE_ROMLIB 85 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0x1000) 86 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0xe000) 87 #define JUNO_BL2_ROMLIB_OPTIMIZATION UL(0x8000) 88 #else 89 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0) 90 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0) 91 #define JUNO_BL2_ROMLIB_OPTIMIZATION UL(0) 92 #endif 93 94 /* 95 * Actual ROM size on Juno is 64 KB, but TBB currently requires at least 80 KB 96 * in debug mode. We can test TBB on Juno bypassing the ROM and using 128 KB of 97 * flash 98 */ 99 100 #if TRUSTED_BOARD_BOOT 101 #define PLAT_ARM_TRUSTED_ROM_SIZE UL(0x00020000) 102 #else 103 #define PLAT_ARM_TRUSTED_ROM_SIZE UL(0x00010000) 104 #endif /* TRUSTED_BOARD_BOOT */ 105 106 /* 107 * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the 108 * plat_arm_mmap array defined for each BL stage. 109 */ 110 #ifdef IMAGE_BL1 111 # define PLAT_ARM_MMAP_ENTRIES 7 112 # define MAX_XLAT_TABLES 4 113 #endif 114 115 #ifdef IMAGE_BL2 116 #ifdef SPD_opteed 117 # define PLAT_ARM_MMAP_ENTRIES 13 118 # define MAX_XLAT_TABLES 5 119 #else 120 # define PLAT_ARM_MMAP_ENTRIES 11 121 # define MAX_XLAT_TABLES 5 122 #endif 123 #endif 124 125 #ifdef IMAGE_BL2U 126 # define PLAT_ARM_MMAP_ENTRIES 5 127 # define MAX_XLAT_TABLES 3 128 #endif 129 130 #ifdef IMAGE_BL31 131 # define PLAT_ARM_MMAP_ENTRIES 8 132 # define MAX_XLAT_TABLES 6 133 #endif 134 135 #ifdef IMAGE_BL32 136 # define PLAT_ARM_MMAP_ENTRIES 6 137 # define MAX_XLAT_TABLES 4 138 #endif 139 140 /* 141 * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size 142 * plus a little space for growth. 143 */ 144 #if TRUSTED_BOARD_BOOT 145 # define PLAT_ARM_MAX_BL1_RW_SIZE UL(0xB000) 146 #else 147 # define PLAT_ARM_MAX_BL1_RW_SIZE UL(0x6000) 148 #endif 149 150 /* 151 * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a 152 * little space for growth. 153 */ 154 #if TRUSTED_BOARD_BOOT 155 #if TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_RSA_AND_ECDSA 156 # define PLAT_ARM_MAX_BL2_SIZE (UL(0x1F000) - JUNO_BL2_ROMLIB_OPTIMIZATION) 157 #elif TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_ECDSA 158 # define PLAT_ARM_MAX_BL2_SIZE (UL(0x1D000) - JUNO_BL2_ROMLIB_OPTIMIZATION) 159 #else 160 # define PLAT_ARM_MAX_BL2_SIZE (UL(0x1D000) - JUNO_BL2_ROMLIB_OPTIMIZATION) 161 #endif 162 #else 163 # define PLAT_ARM_MAX_BL2_SIZE (UL(0x13000) - JUNO_BL2_ROMLIB_OPTIMIZATION) 164 #endif 165 166 /* 167 * Since BL31 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL31_SIZE is 168 * calculated using the current BL31 PROGBITS debug size plus the sizes of 169 * BL2 and BL1-RW. SCP_BL2 image is loaded into the space BL31 -> BL2_BASE. 170 * Hence the BL31 PROGBITS size should be >= PLAT_CSS_MAX_SCP_BL2_SIZE. 171 */ 172 #define PLAT_ARM_MAX_BL31_SIZE UL(0x3D000) 173 174 #if JUNO_AARCH32_EL3_RUNTIME 175 /* 176 * Since BL32 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL32_SIZE is 177 * calculated using the current BL32 PROGBITS debug size plus the sizes of 178 * BL2 and BL1-RW. SCP_BL2 image is loaded into the space BL32 -> BL2_BASE. 179 * Hence the BL32 PROGBITS size should be >= PLAT_CSS_MAX_SCP_BL2_SIZE. 180 */ 181 #define PLAT_ARM_MAX_BL32_SIZE UL(0x3D000) 182 #endif 183 184 /* 185 * Size of cacheable stacks 186 */ 187 #if defined(IMAGE_BL1) 188 # if TRUSTED_BOARD_BOOT 189 # define PLATFORM_STACK_SIZE UL(0x1000) 190 # else 191 # define PLATFORM_STACK_SIZE UL(0x440) 192 # endif 193 #elif defined(IMAGE_BL2) 194 # if TRUSTED_BOARD_BOOT 195 # define PLATFORM_STACK_SIZE UL(0x1000) 196 # else 197 # define PLATFORM_STACK_SIZE UL(0x400) 198 # endif 199 #elif defined(IMAGE_BL2U) 200 # define PLATFORM_STACK_SIZE UL(0x400) 201 #elif defined(IMAGE_BL31) 202 # if PLAT_XLAT_TABLES_DYNAMIC 203 # define PLATFORM_STACK_SIZE UL(0x800) 204 # else 205 # define PLATFORM_STACK_SIZE UL(0x400) 206 # endif 207 #elif defined(IMAGE_BL32) 208 # define PLATFORM_STACK_SIZE UL(0x440) 209 #endif 210 211 /* CCI related constants */ 212 #define PLAT_ARM_CCI_BASE UL(0x2c090000) 213 #define PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX 4 214 #define PLAT_ARM_CCI_CLUSTER1_SL_IFACE_IX 3 215 216 /* System timer related constants */ 217 #define PLAT_ARM_NSTIMER_FRAME_ID U(1) 218 219 /* TZC related constants */ 220 #define PLAT_ARM_TZC_BASE UL(0x2a4a0000) 221 #define PLAT_ARM_TZC_NS_DEV_ACCESS ( \ 222 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_CCI400) | \ 223 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_PCIE) | \ 224 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_HDLCD0) | \ 225 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_HDLCD1) | \ 226 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_USB) | \ 227 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_DMA330) | \ 228 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_THINLINKS) | \ 229 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_AP) | \ 230 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_GPU) | \ 231 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_CORESIGHT)) 232 233 /* TZC related constants */ 234 #define PLAT_ARM_TZC_FILTERS TZC_400_REGION_ATTR_FILTER_BIT_ALL 235 236 /* 237 * Required ARM CSS based platform porting definitions 238 */ 239 240 /* GIC related constants (no GICR in GIC-400) */ 241 #define PLAT_ARM_GICD_BASE UL(0x2c010000) 242 #define PLAT_ARM_GICC_BASE UL(0x2c02f000) 243 #define PLAT_ARM_GICH_BASE UL(0x2c04f000) 244 #define PLAT_ARM_GICV_BASE UL(0x2c06f000) 245 246 /* MHU related constants */ 247 #define PLAT_CSS_MHU_BASE UL(0x2b1f0000) 248 249 /* 250 * Base address of the first memory region used for communication between AP 251 * and SCP. Used by the BOM and SCPI protocols. 252 */ 253 #if !CSS_USE_SCMI_SDS_DRIVER 254 /* 255 * Note that this is located at the same address as SCP_BOOT_CFG_ADDR, which 256 * means the SCP/AP configuration data gets overwritten when the AP initiates 257 * communication with the SCP. The configuration data is expected to be a 258 * 32-bit word on all CSS platforms. On Juno, part of this configuration is 259 * which CPU is the primary, according to the shift and mask definitions below. 260 */ 261 #define PLAT_CSS_SCP_COM_SHARED_MEM_BASE (ARM_TRUSTED_SRAM_BASE + UL(0x80)) 262 #define PLAT_CSS_PRIMARY_CPU_SHIFT 8 263 #define PLAT_CSS_PRIMARY_CPU_BIT_WIDTH 4 264 #endif 265 266 /* 267 * SCP_BL2 uses up whatever remaining space is available as it is loaded before 268 * anything else in this memory region and is handed over to the SCP before 269 * BL31 is loaded over the top. 270 */ 271 #define PLAT_CSS_MAX_SCP_BL2_SIZE \ 272 ((SCP_BL2_LIMIT - ARM_FW_CONFIG_LIMIT) & ~PAGE_SIZE_MASK) 273 274 #define PLAT_CSS_MAX_SCP_BL2U_SIZE PLAT_CSS_MAX_SCP_BL2_SIZE 275 276 #define PLAT_ARM_G1S_IRQ_PROPS(grp) \ 277 CSS_G1S_IRQ_PROPS(grp), \ 278 ARM_G1S_IRQ_PROPS(grp), \ 279 INTR_PROP_DESC(JUNO_IRQ_DMA_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ 280 (grp), GIC_INTR_CFG_LEVEL), \ 281 INTR_PROP_DESC(JUNO_IRQ_HDLCD0_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ 282 (grp), GIC_INTR_CFG_LEVEL), \ 283 INTR_PROP_DESC(JUNO_IRQ_HDLCD1_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ 284 (grp), GIC_INTR_CFG_LEVEL), \ 285 INTR_PROP_DESC(JUNO_IRQ_USB_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ 286 (grp), GIC_INTR_CFG_LEVEL), \ 287 INTR_PROP_DESC(JUNO_IRQ_THIN_LINKS_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ 288 (grp), GIC_INTR_CFG_LEVEL), \ 289 INTR_PROP_DESC(JUNO_IRQ_SEC_I2C, GIC_HIGHEST_SEC_PRIORITY, \ 290 (grp), GIC_INTR_CFG_LEVEL), \ 291 INTR_PROP_DESC(JUNO_IRQ_GPU_SMMU_1, GIC_HIGHEST_SEC_PRIORITY, \ 292 (grp), GIC_INTR_CFG_LEVEL), \ 293 INTR_PROP_DESC(JUNO_IRQ_ETR_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ 294 (grp), GIC_INTR_CFG_LEVEL) 295 296 #define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp) 297 298 /* 299 * Required ARM CSS SoC based platform porting definitions 300 */ 301 302 /* CSS SoC NIC-400 Global Programmers View (GPV) */ 303 #define PLAT_SOC_CSS_NIC400_BASE UL(0x2a000000) 304 305 #define PLAT_ARM_PRIVATE_SDEI_EVENTS ARM_SDEI_PRIVATE_EVENTS 306 #define PLAT_ARM_SHARED_SDEI_EVENTS ARM_SDEI_SHARED_EVENTS 307 308 /* System power domain level */ 309 #define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL2 310 311 /* 312 * Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes 313 */ 314 #ifdef __aarch64__ 315 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 36) 316 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 36) 317 #else 318 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 319 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 320 #endif 321 322 /* Number of SCMI channels on the platform */ 323 #define PLAT_ARM_SCMI_CHANNEL_COUNT U(1) 324 325 /* Protected NSAIDs and memory regions for the Arm(R) Ethos(TM)-N NPU driver */ 326 #ifdef JUNO_ETHOSN_TZMP1 327 #define ETHOSN_NPU_PROT_FW_NSAID JUNO_ETHOSN_TZC400_NSAID_FW_PROT 328 #define ETHOSN_NPU_PROT_RW_DATA_NSAID JUNO_ETHOSN_TZC400_NSAID_DATA_RW_PROT 329 #define ETHOSN_NPU_PROT_RO_DATA_NSAID JUNO_ETHOSN_TZC400_NSAID_DATA_RO_PROT 330 331 #define ETHOSN_NPU_NS_RW_DATA_NSAID JUNO_ETHOSN_TZC400_NSAID_DATA_RW_NS 332 #define ETHOSN_NPU_NS_RO_DATA_NSAID JUNO_ETHOSN_TZC400_NSAID_DATA_RO_NS 333 334 #define ETHOSN_NPU_FW_IMAGE_BASE JUNO_ETHOSN_FW_TZC_PROT_DRAM2_BASE 335 #define ETHOSN_NPU_FW_IMAGE_LIMIT \ 336 (JUNO_ETHOSN_FW_TZC_PROT_DRAM2_BASE + JUNO_ETHOSN_FW_TZC_PROT_DRAM2_SIZE) 337 #endif 338 339 #endif /* PLATFORM_DEF_H */ 340
