1 /* 2 * Copyright (c) 2021-2023, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef ETHOSN_H 8 #define ETHOSN_H 9 10 #include <lib/smccc.h> 11 12 /* Function numbers */ 13 #define ETHOSN_FNUM_VERSION U(0x50) 14 #define ETHOSN_FNUM_IS_SEC U(0x51) 15 #define ETHOSN_FNUM_HARD_RESET U(0x52) 16 #define ETHOSN_FNUM_SOFT_RESET U(0x53) 17 #define ETHOSN_FNUM_IS_SLEEPING U(0x54) 18 #define ETHOSN_FNUM_GET_FW_PROP U(0x55) 19 #define ETHOSN_FNUM_BOOT_FW U(0x56) 20 /* 0x57-0x5F reserved for future use */ 21 22 /* Properties for ETHOSN_FNUM_TZMP_GET_FW_PROP */ 23 #define ETHOSN_FW_PROP_VERSION U(0xF00) 24 #define ETHOSN_FW_PROP_MEM_INFO U(0xF01) 25 #define ETHOSN_FW_PROP_OFFSETS U(0xF02) 26 #define ETHOSN_FW_PROP_VA_MAP U(0xF03) 27 28 /* SMC64 function IDs */ 29 #define ETHOSN_FID_64(func_num) U(0xC2000000 | func_num) 30 #define ETHOSN_FID_VERSION_64 ETHOSN_FID_64(ETHOSN_FNUM_VERSION) 31 #define ETHOSN_FID_IS_SEC_64 ETHOSN_FID_64(ETHOSN_FNUM_IS_SEC) 32 #define ETHOSN_FID_HARD_RESET_64 ETHOSN_FID_64(ETHOSN_FNUM_HARD_RESET) 33 #define ETHOSN_FID_SOFT_RESET_64 ETHOSN_FID_64(ETHOSN_FNUM_SOFT_RESET) 34 35 /* SMC32 function IDs */ 36 #define ETHOSN_FID_32(func_num) U(0x82000000 | func_num) 37 #define ETHOSN_FID_VERSION_32 ETHOSN_FID_32(ETHOSN_FNUM_VERSION) 38 #define ETHOSN_FID_IS_SEC_32 ETHOSN_FID_32(ETHOSN_FNUM_IS_SEC) 39 #define ETHOSN_FID_HARD_RESET_32 ETHOSN_FID_32(ETHOSN_FNUM_HARD_RESET) 40 #define ETHOSN_FID_SOFT_RESET_32 ETHOSN_FID_32(ETHOSN_FNUM_SOFT_RESET) 41 42 #define ETHOSN_NUM_SMC_CALLS 8 43 44 /* Macro to identify function calls */ 45 #define ETHOSN_FID_MASK U(0xFFF0) 46 #define ETHOSN_FID_VALUE U(0x50) 47 #define is_ethosn_fid(_fid) (((_fid) & ETHOSN_FID_MASK) == ETHOSN_FID_VALUE) 48 49 /* Service version */ 50 #define ETHOSN_VERSION_MAJOR U(3) 51 #define ETHOSN_VERSION_MINOR U(0) 52 53 /* Return codes for function calls */ 54 #define ETHOSN_SUCCESS 0 55 #define ETHOSN_NOT_SUPPORTED -1 56 /* -2 Reserved for NOT_REQUIRED */ 57 #define ETHOSN_INVALID_PARAMETER -3 58 #define ETHOSN_FAILURE -4 59 #define ETHOSN_UNKNOWN_CORE_ADDRESS -5 60 #define ETHOSN_UNKNOWN_ALLOCATOR_IDX -6 61 #define ETHOSN_INVALID_CONFIGURATION -7 62 #define ETHOSN_INVALID_STATE -8 63 64 /* 65 * Argument types for soft and hard resets to indicate whether to reset 66 * and reconfigure the NPU or only halt it 67 */ 68 #define ETHOSN_RESET_TYPE_FULL U(0) 69 #define ETHOSN_RESET_TYPE_HALT U(1) 70 71 int ethosn_smc_setup(void); 72 73 uintptr_t ethosn_smc_handler(uint32_t smc_fid, 74 u_register_t core_addr, 75 u_register_t asset_alloc_idx, 76 u_register_t reset_type, 77 u_register_t x4, 78 void *cookie, 79 void *handle, 80 u_register_t flags); 81 82 #endif /* ETHOSN_H */ 83
