1 // Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 // 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 15 #ifndef _ROM_SPI_FLASH_H_ 16 #define _ROM_SPI_FLASH_H_ 17 18 #include <stdint.h> 19 #include <stdbool.h> 20 21 #include "esp_attr.h" 22 23 #include "sdkconfig.h" 24 25 #ifdef CONFIG_LEGACY_INCLUDE_COMMON_HEADERS 26 #include "soc/spi_reg.h" 27 #endif 28 29 #ifdef __cplusplus 30 extern "C" { 31 #endif 32 33 /** \defgroup spi_flash_apis, spi flash operation related apis 34 * @brief spi_flash apis 35 */ 36 37 /** @addtogroup spi_flash_apis 38 * @{ 39 */ 40 41 /************************************************************* 42 * Note 43 ************************************************************* 44 * 1. ESP32 chip have 4 SPI slave/master, however, SPI0 is 45 * used as an SPI master to access Flash and ext-SRAM by 46 * Cache module. It will support Decryto read for Flash, 47 * read/write for ext-SRAM. And SPI1 is also used as an 48 * SPI master for Flash read/write and ext-SRAM read/write. 49 * It will support Encrypto write for Flash. 50 * 2. As an SPI master, SPI support Highest clock to 80M, 51 * however, Flash with 80M Clock should be configured 52 * for different Flash chips. If you want to use 80M 53 * clock We should use the SPI that is certified by 54 * Espressif. However, the certification is not started 55 * at the time, so please use 40M clock at the moment. 56 * 3. SPI Flash can use 2 lines or 4 lines mode. If you 57 * use 2 lines mode, you can save two pad SPIHD and 58 * SPIWP for gpio. ESP32 support configured SPI pad for 59 * Flash, the configuration is stored in efuse and flash. 60 * However, the configurations of pads should be certified 61 * by Espressif. If you use this function, please use 40M 62 * clock at the moment. 63 * 4. ESP32 support to use Common SPI command to configure 64 * Flash to QIO mode, if you failed to configure with fix 65 * command. With Common SPI Command, ESP32 can also provide 66 * a way to use same Common SPI command groups on different 67 * Flash chips. 68 * 5. This functions are not protected by packeting, Please use the 69 ************************************************************* 70 */ 71 72 #define PERIPHS_SPI_FLASH_CMD SPI_CMD_REG(1) 73 #define PERIPHS_SPI_FLASH_ADDR SPI_ADDR_REG(1) 74 #define PERIPHS_SPI_FLASH_CTRL SPI_CTRL_REG(1) 75 #define PERIPHS_SPI_FLASH_CTRL1 SPI_CTRL1_REG(1) 76 #define PERIPHS_SPI_FLASH_STATUS SPI_RD_STATUS_REG(1) 77 #define PERIPHS_SPI_FLASH_USRREG SPI_USER_REG(1) 78 #define PERIPHS_SPI_FLASH_USRREG1 SPI_USER1_REG(1) 79 #define PERIPHS_SPI_FLASH_USRREG2 SPI_USER2_REG(1) 80 #define PERIPHS_SPI_FLASH_C0 SPI_W0_REG(1) 81 #define PERIPHS_SPI_FLASH_C1 SPI_W1_REG(1) 82 #define PERIPHS_SPI_FLASH_C2 SPI_W2_REG(1) 83 #define PERIPHS_SPI_FLASH_C3 SPI_W3_REG(1) 84 #define PERIPHS_SPI_FLASH_C4 SPI_W4_REG(1) 85 #define PERIPHS_SPI_FLASH_C5 SPI_W5_REG(1) 86 #define PERIPHS_SPI_FLASH_C6 SPI_W6_REG(1) 87 #define PERIPHS_SPI_FLASH_C7 SPI_W7_REG(1) 88 #define PERIPHS_SPI_FLASH_TX_CRC SPI_TX_CRC_REG(1) 89 90 #define SPI0_R_QIO_DUMMY_CYCLELEN 3 91 #define SPI0_R_QIO_ADDR_BITSLEN 31 92 #define SPI0_R_FAST_DUMMY_CYCLELEN 7 93 #define SPI0_R_DIO_DUMMY_CYCLELEN 1 94 #define SPI0_R_DIO_ADDR_BITSLEN 27 95 #define SPI0_R_FAST_ADDR_BITSLEN 23 96 #define SPI0_R_SIO_ADDR_BITSLEN 23 97 98 #define SPI1_R_QIO_DUMMY_CYCLELEN 3 99 #define SPI1_R_QIO_ADDR_BITSLEN 31 100 #define SPI1_R_FAST_DUMMY_CYCLELEN 7 101 #define SPI1_R_DIO_DUMMY_CYCLELEN 3 102 #define SPI1_R_DIO_ADDR_BITSLEN 31 103 #define SPI1_R_FAST_ADDR_BITSLEN 23 104 #define SPI1_R_SIO_ADDR_BITSLEN 23 105 106 #define ESP_ROM_SPIFLASH_W_SIO_ADDR_BITSLEN 23 107 108 #define ESP_ROM_SPIFLASH_TWO_BYTE_STATUS_EN SPI_WRSR_2B 109 110 //SPI address register 111 #define ESP_ROM_SPIFLASH_BYTES_LEN 24 112 #define ESP_ROM_SPIFLASH_BUFF_BYTE_WRITE_NUM 32 113 #define ESP_ROM_SPIFLASH_BUFF_BYTE_READ_NUM 64 114 #define ESP_ROM_SPIFLASH_BUFF_BYTE_READ_BITS 0x3f 115 116 //SPI status register 117 #define ESP_ROM_SPIFLASH_BUSY_FLAG BIT0 118 #define ESP_ROM_SPIFLASH_WRENABLE_FLAG BIT1 119 #define ESP_ROM_SPIFLASH_BP0 BIT2 120 #define ESP_ROM_SPIFLASH_BP1 BIT3 121 #define ESP_ROM_SPIFLASH_BP2 BIT4 122 #define ESP_ROM_SPIFLASH_WR_PROTECT (ESP_ROM_SPIFLASH_BP0|ESP_ROM_SPIFLASH_BP1|ESP_ROM_SPIFLASH_BP2) 123 #define ESP_ROM_SPIFLASH_QE BIT9 124 #define ESP_ROM_SPIFLASH_BP_MASK_ISSI (BIT7 | BIT5 | BIT4 | BIT3 | BIT2) 125 126 //Extra dummy for flash read 127 #define ESP_ROM_SPIFLASH_DUMMY_LEN_PLUS_20M 0 128 #define ESP_ROM_SPIFLASH_DUMMY_LEN_PLUS_26M 0 129 #define ESP_ROM_SPIFLASH_DUMMY_LEN_PLUS_40M 1 130 #define ESP_ROM_SPIFLASH_DUMMY_LEN_PLUS_80M 2 131 132 #define FLASH_ID_GD25LQ32C 0xC86016 133 134 typedef enum { 135 ESP_ROM_SPIFLASH_QIO_MODE = 0, 136 ESP_ROM_SPIFLASH_QOUT_MODE, 137 ESP_ROM_SPIFLASH_DIO_MODE, 138 ESP_ROM_SPIFLASH_DOUT_MODE, 139 ESP_ROM_SPIFLASH_FASTRD_MODE, 140 ESP_ROM_SPIFLASH_SLOWRD_MODE 141 } esp_rom_spiflash_read_mode_t; 142 143 typedef enum { 144 ESP_ROM_SPIFLASH_RESULT_OK, 145 ESP_ROM_SPIFLASH_RESULT_ERR, 146 ESP_ROM_SPIFLASH_RESULT_TIMEOUT 147 } esp_rom_spiflash_result_t; 148 149 typedef struct { 150 uint32_t device_id; 151 uint32_t chip_size; // chip size in bytes 152 uint32_t block_size; 153 uint32_t sector_size; 154 uint32_t page_size; 155 uint32_t status_mask; 156 } esp_rom_spiflash_chip_t; 157 158 typedef struct { 159 uint8_t data_length; 160 uint8_t read_cmd0; 161 uint8_t read_cmd1; 162 uint8_t write_cmd; 163 uint16_t data_mask; 164 uint16_t data; 165 } esp_rom_spiflash_common_cmd_t; 166 167 /** 168 * @brief Fix the bug in SPI hardware communication with Flash/Ext-SRAM in High Speed. 169 * Please do not call this function in SDK. 170 * 171 * @param uint8_t spi: 0 for SPI0(Cache Access), 1 for SPI1(Flash read/write). 172 * 173 * @param uint8_t freqdiv: Pll is 80M, 4 for 20M, 3 for 26.7M, 2 for 40M, 1 for 80M. 174 * 175 * @return None 176 */ 177 void esp_rom_spiflash_fix_dummylen(uint8_t spi, uint8_t freqdiv); 178 179 /** 180 * @brief Select SPI Flash to QIO mode when WP pad is read from Flash. 181 * Please do not call this function in SDK. 182 * 183 * @param uint8_t wp_gpio_num: WP gpio number. 184 * 185 * @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping 186 * else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd 187 * 188 * @return None 189 */ 190 void esp_rom_spiflash_select_qiomode(uint8_t wp_gpio_num, uint32_t ishspi); 191 192 /** 193 * @brief Set SPI Flash pad drivers. 194 * Please do not call this function in SDK. 195 * 196 * @param uint8_t wp_gpio_num: WP gpio number. 197 * 198 * @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping 199 * else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd 200 * 201 * @param uint8_t *drvs: drvs[0]-bit[3:0] for cpiclk, bit[7:4] for spiq, drvs[1]-bit[3:0] for spid, drvs[1]-bit[7:4] for spid 202 * drvs[2]-bit[3:0] for spihd, drvs[2]-bit[7:4] for spiwp. 203 * Values usually read from falsh by rom code, function usually callde by rom code. 204 * if value with bit(3) set, the value is valid, bit[2:0] is the real value. 205 * 206 * @return None 207 */ 208 void esp_rom_spiflash_set_drvs(uint8_t wp_gpio_num, uint32_t ishspi, uint8_t *drvs); 209 210 /** 211 * @brief Select SPI Flash function for pads. 212 * Please do not call this function in SDK. 213 * 214 * @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping 215 * else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd 216 * 217 * @return None 218 */ 219 void esp_rom_spiflash_select_padsfunc(uint32_t ishspi); 220 221 /** 222 * @brief SPI Flash init, clock divisor is 4, use 1 line Slow read mode. 223 * Please do not call this function in SDK. 224 * 225 * @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping 226 * else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd 227 * 228 * @param uint8_t legacy: In legacy mode, more SPI command is used in line. 229 * 230 * @return None 231 */ 232 void esp_rom_spiflash_attach(uint32_t ishspi, bool legacy); 233 234 /** 235 * @brief SPI Read Flash status register. We use CMD 0x05 (RDSR). 236 * Please do not call this function in SDK. 237 * 238 * @param esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file. 239 * 240 * @param uint32_t *status : The pointer to which to return the Flash status value. 241 * 242 * @return ESP_ROM_SPIFLASH_RESULT_OK : read OK. 243 * ESP_ROM_SPIFLASH_RESULT_ERR : read error. 244 * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : read timeout. 245 */ 246 esp_rom_spiflash_result_t esp_rom_spiflash_read_status(esp_rom_spiflash_chip_t *spi, uint32_t *status); 247 248 /** 249 * @brief SPI Read Flash status register bits 8-15. We use CMD 0x35 (RDSR2). 250 * Please do not call this function in SDK. 251 * 252 * @param esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file. 253 * 254 * @param uint32_t *status : The pointer to which to return the Flash status value. 255 * 256 * @return ESP_ROM_SPIFLASH_RESULT_OK : read OK. 257 * ESP_ROM_SPIFLASH_RESULT_ERR : read error. 258 * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : read timeout. 259 */ 260 esp_rom_spiflash_result_t esp_rom_spiflash_read_statushigh(esp_rom_spiflash_chip_t *spi, uint32_t *status); 261 262 /** 263 * @brief Write status to Flash status register. 264 * Please do not call this function in SDK. 265 * 266 * @param esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file. 267 * 268 * @param uint32_t status_value : Value to . 269 * 270 * @return ESP_ROM_SPIFLASH_RESULT_OK : write OK. 271 * ESP_ROM_SPIFLASH_RESULT_ERR : write error. 272 * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : write timeout. 273 */ 274 esp_rom_spiflash_result_t esp_rom_spiflash_write_status(esp_rom_spiflash_chip_t *spi, uint32_t status_value); 275 276 /** 277 * @brief Use a command to Read Flash status register. 278 * Please do not call this function in SDK. 279 * 280 * @param esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file. 281 * 282 * @param uint32_t*status : The pointer to which to return the Flash status value. 283 * 284 * @return ESP_ROM_SPIFLASH_RESULT_OK : read OK. 285 * ESP_ROM_SPIFLASH_RESULT_ERR : read error. 286 * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : read timeout. 287 */ 288 esp_rom_spiflash_result_t esp_rom_spiflash_read_user_cmd(uint32_t *status, uint8_t cmd); 289 290 /** 291 * @brief Config SPI Flash read mode when init. 292 * Please do not call this function in SDK. 293 * 294 * @param esp_rom_spiflash_read_mode_t mode : QIO/QOUT/DIO/DOUT/FastRD/SlowRD. 295 * 296 * This function does not try to set the QIO Enable bit in the status register, caller is responsible for this. 297 * 298 * @return ESP_ROM_SPIFLASH_RESULT_OK : config OK. 299 * ESP_ROM_SPIFLASH_RESULT_ERR : config error. 300 * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : config timeout. 301 */ 302 esp_rom_spiflash_result_t esp_rom_spiflash_config_readmode(esp_rom_spiflash_read_mode_t mode); 303 304 /** 305 * @brief Config SPI Flash clock divisor. 306 * Please do not call this function in SDK. 307 * 308 * @param uint8_t freqdiv: clock divisor. 309 * 310 * @param uint8_t spi: 0 for SPI0, 1 for SPI1. 311 * 312 * @return ESP_ROM_SPIFLASH_RESULT_OK : config OK. 313 * ESP_ROM_SPIFLASH_RESULT_ERR : config error. 314 * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : config timeout. 315 */ 316 esp_rom_spiflash_result_t esp_rom_spiflash_config_clk(uint8_t freqdiv, uint8_t spi); 317 318 /** 319 * @brief Send CommonCmd to Flash so that is can go into QIO mode, some Flash use different CMD. 320 * Please do not call this function in SDK. 321 * 322 * @param esp_rom_spiflash_common_cmd_t *cmd : A struct to show the action of a command. 323 * 324 * @return uint16_t 0 : do not send command any more. 325 * 1 : go to the next command. 326 * n > 1 : skip (n - 1) commands. 327 */ 328 uint16_t esp_rom_spiflash_common_cmd(esp_rom_spiflash_common_cmd_t *cmd); 329 330 /** 331 * @brief Unlock SPI write protect. 332 * Please do not call this function in SDK. 333 * 334 * @param None. 335 * 336 * @return ESP_ROM_SPIFLASH_RESULT_OK : Unlock OK. 337 * ESP_ROM_SPIFLASH_RESULT_ERR : Unlock error. 338 * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Unlock timeout. 339 */ 340 esp_rom_spiflash_result_t esp_rom_spiflash_unlock(void); 341 342 /** 343 * @brief SPI write protect. 344 * Please do not call this function in SDK. 345 * 346 * @param None. 347 * 348 * @return ESP_ROM_SPIFLASH_RESULT_OK : Lock OK. 349 * ESP_ROM_SPIFLASH_RESULT_ERR : Lock error. 350 * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Lock timeout. 351 */ 352 esp_rom_spiflash_result_t esp_rom_spiflash_lock(void); 353 354 /** 355 * @brief Update SPI Flash parameter. 356 * Please do not call this function in SDK. 357 * 358 * @param uint32_t deviceId : Device ID read from SPI, the low 32 bit. 359 * 360 * @param uint32_t chip_size : The Flash size. 361 * 362 * @param uint32_t block_size : The Flash block size. 363 * 364 * @param uint32_t sector_size : The Flash sector size. 365 * 366 * @param uint32_t page_size : The Flash page size. 367 * 368 * @param uint32_t status_mask : The Mask used when read status from Flash(use single CMD). 369 * 370 * @return ESP_ROM_SPIFLASH_RESULT_OK : Update OK. 371 * ESP_ROM_SPIFLASH_RESULT_ERR : Update error. 372 * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Update timeout. 373 */ 374 esp_rom_spiflash_result_t esp_rom_spiflash_config_param(uint32_t deviceId, uint32_t chip_size, uint32_t block_size, 375 uint32_t sector_size, uint32_t page_size, uint32_t status_mask); 376 377 /** 378 * @brief Erase whole flash chip. 379 * Please do not call this function in SDK. 380 * 381 * @param None 382 * 383 * @return ESP_ROM_SPIFLASH_RESULT_OK : Erase OK. 384 * ESP_ROM_SPIFLASH_RESULT_ERR : Erase error. 385 * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Erase timeout. 386 */ 387 esp_rom_spiflash_result_t esp_rom_spiflash_erase_chip(void); 388 389 /** 390 * @brief Erase a 64KB block of flash 391 * Uses SPI flash command D8H. 392 * Please do not call this function in SDK. 393 * 394 * @param uint32_t block_num : Which block to erase. 395 * 396 * @return ESP_ROM_SPIFLASH_RESULT_OK : Erase OK. 397 * ESP_ROM_SPIFLASH_RESULT_ERR : Erase error. 398 * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Erase timeout. 399 */ 400 esp_rom_spiflash_result_t esp_rom_spiflash_erase_block(uint32_t block_num); 401 402 /** 403 * @brief Erase a sector of flash. 404 * Uses SPI flash command 20H. 405 * Please do not call this function in SDK. 406 * 407 * @param uint32_t sector_num : Which sector to erase. 408 * 409 * @return ESP_ROM_SPIFLASH_RESULT_OK : Erase OK. 410 * ESP_ROM_SPIFLASH_RESULT_ERR : Erase error. 411 * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Erase timeout. 412 */ 413 esp_rom_spiflash_result_t esp_rom_spiflash_erase_sector(uint32_t sector_num); 414 415 /** 416 * @brief Erase some sectors. 417 * Please do not call this function in SDK. 418 * 419 * @param uint32_t start_addr : Start addr to erase, should be sector aligned. 420 * 421 * @param uint32_t area_len : Length to erase, should be sector aligned. 422 * 423 * @return ESP_ROM_SPIFLASH_RESULT_OK : Erase OK. 424 * ESP_ROM_SPIFLASH_RESULT_ERR : Erase error. 425 * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Erase timeout. 426 */ 427 esp_rom_spiflash_result_t esp_rom_spiflash_erase_area(uint32_t start_addr, uint32_t area_len); 428 429 /** 430 * @brief Write Data to Flash, you should Erase it yourself if need. 431 * Please do not call this function in SDK. 432 * 433 * @param uint32_t dest_addr : Address to write, should be 4 bytes aligned. 434 * 435 * @param const uint32_t *src : The pointer to data which is to write. 436 * 437 * @param uint32_t len : Length to write, should be 4 bytes aligned. 438 * 439 * @return ESP_ROM_SPIFLASH_RESULT_OK : Write OK. 440 * ESP_ROM_SPIFLASH_RESULT_ERR : Write error. 441 * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Write timeout. 442 */ 443 esp_rom_spiflash_result_t esp_rom_spiflash_write(uint32_t dest_addr, const uint32_t *src, int32_t len); 444 445 /** 446 * @brief Read Data from Flash, you should Erase it yourself if need. 447 * Please do not call this function in SDK. 448 * 449 * @param uint32_t src_addr : Address to read, should be 4 bytes aligned. 450 * 451 * @param uint32_t *dest : The buf to read the data. 452 * 453 * @param uint32_t len : Length to read, should be 4 bytes aligned. 454 * 455 * @return ESP_ROM_SPIFLASH_RESULT_OK : Read OK. 456 * ESP_ROM_SPIFLASH_RESULT_ERR : Read error. 457 * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Read timeout. 458 */ 459 esp_rom_spiflash_result_t esp_rom_spiflash_read(uint32_t src_addr, uint32_t *dest, int32_t len); 460 461 /** 462 * @brief SPI1 go into encrypto mode. 463 * Please do not call this function in SDK. 464 * 465 * @param None 466 * 467 * @return None 468 */ 469 void esp_rom_spiflash_write_encrypted_enable(void); 470 471 /** 472 * @brief Prepare 32 Bytes data to encrpto writing, you should Erase it yourself if need. 473 * Please do not call this function in SDK. 474 * 475 * @param uint32_t flash_addr : Address to write, should be 32 bytes aligned. 476 * 477 * @param uint32_t *data : The pointer to data which is to write. 478 * 479 * @return ESP_ROM_SPIFLASH_RESULT_OK : Prepare OK. 480 * ESP_ROM_SPIFLASH_RESULT_ERR : Prepare error. 481 * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Prepare timeout. 482 */ 483 esp_rom_spiflash_result_t esp_rom_spiflash_prepare_encrypted_data(uint32_t flash_addr, uint32_t *data); 484 485 /** 486 * @brief SPI1 go out of encrypto mode. 487 * Please do not call this function in SDK. 488 * 489 * @param None 490 * 491 * @return None 492 */ 493 void esp_rom_spiflash_write_encrypted_disable(void); 494 495 /** 496 * @brief Write data to flash with transparent encryption. 497 * @note Sectors to be written should already be erased. 498 * 499 * @note Please do not call this function in SDK. 500 * 501 * @param uint32_t flash_addr : Address to write, should be 32 byte aligned. 502 * 503 * @param uint32_t *data : The pointer to data to write. Note, this pointer must 504 * be 32 bit aligned and the content of the data will be 505 * modified by the encryption function. 506 * 507 * @param uint32_t len : Length to write, should be 32 bytes aligned. 508 * 509 * @return ESP_ROM_SPIFLASH_RESULT_OK : Data written successfully. 510 * ESP_ROM_SPIFLASH_RESULT_ERR : Encryption write error. 511 * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Encrypto write timeout. 512 */ 513 esp_rom_spiflash_result_t esp_rom_spiflash_write_encrypted(uint32_t flash_addr, uint32_t *data, uint32_t len); 514 515 516 /** @brief Wait until SPI flash write operation is complete 517 * 518 * @note Please do not call this function in SDK. 519 * 520 * Reads the Write In Progress bit of the SPI flash status register, 521 * repeats until this bit is zero (indicating write complete). 522 * 523 * @return ESP_ROM_SPIFLASH_RESULT_OK : Write is complete 524 * ESP_ROM_SPIFLASH_RESULT_ERR : Error while reading status. 525 */ 526 esp_rom_spiflash_result_t esp_rom_spiflash_wait_idle(esp_rom_spiflash_chip_t *spi); 527 528 529 /** @brief Enable Quad I/O pin functions 530 * 531 * @note Please do not call this function in SDK. 532 * 533 * Sets the HD & WP pin functions for Quad I/O modes, based on the 534 * efuse SPI pin configuration. 535 * 536 * @param wp_gpio_num - Number of the WP pin to reconfigure for quad I/O. 537 * 538 * @param spiconfig - Pin configuration, as returned from ets_efuse_get_spiconfig(). 539 * - If this parameter is 0, default SPI pins are used and wp_gpio_num parameter is ignored. 540 * - If this parameter is 1, default HSPI pins are used and wp_gpio_num parameter is ignored. 541 * - For other values, this parameter encodes the HD pin number and also the CLK pin number. CLK pin selection is used 542 * to determine if HSPI or SPI peripheral will be used (use HSPI if CLK pin is the HSPI clock pin, otherwise use SPI). 543 * Both HD & WP pins are configured via GPIO matrix to map to the selected peripheral. 544 */ 545 void esp_rom_spiflash_select_qio_pins(uint8_t wp_gpio_num, uint32_t spiconfig); 546 547 /** 548 * @brief Clear WEL bit unconditionally. 549 * 550 * @return always ESP_ROM_SPIFLASH_RESULT_OK 551 */ 552 esp_rom_spiflash_result_t esp_rom_spiflash_write_disable(void); 553 554 /** @brief Global esp_rom_spiflash_chip_t structure used by ROM functions 555 * 556 */ 557 extern esp_rom_spiflash_chip_t g_rom_flashchip; 558 559 extern uint8_t g_rom_spiflash_dummy_len_plus[]; 560 561 /** 562 * @} 563 */ 564 565 #ifdef __cplusplus 566 } 567 #endif 568 569 #endif /* _ROM_SPI_FLASH_H_ */ 570
