1 // Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at", 6 // 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License 14 15 #include "sdkconfig.h" 16 #include "esp_efuse.h" 17 #include <assert.h> 18 #include "esp_efuse_table.h" 19 20 // md5_digest_table f9a84eb22f94a7bc083b4c6817a33a59 21 // This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY. 22 // If you want to change some fields, you need to change esp_efuse_table.csv file 23 // then run `efuse_common_table` or `efuse_custom_table` command it will generate this file. 24 // To show efuse_table run the command 'show_efuse_table'. 25 26 static const esp_efuse_desc_t WR_DIS_RD_DIS[] = { 27 {EFUSE_BLK0, 0, 1}, // Write protection for RD_DIS_KEY0 RD_DIS_KEY1 RD_DIS_KEY2 RD_DIS_KEY3 RD_DIS_KEY4 RD_DIS_KEY5 RD_DIS_SYS_DATA_PART2, 28 }; 29 30 static const esp_efuse_desc_t WR_DIS_GROUP_1[] = { 31 {EFUSE_BLK0, 2, 1}, // Write protection for DIS_ICACHE DIS_DOWNLOAD_ICACHE DIS_FORCE_DOWNLOAD DIS_USB DIS_CAN SOFT_DIS_JTAG DIS_DOWNLOAD_MANUAL_ENCRYPT, 32 }; 33 34 static const esp_efuse_desc_t WR_DIS_GROUP_2[] = { 35 {EFUSE_BLK0, 3, 1}, // Write protection for WDT_DELAY_SEL, 36 }; 37 38 static const esp_efuse_desc_t WR_DIS_SPI_BOOT_CRYPT_CNT[] = { 39 {EFUSE_BLK0, 4, 1}, // Write protection for SPI_BOOT_CRYPT_CNT, 40 }; 41 42 static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_KEY_REVOKE0[] = { 43 {EFUSE_BLK0, 5, 1}, // Write protection for SECURE_BOOT_KEY_REVOKE0, 44 }; 45 46 static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_KEY_REVOKE1[] = { 47 {EFUSE_BLK0, 6, 1}, // Write protection for SECURE_BOOT_KEY_REVOKE1, 48 }; 49 50 static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_KEY_REVOKE2[] = { 51 {EFUSE_BLK0, 7, 1}, // Write protection for SECURE_BOOT_KEY_REVOKE2, 52 }; 53 54 static const esp_efuse_desc_t WR_DIS_KEY0_PURPOSE[] = { 55 {EFUSE_BLK0, 8, 1}, // Write protection for key_purpose. KEY0, 56 }; 57 58 static const esp_efuse_desc_t WR_DIS_KEY1_PURPOSE[] = { 59 {EFUSE_BLK0, 9, 1}, // Write protection for key_purpose. KEY1, 60 }; 61 62 static const esp_efuse_desc_t WR_DIS_KEY2_PURPOSE[] = { 63 {EFUSE_BLK0, 10, 1}, // Write protection for key_purpose. KEY2, 64 }; 65 66 static const esp_efuse_desc_t WR_DIS_KEY3_PURPOSE[] = { 67 {EFUSE_BLK0, 11, 1}, // Write protection for key_purpose. KEY3, 68 }; 69 70 static const esp_efuse_desc_t WR_DIS_KEY4_PURPOSE[] = { 71 {EFUSE_BLK0, 12, 1}, // Write protection for key_purpose. KEY4, 72 }; 73 74 static const esp_efuse_desc_t WR_DIS_KEY5_PURPOSE[] = { 75 {EFUSE_BLK0, 13, 1}, // Write protection for key_purpose. KEY5, 76 }; 77 78 static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_EN[] = { 79 {EFUSE_BLK0, 15, 1}, // Write protection for SECURE_BOOT_EN, 80 }; 81 82 static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[] = { 83 {EFUSE_BLK0, 16, 1}, // Write protection for SECURE_BOOT_AGGRESSIVE_REVOKE, 84 }; 85 86 static const esp_efuse_desc_t WR_DIS_GROUP_3[] = { 87 {EFUSE_BLK0, 18, 1}, // Write protection for FLASH_TPUW DIS_DOWNLOAD_MODE DIS_LEGACY_SPI_BOOT UART_PRINT_CHANNEL DIS_TINY_BASIC DIS_USB_DOWNLOAD_MODE ENABLE_SECURITY_DOWNLOAD UART_PRINT_CONTROL PIN_POWER_SELECTION FLASH_TYPE FORCE_SEND_RESUME SECURE_VERSION, 88 }; 89 90 static const esp_efuse_desc_t WR_DIS_BLK1[] = { 91 {EFUSE_BLK0, 20, 1}, // Write protection for EFUSE_BLK1. MAC_SPI_8M_SYS, 92 }; 93 94 static const esp_efuse_desc_t WR_DIS_SYS_DATA_PART1[] = { 95 {EFUSE_BLK0, 21, 1}, // Write protection for EFUSE_BLK2. SYS_DATA_PART1, 96 }; 97 98 static const esp_efuse_desc_t WR_DIS_USER_DATA[] = { 99 {EFUSE_BLK0, 22, 1}, // Write protection for EFUSE_BLK3. USER_DATA, 100 }; 101 102 static const esp_efuse_desc_t WR_DIS_KEY0[] = { 103 {EFUSE_BLK0, 23, 1}, // Write protection for EFUSE_BLK4. KEY0, 104 }; 105 106 static const esp_efuse_desc_t WR_DIS_KEY1[] = { 107 {EFUSE_BLK0, 24, 1}, // Write protection for EFUSE_BLK5. KEY1, 108 }; 109 110 static const esp_efuse_desc_t WR_DIS_KEY2[] = { 111 {EFUSE_BLK0, 25, 1}, // Write protection for EFUSE_BLK6. KEY2, 112 }; 113 114 static const esp_efuse_desc_t WR_DIS_KEY3[] = { 115 {EFUSE_BLK0, 26, 1}, // Write protection for EFUSE_BLK7. KEY3, 116 }; 117 118 static const esp_efuse_desc_t WR_DIS_KEY4[] = { 119 {EFUSE_BLK0, 27, 1}, // Write protection for EFUSE_BLK8. KEY4, 120 }; 121 122 static const esp_efuse_desc_t WR_DIS_KEY5[] = { 123 {EFUSE_BLK0, 28, 1}, // Write protection for EFUSE_BLK9. KEY5, 124 }; 125 126 static const esp_efuse_desc_t WR_DIS_SYS_DATA_PART2[] = { 127 {EFUSE_BLK0, 29, 1}, // Write protection for EFUSE_BLK10. SYS_DATA_PART2, 128 }; 129 130 static const esp_efuse_desc_t RD_DIS_KEY0[] = { 131 {EFUSE_BLK0, 32, 1}, // Read protection for EFUSE_BLK4. KEY0, 132 }; 133 134 static const esp_efuse_desc_t RD_DIS_KEY1[] = { 135 {EFUSE_BLK0, 33, 1}, // Read protection for EFUSE_BLK5. KEY1, 136 }; 137 138 static const esp_efuse_desc_t RD_DIS_KEY2[] = { 139 {EFUSE_BLK0, 34, 1}, // Read protection for EFUSE_BLK6. KEY2, 140 }; 141 142 static const esp_efuse_desc_t RD_DIS_KEY3[] = { 143 {EFUSE_BLK0, 35, 1}, // Read protection for EFUSE_BLK7. KEY3, 144 }; 145 146 static const esp_efuse_desc_t RD_DIS_KEY4[] = { 147 {EFUSE_BLK0, 36, 1}, // Read protection for EFUSE_BLK8. KEY4, 148 }; 149 150 static const esp_efuse_desc_t RD_DIS_KEY5[] = { 151 {EFUSE_BLK0, 37, 1}, // Read protection for EFUSE_BLK9. KEY5, 152 }; 153 154 static const esp_efuse_desc_t RD_DIS_SYS_DATA_PART2[] = { 155 {EFUSE_BLK0, 38, 1}, // Read protection for EFUSE_BLK10. SYS_DATA_PART2, 156 }; 157 158 static const esp_efuse_desc_t DIS_RTC_RAM_BOOT[] = { 159 {EFUSE_BLK0, 39, 1}, // Disable boot from RTC RAM, 160 }; 161 162 static const esp_efuse_desc_t DIS_ICACHE[] = { 163 {EFUSE_BLK0, 40, 1}, // Disable Icache, 164 }; 165 166 static const esp_efuse_desc_t DIS_USB_JTAG[] = { 167 {EFUSE_BLK0, 41, 1}, // Disable USB JTAG, 168 }; 169 170 static const esp_efuse_desc_t DIS_DOWNLOAD_ICACHE[] = { 171 {EFUSE_BLK0, 42, 1}, // Disable Icache in download mode, 172 }; 173 174 static const esp_efuse_desc_t DIS_USB_DEVICE[] = { 175 {EFUSE_BLK0, 43, 1}, // Disable USB_DEVICE, 176 }; 177 178 static const esp_efuse_desc_t DIS_FORCE_DOWNLOAD[] = { 179 {EFUSE_BLK0, 44, 1}, // Disable force chip go to download mode function, 180 }; 181 182 static const esp_efuse_desc_t DIS_USB[] = { 183 {EFUSE_BLK0, 45, 1}, // Disable USB function, 184 }; 185 186 static const esp_efuse_desc_t DIS_CAN[] = { 187 {EFUSE_BLK0, 46, 1}, // Disable CAN function, 188 }; 189 190 static const esp_efuse_desc_t JTAG_SEL_ENABLE[] = { 191 {EFUSE_BLK0, 47, 1}, // Set this bit to enable selection between usb_to_jtag and pad_to_jtag through strapping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0., 192 }; 193 194 static const esp_efuse_desc_t SOFT_DIS_JTAG[] = { 195 {EFUSE_BLK0, 48, 2}, // Set these bits to disable JTAG in the soft way (odd number 1 means disable). JTAG can be enabled in HMAC module., 196 }; 197 198 static const esp_efuse_desc_t DIS_PAD_JTAG[] = { 199 {EFUSE_BLK0, 51, 1}, // Disable JTAG in the hard way. JTAG is disabled permanently., 200 }; 201 202 static const esp_efuse_desc_t DIS_DOWNLOAD_MANUAL_ENCRYPT[] = { 203 {EFUSE_BLK0, 52, 1}, // Disable flash encryption when in download boot modes., 204 }; 205 206 static const esp_efuse_desc_t USB_DREFH[] = { 207 {EFUSE_BLK0, 53, 2}, // Controls single-end input threshold vrefh 1.76 V to 2 V with step of 80 mV stored in eFuse., 208 }; 209 210 static const esp_efuse_desc_t USB_DREFL[] = { 211 {EFUSE_BLK0, 55, 2}, // Controls single-end input threshold vrefl 0.8 V to 1.04 V with step of 80 mV stored in eFuse., 212 }; 213 214 static const esp_efuse_desc_t USB_EXCHG_PINS[] = { 215 {EFUSE_BLK0, 57, 1}, // Exchange D+ D- pins, 216 }; 217 218 static const esp_efuse_desc_t VDD_SPI_AS_GPIO[] = { 219 {EFUSE_BLK0, 58, 1}, // Set this bit to vdd spi pin function as gpio, 220 }; 221 222 static const esp_efuse_desc_t BTLC_GPIO_ENABLE[] = { 223 {EFUSE_BLK0, 59, 2}, // Enable btlc gpio, 224 }; 225 226 static const esp_efuse_desc_t POWERGLITCH_EN[] = { 227 {EFUSE_BLK0, 61, 1}, // Set this bit to enable power glitch function, 228 }; 229 230 static const esp_efuse_desc_t POWER_GLITCH_DSENSE[] = { 231 {EFUSE_BLK0, 62, 2}, // Sample delay configuration of power glitch, 232 }; 233 234 static const esp_efuse_desc_t WDT_DELAY_SEL[] = { 235 {EFUSE_BLK0, 80, 2}, // Select RTC WDT time out threshold, 236 }; 237 238 static const esp_efuse_desc_t SPI_BOOT_CRYPT_CNT[] = { 239 {EFUSE_BLK0, 82, 3}, // SPI boot encrypt decrypt enable. odd number 1 enable. even number 1 disable, 240 }; 241 242 static const esp_efuse_desc_t SECURE_BOOT_KEY_REVOKE0[] = { 243 {EFUSE_BLK0, 85, 1}, // Enable revoke first secure boot key, 244 }; 245 246 static const esp_efuse_desc_t SECURE_BOOT_KEY_REVOKE1[] = { 247 {EFUSE_BLK0, 86, 1}, // Enable revoke second secure boot key, 248 }; 249 250 static const esp_efuse_desc_t SECURE_BOOT_KEY_REVOKE2[] = { 251 {EFUSE_BLK0, 87, 1}, // Enable revoke third secure boot key, 252 }; 253 254 static const esp_efuse_desc_t KEY_PURPOSE_0[] = { 255 {EFUSE_BLK0, 88, 4}, // Key0 purpose, 256 }; 257 258 static const esp_efuse_desc_t KEY_PURPOSE_1[] = { 259 {EFUSE_BLK0, 92, 4}, // Key1 purpose, 260 }; 261 262 static const esp_efuse_desc_t KEY_PURPOSE_2[] = { 263 {EFUSE_BLK0, 96, 4}, // Key2 purpose, 264 }; 265 266 static const esp_efuse_desc_t KEY_PURPOSE_3[] = { 267 {EFUSE_BLK0, 100, 4}, // Key3 purpose, 268 }; 269 270 static const esp_efuse_desc_t KEY_PURPOSE_4[] = { 271 {EFUSE_BLK0, 104, 4}, // Key4 purpose, 272 }; 273 274 static const esp_efuse_desc_t KEY_PURPOSE_5[] = { 275 {EFUSE_BLK0, 108, 4}, // Key5 purpose, 276 }; 277 278 static const esp_efuse_desc_t SECURE_BOOT_EN[] = { 279 {EFUSE_BLK0, 116, 1}, // Secure boot enable, 280 }; 281 282 static const esp_efuse_desc_t SECURE_BOOT_AGGRESSIVE_REVOKE[] = { 283 {EFUSE_BLK0, 117, 1}, // Enable aggressive secure boot revoke, 284 }; 285 286 static const esp_efuse_desc_t FLASH_TPUW[] = { 287 {EFUSE_BLK0, 124, 4}, // Flash wait time after power up. (unit is ms). When value is 15. the time is 30 ms, 288 }; 289 290 static const esp_efuse_desc_t DIS_DOWNLOAD_MODE[] = { 291 {EFUSE_BLK0, 128, 1}, // Disble download mode include boot_mode[3:0] is 0 1 2 3 6 7, 292 }; 293 294 static const esp_efuse_desc_t DIS_LEGACY_SPI_BOOT[] = { 295 {EFUSE_BLK0, 129, 1}, // Disable_Legcy_SPI_boot mode include boot_mode[3:0] is 4, 296 }; 297 298 static const esp_efuse_desc_t UART_PRINT_CHANNEL[] = { 299 {EFUSE_BLK0, 130, 1}, // 0: UART0. 1: UART1, 300 }; 301 302 static const esp_efuse_desc_t FLASH_ECC_MODE[] = { 303 {EFUSE_BLK0, 131, 1}, // Set this bit to set flsah ecc mode. 0:flash ecc 16to18 byte mode. 1:flash ecc 16to17 byte mode, 304 }; 305 306 static const esp_efuse_desc_t DIS_USB_DOWNLOAD_MODE[] = { 307 {EFUSE_BLK0, 132, 1}, // Disable download through USB, 308 }; 309 310 static const esp_efuse_desc_t ENABLE_SECURITY_DOWNLOAD[] = { 311 {EFUSE_BLK0, 133, 1}, // Enable security download mode, 312 }; 313 314 static const esp_efuse_desc_t UART_PRINT_CONTROL[] = { 315 {EFUSE_BLK0, 134, 2}, // b00:force print. b01:control by GPIO8 - low level print. b10:control by GPIO8 - high level print. b11:force disable print., 316 }; 317 318 static const esp_efuse_desc_t PIN_POWER_SELECTION[] = { 319 {EFUSE_BLK0, 136, 1}, // GPIO33-GPIO37 power supply selection in ROM code. 0:VDD3P3_CPU. 1:VDD_SPI., 320 }; 321 322 static const esp_efuse_desc_t FLASH_TYPE[] = { 323 {EFUSE_BLK0, 137, 1}, // Connected Flash interface type. 0: 4 data line. 1: 8 data line, 324 }; 325 326 static const esp_efuse_desc_t FLASH_PAGE_SIZE[] = { 327 {EFUSE_BLK0, 138, 2}, // Flash page size, 328 }; 329 330 static const esp_efuse_desc_t FLASH_ECC_EN[] = { 331 {EFUSE_BLK0, 140, 1}, // Enable ECC for flash boot, 332 }; 333 334 static const esp_efuse_desc_t FORCE_SEND_RESUME[] = { 335 {EFUSE_BLK0, 141, 1}, // Force ROM code to send a resume command during SPI boot, 336 }; 337 338 static const esp_efuse_desc_t SECURE_VERSION[] = { 339 {EFUSE_BLK0, 142, 16}, // Secure version for anti-rollback, 340 }; 341 342 static const esp_efuse_desc_t MAC_FACTORY[] = { 343 {EFUSE_BLK1, 40, 8}, // Factory MAC addr [0], 344 {EFUSE_BLK1, 32, 8}, // Factory MAC addr [1], 345 {EFUSE_BLK1, 24, 8}, // Factory MAC addr [2], 346 {EFUSE_BLK1, 16, 8}, // Factory MAC addr [3], 347 {EFUSE_BLK1, 8, 8}, // Factory MAC addr [4], 348 {EFUSE_BLK1, 0, 8}, // Factory MAC addr [5], 349 }; 350 351 static const esp_efuse_desc_t SPI_PAD_CONFIG_CLK[] = { 352 {EFUSE_BLK1, 48, 6}, // SPI_PAD_configure CLK, 353 }; 354 355 static const esp_efuse_desc_t SPI_PAD_CONFIG_Q_D1[] = { 356 {EFUSE_BLK1, 54, 6}, // SPI_PAD_configure Q(D1), 357 }; 358 359 static const esp_efuse_desc_t SPI_PAD_CONFIG_D_D0[] = { 360 {EFUSE_BLK1, 60, 6}, // SPI_PAD_configure D(D0), 361 }; 362 363 static const esp_efuse_desc_t SPI_PAD_CONFIG_CS[] = { 364 {EFUSE_BLK1, 66, 6}, // SPI_PAD_configure CS, 365 }; 366 367 static const esp_efuse_desc_t SPI_PAD_CONFIG_HD_D3[] = { 368 {EFUSE_BLK1, 72, 6}, // SPI_PAD_configure HD(D3), 369 }; 370 371 static const esp_efuse_desc_t SPI_PAD_CONFIG_WP_D2[] = { 372 {EFUSE_BLK1, 78, 6}, // SPI_PAD_configure WP(D2), 373 }; 374 375 static const esp_efuse_desc_t SPI_PAD_CONFIG_DQS[] = { 376 {EFUSE_BLK1, 84, 6}, // SPI_PAD_configure DQS, 377 }; 378 379 static const esp_efuse_desc_t SPI_PAD_CONFIG_D4[] = { 380 {EFUSE_BLK1, 90, 6}, // SPI_PAD_configure D4, 381 }; 382 383 static const esp_efuse_desc_t SPI_PAD_CONFIG_D5[] = { 384 {EFUSE_BLK1, 96, 6}, // SPI_PAD_configure D5, 385 }; 386 387 static const esp_efuse_desc_t SPI_PAD_CONFIG_D6[] = { 388 {EFUSE_BLK1, 102, 6}, // SPI_PAD_configure D6, 389 }; 390 391 static const esp_efuse_desc_t SPI_PAD_CONFIG_D7[] = { 392 {EFUSE_BLK1, 108, 6}, // SPI_PAD_configure D7, 393 }; 394 395 static const esp_efuse_desc_t WAFER_VERSION[] = { 396 {EFUSE_BLK1, 114, 3}, // WAFER version, 397 }; 398 399 static const esp_efuse_desc_t PKG_VERSION[] = { 400 {EFUSE_BLK1, 117, 3}, // Package version 0:ESP32C3, 401 }; 402 403 static const esp_efuse_desc_t BLOCK1_VERSION[] = { 404 {EFUSE_BLK1, 120, 3}, // BLOCK1 efuse version, 405 }; 406 407 static const esp_efuse_desc_t OPTIONAL_UNIQUE_ID[] = { 408 {EFUSE_BLK2, 0, 128}, // Optional unique 128-bit ID, 409 }; 410 411 static const esp_efuse_desc_t BLOCK2_VERSION[] = { 412 {EFUSE_BLK2, 128, 3}, // Version of BLOCK2, 413 }; 414 415 static const esp_efuse_desc_t TEMP_CALIB[] = { 416 {EFUSE_BLK2, 131, 9}, // Temperature calibration data, 417 }; 418 419 static const esp_efuse_desc_t OCODE[] = { 420 {EFUSE_BLK2, 140, 8}, // ADC OCode, 421 }; 422 423 static const esp_efuse_desc_t ADC1_INIT_CODE_ATTEN0[] = { 424 {EFUSE_BLK2, 148, 10}, // ADC1 init code at atten0, 425 }; 426 427 static const esp_efuse_desc_t ADC1_INIT_CODE_ATTEN1[] = { 428 {EFUSE_BLK2, 158, 10}, // ADC1 init code at atten1, 429 }; 430 431 static const esp_efuse_desc_t ADC1_INIT_CODE_ATTEN2[] = { 432 {EFUSE_BLK2, 168, 10}, // ADC1 init code at atten2, 433 }; 434 435 static const esp_efuse_desc_t ADC1_INIT_CODE_ATTEN3[] = { 436 {EFUSE_BLK2, 178, 10}, // ADC1 init code at atten3, 437 }; 438 439 static const esp_efuse_desc_t ADC1_CAL_VOL_ATTEN0[] = { 440 {EFUSE_BLK2, 188, 10}, // ADC1 calibration voltage at atten0, 441 }; 442 443 static const esp_efuse_desc_t ADC1_CAL_VOL_ATTEN1[] = { 444 {EFUSE_BLK2, 198, 10}, // ADC1 calibration voltage at atten1, 445 }; 446 447 static const esp_efuse_desc_t ADC1_CAL_VOL_ATTEN2[] = { 448 {EFUSE_BLK2, 208, 10}, // ADC1 calibration voltage at atten2, 449 }; 450 451 static const esp_efuse_desc_t ADC1_CAL_VOL_ATTEN3[] = { 452 {EFUSE_BLK2, 218, 10}, // ADC1 calibration voltage at atten3, 453 }; 454 455 static const esp_efuse_desc_t USER_DATA[] = { 456 {EFUSE_BLK3, 0, 256}, // User data, 457 }; 458 459 static const esp_efuse_desc_t KEY0[] = { 460 {EFUSE_BLK4, 0, 256}, // Key0 or user data, 461 }; 462 463 static const esp_efuse_desc_t KEY1[] = { 464 {EFUSE_BLK5, 0, 256}, // Key1 or user data, 465 }; 466 467 static const esp_efuse_desc_t KEY2[] = { 468 {EFUSE_BLK6, 0, 256}, // Key2 or user data, 469 }; 470 471 static const esp_efuse_desc_t KEY3[] = { 472 {EFUSE_BLK7, 0, 256}, // Key3 or user data, 473 }; 474 475 static const esp_efuse_desc_t KEY4[] = { 476 {EFUSE_BLK8, 0, 256}, // Key4 or user data, 477 }; 478 479 static const esp_efuse_desc_t KEY5[] = { 480 {EFUSE_BLK9, 0, 256}, // Key5 or user data, 481 }; 482 483 static const esp_efuse_desc_t SYS_DATA_PART2[] = { 484 {EFUSE_BLK10, 0, 256}, // System configuration, 485 }; 486 487 488 489 490 491 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RD_DIS[] = { 492 &WR_DIS_RD_DIS[0], // Write protection for RD_DIS_KEY0 RD_DIS_KEY1 RD_DIS_KEY2 RD_DIS_KEY3 RD_DIS_KEY4 RD_DIS_KEY5 RD_DIS_SYS_DATA_PART2 493 NULL 494 }; 495 496 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_1[] = { 497 &WR_DIS_GROUP_1[0], // Write protection for DIS_ICACHE DIS_DOWNLOAD_ICACHE DIS_FORCE_DOWNLOAD DIS_USB DIS_CAN SOFT_DIS_JTAG DIS_DOWNLOAD_MANUAL_ENCRYPT 498 NULL 499 }; 500 501 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_2[] = { 502 &WR_DIS_GROUP_2[0], // Write protection for WDT_DELAY_SEL 503 NULL 504 }; 505 506 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_BOOT_CRYPT_CNT[] = { 507 &WR_DIS_SPI_BOOT_CRYPT_CNT[0], // Write protection for SPI_BOOT_CRYPT_CNT 508 NULL 509 }; 510 511 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE0[] = { 512 &WR_DIS_SECURE_BOOT_KEY_REVOKE0[0], // Write protection for SECURE_BOOT_KEY_REVOKE0 513 NULL 514 }; 515 516 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE1[] = { 517 &WR_DIS_SECURE_BOOT_KEY_REVOKE1[0], // Write protection for SECURE_BOOT_KEY_REVOKE1 518 NULL 519 }; 520 521 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE2[] = { 522 &WR_DIS_SECURE_BOOT_KEY_REVOKE2[0], // Write protection for SECURE_BOOT_KEY_REVOKE2 523 NULL 524 }; 525 526 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY0_PURPOSE[] = { 527 &WR_DIS_KEY0_PURPOSE[0], // Write protection for key_purpose. KEY0 528 NULL 529 }; 530 531 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY1_PURPOSE[] = { 532 &WR_DIS_KEY1_PURPOSE[0], // Write protection for key_purpose. KEY1 533 NULL 534 }; 535 536 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY2_PURPOSE[] = { 537 &WR_DIS_KEY2_PURPOSE[0], // Write protection for key_purpose. KEY2 538 NULL 539 }; 540 541 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY3_PURPOSE[] = { 542 &WR_DIS_KEY3_PURPOSE[0], // Write protection for key_purpose. KEY3 543 NULL 544 }; 545 546 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY4_PURPOSE[] = { 547 &WR_DIS_KEY4_PURPOSE[0], // Write protection for key_purpose. KEY4 548 NULL 549 }; 550 551 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY5_PURPOSE[] = { 552 &WR_DIS_KEY5_PURPOSE[0], // Write protection for key_purpose. KEY5 553 NULL 554 }; 555 556 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_EN[] = { 557 &WR_DIS_SECURE_BOOT_EN[0], // Write protection for SECURE_BOOT_EN 558 NULL 559 }; 560 561 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[] = { 562 &WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[0], // Write protection for SECURE_BOOT_AGGRESSIVE_REVOKE 563 NULL 564 }; 565 566 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_3[] = { 567 &WR_DIS_GROUP_3[0], // Write protection for FLASH_TPUW DIS_DOWNLOAD_MODE DIS_LEGACY_SPI_BOOT UART_PRINT_CHANNEL DIS_TINY_BASIC DIS_USB_DOWNLOAD_MODE ENABLE_SECURITY_DOWNLOAD UART_PRINT_CONTROL PIN_POWER_SELECTION FLASH_TYPE FORCE_SEND_RESUME SECURE_VERSION 568 NULL 569 }; 570 571 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK1[] = { 572 &WR_DIS_BLK1[0], // Write protection for EFUSE_BLK1. MAC_SPI_8M_SYS 573 NULL 574 }; 575 576 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART1[] = { 577 &WR_DIS_SYS_DATA_PART1[0], // Write protection for EFUSE_BLK2. SYS_DATA_PART1 578 NULL 579 }; 580 581 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USER_DATA[] = { 582 &WR_DIS_USER_DATA[0], // Write protection for EFUSE_BLK3. USER_DATA 583 NULL 584 }; 585 586 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY0[] = { 587 &WR_DIS_KEY0[0], // Write protection for EFUSE_BLK4. KEY0 588 NULL 589 }; 590 591 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY1[] = { 592 &WR_DIS_KEY1[0], // Write protection for EFUSE_BLK5. KEY1 593 NULL 594 }; 595 596 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY2[] = { 597 &WR_DIS_KEY2[0], // Write protection for EFUSE_BLK6. KEY2 598 NULL 599 }; 600 601 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY3[] = { 602 &WR_DIS_KEY3[0], // Write protection for EFUSE_BLK7. KEY3 603 NULL 604 }; 605 606 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY4[] = { 607 &WR_DIS_KEY4[0], // Write protection for EFUSE_BLK8. KEY4 608 NULL 609 }; 610 611 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY5[] = { 612 &WR_DIS_KEY5[0], // Write protection for EFUSE_BLK9. KEY5 613 NULL 614 }; 615 616 const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART2[] = { 617 &WR_DIS_SYS_DATA_PART2[0], // Write protection for EFUSE_BLK10. SYS_DATA_PART2 618 NULL 619 }; 620 621 const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY0[] = { 622 &RD_DIS_KEY0[0], // Read protection for EFUSE_BLK4. KEY0 623 NULL 624 }; 625 626 const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY1[] = { 627 &RD_DIS_KEY1[0], // Read protection for EFUSE_BLK5. KEY1 628 NULL 629 }; 630 631 const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY2[] = { 632 &RD_DIS_KEY2[0], // Read protection for EFUSE_BLK6. KEY2 633 NULL 634 }; 635 636 const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY3[] = { 637 &RD_DIS_KEY3[0], // Read protection for EFUSE_BLK7. KEY3 638 NULL 639 }; 640 641 const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY4[] = { 642 &RD_DIS_KEY4[0], // Read protection for EFUSE_BLK8. KEY4 643 NULL 644 }; 645 646 const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY5[] = { 647 &RD_DIS_KEY5[0], // Read protection for EFUSE_BLK9. KEY5 648 NULL 649 }; 650 651 const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_SYS_DATA_PART2[] = { 652 &RD_DIS_SYS_DATA_PART2[0], // Read protection for EFUSE_BLK10. SYS_DATA_PART2 653 NULL 654 }; 655 656 const esp_efuse_desc_t* ESP_EFUSE_DIS_RTC_RAM_BOOT[] = { 657 &DIS_RTC_RAM_BOOT[0], // Disable boot from RTC RAM 658 NULL 659 }; 660 661 const esp_efuse_desc_t* ESP_EFUSE_DIS_ICACHE[] = { 662 &DIS_ICACHE[0], // Disable Icache 663 NULL 664 }; 665 666 const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_JTAG[] = { 667 &DIS_USB_JTAG[0], // Disable USB JTAG 668 NULL 669 }; 670 671 const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_ICACHE[] = { 672 &DIS_DOWNLOAD_ICACHE[0], // Disable Icache in download mode 673 NULL 674 }; 675 676 const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_DEVICE[] = { 677 &DIS_USB_DEVICE[0], // Disable USB_DEVICE 678 NULL 679 }; 680 681 const esp_efuse_desc_t* ESP_EFUSE_DIS_FORCE_DOWNLOAD[] = { 682 &DIS_FORCE_DOWNLOAD[0], // Disable force chip go to download mode function 683 NULL 684 }; 685 686 const esp_efuse_desc_t* ESP_EFUSE_DIS_USB[] = { 687 &DIS_USB[0], // Disable USB function 688 NULL 689 }; 690 691 const esp_efuse_desc_t* ESP_EFUSE_DIS_CAN[] = { 692 &DIS_CAN[0], // Disable CAN function 693 NULL 694 }; 695 696 const esp_efuse_desc_t* ESP_EFUSE_JTAG_SEL_ENABLE[] = { 697 &JTAG_SEL_ENABLE[0], // Set this bit to enable selection between usb_to_jtag and pad_to_jtag through strapping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0. 698 NULL 699 }; 700 701 const esp_efuse_desc_t* ESP_EFUSE_SOFT_DIS_JTAG[] = { 702 &SOFT_DIS_JTAG[0], // Set these bits to disable JTAG in the soft way (odd number 1 means disable). JTAG can be enabled in HMAC module. 703 NULL 704 }; 705 706 const esp_efuse_desc_t* ESP_EFUSE_DIS_PAD_JTAG[] = { 707 &DIS_PAD_JTAG[0], // Disable JTAG in the hard way. JTAG is disabled permanently. 708 NULL 709 }; 710 711 const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT[] = { 712 &DIS_DOWNLOAD_MANUAL_ENCRYPT[0], // Disable flash encryption when in download boot modes. 713 NULL 714 }; 715 716 const esp_efuse_desc_t* ESP_EFUSE_USB_DREFH[] = { 717 &USB_DREFH[0], // Controls single-end input threshold vrefh 1.76 V to 2 V with step of 80 mV stored in eFuse. 718 NULL 719 }; 720 721 const esp_efuse_desc_t* ESP_EFUSE_USB_DREFL[] = { 722 &USB_DREFL[0], // Controls single-end input threshold vrefl 0.8 V to 1.04 V with step of 80 mV stored in eFuse. 723 NULL 724 }; 725 726 const esp_efuse_desc_t* ESP_EFUSE_USB_EXCHG_PINS[] = { 727 &USB_EXCHG_PINS[0], // Exchange D+ D- pins 728 NULL 729 }; 730 731 const esp_efuse_desc_t* ESP_EFUSE_VDD_SPI_AS_GPIO[] = { 732 &VDD_SPI_AS_GPIO[0], // Set this bit to vdd spi pin function as gpio 733 NULL 734 }; 735 736 const esp_efuse_desc_t* ESP_EFUSE_BTLC_GPIO_ENABLE[] = { 737 &BTLC_GPIO_ENABLE[0], // Enable btlc gpio 738 NULL 739 }; 740 741 const esp_efuse_desc_t* ESP_EFUSE_POWERGLITCH_EN[] = { 742 &POWERGLITCH_EN[0], // Set this bit to enable power glitch function 743 NULL 744 }; 745 746 const esp_efuse_desc_t* ESP_EFUSE_POWER_GLITCH_DSENSE[] = { 747 &POWER_GLITCH_DSENSE[0], // Sample delay configuration of power glitch 748 NULL 749 }; 750 751 const esp_efuse_desc_t* ESP_EFUSE_WDT_DELAY_SEL[] = { 752 &WDT_DELAY_SEL[0], // Select RTC WDT time out threshold 753 NULL 754 }; 755 756 const esp_efuse_desc_t* ESP_EFUSE_SPI_BOOT_CRYPT_CNT[] = { 757 &SPI_BOOT_CRYPT_CNT[0], // SPI boot encrypt decrypt enable. odd number 1 enable. even number 1 disable 758 NULL 759 }; 760 761 const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE0[] = { 762 &SECURE_BOOT_KEY_REVOKE0[0], // Enable revoke first secure boot key 763 NULL 764 }; 765 766 const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE1[] = { 767 &SECURE_BOOT_KEY_REVOKE1[0], // Enable revoke second secure boot key 768 NULL 769 }; 770 771 const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE2[] = { 772 &SECURE_BOOT_KEY_REVOKE2[0], // Enable revoke third secure boot key 773 NULL 774 }; 775 776 const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_0[] = { 777 &KEY_PURPOSE_0[0], // Key0 purpose 778 NULL 779 }; 780 781 const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_1[] = { 782 &KEY_PURPOSE_1[0], // Key1 purpose 783 NULL 784 }; 785 786 const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_2[] = { 787 &KEY_PURPOSE_2[0], // Key2 purpose 788 NULL 789 }; 790 791 const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_3[] = { 792 &KEY_PURPOSE_3[0], // Key3 purpose 793 NULL 794 }; 795 796 const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_4[] = { 797 &KEY_PURPOSE_4[0], // Key4 purpose 798 NULL 799 }; 800 801 const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_5[] = { 802 &KEY_PURPOSE_5[0], // Key5 purpose 803 NULL 804 }; 805 806 const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_EN[] = { 807 &SECURE_BOOT_EN[0], // Secure boot enable 808 NULL 809 }; 810 811 const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE[] = { 812 &SECURE_BOOT_AGGRESSIVE_REVOKE[0], // Enable aggressive secure boot revoke 813 NULL 814 }; 815 816 const esp_efuse_desc_t* ESP_EFUSE_FLASH_TPUW[] = { 817 &FLASH_TPUW[0], // Flash wait time after power up. (unit is ms). When value is 15. the time is 30 ms 818 NULL 819 }; 820 821 const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MODE[] = { 822 &DIS_DOWNLOAD_MODE[0], // Disble download mode include boot_mode[3:0] is 0 1 2 3 6 7 823 NULL 824 }; 825 826 const esp_efuse_desc_t* ESP_EFUSE_DIS_LEGACY_SPI_BOOT[] = { 827 &DIS_LEGACY_SPI_BOOT[0], // Disable_Legcy_SPI_boot mode include boot_mode[3:0] is 4 828 NULL 829 }; 830 831 const esp_efuse_desc_t* ESP_EFUSE_UART_PRINT_CHANNEL[] = { 832 &UART_PRINT_CHANNEL[0], // 0: UART0. 1: UART1 833 NULL 834 }; 835 836 const esp_efuse_desc_t* ESP_EFUSE_FLASH_ECC_MODE[] = { 837 &FLASH_ECC_MODE[0], // Set this bit to set flsah ecc mode. 0:flash ecc 16to18 byte mode. 1:flash ecc 16to17 byte mode 838 NULL 839 }; 840 841 const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_DOWNLOAD_MODE[] = { 842 &DIS_USB_DOWNLOAD_MODE[0], // Disable download through USB 843 NULL 844 }; 845 846 const esp_efuse_desc_t* ESP_EFUSE_ENABLE_SECURITY_DOWNLOAD[] = { 847 &ENABLE_SECURITY_DOWNLOAD[0], // Enable security download mode 848 NULL 849 }; 850 851 const esp_efuse_desc_t* ESP_EFUSE_UART_PRINT_CONTROL[] = { 852 &UART_PRINT_CONTROL[0], // b00:force print. b01:control by GPIO8 - low level print. b10:control by GPIO8 - high level print. b11:force disable print. 853 NULL 854 }; 855 856 const esp_efuse_desc_t* ESP_EFUSE_PIN_POWER_SELECTION[] = { 857 &PIN_POWER_SELECTION[0], // GPIO33-GPIO37 power supply selection in ROM code. 0:VDD3P3_CPU. 1:VDD_SPI. 858 NULL 859 }; 860 861 const esp_efuse_desc_t* ESP_EFUSE_FLASH_TYPE[] = { 862 &FLASH_TYPE[0], // Connected Flash interface type. 0: 4 data line. 1: 8 data line 863 NULL 864 }; 865 866 const esp_efuse_desc_t* ESP_EFUSE_FLASH_PAGE_SIZE[] = { 867 &FLASH_PAGE_SIZE[0], // Flash page size 868 NULL 869 }; 870 871 const esp_efuse_desc_t* ESP_EFUSE_FLASH_ECC_EN[] = { 872 &FLASH_ECC_EN[0], // Enable ECC for flash boot 873 NULL 874 }; 875 876 const esp_efuse_desc_t* ESP_EFUSE_FORCE_SEND_RESUME[] = { 877 &FORCE_SEND_RESUME[0], // Force ROM code to send a resume command during SPI boot 878 NULL 879 }; 880 881 const esp_efuse_desc_t* ESP_EFUSE_SECURE_VERSION[] = { 882 &SECURE_VERSION[0], // Secure version for anti-rollback 883 NULL 884 }; 885 886 const esp_efuse_desc_t* ESP_EFUSE_MAC_FACTORY[] = { 887 &MAC_FACTORY[0], // Factory MAC addr [0] 888 &MAC_FACTORY[1], // Factory MAC addr [1] 889 &MAC_FACTORY[2], // Factory MAC addr [2] 890 &MAC_FACTORY[3], // Factory MAC addr [3] 891 &MAC_FACTORY[4], // Factory MAC addr [4] 892 &MAC_FACTORY[5], // Factory MAC addr [5] 893 NULL 894 }; 895 896 const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_CLK[] = { 897 &SPI_PAD_CONFIG_CLK[0], // SPI_PAD_configure CLK 898 NULL 899 }; 900 901 const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_Q_D1[] = { 902 &SPI_PAD_CONFIG_Q_D1[0], // SPI_PAD_configure Q(D1) 903 NULL 904 }; 905 906 const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D_D0[] = { 907 &SPI_PAD_CONFIG_D_D0[0], // SPI_PAD_configure D(D0) 908 NULL 909 }; 910 911 const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_CS[] = { 912 &SPI_PAD_CONFIG_CS[0], // SPI_PAD_configure CS 913 NULL 914 }; 915 916 const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_HD_D3[] = { 917 &SPI_PAD_CONFIG_HD_D3[0], // SPI_PAD_configure HD(D3) 918 NULL 919 }; 920 921 const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_WP_D2[] = { 922 &SPI_PAD_CONFIG_WP_D2[0], // SPI_PAD_configure WP(D2) 923 NULL 924 }; 925 926 const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_DQS[] = { 927 &SPI_PAD_CONFIG_DQS[0], // SPI_PAD_configure DQS 928 NULL 929 }; 930 931 const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D4[] = { 932 &SPI_PAD_CONFIG_D4[0], // SPI_PAD_configure D4 933 NULL 934 }; 935 936 const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D5[] = { 937 &SPI_PAD_CONFIG_D5[0], // SPI_PAD_configure D5 938 NULL 939 }; 940 941 const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D6[] = { 942 &SPI_PAD_CONFIG_D6[0], // SPI_PAD_configure D6 943 NULL 944 }; 945 946 const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D7[] = { 947 &SPI_PAD_CONFIG_D7[0], // SPI_PAD_configure D7 948 NULL 949 }; 950 951 const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION[] = { 952 &WAFER_VERSION[0], // WAFER version 953 NULL 954 }; 955 956 const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[] = { 957 &PKG_VERSION[0], // Package version 0:ESP32C3 958 NULL 959 }; 960 961 const esp_efuse_desc_t* ESP_EFUSE_BLOCK1_VERSION[] = { 962 &BLOCK1_VERSION[0], // BLOCK1 efuse version 963 NULL 964 }; 965 966 const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[] = { 967 &OPTIONAL_UNIQUE_ID[0], // Optional unique 128-bit ID 968 NULL 969 }; 970 971 const esp_efuse_desc_t* ESP_EFUSE_BLOCK2_VERSION[] = { 972 &BLOCK2_VERSION[0], // Version of BLOCK2 973 NULL 974 }; 975 976 const esp_efuse_desc_t* ESP_EFUSE_TEMP_CALIB[] = { 977 &TEMP_CALIB[0], // Temperature calibration data 978 NULL 979 }; 980 981 const esp_efuse_desc_t* ESP_EFUSE_OCODE[] = { 982 &OCODE[0], // ADC OCode 983 NULL 984 }; 985 986 const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN0[] = { 987 &ADC1_INIT_CODE_ATTEN0[0], // ADC1 init code at atten0 988 NULL 989 }; 990 991 const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN1[] = { 992 &ADC1_INIT_CODE_ATTEN1[0], // ADC1 init code at atten1 993 NULL 994 }; 995 996 const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN2[] = { 997 &ADC1_INIT_CODE_ATTEN2[0], // ADC1 init code at atten2 998 NULL 999 }; 1000 1001 const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN3[] = { 1002 &ADC1_INIT_CODE_ATTEN3[0], // ADC1 init code at atten3 1003 NULL 1004 }; 1005 1006 const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN0[] = { 1007 &ADC1_CAL_VOL_ATTEN0[0], // ADC1 calibration voltage at atten0 1008 NULL 1009 }; 1010 1011 const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN1[] = { 1012 &ADC1_CAL_VOL_ATTEN1[0], // ADC1 calibration voltage at atten1 1013 NULL 1014 }; 1015 1016 const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN2[] = { 1017 &ADC1_CAL_VOL_ATTEN2[0], // ADC1 calibration voltage at atten2 1018 NULL 1019 }; 1020 1021 const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN3[] = { 1022 &ADC1_CAL_VOL_ATTEN3[0], // ADC1 calibration voltage at atten3 1023 NULL 1024 }; 1025 1026 const esp_efuse_desc_t* ESP_EFUSE_USER_DATA[] = { 1027 &USER_DATA[0], // User data 1028 NULL 1029 }; 1030 1031 const esp_efuse_desc_t* ESP_EFUSE_KEY0[] = { 1032 &KEY0[0], // Key0 or user data 1033 NULL 1034 }; 1035 1036 const esp_efuse_desc_t* ESP_EFUSE_KEY1[] = { 1037 &KEY1[0], // Key1 or user data 1038 NULL 1039 }; 1040 1041 const esp_efuse_desc_t* ESP_EFUSE_KEY2[] = { 1042 &KEY2[0], // Key2 or user data 1043 NULL 1044 }; 1045 1046 const esp_efuse_desc_t* ESP_EFUSE_KEY3[] = { 1047 &KEY3[0], // Key3 or user data 1048 NULL 1049 }; 1050 1051 const esp_efuse_desc_t* ESP_EFUSE_KEY4[] = { 1052 &KEY4[0], // Key4 or user data 1053 NULL 1054 }; 1055 1056 const esp_efuse_desc_t* ESP_EFUSE_KEY5[] = { 1057 &KEY5[0], // Key5 or user data 1058 NULL 1059 }; 1060 1061 const esp_efuse_desc_t* ESP_EFUSE_SYS_DATA_PART2[] = { 1062 &SYS_DATA_PART2[0], // System configuration 1063 NULL 1064 }; 1065
