1 /* 2 * Copyright 2022 NXP 3 * All rights reserved. 4 * 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #include "fsl_erm.h" 10 11 /******************************************************************************* 12 * Definitions 13 ******************************************************************************/ 14 15 /* Component ID definition, used by tools. */ 16 #ifndef FSL_COMPONENT_ID 17 #define FSL_COMPONENT_ID "platform.drivers.erm" 18 #endif 19 20 /******************************************************************************* 21 * Prototypes 22 ******************************************************************************/ 23 24 /******************************************************************************* 25 * Variables 26 ******************************************************************************/ 27 /*! @brief Pointers to ERM bases for each instance. */ 28 static ERM_Type *const s_ermBases[] = ERM_BASE_PTRS; 29 30 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) 31 /*! @brief Pointers to ERM clocks for each instance. */ 32 static const clock_ip_name_t s_ermClocks[] = ERM_CLOCKS; 33 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ 34 /******************************************************************************* 35 * Code 36 ******************************************************************************/ ERM_GetInstance(ERM_Type * base)37static uint32_t ERM_GetInstance(ERM_Type *base) 38 { 39 uint32_t instance; 40 41 /* Find the instance index from base address mappings. */ 42 for (instance = 0; instance < ARRAY_SIZE(s_ermBases); instance++) 43 { 44 if (s_ermBases[instance] == base) 45 { 46 break; 47 } 48 } 49 50 assert(instance < ARRAY_SIZE(s_ermBases)); 51 52 return instance; 53 } 54 55 /*! 56 * brief ERM module initialization function. 57 * 58 * param base ERM base address. 59 */ ERM_Init(ERM_Type * base)60void ERM_Init(ERM_Type *base) 61 { 62 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) 63 /* Ungate ERM clock. */ 64 CLOCK_EnableClock(s_ermClocks[ERM_GetInstance(base)]); 65 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ 66 67 base->CR0 = 0x00U; 68 #ifdef ERM_CR1_ENCIE8_MASK 69 base->CR1 = 0x00U; 70 #endif 71 base->SR0 = 0xFFFFFFFFU; 72 #ifdef ERM_SR1_SBC8_MASK 73 base->SR1 = 0xFFFFFFFFU; 74 #endif 75 } 76 77 /*! 78 * brief Deinitializes the ERM. 79 * 80 */ ERM_Deinit(ERM_Type * base)81void ERM_Deinit(ERM_Type *base) 82 { 83 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) 84 /* Ungate ERM clock. */ 85 CLOCK_DisableClock(s_ermClocks[ERM_GetInstance(base)]); 86 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ 87 } 88 ERM_GetMemoryErrorAddr(ERM_Type * base,erm_memory_channel_t channel)89uint32_t ERM_GetMemoryErrorAddr(ERM_Type *base, erm_memory_channel_t channel) 90 { 91 uint32_t absoluteErrorAddress = 0x00U; 92 93 switch ((uint8_t)channel) 94 { 95 case 0U: 96 absoluteErrorAddress = base->EAR0; 97 break; 98 #ifdef ERM_EAR1_EAR_MASK 99 case 1U: 100 absoluteErrorAddress = base->EAR1; 101 break; 102 #endif 103 #ifdef ERM_EAR2_EAR_MASK 104 case 2U: 105 absoluteErrorAddress = base->EAR2; 106 break; 107 #endif 108 #ifdef ERM_EAR3_EAR_MASK 109 case 3U: 110 absoluteErrorAddress = base->EAR3; 111 break; 112 #endif 113 #ifdef ERM_EAR4_EAR_MASK 114 case 4U: 115 absoluteErrorAddress = base->EAR4; 116 break; 117 #endif 118 #ifdef ERM_EAR5_EAR_MASK 119 case 5U: 120 absoluteErrorAddress = base->EAR5; 121 break; 122 #endif 123 #ifdef ERM_EAR6_EAR_MASK 124 case 6U: 125 absoluteErrorAddress = base->EAR6; 126 break; 127 #endif 128 default: 129 assert(NULL); 130 break; 131 } 132 133 return absoluteErrorAddress; 134 } 135 ERM_GetSyndrome(ERM_Type * base,erm_memory_channel_t channel)136uint32_t ERM_GetSyndrome(ERM_Type *base, erm_memory_channel_t channel) 137 { 138 uint32_t syndrome = 0x00U; 139 140 switch ((uint8_t)channel) 141 { 142 case 0U: 143 syndrome = (base->SYN0 & ERM_SYN0_SYNDROME_MASK) >> ERM_SYN0_SYNDROME_SHIFT; 144 break; 145 #ifdef ERM_SYN1_SYNDROME_MASK 146 case 1U: 147 syndrome = (base->SYN1 & ERM_SYN1_SYNDROME_MASK) >> ERM_SYN1_SYNDROME_SHIFT; 148 break; 149 #endif 150 #ifdef ERM_SYN2_SYNDROME_MASK 151 case 2U: 152 syndrome = (base->SYN2 & ERM_SYN2_SYNDROME_MASK) >> ERM_SYN2_SYNDROME_SHIFT; 153 break; 154 #endif 155 #ifdef ERM_SYN3_SYNDROME_MASK 156 case 3U: 157 syndrome = (base->SYN3 & ERM_SYN3_SYNDROME_MASK) >> ERM_SYN3_SYNDROME_SHIFT; 158 break; 159 #endif 160 #ifdef ERM_SYN4_SYNDROME_MASK 161 case 4U: 162 syndrome = (base->SYN4 & ERM_SYN4_SYNDROME_MASK) >> ERM_SYN4_SYNDROME_SHIFT; 163 break; 164 #endif 165 #ifdef ERM_SYN5_SYNDROME_MASK 166 case 5U: 167 syndrome = (base->SYN5 & ERM_SYN5_SYNDROME_MASK) >> ERM_SYN5_SYNDROME_SHIFT; 168 break; 169 #endif 170 #ifdef ERM_SYN6_SYNDROME_MASK 171 case 6U: 172 syndrome = (base->SYN6 & ERM_SYN6_SYNDROME_MASK) >> ERM_SYN6_SYNDROME_SHIFT; 173 break; 174 #endif 175 #ifdef ERM_SYN7_SYNDROME_MASK 176 case 7U: 177 syndrome = (base->SYN7 & ERM_SYN6_SYNDROME_MASK) >> ERM_SYN7_SYNDROME_SHIFT; 178 break; 179 #endif 180 #ifdef ERM_SYN8_SYNDROME_MASK 181 case 8U: 182 syndrome = (base->SYN8 & ERM_SYN8_SYNDROME_MASK) >> ERM_SYN8_SYNDROME_SHIFT; 183 break; 184 #endif 185 #ifdef ERM_SYN9_SYNDROME_MASK 186 case 8U: 187 syndrome = (base->SYN9 & ERM_SYN9_SYNDROME_MASK) >> ERM_SYN9_SYNDROME_SHIFT; 188 break; 189 #endif 190 default: 191 assert(NULL); 192 break; 193 } 194 195 return syndrome; 196 } 197 ERM_GetErrorCount(ERM_Type * base,erm_memory_channel_t channel)198uint32_t ERM_GetErrorCount(ERM_Type *base, erm_memory_channel_t channel) 199 { 200 uint32_t count = 0x00U; 201 202 switch ((uint8_t)channel) 203 { 204 case 0U: 205 count = (base->CORR_ERR_CNT0 & ERM_CORR_ERR_CNT0_COUNT_MASK) >> ERM_CORR_ERR_CNT0_COUNT_SHIFT; 206 break; 207 #ifdef ERM_CORR_ERR_CNT1_COUNT_MASK 208 case 1U: 209 count = (base->CORR_ERR_CNT1 & ERM_CORR_ERR_CNT1_COUNT_MASK) >> ERM_CORR_ERR_CNT1_COUNT_SHIFT; 210 break; 211 #endif 212 #ifdef ERM_CORR_ERR_CNT2_COUNT_MASK 213 case 2U: 214 count = (base->CORR_ERR_CNT2 & ERM_CORR_ERR_CNT2_COUNT_MASK) >> ERM_CORR_ERR_CNT2_COUNT_SHIFT; 215 break; 216 #endif 217 #ifdef ERM_CORR_ERR_CNT3_COUNT_MASK 218 case 3U: 219 count = (base->CORR_ERR_CNT3 & ERM_CORR_ERR_CNT3_COUNT_MASK) >> ERM_CORR_ERR_CNT3_COUNT_SHIFT; 220 break; 221 #endif 222 #ifdef ERM_CORR_ERR_CNT4_COUNT_MASK 223 case 4U: 224 count = (base->CORR_ERR_CNT4 & ERM_CORR_ERR_CNT4_COUNT_MASK) >> ERM_CORR_ERR_CNT4_COUNT_SHIFT; 225 break; 226 #endif 227 #ifdef ERM_CORR_ERR_CNT5_COUNT_MASK 228 case 5U: 229 count = (base->CORR_ERR_CNT5 & ERM_CORR_ERR_CNT5_COUNT_MASK) >> ERM_CORR_ERR_CNT5_COUNT_SHIFT; 230 break; 231 #endif 232 #ifdef ERM_CORR_ERR_CNT6_COUNT_MASK 233 case 6U: 234 count = (base->CORR_ERR_CNT6 & ERM_CORR_ERR_CNT6_COUNT_MASK) >> ERM_CORR_ERR_CNT6_COUNT_SHIFT; 235 break; 236 #endif 237 #ifdef ERM_CORR_ERR_CNT7_COUNT_MASK 238 case 7U: 239 count = (base->CORR_ERR_CNT7 & ERM_CORR_ERR_CNT7_COUNT_MASK) >> ERM_CORR_ERR_CNT7_COUNT_SHIFT; 240 break; 241 #endif 242 #ifdef ERM_CORR_ERR_CNT8_COUNT_MASK 243 case 8U: 244 count = (base->CORR_ERR_CNT8 & ERM_CORR_ERR_CNT8_COUNT_MASK) >> ERM_CORR_ERR_CNT8_COUNT_SHIFT; 245 break; 246 #endif 247 #ifdef ERM_CORR_ERR_CNT9_COUNT_MASK 248 case 9U: 249 count = (base->CORR_ERR_CNT9 & ERM_CORR_ERR_CNT9_COUNT_MASK) >> ERM_CORR_ERR_CNT9_COUNT_SHIFT; 250 break; 251 #endif 252 default: 253 assert(NULL); 254 break; 255 } 256 257 return count; 258 } 259 ERM_ResetErrorCount(ERM_Type * base,erm_memory_channel_t channel)260void ERM_ResetErrorCount(ERM_Type *base, erm_memory_channel_t channel) 261 { 262 switch ((uint8_t)channel) 263 { 264 case 0U: 265 base->CORR_ERR_CNT0 = 0x00U; 266 break; 267 268 #ifdef ERM_CORR_ERR_CNT1_COUNT_MASK 269 case 1U: 270 base->CORR_ERR_CNT1 = 0x00U; 271 break; 272 #endif 273 #ifdef ERM_CORR_ERR_CNT2_COUNT_MASK 274 case 2U: 275 base->CORR_ERR_CNT2 = 0x00U; 276 break; 277 #endif 278 #ifdef ERM_CORR_ERR_CNT3_COUNT_MASK 279 case 3U: 280 base->CORR_ERR_CNT3 = 0x00U; 281 break; 282 #endif 283 #ifdef ERM_CORR_ERR_CNT4_COUNT_MASK 284 case 4U: 285 base->CORR_ERR_CNT4 = 0x00U; 286 break; 287 #endif 288 #ifdef ERM_CORR_ERR_CNT5_COUNT_MASK 289 case 5U: 290 base->CORR_ERR_CNT5 = 0x00U; 291 break; 292 #endif 293 #ifdef ERM_CORR_ERR_CNT6_COUNT_MASK 294 case 6U: 295 base->CORR_ERR_CNT6 = 0x00U; 296 break; 297 #endif 298 #ifdef ERM_CORR_ERR_CNT6_COUNT_MASK 299 case 7U: 300 base->CORR_ERR_CNT7 = 0x00U; 301 break; 302 #endif 303 #ifdef ERM_CORR_ERR_CNT8_COUNT_MASK 304 case 8U: 305 base->CORR_ERR_CNT8 = 0x00U; 306 break; 307 #endif 308 #ifdef ERM_CORR_ERR_CNT9_COUNT_MASK 309 case 9U: 310 base->CORR_ERR_CNT9 = 0x00U; 311 break; 312 #endif 313 default: 314 assert(NULL); 315 break; 316 } 317 } 318
