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Searched defs:ENET_QOS_DMA_INTERRUPT_STATUS_DC2IS_MASK (Results 1 – 11 of 11) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1176/
DMIMXRT1176_cm7.h46409 #define ENET_QOS_DMA_INTERRUPT_STATUS_DC2IS_MASK (0x4U) macro
DMIMXRT1176_cm4.h46407 #define ENET_QOS_DMA_INTERRUPT_STATUS_DC2IS_MASK (0x4U) macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX9131/
DMIMX9131.h29067 #define ENET_QOS_DMA_INTERRUPT_STATUS_DC2IS_MASK (0x4U) macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8ML6/
DMIMX8ML6_cm7.h43622 #define ENET_QOS_DMA_INTERRUPT_STATUS_DC2IS_MASK (0x4U) macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8ML4/
DMIMX8ML4_cm7.h43622 #define ENET_QOS_DMA_INTERRUPT_STATUS_DC2IS_MASK (0x4U) macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8ML3/
DMIMX8ML3_cm7.h43622 #define ENET_QOS_DMA_INTERRUPT_STATUS_DC2IS_MASK (0x4U) macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX9352/
DMIMX9352_cm33.h28110 #define ENET_QOS_DMA_INTERRUPT_STATUS_DC2IS_MASK (0x4U) macro
DMIMX9352_ca55.h31012 #define ENET_QOS_DMA_INTERRUPT_STATUS_DC2IS_MASK (0x4U) macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8ML8/
DMIMX8ML8_dsp.h41915 #define ENET_QOS_DMA_INTERRUPT_STATUS_DC2IS_MASK (0x4U) macro
DMIMX8ML8_cm7.h43622 #define ENET_QOS_DMA_INTERRUPT_STATUS_DC2IS_MASK (0x4U) macro
DMIMX8ML8_ca53.h43648 #define ENET_QOS_DMA_INTERRUPT_STATUS_DC2IS_MASK (0x4U) macro