1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2023 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_ENETC_PORT.h 10 * @version 2.1 11 * @date 2023-07-20 12 * @brief Peripheral Access Layer for S32Z2_ENETC_PORT 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_ENETC_PORT_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_ENETC_PORT_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- ENETC_PORT Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup ENETC_PORT_Peripheral_Access_Layer ENETC_PORT Peripheral Access Layer 68 * @{ 69 */ 70 71 /** ENETC_PORT - Size of Registers Arrays */ 72 #define ENETC_PORT_TCT_NUM_COUNT 8u 73 74 /** ENETC_PORT - Register Layout Typedef */ 75 typedef struct { 76 __I uint32_t PCAPR; /**< Port capability register, offset: 0x0 */ 77 __I uint32_t PMCAPR; /**< Port MAC capability register, offset: 0x4 */ 78 __I uint32_t PIOCAPR; /**< Port I/O capability register, offset: 0x8 */ 79 uint8_t RESERVED_0[4]; 80 __IO uint32_t PCR; /**< Port configuration register, offset: 0x10 */ 81 uint8_t RESERVED_1[12]; 82 __IO uint32_t PMAR0; /**< Port MAC address register 0, offset: 0x20 */ 83 __IO uint32_t PMAR1; /**< Port MAC address register 1, offset: 0x24 */ 84 uint8_t RESERVED_2[40]; 85 __IO uint32_t PTAR; /**< Port TPID acceptance register, offset: 0x50 */ 86 __IO uint32_t PQOSMR; /**< Port QoS mode register, offset: 0x54 */ 87 uint8_t RESERVED_3[40]; 88 __IO uint32_t PPCR; /**< Port parser configuration register, offset: 0x80 */ 89 __IO uint32_t PIPFCR; /**< Port ingress port filter configuration register, offset: 0x84 */ 90 uint8_t RESERVED_4[24]; 91 __IO uint32_t PSGCR; /**< Port stream gate configuration register, offset: 0xA0 */ 92 uint8_t RESERVED_5[92]; 93 __IO uint32_t POR; /**< Port operational register, offset: 0x100 */ 94 __I uint32_t PSR; /**< Port status register, offset: 0x104 */ 95 __IO uint32_t PRXSDUOR; /**< Port receive SDU overhead register, offset: 0x108 */ 96 __IO uint32_t PTXSDUOR; /**< Port transmit SDU overhead register, offset: 0x10C */ 97 __IO uint32_t PTGSCR; /**< Port time gate scheduling control register, offset: 0x110 */ 98 __I uint32_t PTGAGLSR; /**< Port time gate scheduling admin gate list status register, offset: 0x114 */ 99 __I uint32_t PTGAGLLR; /**< Port time gate scheduling admin gate list length register, offset: 0x118 */ 100 __I uint32_t PTGOGLLR; /**< Port time gating operational gate list length register, offset: 0x11C */ 101 __IO uint32_t PTGSATOR; /**< Port time gate scheduling advance time offset register, offset: 0x120 */ 102 uint8_t RESERVED_6[156]; 103 __I uint32_t PRXDCR; /**< Port Rx discard count register, offset: 0x1C0 */ 104 uint8_t RESERVED_7[4]; 105 __IO uint32_t PRXDCRR0; /**< Port Rx discard count reason register 0, offset: 0x1C8 */ 106 __IO uint32_t PRXDCRR1; /**< Port Rx discard count reason register 1, offset: 0x1CC */ 107 uint8_t RESERVED_8[48]; 108 struct { /* offset: 0x200, array step: 0x20 */ 109 __I uint32_t PTGSTCSR; /**< Port time gate scheduling traffic class 0 status register..Port time gate scheduling traffic class 7 status register, array offset: 0x200, array step: 0x20 */ 110 uint8_t RESERVED_0[4]; 111 __IO uint32_t PTCTMSDUR; /**< Port traffic class 0 transmit maximum SDU register..Port traffic class 7 transmit maximum SDU register, array offset: 0x208, array step: 0x20 */ 112 uint8_t RESERVED_1[4]; 113 __IO uint32_t PTCCBSR0; /**< Port transmit traffic class 0 credit based shaper register 0..Port transmit traffic class 7 credit based shaper register 0, array offset: 0x210, array step: 0x20 */ 114 __IO uint32_t PTCCBSR1; /**< Port traffic class 0 credit based shaper register 1..Port traffic class 7 credit based shaper register 1, array offset: 0x214, array step: 0x20 */ 115 uint8_t RESERVED_2[8]; 116 } TCT_NUM[ENETC_PORT_TCT_NUM_COUNT]; 117 uint8_t RESERVED_9[312]; 118 __IO uint32_t PPCPDEIMR; /**< Port PCP DEI mapping register, offset: 0x438 */ 119 uint8_t RESERVED_10[36]; 120 __IO uint32_t PISIDCR; /**< Port ingress stream identification configuration register, offset: 0x460 */ 121 } ENETC_PORT_Type, *ENETC_PORT_MemMapPtr; 122 123 /** Number of instances of the ENETC_PORT module. */ 124 #define ENETC_PORT_INSTANCE_COUNT (1u) 125 126 /* ENETC_PORT - Peripheral instance base addresses */ 127 /** Peripheral NETC__ENETC0_PORT base address */ 128 #define IP_NETC__ENETC0_PORT_BASE (0x74B14000u) 129 /** Peripheral NETC__ENETC0_PORT base pointer */ 130 #define IP_NETC__ENETC0_PORT ((ENETC_PORT_Type *)IP_NETC__ENETC0_PORT_BASE) 131 /** Array initializer of ENETC_PORT peripheral base addresses */ 132 #define IP_ENETC_PORT_BASE_ADDRS { IP_NETC__ENETC0_PORT_BASE } 133 /** Array initializer of ENETC_PORT peripheral base pointers */ 134 #define IP_ENETC_PORT_BASE_PTRS { IP_NETC__ENETC0_PORT } 135 136 /* ---------------------------------------------------------------------------- 137 -- ENETC_PORT Register Masks 138 ---------------------------------------------------------------------------- */ 139 140 /*! 141 * @addtogroup ENETC_PORT_Register_Masks ENETC_PORT Register Masks 142 * @{ 143 */ 144 145 /*! @name PCAPR - Port capability register */ 146 /*! @{ */ 147 148 #define ENETC_PORT_PCAPR_LINK_TYPE_MASK (0x10U) 149 #define ENETC_PORT_PCAPR_LINK_TYPE_SHIFT (4U) 150 #define ENETC_PORT_PCAPR_LINK_TYPE_WIDTH (1U) 151 #define ENETC_PORT_PCAPR_LINK_TYPE(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PORT_PCAPR_LINK_TYPE_SHIFT)) & ENETC_PORT_PCAPR_LINK_TYPE_MASK) 152 153 #define ENETC_PORT_PCAPR_NUM_TC_MASK (0xF000U) 154 #define ENETC_PORT_PCAPR_NUM_TC_SHIFT (12U) 155 #define ENETC_PORT_PCAPR_NUM_TC_WIDTH (4U) 156 #define ENETC_PORT_PCAPR_NUM_TC(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PORT_PCAPR_NUM_TC_SHIFT)) & ENETC_PORT_PCAPR_NUM_TC_MASK) 157 158 #define ENETC_PORT_PCAPR_NUM_Q_MASK (0xF0000U) 159 #define ENETC_PORT_PCAPR_NUM_Q_SHIFT (16U) 160 #define ENETC_PORT_PCAPR_NUM_Q_WIDTH (4U) 161 #define ENETC_PORT_PCAPR_NUM_Q(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PORT_PCAPR_NUM_Q_SHIFT)) & ENETC_PORT_PCAPR_NUM_Q_MASK) 162 163 #define ENETC_PORT_PCAPR_NUM_CG_MASK (0xF000000U) 164 #define ENETC_PORT_PCAPR_NUM_CG_SHIFT (24U) 165 #define ENETC_PORT_PCAPR_NUM_CG_WIDTH (4U) 166 #define ENETC_PORT_PCAPR_NUM_CG(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PORT_PCAPR_NUM_CG_SHIFT)) & ENETC_PORT_PCAPR_NUM_CG_MASK) 167 168 #define ENETC_PORT_PCAPR_TGS_MASK (0x10000000U) 169 #define ENETC_PORT_PCAPR_TGS_SHIFT (28U) 170 #define ENETC_PORT_PCAPR_TGS_WIDTH (1U) 171 #define ENETC_PORT_PCAPR_TGS(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PORT_PCAPR_TGS_SHIFT)) & ENETC_PORT_PCAPR_TGS_MASK) 172 173 #define ENETC_PORT_PCAPR_CBS_MASK (0x20000000U) 174 #define ENETC_PORT_PCAPR_CBS_SHIFT (29U) 175 #define ENETC_PORT_PCAPR_CBS_WIDTH (1U) 176 #define ENETC_PORT_PCAPR_CBS(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PORT_PCAPR_CBS_SHIFT)) & ENETC_PORT_PCAPR_CBS_MASK) 177 /*! @} */ 178 179 /*! @name PMCAPR - Port MAC capability register */ 180 /*! @{ */ 181 182 #define ENETC_PORT_PMCAPR_MAC_VAR_MASK (0x7U) 183 #define ENETC_PORT_PMCAPR_MAC_VAR_SHIFT (0U) 184 #define ENETC_PORT_PMCAPR_MAC_VAR_WIDTH (3U) 185 #define ENETC_PORT_PMCAPR_MAC_VAR(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PORT_PMCAPR_MAC_VAR_SHIFT)) & ENETC_PORT_PMCAPR_MAC_VAR_MASK) 186 187 #define ENETC_PORT_PMCAPR_EFPAD_MASK (0x30U) 188 #define ENETC_PORT_PMCAPR_EFPAD_SHIFT (4U) 189 #define ENETC_PORT_PMCAPR_EFPAD_WIDTH (2U) 190 #define ENETC_PORT_PMCAPR_EFPAD(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PORT_PMCAPR_EFPAD_SHIFT)) & ENETC_PORT_PMCAPR_EFPAD_MASK) 191 192 #define ENETC_PORT_PMCAPR_HD_MASK (0x100U) 193 #define ENETC_PORT_PMCAPR_HD_SHIFT (8U) 194 #define ENETC_PORT_PMCAPR_HD_WIDTH (1U) 195 #define ENETC_PORT_PMCAPR_HD(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PORT_PMCAPR_HD_SHIFT)) & ENETC_PORT_PMCAPR_HD_MASK) 196 197 #define ENETC_PORT_PMCAPR_FP_MASK (0x600U) 198 #define ENETC_PORT_PMCAPR_FP_SHIFT (9U) 199 #define ENETC_PORT_PMCAPR_FP_WIDTH (2U) 200 #define ENETC_PORT_PMCAPR_FP(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PORT_PMCAPR_FP_SHIFT)) & ENETC_PORT_PMCAPR_FP_MASK) 201 202 #define ENETC_PORT_PMCAPR_MII_PROT_MASK (0xF000000U) 203 #define ENETC_PORT_PMCAPR_MII_PROT_SHIFT (24U) 204 #define ENETC_PORT_PMCAPR_MII_PROT_WIDTH (4U) 205 #define ENETC_PORT_PMCAPR_MII_PROT(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PORT_PMCAPR_MII_PROT_SHIFT)) & ENETC_PORT_PMCAPR_MII_PROT_MASK) 206 /*! @} */ 207 208 /*! @name PIOCAPR - Port I/O capability register */ 209 /*! @{ */ 210 211 #define ENETC_PORT_PIOCAPR_PCS_PROT_MASK (0xFFFFU) 212 #define ENETC_PORT_PIOCAPR_PCS_PROT_SHIFT (0U) 213 #define ENETC_PORT_PIOCAPR_PCS_PROT_WIDTH (16U) 214 #define ENETC_PORT_PIOCAPR_PCS_PROT(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PORT_PIOCAPR_PCS_PROT_SHIFT)) & ENETC_PORT_PIOCAPR_PCS_PROT_MASK) 215 216 #define ENETC_PORT_PIOCAPR_IO_VAR_MASK (0xF000000U) 217 #define ENETC_PORT_PIOCAPR_IO_VAR_SHIFT (24U) 218 #define ENETC_PORT_PIOCAPR_IO_VAR_WIDTH (4U) 219 #define ENETC_PORT_PIOCAPR_IO_VAR(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PORT_PIOCAPR_IO_VAR_SHIFT)) & ENETC_PORT_PIOCAPR_IO_VAR_MASK) 220 221 #define ENETC_PORT_PIOCAPR_EMDIO_MASK (0x10000000U) 222 #define ENETC_PORT_PIOCAPR_EMDIO_SHIFT (28U) 223 #define ENETC_PORT_PIOCAPR_EMDIO_WIDTH (1U) 224 #define ENETC_PORT_PIOCAPR_EMDIO(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PORT_PIOCAPR_EMDIO_SHIFT)) & ENETC_PORT_PIOCAPR_EMDIO_MASK) 225 226 #define ENETC_PORT_PIOCAPR_REVMII_RATE_MASK (0x40000000U) 227 #define ENETC_PORT_PIOCAPR_REVMII_RATE_SHIFT (30U) 228 #define ENETC_PORT_PIOCAPR_REVMII_RATE_WIDTH (1U) 229 #define ENETC_PORT_PIOCAPR_REVMII_RATE(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PORT_PIOCAPR_REVMII_RATE_SHIFT)) & ENETC_PORT_PIOCAPR_REVMII_RATE_MASK) 230 231 #define ENETC_PORT_PIOCAPR_REVMII_MASK (0x80000000U) 232 #define ENETC_PORT_PIOCAPR_REVMII_SHIFT (31U) 233 #define ENETC_PORT_PIOCAPR_REVMII_WIDTH (1U) 234 #define ENETC_PORT_PIOCAPR_REVMII(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PORT_PIOCAPR_REVMII_SHIFT)) & ENETC_PORT_PIOCAPR_REVMII_MASK) 235 /*! @} */ 236 237 /*! @name PCR - Port configuration register */ 238 /*! @{ */ 239 240 #define ENETC_PORT_PCR_HDR_FMT_MASK (0x1U) 241 #define ENETC_PORT_PCR_HDR_FMT_SHIFT (0U) 242 #define ENETC_PORT_PCR_HDR_FMT_WIDTH (1U) 243 #define ENETC_PORT_PCR_HDR_FMT(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PORT_PCR_HDR_FMT_SHIFT)) & ENETC_PORT_PCR_HDR_FMT_MASK) 244 245 #define ENETC_PORT_PCR_L2DOSE_MASK (0x10U) 246 #define ENETC_PORT_PCR_L2DOSE_SHIFT (4U) 247 #define ENETC_PORT_PCR_L2DOSE_WIDTH (1U) 248 #define ENETC_PORT_PCR_L2DOSE(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PORT_PCR_L2DOSE_SHIFT)) & ENETC_PORT_PCR_L2DOSE_MASK) 249 250 #define ENETC_PORT_PCR_TIMER_CS_MASK (0x100U) 251 #define ENETC_PORT_PCR_TIMER_CS_SHIFT (8U) 252 #define ENETC_PORT_PCR_TIMER_CS_WIDTH (1U) 253 #define ENETC_PORT_PCR_TIMER_CS(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PORT_PCR_TIMER_CS_SHIFT)) & ENETC_PORT_PCR_TIMER_CS_MASK) 254 255 #define ENETC_PORT_PCR_FCSEA_MASK (0x1000U) 256 #define ENETC_PORT_PCR_FCSEA_SHIFT (12U) 257 #define ENETC_PORT_PCR_FCSEA_WIDTH (1U) 258 #define ENETC_PORT_PCR_FCSEA(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PORT_PCR_FCSEA_SHIFT)) & ENETC_PORT_PCR_FCSEA_MASK) 259 260 #define ENETC_PORT_PCR_PSPEED_MASK (0x3FFF0000U) 261 #define ENETC_PORT_PCR_PSPEED_SHIFT (16U) 262 #define ENETC_PORT_PCR_PSPEED_WIDTH (14U) 263 #define ENETC_PORT_PCR_PSPEED(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PORT_PCR_PSPEED_SHIFT)) & ENETC_PORT_PCR_PSPEED_MASK) 264 /*! @} */ 265 266 /*! @name PMAR0 - Port MAC address register 0 */ 267 /*! @{ */ 268 269 #define ENETC_PORT_PMAR0_PRIM_MAC_ADDR_MASK (0xFFFFFFFFU) 270 #define ENETC_PORT_PMAR0_PRIM_MAC_ADDR_SHIFT (0U) 271 #define ENETC_PORT_PMAR0_PRIM_MAC_ADDR_WIDTH (32U) 272 #define ENETC_PORT_PMAR0_PRIM_MAC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PORT_PMAR0_PRIM_MAC_ADDR_SHIFT)) & ENETC_PORT_PMAR0_PRIM_MAC_ADDR_MASK) 273 /*! @} */ 274 275 /*! @name PMAR1 - Port MAC address register 1 */ 276 /*! @{ */ 277 278 #define ENETC_PORT_PMAR1_PRIM_MAC_ADDR_MASK (0xFFFFU) 279 #define ENETC_PORT_PMAR1_PRIM_MAC_ADDR_SHIFT (0U) 280 #define ENETC_PORT_PMAR1_PRIM_MAC_ADDR_WIDTH (16U) 281 #define ENETC_PORT_PMAR1_PRIM_MAC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PORT_PMAR1_PRIM_MAC_ADDR_SHIFT)) & ENETC_PORT_PMAR1_PRIM_MAC_ADDR_MASK) 282 /*! @} */ 283 284 /*! @name PTAR - Port TPID acceptance register */ 285 /*! @{ */ 286 287 #define ENETC_PORT_PTAR_OVTPIDL_MASK (0xFU) 288 #define ENETC_PORT_PTAR_OVTPIDL_SHIFT (0U) 289 #define ENETC_PORT_PTAR_OVTPIDL_WIDTH (4U) 290 #define ENETC_PORT_PTAR_OVTPIDL(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PORT_PTAR_OVTPIDL_SHIFT)) & ENETC_PORT_PTAR_OVTPIDL_MASK) 291 292 #define ENETC_PORT_PTAR_IVTPIDL_MASK (0xF0U) 293 #define ENETC_PORT_PTAR_IVTPIDL_SHIFT (4U) 294 #define ENETC_PORT_PTAR_IVTPIDL_WIDTH (4U) 295 #define ENETC_PORT_PTAR_IVTPIDL(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PORT_PTAR_IVTPIDL_SHIFT)) & ENETC_PORT_PTAR_IVTPIDL_MASK) 296 /*! @} */ 297 298 /*! @name PQOSMR - Port QoS mode register */ 299 /*! @{ */ 300 301 #define ENETC_PORT_PQOSMR_VS_MASK (0x1U) 302 #define ENETC_PORT_PQOSMR_VS_SHIFT (0U) 303 #define ENETC_PORT_PQOSMR_VS_WIDTH (1U) 304 #define ENETC_PORT_PQOSMR_VS(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PORT_PQOSMR_VS_SHIFT)) & ENETC_PORT_PQOSMR_VS_MASK) 305 306 #define ENETC_PORT_PQOSMR_VE_MASK (0x2U) 307 #define ENETC_PORT_PQOSMR_VE_SHIFT (1U) 308 #define ENETC_PORT_PQOSMR_VE_WIDTH (1U) 309 #define ENETC_PORT_PQOSMR_VE(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PORT_PQOSMR_VE_SHIFT)) & ENETC_PORT_PQOSMR_VE_MASK) 310 311 #define ENETC_PORT_PQOSMR_DDR_MASK (0xCU) 312 #define ENETC_PORT_PQOSMR_DDR_SHIFT (2U) 313 #define ENETC_PORT_PQOSMR_DDR_WIDTH (2U) 314 #define ENETC_PORT_PQOSMR_DDR(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PORT_PQOSMR_DDR_SHIFT)) & ENETC_PORT_PQOSMR_DDR_MASK) 315 316 #define ENETC_PORT_PQOSMR_DIPV_MASK (0x70U) 317 #define ENETC_PORT_PQOSMR_DIPV_SHIFT (4U) 318 #define ENETC_PORT_PQOSMR_DIPV_WIDTH (3U) 319 #define ENETC_PORT_PQOSMR_DIPV(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PORT_PQOSMR_DIPV_SHIFT)) & ENETC_PORT_PQOSMR_DIPV_MASK) 320 321 #define ENETC_PORT_PQOSMR_VQMP_MASK (0xF0000U) 322 #define ENETC_PORT_PQOSMR_VQMP_SHIFT (16U) 323 #define ENETC_PORT_PQOSMR_VQMP_WIDTH (4U) 324 #define ENETC_PORT_PQOSMR_VQMP(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PORT_PQOSMR_VQMP_SHIFT)) & ENETC_PORT_PQOSMR_VQMP_MASK) 325 /*! @} */ 326 327 /*! @name PPCR - Port parser configuration register */ 328 /*! @{ */ 329 330 #define ENETC_PORT_PPCR_L1PFS_MASK (0x3EU) 331 #define ENETC_PORT_PPCR_L1PFS_SHIFT (1U) 332 #define ENETC_PORT_PPCR_L1PFS_WIDTH (5U) 333 #define ENETC_PORT_PPCR_L1PFS(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PORT_PPCR_L1PFS_SHIFT)) & ENETC_PORT_PPCR_L1PFS_MASK) 334 335 #define ENETC_PORT_PPCR_L2PFS_MASK (0x3E00U) 336 #define ENETC_PORT_PPCR_L2PFS_SHIFT (9U) 337 #define ENETC_PORT_PPCR_L2PFS_WIDTH (5U) 338 #define ENETC_PORT_PPCR_L2PFS(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PORT_PPCR_L2PFS_SHIFT)) & ENETC_PORT_PPCR_L2PFS_MASK) 339 340 #define ENETC_PORT_PPCR_L3HFP_MASK (0x10000U) 341 #define ENETC_PORT_PPCR_L3HFP_SHIFT (16U) 342 #define ENETC_PORT_PPCR_L3HFP_WIDTH (1U) 343 #define ENETC_PORT_PPCR_L3HFP(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PORT_PPCR_L3HFP_SHIFT)) & ENETC_PORT_PPCR_L3HFP_MASK) 344 345 #define ENETC_PORT_PPCR_L3PFS_MASK (0x3E0000U) 346 #define ENETC_PORT_PPCR_L3PFS_SHIFT (17U) 347 #define ENETC_PORT_PPCR_L3PFS_WIDTH (5U) 348 #define ENETC_PORT_PPCR_L3PFS(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PORT_PPCR_L3PFS_SHIFT)) & ENETC_PORT_PPCR_L3PFS_MASK) 349 350 #define ENETC_PORT_PPCR_L4HFP_MASK (0x1000000U) 351 #define ENETC_PORT_PPCR_L4HFP_SHIFT (24U) 352 #define ENETC_PORT_PPCR_L4HFP_WIDTH (1U) 353 #define ENETC_PORT_PPCR_L4HFP(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PORT_PPCR_L4HFP_SHIFT)) & ENETC_PORT_PPCR_L4HFP_MASK) 354 355 #define ENETC_PORT_PPCR_L4PFS_MASK (0x3E000000U) 356 #define ENETC_PORT_PPCR_L4PFS_SHIFT (25U) 357 #define ENETC_PORT_PPCR_L4PFS_WIDTH (5U) 358 #define ENETC_PORT_PPCR_L4PFS(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PORT_PPCR_L4PFS_SHIFT)) & ENETC_PORT_PPCR_L4PFS_MASK) 359 /*! @} */ 360 361 /*! @name PIPFCR - Port ingress port filter configuration register */ 362 /*! @{ */ 363 364 #define ENETC_PORT_PIPFCR_EN_MASK (0x1U) 365 #define ENETC_PORT_PIPFCR_EN_SHIFT (0U) 366 #define ENETC_PORT_PIPFCR_EN_WIDTH (1U) 367 #define ENETC_PORT_PIPFCR_EN(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PORT_PIPFCR_EN_SHIFT)) & ENETC_PORT_PIPFCR_EN_MASK) 368 /*! @} */ 369 370 /*! @name PSGCR - Port stream gate configuration register */ 371 /*! @{ */ 372 373 #define ENETC_PORT_PSGCR_PDELAY_MASK (0xFFFFFFU) 374 #define ENETC_PORT_PSGCR_PDELAY_SHIFT (0U) 375 #define ENETC_PORT_PSGCR_PDELAY_WIDTH (24U) 376 #define ENETC_PORT_PSGCR_PDELAY(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PORT_PSGCR_PDELAY_SHIFT)) & ENETC_PORT_PSGCR_PDELAY_MASK) 377 378 #define ENETC_PORT_PSGCR_OGC_MASK (0x80000000U) 379 #define ENETC_PORT_PSGCR_OGC_SHIFT (31U) 380 #define ENETC_PORT_PSGCR_OGC_WIDTH (1U) 381 #define ENETC_PORT_PSGCR_OGC(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PORT_PSGCR_OGC_SHIFT)) & ENETC_PORT_PSGCR_OGC_MASK) 382 /*! @} */ 383 384 /*! @name POR - Port operational register */ 385 /*! @{ */ 386 387 #define ENETC_PORT_POR_TXDIS_MASK (0x1U) 388 #define ENETC_PORT_POR_TXDIS_SHIFT (0U) 389 #define ENETC_PORT_POR_TXDIS_WIDTH (1U) 390 #define ENETC_PORT_POR_TXDIS(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PORT_POR_TXDIS_SHIFT)) & ENETC_PORT_POR_TXDIS_MASK) 391 392 #define ENETC_PORT_POR_RXDIS_MASK (0x2U) 393 #define ENETC_PORT_POR_RXDIS_SHIFT (1U) 394 #define ENETC_PORT_POR_RXDIS_WIDTH (1U) 395 #define ENETC_PORT_POR_RXDIS(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PORT_POR_RXDIS_SHIFT)) & ENETC_PORT_POR_RXDIS_MASK) 396 /*! @} */ 397 398 /*! @name PSR - Port status register */ 399 /*! @{ */ 400 401 #define ENETC_PORT_PSR_TX_BUSY_MASK (0x1U) 402 #define ENETC_PORT_PSR_TX_BUSY_SHIFT (0U) 403 #define ENETC_PORT_PSR_TX_BUSY_WIDTH (1U) 404 #define ENETC_PORT_PSR_TX_BUSY(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PORT_PSR_TX_BUSY_SHIFT)) & ENETC_PORT_PSR_TX_BUSY_MASK) 405 406 #define ENETC_PORT_PSR_RX_BUSY_MASK (0x2U) 407 #define ENETC_PORT_PSR_RX_BUSY_SHIFT (1U) 408 #define ENETC_PORT_PSR_RX_BUSY_WIDTH (1U) 409 #define ENETC_PORT_PSR_RX_BUSY(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PORT_PSR_RX_BUSY_SHIFT)) & ENETC_PORT_PSR_RX_BUSY_MASK) 410 /*! @} */ 411 412 /*! @name PRXSDUOR - Port receive SDU overhead register */ 413 /*! @{ */ 414 415 #define ENETC_PORT_PRXSDUOR_PPDU_BCO_MASK (0x1FU) 416 #define ENETC_PORT_PRXSDUOR_PPDU_BCO_SHIFT (0U) 417 #define ENETC_PORT_PRXSDUOR_PPDU_BCO_WIDTH (5U) 418 #define ENETC_PORT_PRXSDUOR_PPDU_BCO(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PORT_PRXSDUOR_PPDU_BCO_SHIFT)) & ENETC_PORT_PRXSDUOR_PPDU_BCO_MASK) 419 420 #define ENETC_PORT_PRXSDUOR_MACSEC_BCO_MASK (0x1F00U) 421 #define ENETC_PORT_PRXSDUOR_MACSEC_BCO_SHIFT (8U) 422 #define ENETC_PORT_PRXSDUOR_MACSEC_BCO_WIDTH (5U) 423 #define ENETC_PORT_PRXSDUOR_MACSEC_BCO(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PORT_PRXSDUOR_MACSEC_BCO_SHIFT)) & ENETC_PORT_PRXSDUOR_MACSEC_BCO_MASK) 424 /*! @} */ 425 426 /*! @name PTXSDUOR - Port transmit SDU overhead register */ 427 /*! @{ */ 428 429 #define ENETC_PORT_PTXSDUOR_PPDU_BCO_MASK (0x1FU) 430 #define ENETC_PORT_PTXSDUOR_PPDU_BCO_SHIFT (0U) 431 #define ENETC_PORT_PTXSDUOR_PPDU_BCO_WIDTH (5U) 432 #define ENETC_PORT_PTXSDUOR_PPDU_BCO(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PORT_PTXSDUOR_PPDU_BCO_SHIFT)) & ENETC_PORT_PTXSDUOR_PPDU_BCO_MASK) 433 434 #define ENETC_PORT_PTXSDUOR_MACSEC_BCO_MASK (0x1F00U) 435 #define ENETC_PORT_PTXSDUOR_MACSEC_BCO_SHIFT (8U) 436 #define ENETC_PORT_PTXSDUOR_MACSEC_BCO_WIDTH (5U) 437 #define ENETC_PORT_PTXSDUOR_MACSEC_BCO(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PORT_PTXSDUOR_MACSEC_BCO_SHIFT)) & ENETC_PORT_PTXSDUOR_MACSEC_BCO_MASK) 438 /*! @} */ 439 440 /*! @name PTGSCR - Port time gate scheduling control register */ 441 /*! @{ */ 442 443 #define ENETC_PORT_PTGSCR_TGE_MASK (0x80000000U) 444 #define ENETC_PORT_PTGSCR_TGE_SHIFT (31U) 445 #define ENETC_PORT_PTGSCR_TGE_WIDTH (1U) 446 #define ENETC_PORT_PTGSCR_TGE(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PORT_PTGSCR_TGE_SHIFT)) & ENETC_PORT_PTGSCR_TGE_MASK) 447 /*! @} */ 448 449 /*! @name PTGAGLSR - Port time gate scheduling admin gate list status register */ 450 /*! @{ */ 451 452 #define ENETC_PORT_PTGAGLSR_TG_MASK (0x1U) 453 #define ENETC_PORT_PTGAGLSR_TG_SHIFT (0U) 454 #define ENETC_PORT_PTGAGLSR_TG_WIDTH (1U) 455 #define ENETC_PORT_PTGAGLSR_TG(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PORT_PTGAGLSR_TG_SHIFT)) & ENETC_PORT_PTGAGLSR_TG_MASK) 456 457 #define ENETC_PORT_PTGAGLSR_CFG_PEND_MASK (0x2U) 458 #define ENETC_PORT_PTGAGLSR_CFG_PEND_SHIFT (1U) 459 #define ENETC_PORT_PTGAGLSR_CFG_PEND_WIDTH (1U) 460 #define ENETC_PORT_PTGAGLSR_CFG_PEND(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PORT_PTGAGLSR_CFG_PEND_SHIFT)) & ENETC_PORT_PTGAGLSR_CFG_PEND_MASK) 461 /*! @} */ 462 463 /*! @name PTGAGLLR - Port time gate scheduling admin gate list length register */ 464 /*! @{ */ 465 466 #define ENETC_PORT_PTGAGLLR_ADMIN_GATE_LIST_LENGTH_MASK (0xFFFFU) 467 #define ENETC_PORT_PTGAGLLR_ADMIN_GATE_LIST_LENGTH_SHIFT (0U) 468 #define ENETC_PORT_PTGAGLLR_ADMIN_GATE_LIST_LENGTH_WIDTH (16U) 469 #define ENETC_PORT_PTGAGLLR_ADMIN_GATE_LIST_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PORT_PTGAGLLR_ADMIN_GATE_LIST_LENGTH_SHIFT)) & ENETC_PORT_PTGAGLLR_ADMIN_GATE_LIST_LENGTH_MASK) 470 /*! @} */ 471 472 /*! @name PTGOGLLR - Port time gating operational gate list length register */ 473 /*! @{ */ 474 475 #define ENETC_PORT_PTGOGLLR_OPER_GATE_LIST_LENGTH_MASK (0xFFFFU) 476 #define ENETC_PORT_PTGOGLLR_OPER_GATE_LIST_LENGTH_SHIFT (0U) 477 #define ENETC_PORT_PTGOGLLR_OPER_GATE_LIST_LENGTH_WIDTH (16U) 478 #define ENETC_PORT_PTGOGLLR_OPER_GATE_LIST_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PORT_PTGOGLLR_OPER_GATE_LIST_LENGTH_SHIFT)) & ENETC_PORT_PTGOGLLR_OPER_GATE_LIST_LENGTH_MASK) 479 /*! @} */ 480 481 /*! @name PTGSATOR - Port time gate scheduling advance time offset register */ 482 /*! @{ */ 483 484 #define ENETC_PORT_PTGSATOR_ADV_TIME_OFFSET_MASK (0xFFFFU) 485 #define ENETC_PORT_PTGSATOR_ADV_TIME_OFFSET_SHIFT (0U) 486 #define ENETC_PORT_PTGSATOR_ADV_TIME_OFFSET_WIDTH (16U) 487 #define ENETC_PORT_PTGSATOR_ADV_TIME_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PORT_PTGSATOR_ADV_TIME_OFFSET_SHIFT)) & ENETC_PORT_PTGSATOR_ADV_TIME_OFFSET_MASK) 488 /*! @} */ 489 490 /*! @name PRXDCR - Port Rx discard count register */ 491 /*! @{ */ 492 493 #define ENETC_PORT_PRXDCR_COUNT_MASK (0xFFFFFFFFU) 494 #define ENETC_PORT_PRXDCR_COUNT_SHIFT (0U) 495 #define ENETC_PORT_PRXDCR_COUNT_WIDTH (32U) 496 #define ENETC_PORT_PRXDCR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PORT_PRXDCR_COUNT_SHIFT)) & ENETC_PORT_PRXDCR_COUNT_MASK) 497 /*! @} */ 498 499 /*! @name PRXDCRR0 - Port Rx discard count reason register 0 */ 500 /*! @{ */ 501 502 #define ENETC_PORT_PRXDCRR0_PCDR_MASK (0x1U) 503 #define ENETC_PORT_PRXDCRR0_PCDR_SHIFT (0U) 504 #define ENETC_PORT_PRXDCRR0_PCDR_WIDTH (1U) 505 #define ENETC_PORT_PRXDCRR0_PCDR(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PORT_PRXDCRR0_PCDR_SHIFT)) & ENETC_PORT_PRXDCRR0_PCDR_MASK) 506 507 #define ENETC_PORT_PRXDCRR0_SMREDR_MASK (0x2U) 508 #define ENETC_PORT_PRXDCRR0_SMREDR_SHIFT (1U) 509 #define ENETC_PORT_PRXDCRR0_SMREDR_WIDTH (1U) 510 #define ENETC_PORT_PRXDCRR0_SMREDR(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PORT_PRXDCRR0_SMREDR_SHIFT)) & ENETC_PORT_PRXDCRR0_SMREDR_MASK) 511 512 #define ENETC_PORT_PRXDCRR0_RXDISDR_MASK (0x4U) 513 #define ENETC_PORT_PRXDCRR0_RXDISDR_SHIFT (2U) 514 #define ENETC_PORT_PRXDCRR0_RXDISDR_WIDTH (1U) 515 #define ENETC_PORT_PRXDCRR0_RXDISDR(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PORT_PRXDCRR0_RXDISDR_SHIFT)) & ENETC_PORT_PRXDCRR0_RXDISDR_MASK) 516 517 #define ENETC_PORT_PRXDCRR0_IPFDR_MASK (0x8U) 518 #define ENETC_PORT_PRXDCRR0_IPFDR_SHIFT (3U) 519 #define ENETC_PORT_PRXDCRR0_IPFDR_WIDTH (1U) 520 #define ENETC_PORT_PRXDCRR0_IPFDR(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PORT_PRXDCRR0_IPFDR_SHIFT)) & ENETC_PORT_PRXDCRR0_IPFDR_MASK) 521 522 #define ENETC_PORT_PRXDCRR0_RPDR_MASK (0x10U) 523 #define ENETC_PORT_PRXDCRR0_RPDR_SHIFT (4U) 524 #define ENETC_PORT_PRXDCRR0_RPDR_WIDTH (1U) 525 #define ENETC_PORT_PRXDCRR0_RPDR(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PORT_PRXDCRR0_RPDR_SHIFT)) & ENETC_PORT_PRXDCRR0_RPDR_MASK) 526 527 #define ENETC_PORT_PRXDCRR0_ISFDR_MASK (0x20U) 528 #define ENETC_PORT_PRXDCRR0_ISFDR_SHIFT (5U) 529 #define ENETC_PORT_PRXDCRR0_ISFDR_WIDTH (1U) 530 #define ENETC_PORT_PRXDCRR0_ISFDR(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PORT_PRXDCRR0_ISFDR_SHIFT)) & ENETC_PORT_PRXDCRR0_ISFDR_MASK) 531 532 #define ENETC_PORT_PRXDCRR0_SGCDR_MASK (0x40U) 533 #define ENETC_PORT_PRXDCRR0_SGCDR_SHIFT (6U) 534 #define ENETC_PORT_PRXDCRR0_SGCDR_WIDTH (1U) 535 #define ENETC_PORT_PRXDCRR0_SGCDR(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PORT_PRXDCRR0_SGCDR_SHIFT)) & ENETC_PORT_PRXDCRR0_SGCDR_MASK) 536 537 #define ENETC_PORT_PRXDCRR0_SGOEDR_MASK (0x80U) 538 #define ENETC_PORT_PRXDCRR0_SGOEDR_SHIFT (7U) 539 #define ENETC_PORT_PRXDCRR0_SGOEDR_WIDTH (1U) 540 #define ENETC_PORT_PRXDCRR0_SGOEDR(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PORT_PRXDCRR0_SGOEDR_SHIFT)) & ENETC_PORT_PRXDCRR0_SGOEDR_MASK) 541 542 #define ENETC_PORT_PRXDCRR0_MSDUEDR_MASK (0x100U) 543 #define ENETC_PORT_PRXDCRR0_MSDUEDR_SHIFT (8U) 544 #define ENETC_PORT_PRXDCRR0_MSDUEDR_WIDTH (1U) 545 #define ENETC_PORT_PRXDCRR0_MSDUEDR(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PORT_PRXDCRR0_MSDUEDR_SHIFT)) & ENETC_PORT_PRXDCRR0_MSDUEDR_MASK) 546 547 #define ENETC_PORT_PRXDCRR0_ITEDR_MASK (0x800U) 548 #define ENETC_PORT_PRXDCRR0_ITEDR_SHIFT (11U) 549 #define ENETC_PORT_PRXDCRR0_ITEDR_WIDTH (1U) 550 #define ENETC_PORT_PRXDCRR0_ITEDR(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PORT_PRXDCRR0_ITEDR_SHIFT)) & ENETC_PORT_PRXDCRR0_ITEDR_MASK) 551 552 #define ENETC_PORT_PRXDCRR0_ECCEDR_MASK (0x1000U) 553 #define ENETC_PORT_PRXDCRR0_ECCEDR_SHIFT (12U) 554 #define ENETC_PORT_PRXDCRR0_ECCEDR_WIDTH (1U) 555 #define ENETC_PORT_PRXDCRR0_ECCEDR(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PORT_PRXDCRR0_ECCEDR_SHIFT)) & ENETC_PORT_PRXDCRR0_ECCEDR_MASK) 556 557 #define ENETC_PORT_PRXDCRR0_SIFDR_MASK (0x2000U) 558 #define ENETC_PORT_PRXDCRR0_SIFDR_SHIFT (13U) 559 #define ENETC_PORT_PRXDCRR0_SIFDR_WIDTH (1U) 560 #define ENETC_PORT_PRXDCRR0_SIFDR(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PORT_PRXDCRR0_SIFDR_SHIFT)) & ENETC_PORT_PRXDCRR0_SIFDR_MASK) 561 562 #define ENETC_PORT_PRXDCRR0_L2DOSDR_MASK (0x4000U) 563 #define ENETC_PORT_PRXDCRR0_L2DOSDR_SHIFT (14U) 564 #define ENETC_PORT_PRXDCRR0_L2DOSDR_WIDTH (1U) 565 #define ENETC_PORT_PRXDCRR0_L2DOSDR(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PORT_PRXDCRR0_L2DOSDR_SHIFT)) & ENETC_PORT_PRXDCRR0_L2DOSDR_MASK) 566 567 #define ENETC_PORT_PRXDCRR0_PEDR_MASK (0x10000U) 568 #define ENETC_PORT_PRXDCRR0_PEDR_SHIFT (16U) 569 #define ENETC_PORT_PRXDCRR0_PEDR_WIDTH (1U) 570 #define ENETC_PORT_PRXDCRR0_PEDR(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PORT_PRXDCRR0_PEDR_SHIFT)) & ENETC_PORT_PRXDCRR0_PEDR_MASK) 571 572 #define ENETC_PORT_PRXDCRR0_NODESTDR_MASK (0x20000U) 573 #define ENETC_PORT_PRXDCRR0_NODESTDR_SHIFT (17U) 574 #define ENETC_PORT_PRXDCRR0_NODESTDR_WIDTH (1U) 575 #define ENETC_PORT_PRXDCRR0_NODESTDR(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PORT_PRXDCRR0_NODESTDR_SHIFT)) & ENETC_PORT_PRXDCRR0_NODESTDR_MASK) 576 /*! @} */ 577 578 /*! @name PRXDCRR1 - Port Rx discard count reason register 1 */ 579 /*! @{ */ 580 581 #define ENETC_PORT_PRXDCRR1_ENTRYID_MASK (0xFFFFU) 582 #define ENETC_PORT_PRXDCRR1_ENTRYID_SHIFT (0U) 583 #define ENETC_PORT_PRXDCRR1_ENTRYID_WIDTH (16U) 584 #define ENETC_PORT_PRXDCRR1_ENTRYID(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PORT_PRXDCRR1_ENTRYID_SHIFT)) & ENETC_PORT_PRXDCRR1_ENTRYID_MASK) 585 586 #define ENETC_PORT_PRXDCRR1_TT_MASK (0xF0000000U) 587 #define ENETC_PORT_PRXDCRR1_TT_SHIFT (28U) 588 #define ENETC_PORT_PRXDCRR1_TT_WIDTH (4U) 589 #define ENETC_PORT_PRXDCRR1_TT(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PORT_PRXDCRR1_TT_SHIFT)) & ENETC_PORT_PRXDCRR1_TT_MASK) 590 /*! @} */ 591 592 /*! @name PTGSTCSR - Port time gate scheduling traffic class 0 status register..Port time gate scheduling traffic class 7 status register */ 593 /*! @{ */ 594 595 #define ENETC_PORT_PTGSTCSR_LH_STATE_MASK (0x10000U) 596 #define ENETC_PORT_PTGSTCSR_LH_STATE_SHIFT (16U) 597 #define ENETC_PORT_PTGSTCSR_LH_STATE_WIDTH (1U) 598 #define ENETC_PORT_PTGSTCSR_LH_STATE(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PORT_PTGSTCSR_LH_STATE_SHIFT)) & ENETC_PORT_PTGSTCSR_LH_STATE_MASK) 599 /*! @} */ 600 601 /*! @name PTCTMSDUR - Port traffic class 0 transmit maximum SDU register..Port traffic class 7 transmit maximum SDU register */ 602 /*! @{ */ 603 604 #define ENETC_PORT_PTCTMSDUR_MAXSDU_MASK (0xFFFFU) 605 #define ENETC_PORT_PTCTMSDUR_MAXSDU_SHIFT (0U) 606 #define ENETC_PORT_PTCTMSDUR_MAXSDU_WIDTH (16U) 607 #define ENETC_PORT_PTCTMSDUR_MAXSDU(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PORT_PTCTMSDUR_MAXSDU_SHIFT)) & ENETC_PORT_PTCTMSDUR_MAXSDU_MASK) 608 609 #define ENETC_PORT_PTCTMSDUR_SDU_TYPE_MASK (0x30000U) 610 #define ENETC_PORT_PTCTMSDUR_SDU_TYPE_SHIFT (16U) 611 #define ENETC_PORT_PTCTMSDUR_SDU_TYPE_WIDTH (2U) 612 #define ENETC_PORT_PTCTMSDUR_SDU_TYPE(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PORT_PTCTMSDUR_SDU_TYPE_SHIFT)) & ENETC_PORT_PTCTMSDUR_SDU_TYPE_MASK) 613 614 #define ENETC_PORT_PTCTMSDUR_SF_MAXSDU_DIS_MASK (0x1000000U) 615 #define ENETC_PORT_PTCTMSDUR_SF_MAXSDU_DIS_SHIFT (24U) 616 #define ENETC_PORT_PTCTMSDUR_SF_MAXSDU_DIS_WIDTH (1U) 617 #define ENETC_PORT_PTCTMSDUR_SF_MAXSDU_DIS(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PORT_PTCTMSDUR_SF_MAXSDU_DIS_SHIFT)) & ENETC_PORT_PTCTMSDUR_SF_MAXSDU_DIS_MASK) 618 /*! @} */ 619 620 /*! @name PTCCBSR0 - Port transmit traffic class 0 credit based shaper register 0..Port transmit traffic class 7 credit based shaper register 0 */ 621 /*! @{ */ 622 623 #define ENETC_PORT_PTCCBSR0_BW_MASK (0x7FU) 624 #define ENETC_PORT_PTCCBSR0_BW_SHIFT (0U) 625 #define ENETC_PORT_PTCCBSR0_BW_WIDTH (7U) 626 #define ENETC_PORT_PTCCBSR0_BW(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PORT_PTCCBSR0_BW_SHIFT)) & ENETC_PORT_PTCCBSR0_BW_MASK) 627 628 #define ENETC_PORT_PTCCBSR0_CBSE_MASK (0x80000000U) 629 #define ENETC_PORT_PTCCBSR0_CBSE_SHIFT (31U) 630 #define ENETC_PORT_PTCCBSR0_CBSE_WIDTH (1U) 631 #define ENETC_PORT_PTCCBSR0_CBSE(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PORT_PTCCBSR0_CBSE_SHIFT)) & ENETC_PORT_PTCCBSR0_CBSE_MASK) 632 /*! @} */ 633 634 /*! @name PTCCBSR1 - Port traffic class 0 credit based shaper register 1..Port traffic class 7 credit based shaper register 1 */ 635 /*! @{ */ 636 637 #define ENETC_PORT_PTCCBSR1_HI_CREDIT_MASK (0xFFFFFFFFU) 638 #define ENETC_PORT_PTCCBSR1_HI_CREDIT_SHIFT (0U) 639 #define ENETC_PORT_PTCCBSR1_HI_CREDIT_WIDTH (32U) 640 #define ENETC_PORT_PTCCBSR1_HI_CREDIT(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PORT_PTCCBSR1_HI_CREDIT_SHIFT)) & ENETC_PORT_PTCCBSR1_HI_CREDIT_MASK) 641 /*! @} */ 642 643 /*! @name PPCPDEIMR - Port PCP DEI mapping register */ 644 /*! @{ */ 645 646 #define ENETC_PORT_PPCPDEIMR_IPCPMP_MASK (0xFU) 647 #define ENETC_PORT_PPCPDEIMR_IPCPMP_SHIFT (0U) 648 #define ENETC_PORT_PPCPDEIMR_IPCPMP_WIDTH (4U) 649 #define ENETC_PORT_PPCPDEIMR_IPCPMP(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PORT_PPCPDEIMR_IPCPMP_SHIFT)) & ENETC_PORT_PPCPDEIMR_IPCPMP_MASK) 650 651 #define ENETC_PORT_PPCPDEIMR_IPCPMPV_MASK (0x80U) 652 #define ENETC_PORT_PPCPDEIMR_IPCPMPV_SHIFT (7U) 653 #define ENETC_PORT_PPCPDEIMR_IPCPMPV_WIDTH (1U) 654 #define ENETC_PORT_PPCPDEIMR_IPCPMPV(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PORT_PPCPDEIMR_IPCPMPV_SHIFT)) & ENETC_PORT_PPCPDEIMR_IPCPMPV_MASK) 655 656 #define ENETC_PORT_PPCPDEIMR_EPCPMP_MASK (0xF00U) 657 #define ENETC_PORT_PPCPDEIMR_EPCPMP_SHIFT (8U) 658 #define ENETC_PORT_PPCPDEIMR_EPCPMP_WIDTH (4U) 659 #define ENETC_PORT_PPCPDEIMR_EPCPMP(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PORT_PPCPDEIMR_EPCPMP_SHIFT)) & ENETC_PORT_PPCPDEIMR_EPCPMP_MASK) 660 661 #define ENETC_PORT_PPCPDEIMR_EPCPMPV_MASK (0x8000U) 662 #define ENETC_PORT_PPCPDEIMR_EPCPMPV_SHIFT (15U) 663 #define ENETC_PORT_PPCPDEIMR_EPCPMPV_WIDTH (1U) 664 #define ENETC_PORT_PPCPDEIMR_EPCPMPV(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PORT_PPCPDEIMR_EPCPMPV_SHIFT)) & ENETC_PORT_PPCPDEIMR_EPCPMPV_MASK) 665 666 #define ENETC_PORT_PPCPDEIMR_DR0DEI_MASK (0x10000U) 667 #define ENETC_PORT_PPCPDEIMR_DR0DEI_SHIFT (16U) 668 #define ENETC_PORT_PPCPDEIMR_DR0DEI_WIDTH (1U) 669 #define ENETC_PORT_PPCPDEIMR_DR0DEI(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PORT_PPCPDEIMR_DR0DEI_SHIFT)) & ENETC_PORT_PPCPDEIMR_DR0DEI_MASK) 670 671 #define ENETC_PORT_PPCPDEIMR_DR1DEI_MASK (0x20000U) 672 #define ENETC_PORT_PPCPDEIMR_DR1DEI_SHIFT (17U) 673 #define ENETC_PORT_PPCPDEIMR_DR1DEI_WIDTH (1U) 674 #define ENETC_PORT_PPCPDEIMR_DR1DEI(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PORT_PPCPDEIMR_DR1DEI_SHIFT)) & ENETC_PORT_PPCPDEIMR_DR1DEI_MASK) 675 676 #define ENETC_PORT_PPCPDEIMR_DR2DEI_MASK (0x40000U) 677 #define ENETC_PORT_PPCPDEIMR_DR2DEI_SHIFT (18U) 678 #define ENETC_PORT_PPCPDEIMR_DR2DEI_WIDTH (1U) 679 #define ENETC_PORT_PPCPDEIMR_DR2DEI(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PORT_PPCPDEIMR_DR2DEI_SHIFT)) & ENETC_PORT_PPCPDEIMR_DR2DEI_MASK) 680 681 #define ENETC_PORT_PPCPDEIMR_DR3DEI_MASK (0x80000U) 682 #define ENETC_PORT_PPCPDEIMR_DR3DEI_SHIFT (19U) 683 #define ENETC_PORT_PPCPDEIMR_DR3DEI_WIDTH (1U) 684 #define ENETC_PORT_PPCPDEIMR_DR3DEI(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PORT_PPCPDEIMR_DR3DEI_SHIFT)) & ENETC_PORT_PPCPDEIMR_DR3DEI_MASK) 685 686 #define ENETC_PORT_PPCPDEIMR_DRME_MASK (0x100000U) 687 #define ENETC_PORT_PPCPDEIMR_DRME_SHIFT (20U) 688 #define ENETC_PORT_PPCPDEIMR_DRME_WIDTH (1U) 689 #define ENETC_PORT_PPCPDEIMR_DRME(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PORT_PPCPDEIMR_DRME_SHIFT)) & ENETC_PORT_PPCPDEIMR_DRME_MASK) 690 /*! @} */ 691 692 /*! @name PISIDCR - Port ingress stream identification configuration register */ 693 /*! @{ */ 694 695 #define ENETC_PORT_PISIDCR_KCPAIR_MASK (0x1U) 696 #define ENETC_PORT_PISIDCR_KCPAIR_SHIFT (0U) 697 #define ENETC_PORT_PISIDCR_KCPAIR_WIDTH (1U) 698 #define ENETC_PORT_PISIDCR_KCPAIR(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PORT_PISIDCR_KCPAIR_SHIFT)) & ENETC_PORT_PISIDCR_KCPAIR_MASK) 699 700 #define ENETC_PORT_PISIDCR_KC0EN_MASK (0x2U) 701 #define ENETC_PORT_PISIDCR_KC0EN_SHIFT (1U) 702 #define ENETC_PORT_PISIDCR_KC0EN_WIDTH (1U) 703 #define ENETC_PORT_PISIDCR_KC0EN(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PORT_PISIDCR_KC0EN_SHIFT)) & ENETC_PORT_PISIDCR_KC0EN_MASK) 704 705 #define ENETC_PORT_PISIDCR_KC1EN_MASK (0x4U) 706 #define ENETC_PORT_PISIDCR_KC1EN_SHIFT (2U) 707 #define ENETC_PORT_PISIDCR_KC1EN_WIDTH (1U) 708 #define ENETC_PORT_PISIDCR_KC1EN(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PORT_PISIDCR_KC1EN_SHIFT)) & ENETC_PORT_PISIDCR_KC1EN_MASK) 709 710 #define ENETC_PORT_PISIDCR_ISEID_MASK (0xFFFF0000U) 711 #define ENETC_PORT_PISIDCR_ISEID_SHIFT (16U) 712 #define ENETC_PORT_PISIDCR_ISEID_WIDTH (16U) 713 #define ENETC_PORT_PISIDCR_ISEID(x) (((uint32_t)(((uint32_t)(x)) << ENETC_PORT_PISIDCR_ISEID_SHIFT)) & ENETC_PORT_PISIDCR_ISEID_MASK) 714 /*! @} */ 715 716 /*! 717 * @} 718 */ /* end of group ENETC_PORT_Register_Masks */ 719 720 /*! 721 * @} 722 */ /* end of group ENETC_PORT_Peripheral_Access_Layer */ 723 724 #endif /* #if !defined(S32Z2_ENETC_PORT_H_) */ 725
