1 /*
2 * Copyright 2020-2023 NXP
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #ifndef EMIOS_PWM_IP_HWACCESS_H
8 #define EMIOS_PWM_IP_HWACCESS_H
9
10 /**
11 * @file Emios_Pwm_Ip_HwAccess.h
12 * @implements Emios_Pwm_Ip_HwAccess.h_Artifact
13 *
14 * @addtogroup emios_pwm_ip Emios Pwm IPL
15 * @{
16 */
17
18 #ifdef __cplusplus
19 extern "C"{
20 #endif
21
22
23 /*==================================================================================================
24 * INCLUDE FILES
25 * 1) system and project includes
26 * 2) needed interfaces from external units
27 * 3) internal and external interfaces from this unit
28 ==================================================================================================*/
29 #include "Std_Types.h"
30 #include "Emios_Pwm_Ip_Cfg.h"
31
32 /*==================================================================================================
33 * SOURCE FILE VERSION INFORMATION
34 ==================================================================================================*/
35 #define EMIOS_PWM_IP_HWACCESS_VENDOR_ID 43
36 #define EMIOS_PWM_IP_HWACCESS_MODULE_ID 121
37 #define EMIOS_PWM_IP_HWACCESS_AR_RELEASE_MAJOR_VERSION 4
38 #define EMIOS_PWM_IP_HWACCESS_AR_RELEASE_MINOR_VERSION 7
39 #define EMIOS_PWM_IP_HWACCESS_AR_RELEASE_REVISION_VERSION 0
40 #define EMIOS_PWM_IP_HWACCESS_SW_MAJOR_VERSION 3
41 #define EMIOS_PWM_IP_HWACCESS_SW_MINOR_VERSION 0
42 #define EMIOS_PWM_IP_HWACCESS_SW_PATCH_VERSION 0
43
44 /*==================================================================================================
45 * FILE VERSION CHECKS
46 ==================================================================================================*/
47 #ifndef DISABLE_MCAL_INTERMODULE_ASR_CHECK
48 /* Check if header file and Std_Types.h are of the same AUTOSAR version */
49 #if ((EMIOS_PWM_IP_HWACCESS_AR_RELEASE_MAJOR_VERSION != STD_AR_RELEASE_MAJOR_VERSION) || \
50 (EMIOS_PWM_IP_HWACCESS_AR_RELEASE_MINOR_VERSION != STD_AR_RELEASE_MINOR_VERSION))
51 #error "AUTOSAR Version Numbers of Emios_Pwm_Ip_HwAccess.h and Std_Types.h are different"
52 #endif
53 #endif
54
55 /* Check if header file and Emios_Pwm_Ip_Cfg header file are of the same vendor */
56 #if (EMIOS_PWM_IP_HWACCESS_VENDOR_ID != EMIOS_PWM_IP_CFG_VENDOR_ID)
57 #error "Vendor IDs of Emios_Pwm_Ip_HwAccess.h and Emios_Pwm_Ip_Cfg.h are different."
58 #endif
59
60 /* Check if header file and Emios_Pwm_Ip_Cfg header file are of the same AUTOSAR version */
61 #if ((EMIOS_PWM_IP_HWACCESS_AR_RELEASE_MAJOR_VERSION != EMIOS_PWM_IP_CFG_AR_RELEASE_MAJOR_VERSION) || \
62 (EMIOS_PWM_IP_HWACCESS_AR_RELEASE_MINOR_VERSION != EMIOS_PWM_IP_CFG_AR_RELEASE_MINOR_VERSION) || \
63 (EMIOS_PWM_IP_HWACCESS_AR_RELEASE_REVISION_VERSION != EMIOS_PWM_IP_CFG_AR_RELEASE_REVISION_VERSION))
64 #error "AUTOSAR version numbers of Emios_Pwm_Ip_HwAccess.h and Emios_Pwm_Ip_Cfg.h are different."
65 #endif
66
67 /* Check if header file and Emios_Pwm_Ip_Cfg header file are of the same software version */
68 #if ((EMIOS_PWM_IP_HWACCESS_SW_MAJOR_VERSION != EMIOS_PWM_IP_CFG_SW_MAJOR_VERSION) || \
69 (EMIOS_PWM_IP_HWACCESS_SW_MINOR_VERSION != EMIOS_PWM_IP_CFG_SW_MINOR_VERSION) || \
70 (EMIOS_PWM_IP_HWACCESS_SW_PATCH_VERSION != EMIOS_PWM_IP_CFG_SW_PATCH_VERSION))
71 #error "Software version numbers of Emios_Pwm_Ip_HwAccess.h and Emios_Pwm_Ip_Cfg.h are different."
72 #endif
73
74 /*==================================================================================================
75 * CONSTANTS
76 ==================================================================================================*/
77
78 /*==================================================================================================
79 * DEFINES AND MACROS
80 ==================================================================================================*/
81
82 /*==================================================================================================
83 * ENUMS
84 ==================================================================================================*/
85 /*!
86 * @brief Emios PWM Channel modes
87 */
88 typedef enum
89 {
90 /** @brief Output Pulse Width and Frequency Modulation Buffered.*/
91 EMIOS_PWM_IP_HW_MODE_OPWFMB = 0x00U,
92 /** @brief Center Aligned Output Pulse Width Modulation Buffered */
93 EMIOS_PWM_IP_HW_MODE_OPWMCB = 0x01U,
94 /** @brief Output Pulse Width Modulation Buffered. */
95 EMIOS_PWM_IP_HW_MODE_OPWMB = 0x02U,
96 /** @brief Output Pulse-Width Modulation with Trigger */
97 EMIOS_PWM_IP_HW_MODE_OPWMT = 0x03U,
98 /** @brief Double Action Output Compare */
99 EMIOS_PWM_IP_HW_MODE_DAOC = 0x04U,
100 /** @brief Center Aligned Output Pulse Width Modulation */
101 EMIOS_PWM_IP_HW_MODE_OPWMC = 0x05U,
102 /** @brief Output Pulse Width Modulation. */
103 EMIOS_PWM_IP_HW_MODE_OPWM = 0x06U,
104 /** @brief Output Pulse Width and Frequency Modulation.*/
105 EMIOS_PWM_IP_HW_MODE_OPWFM = 0x07U
106 } Emios_Pwm_Ip_PwmType;
107
108 /*!
109 * @brief Emios PWM master bus modes
110 */
111 typedef enum
112 {
113 EMIOS_PWM_IP_MC_UP_COUNTER_START = 16u,
114 EMIOS_PWM_IP_MC_UP_COUNTER_END = 18u,
115 EMIOS_PWM_IP_MC_UP_DOWN_COUNTER = 20u,
116 EMIOS_PWM_IP_MCB_UP_COUNTER = 80u,
117 EMIOS_PWM_IP_MCB_UP_DOWN_COUNTER = 84u,
118 EMIOS_PWM_IP_NODEFINE_COUNTER = 0u
119 } Emios_Pwm_Ip_MasterBusModeType;
120
121 /*==================================================================================================
122 * STRUCTURES AND OTHER TYPEDEFS
123 ==================================================================================================*/
124
125 /*==================================================================================================
126 * GLOBAL VARIABLE DECLARATIONS
127 ==================================================================================================*/
128
129 /*==================================================================================================
130 * FUNCTION PROTOTYPES
131 ==================================================================================================*/
132 #define PWM_START_SEC_CODE
133 #include "Pwm_MemMap.h"
134 /*-----------------------MCR Register----------------------------*/
135 /*!
136 * brief Get MCR Freeze enable bit
137 * param[in] Base The Emios base address pointer
138 */
Emios_Pwm_Ip_GetDebugMode(const Emios_Pwm_Ip_HwAddrType * const Base)139 static inline boolean Emios_Pwm_Ip_GetDebugMode(const Emios_Pwm_Ip_HwAddrType *const Base)
140 {
141 return (((Base->MCR & eMIOS_MCR_FRZ_MASK) >> eMIOS_MCR_FRZ_SHIFT) == 0U)? FALSE : TRUE;
142 }
143
144 /*-----------------------OUDIS Register----------------------------*/
145 /*!
146 * brief Set OUDIS Channel n enable bit
147 * param[in] Base The Emios Base address pointer
148 * param[in] Channel The Channel id for the given instance
149 * param[in] Value The Value to set
150 */
Emios_Pwm_Ip_SetOutputUpdate(Emios_Pwm_Ip_HwAddrType * const Base,uint8 Channel,boolean Value)151 static inline void Emios_Pwm_Ip_SetOutputUpdate(Emios_Pwm_Ip_HwAddrType *const Base,
152 uint8 Channel,
153 boolean Value)
154 {
155 Base->OUDIS = Base->OUDIS | (eMIOS_OUDIS_OU0((Value == TRUE) ? 0x00U : 0x01U) << Channel);
156 }
157
158 /*!
159 * brief Get OUDIS Channel n enable bit
160 * param[in] Base The Emios Base address pointer
161 * param[in] Channel The Channel id for the given instance
162 */
Emios_Pwm_Ip_GetOutputUpdate(const Emios_Pwm_Ip_HwAddrType * const Base,uint8 Channel)163 static inline boolean Emios_Pwm_Ip_GetOutputUpdate(const Emios_Pwm_Ip_HwAddrType *const Base,
164 uint8 Channel)
165 {
166 return (((Base->OUDIS & (uint32)((uint32)eMIOS_OUDIS_OU0_MASK << (uint32)Channel)) >> Channel) == 0U) ? TRUE : FALSE;
167 }
168
169 /*!
170 * brief Get OUDIS register
171 * param[in] Base The Emios Base address pointer
172 */
Emios_Pwm_Ip_GetOutputUpdateInstance(const Emios_Pwm_Ip_HwAddrType * const Base)173 static inline uint32 Emios_Pwm_Ip_GetOutputUpdateInstance(const Emios_Pwm_Ip_HwAddrType *const Base)
174 {
175 return (Base->OUDIS);
176 }
177
178 /*-----------------------UCDIS Register----------------------------*/
179 /*!
180 * brief Set UCDIS Channel n enable bit
181 * param[in] Base The Emios Base address pointer
182 * param[in] Channel The Channel id for the given instance
183 * param[in] Value The Value to set
184 */
Emios_Pwm_Ip_SetChannelEnable(Emios_Pwm_Ip_HwAddrType * const Base,uint8 Channel,boolean Value)185 static inline void Emios_Pwm_Ip_SetChannelEnable(Emios_Pwm_Ip_HwAddrType *const Base,
186 uint8 Channel,
187 boolean Value)
188 {
189 Base->UCDIS = Base->UCDIS | (eMIOS_UCDIS_UCDIS0((Value == TRUE) ? 0x00U : 0x01U) << Channel);
190 }
191
192 /*!
193 * brief Get UCDIS Channel n enable bit
194 * param[in] Base The Emios Base address pointer
195 * param[in] Channel The Channel id for the given instance
196 * param[in] Value The Value to set
197 */
Emios_Pwm_Ip_GetChannelEnable(const Emios_Pwm_Ip_HwAddrType * const Base,uint8 Channel)198 static inline boolean Emios_Pwm_Ip_GetChannelEnable(const Emios_Pwm_Ip_HwAddrType *const Base,
199 uint8 Channel)
200 {
201 return (((Base->UCDIS & (uint32)((uint32)eMIOS_UCDIS_UCDIS0_MASK << (uint32)Channel)) >> Channel) == 0U) ? TRUE : FALSE;
202 }
203
204 /*-----------------------UC register A-----------------------------*/
205 /*!
206 * brief Set A register's Value, maximum Value is 0xFFFFFF
207 * param[in] Base The Emios Base address pointer
208 * param[in] Channel The Channel id for the given instance
209 * param[in] Value The Value to set
210 */
Emios_Pwm_Ip_SetUCRegA(Emios_Pwm_Ip_HwAddrType * const Base,uint8 Channel,Emios_Pwm_Ip_PeriodType Value)211 static inline void Emios_Pwm_Ip_SetUCRegA(Emios_Pwm_Ip_HwAddrType *const Base,
212 uint8 Channel,
213 Emios_Pwm_Ip_PeriodType Value)
214 {
215 Base->CH.UC[Channel].A = eMIOS_A_A(Value);
216 }
217
218 /*!
219 * brief Get A register's Value
220 * param[in] Base The Emios Base address pointer
221 * param[in] Channel The Channel id for the given instance
222 * return Value of Unified Channels A register
223 */
Emios_Pwm_Ip_GetUCRegA(const Emios_Pwm_Ip_HwAddrType * const Base,uint8 Channel)224 static inline Emios_Pwm_Ip_PeriodType Emios_Pwm_Ip_GetUCRegA(const Emios_Pwm_Ip_HwAddrType *const Base,
225 uint8 Channel)
226 {
227 return (Emios_Pwm_Ip_PeriodType)((Base->CH.UC[Channel].A & eMIOS_A_A_MASK) >> eMIOS_A_A_SHIFT);
228 }
229
230 /*-----------------------UC register B-----------------------------*/
231 /*!
232 * brief Set B register's Value, maximum Value is 0xFFFFFF
233 * param[in] Base The Emios Base address pointer
234 * param[in] Channel The Channel id for the given instance
235 * param[in] Value The Value to set
236 */
Emios_Pwm_Ip_SetUCRegB(Emios_Pwm_Ip_HwAddrType * const Base,uint8 Channel,Emios_Pwm_Ip_PeriodType Value)237 static inline void Emios_Pwm_Ip_SetUCRegB(Emios_Pwm_Ip_HwAddrType *const Base,
238 uint8 Channel,
239 Emios_Pwm_Ip_PeriodType Value)
240 {
241 Base->CH.UC[Channel].B = eMIOS_B_B(Value);
242 }
243
244 /*!
245 * brief Get B register's Value
246 * param[in] Base The Emios Base address pointer
247 * param[in] Channel The Channel id for the given instance
248 * return Value of Unified Channels B register
249 */
Emios_Pwm_Ip_GetUCRegB(const Emios_Pwm_Ip_HwAddrType * const Base,uint8 Channel)250 static inline Emios_Pwm_Ip_PeriodType Emios_Pwm_Ip_GetUCRegB(const Emios_Pwm_Ip_HwAddrType *const Base,
251 uint8 Channel)
252 {
253 return (Emios_Pwm_Ip_PeriodType)((Base->CH.UC[Channel].B & eMIOS_B_B_MASK) >> eMIOS_B_B_SHIFT);
254 }
255
256 /*-----------------------UC register CNT-----------------------------*/
257 /*!
258 * brief Get CNT register's Value
259 * param[in] Base The Emios Base address pointer
260 * param[in] Channel The Channel id for the given instance
261 * return Value of Unified Channels CNT register
262 */
Emios_Pwm_Ip_GetInternalCounterValue(const Emios_Pwm_Ip_HwAddrType * const Base,uint8 Channel)263 static inline Emios_Pwm_Ip_PeriodType Emios_Pwm_Ip_GetInternalCounterValue(const Emios_Pwm_Ip_HwAddrType *const Base,
264 uint8 Channel)
265 {
266 return (Emios_Pwm_Ip_PeriodType)((Base->CH.UC[Channel].CNT & eMIOS_CNT_C_MASK) >> eMIOS_CNT_C_SHIFT);
267 }
268
269 /*----------------------------UC register C bit fields--------------------------*/
270 /*!
271 * brief Set Freeze Enable bit
272 * param[in] Base The Emios Base address pointer
273 * param[in] Channel The Channel id for the given instance
274 * param[in] Value The Value to set
275 * - 0 Normal operation
276 * - 1 Freeze UC registers values
277 */
Emios_Pwm_Ip_SetFreezeEnable(Emios_Pwm_Ip_HwAddrType * const Base,uint8 Channel,boolean Value)278 static inline void Emios_Pwm_Ip_SetFreezeEnable(Emios_Pwm_Ip_HwAddrType *const Base,
279 uint8 Channel,
280 boolean Value)
281 {
282 uint8 ValueConvert = (Value == FALSE)? 0U : 1U;
283 Base->CH.UC[Channel].C = (Base->CH.UC[Channel].C & ~(eMIOS_C_FREN_MASK)) | eMIOS_C_FREN(ValueConvert);
284 }
285
286 /*!
287 * brief Set Output Disable bit
288 * param[in] Base The Emios Base address pointer
289 * param[in] Channel The Channel id for the given instance
290 * param[in] Value The Value to set
291 */
Emios_Pwm_Ip_SetOutDisable(Emios_Pwm_Ip_HwAddrType * const Base,uint8 Channel,boolean Value)292 static inline void Emios_Pwm_Ip_SetOutDisable(Emios_Pwm_Ip_HwAddrType *const Base,
293 uint8 Channel,
294 boolean Value)
295 {
296 uint8 ValueConvert = (Value == FALSE)? 0U : 1U;
297 Base->CH.UC[Channel].C = (Base->CH.UC[Channel].C & ~(eMIOS_C_ODIS_MASK)) | eMIOS_C_ODIS(ValueConvert);
298 }
299
300 /*!
301 * brief Set Output Disable select Value
302 * param[in] Base The Emios Base address pointer
303 * param[in] Channel The Channel id for the given instance
304 * param[in] Value The Value to set
305 */
Emios_Pwm_Ip_SetOutDisableSource(Emios_Pwm_Ip_HwAddrType * const Base,uint8 Channel,Emios_Pwm_Ip_OutDisableSourceType Value)306 static inline void Emios_Pwm_Ip_SetOutDisableSource(Emios_Pwm_Ip_HwAddrType *const Base,
307 uint8 Channel,
308 Emios_Pwm_Ip_OutDisableSourceType Value)
309 {
310 Base->CH.UC[Channel].C = (Base->CH.UC[Channel].C & ~(eMIOS_C_ODISSL_MASK)) | eMIOS_C_ODISSL(Value);
311 }
312
313 /*!
314 * brief Set Prescaler Enable bit.
315 * param[in] Base The Emios Base address pointer
316 * param[in] Channel The Channel id for the given instance
317 * param[in] Value The Value to set
318 * - 0 Prescaler disabled (no clock)
319 * - 1 Prescaler enabled
320 */
Emios_Pwm_Ip_SetPrescalerEnable(Emios_Pwm_Ip_HwAddrType * const Base,uint8 Channel,boolean Value)321 static inline void Emios_Pwm_Ip_SetPrescalerEnable(Emios_Pwm_Ip_HwAddrType *const Base,
322 uint8 Channel,
323 boolean Value)
324 {
325 uint8 ValueConvert = (Value == FALSE)? 0U : 1U;
326 Base->CH.UC[Channel].C = (Base->CH.UC[Channel].C & ~(eMIOS_C_UCPREN_MASK)) | eMIOS_C_UCPREN(ValueConvert);
327 }
328
329 /* Bitfiled UCPRE is not used. Instead the Value is controled using UCEXTPRE from C2 */
330
331 /*!
332 * brief Set Direct Memory Access bit
333 * param[in] Base The Emios Base address pointer
334 * param[in] Channel The Channel id for the given instance
335 * param[in] Value The Value to set
336 * - 0 Flag/overrun assigned to Interrupt request.
337 * - 1 Flag/overrun assigned to DMA request.
338 */
Emios_Pwm_Ip_SetDMARequest(Emios_Pwm_Ip_HwAddrType * const Base,uint8 Channel,boolean Value)339 static inline void Emios_Pwm_Ip_SetDMARequest(Emios_Pwm_Ip_HwAddrType *const Base,
340 uint8 Channel,
341 boolean Value)
342 {
343 uint8 ValueConvert = (Value == FALSE)? 0U : 1U;
344 Base->CH.UC[Channel].C = (Base->CH.UC[Channel].C & ~(eMIOS_C_DMA_MASK)) | eMIOS_C_DMA(ValueConvert);
345 }
346
347 /*!
348 * brief Get Direct Memory Access bit
349 * param[in] Base The Emios Base address pointer
350 * param[in] Channel The Channel id for the given instance
351 * return Value of Direct Memory Access state in Unified Channels Control register
352 * - 0 Flag/overrun assigned to Interrupt request.
353 * - 1 Flag/overrun assigned to DMA request.
354 */
Emios_Pwm_Ip_GetDMARequest(const Emios_Pwm_Ip_HwAddrType * const Base,uint8 Channel)355 static inline boolean Emios_Pwm_Ip_GetDMARequest(const Emios_Pwm_Ip_HwAddrType *const Base,
356 uint8 Channel)
357 {
358 return (((Base->CH.UC[Channel].C & eMIOS_C_DMA_MASK) >> eMIOS_C_DMA_SHIFT) == 0U)? FALSE : TRUE;
359 }
360
361 /*!
362 * brief Set FLAG Enable bit
363 * param[in] Base The Emios Base address pointer
364 * param[in] Channel The Channel id for the given instance
365 * param[in] Value The Value to set
366 * - 0 Disable (FLAG does not generate an interrupt request)
367 * - 1 Enable (FLAG generates an interrupt request)
368 */
Emios_Pwm_Ip_SetInterruptRequest(Emios_Pwm_Ip_HwAddrType * const Base,uint8 Channel,boolean Value)369 static inline void Emios_Pwm_Ip_SetInterruptRequest(Emios_Pwm_Ip_HwAddrType *const Base,
370 uint8 Channel,
371 boolean Value)
372 {
373 uint8 ValueConvert = (Value == FALSE)? 0U : 1U;
374 Base->CH.UC[Channel].C = (Base->CH.UC[Channel].C & ~(eMIOS_C_FEN_MASK)) | eMIOS_C_FEN(ValueConvert);
375 }
376
377 /*!
378 * brief Get FLAG Enable bit
379 * param[in] Base The Emios Base address pointer
380 * param[in] Channel The Channel id for the given instance
381 * return Value of FLAG Enable bit
382 * - 0 Disable (FLAG does not generate an interrupt request)
383 * - 1 Enable (FLAG generates an interrupt request)
384 */
Emios_Pwm_Ip_GetInterruptRequest(const Emios_Pwm_Ip_HwAddrType * const Base,uint8 Channel)385 static inline boolean Emios_Pwm_Ip_GetInterruptRequest(const Emios_Pwm_Ip_HwAddrType *const Base,
386 uint8 Channel)
387 {
388 return (((Base->CH.UC[Channel].C & eMIOS_C_FEN_MASK) >> eMIOS_C_FEN_SHIFT) == 0U)? FALSE : TRUE;
389 }
390
391 /*!
392 * brief Force Match A bit
393 * param[in] Base The Emios Base address pointer
394 * param[in] Channel The Channel id for the given instance
395 * param[in] Value The Value to set
396 * - 0 Has no effect.
397 * - 1 Force a match at comparator A
398 */
Emios_Pwm_Ip_SetForceMatchA(Emios_Pwm_Ip_HwAddrType * const Base,uint8 Channel,boolean Value)399 static inline void Emios_Pwm_Ip_SetForceMatchA(Emios_Pwm_Ip_HwAddrType *const Base,
400 uint8 Channel,
401 boolean Value)
402 {
403 uint8 ValueConvert = (Value == FALSE)? 0U : 1U;
404 Base->CH.UC[Channel].C = (Base->CH.UC[Channel].C & ~(eMIOS_C_FORCMA_MASK)) | eMIOS_C_FORCMA(ValueConvert);
405 }
406
407 /*!
408 * brief Force Match B bit
409 * param[in] Base The Emios Base address pointer
410 * param[in] Channel The Channel id for the given instance
411 * param[in] Value The Value to set
412 * - 0 Has no effect.
413 * - 1 Force a match at comparator B
414 */
Emios_Pwm_Ip_SetForceMatchB(Emios_Pwm_Ip_HwAddrType * const Base,uint8 Channel,boolean Value)415 static inline void Emios_Pwm_Ip_SetForceMatchB(Emios_Pwm_Ip_HwAddrType *const Base,
416 uint8 Channel,
417 boolean Value)
418 {
419 uint8 ValueConvert = (Value == FALSE)? 0U : 1U;
420 Base->CH.UC[Channel].C = (Base->CH.UC[Channel].C & ~(eMIOS_C_FORCMB_MASK)) | eMIOS_C_FORCMB(ValueConvert);
421 }
422
423 /*!
424 * brief Set Bus Select bits.
425 * param[in] Base The Emios Base address pointer
426 * param[in] Channel The Channel id for the given instance
427 * param[in] Value The Value to set
428 */
Emios_Pwm_Ip_SetCounterBus(Emios_Pwm_Ip_HwAddrType * const Base,uint8 Channel,Emios_Pwm_Ip_CounterBusSourceType Value)429 static inline void Emios_Pwm_Ip_SetCounterBus(Emios_Pwm_Ip_HwAddrType *const Base,
430 uint8 Channel,
431 Emios_Pwm_Ip_CounterBusSourceType Value)
432 {
433 Base->CH.UC[Channel].C = (Base->CH.UC[Channel].C & ~(eMIOS_C_BSL_MASK)) | eMIOS_C_BSL(Value);
434 }
435
436 /*!
437 * brief Get Bus Select Value
438 * param[in] Base The Emios Base address pointer
439 * param[in] Channel The Channel id for the given instance
440 * return Value of Bus Select in Unified Channels Control register
441 */
Emios_Pwm_Ip_GetCounterBus(const Emios_Pwm_Ip_HwAddrType * const Base,uint8 Channel)442 static inline Emios_Pwm_Ip_CounterBusSourceType Emios_Pwm_Ip_GetCounterBus(const Emios_Pwm_Ip_HwAddrType *const Base,
443 uint8 Channel)
444 {
445 Emios_Pwm_Ip_CounterBusSourceType CounterBus;
446 switch((Base->CH.UC[Channel].C & eMIOS_C_BSL_MASK) >> eMIOS_C_BSL_SHIFT)
447 {
448 case 0x00U:
449 CounterBus = EMIOS_PWM_IP_BUS_A;
450 break;
451 case 0x01U:
452 CounterBus = EMIOS_PWM_IP_BUS_BCDE;
453 break;
454 case 0x02U:
455 CounterBus = EMIOS_PWM_IP_BUS_F;
456 break;
457 default:
458 CounterBus = EMIOS_PWM_IP_BUS_INTERNAL;
459 break;
460 }
461 return CounterBus;
462 }
463
464 /*!
465 * brief Get the timebase channel
466 * param[in] Channel The channel id for the given instance
467 * param[in] Value Bus Select in Unified Channels Control register
468 * return Timebase channel.
469 */
Emios_Pwm_Ip_GetTimebaseChannel(uint8 Channel,Emios_Pwm_Ip_CounterBusSourceType Value)470 static inline uint8 Emios_Pwm_Ip_GetTimebaseChannel(uint8 Channel,
471 Emios_Pwm_Ip_CounterBusSourceType Value)
472 {
473 uint8 TimbaseChannel;
474 switch(Value)
475 {
476 case EMIOS_PWM_IP_BUS_A:
477 TimbaseChannel = (uint8)EMIOS_PWM_IP_COUNTER_BUS_A;
478 break;
479 case EMIOS_PWM_IP_BUS_F:
480 TimbaseChannel = (uint8)EMIOS_PWM_IP_COUNTER_BUS_F;
481 break;
482 case EMIOS_PWM_IP_BUS_BCDE:
483 TimbaseChannel = Channel & (uint8)EMIOS_PWM_IP_COUNTER_BUS_BCDE;
484 break;
485 default:
486 TimbaseChannel = (uint8)0xFFU;
487 break;
488 }
489 (void)Channel;
490
491 return TimbaseChannel;
492 }
493
494 /*!
495 * brief Set Edge Polarity bit.
496 * param[in] Base The Emios Base address pointer
497 * param[in] Channel The Channel id for the given instance
498 * param[in] Value The Value to set
499 */
Emios_Pwm_Ip_SetEdgePolarity(Emios_Pwm_Ip_HwAddrType * const Base,uint8 Channel,Emios_Pwm_Ip_PolarityType Value)500 static inline void Emios_Pwm_Ip_SetEdgePolarity(Emios_Pwm_Ip_HwAddrType *const Base,
501 uint8 Channel,
502 Emios_Pwm_Ip_PolarityType Value)
503 {
504 Base->CH.UC[Channel].C = (Base->CH.UC[Channel].C & ~(eMIOS_C_EDPOL_MASK)) | eMIOS_C_EDPOL(Value);
505 }
506
507 /*!
508 * brief Get Edge Polarity bit.
509 * param[in] Base The Emios Base address pointer
510 * param[in] Channel The Channel id for the given instance
511 * return Value of Edge Polarity bit in Unified Channels Control register
512 */
Emios_Pwm_Ip_GetEdgePolarity(const Emios_Pwm_Ip_HwAddrType * const Base,uint8 Channel)513 static inline Emios_Pwm_Ip_PolarityType Emios_Pwm_Ip_GetEdgePolarity(const Emios_Pwm_Ip_HwAddrType *const Base,
514 uint8 Channel)
515 {
516 return (((Base->CH.UC[Channel].C & eMIOS_C_EDPOL_MASK) >> eMIOS_C_EDPOL_SHIFT) == 0U)? (Emios_Pwm_Ip_PolarityType)EMIOS_PWM_IP_ACTIVE_LOW : (Emios_Pwm_Ip_PolarityType)EMIOS_PWM_IP_ACTIVE_HIGH;
517 }
518
519 /*!
520 * brief Set mode of operation of the Unified Channel
521 * param[in] Base The Emios Base address pointer
522 * param[in] Channel The Channel id for the given instance
523 * param[in] Mode The mode to set
524 */
Emios_Pwm_Ip_SetPwmMode(Emios_Pwm_Ip_HwAddrType * const Base,uint8 Channel,Emios_Pwm_Ip_PwmModeType Mode)525 static inline void Emios_Pwm_Ip_SetPwmMode(Emios_Pwm_Ip_HwAddrType *const Base,
526 uint8 Channel,
527 Emios_Pwm_Ip_PwmModeType Mode)
528 {
529 Base->CH.UC[Channel].C = (Base->CH.UC[Channel].C & ~(eMIOS_C_MODE_MASK)) | eMIOS_C_MODE(Mode);
530 }
531
532 /*!
533 * brief Set mode and Edge Polarity bit of operation of the Unified Channel at the same time to avoid spike pulse
534 * param[in] Base The Emios Base address pointer
535 * param[in] Channel The Channel id for the given instance
536 * param[in] Mode The mode to set
537 * param[in] Pol The Edge polarity to set
538 * return void
539 */
Emios_Pwm_Ip_SetPwmModePol(Emios_Pwm_Ip_HwAddrType * const Base,uint8 Channel,Emios_Pwm_Ip_PwmModeType Mode,Emios_Pwm_Ip_PolarityType Pol)540 static inline void Emios_Pwm_Ip_SetPwmModePol(Emios_Pwm_Ip_HwAddrType *const Base,
541 uint8 Channel,
542 Emios_Pwm_Ip_PwmModeType Mode,
543 Emios_Pwm_Ip_PolarityType Pol)
544 {
545 Base->CH.UC[Channel].C = (Base->CH.UC[Channel].C & ~(eMIOS_C_MODE_MASK) & ~(eMIOS_C_EDPOL_MASK)) | eMIOS_C_MODE(Mode) | eMIOS_C_EDPOL(Pol);
546 }
547
548 /*!
549 * brief Get mode of operation of the Unified Channel
550 * param[in] Base The Emios Base address pointer
551 * param[in] Channel The Channel id for the given instance
552 * return Value of Mode selection in Unified Channels Control register
553 */
Emios_Pwm_Ip_GetChannelPwmMode(const Emios_Pwm_Ip_HwAddrType * const Base,uint8 Channel)554 static inline Emios_Pwm_Ip_MasterBusModeType Emios_Pwm_Ip_GetChannelPwmMode( const Emios_Pwm_Ip_HwAddrType *const Base,
555 uint8 Channel)
556 {
557 Emios_Pwm_Ip_MasterBusModeType MasterBusMode;
558 switch ((Base->CH.UC[Channel].C & eMIOS_C_MODE_MASK) >> eMIOS_C_MODE_SHIFT)
559 {
560 case 16U:
561 MasterBusMode = EMIOS_PWM_IP_MC_UP_COUNTER_START;
562 break;
563 case 18U:
564 MasterBusMode = EMIOS_PWM_IP_MC_UP_COUNTER_END;
565 break;
566 case 20U:
567 MasterBusMode = EMIOS_PWM_IP_MC_UP_DOWN_COUNTER;
568 break;
569 case 80U:
570 MasterBusMode = EMIOS_PWM_IP_MCB_UP_COUNTER;
571 break;
572 case 84U:
573 MasterBusMode = EMIOS_PWM_IP_MCB_UP_DOWN_COUNTER;
574 break;
575 default:
576 MasterBusMode = EMIOS_PWM_IP_NODEFINE_COUNTER;
577 break;
578 }
579 return MasterBusMode;
580 }
581
582 /*----------------------UC register S bit field-----------------------------*/
583 /*!
584 * brief Write 1 to clear overrun bit
585 * param[in] Base The Emios Base address pointer
586 * param[in] Channel The Channel id for the given instance
587 */
Emios_Pwm_Ip_ClearOverRunFlag(Emios_Pwm_Ip_HwAddrType * const Base,uint8 Channel)588 static inline void Emios_Pwm_Ip_ClearOverRunFlag(Emios_Pwm_Ip_HwAddrType *const Base,
589 uint8 Channel)
590 {
591 /* OVR bit, OVFL bit & FLAG bit can be cleared when write 1 to them */
592 Base->CH.UC[Channel].S = (Base->CH.UC[Channel].S & ~((eMIOS_S_FLAG_MASK & eMIOS_S_OVFL_MASK) & eMIOS_S_OVR_MASK)) | eMIOS_S_OVR(1UL);
593 }
594
595 /*!
596 * brief Get overrun bit
597 * param[in] Base The Emios Base address pointer
598 * param[in] Channel The Channel id for the given instance
599 * return Value of Overrun bit in Unified Channels Control register
600 * The OVR bit indicates that FLAG generation occurred when the FLAG bit was already set .
601 * The OVR bit can be cleared either by clearing the FLAG bit or by writing a 1 to the OVR bit.
602 * - 0 Overrun has not occurred
603 * - 1 Overrun has occurred
604 */
Emios_Pwm_Ip_GetOverRunFlag(const Emios_Pwm_Ip_HwAddrType * const Base,uint8 Channel)605 static inline boolean Emios_Pwm_Ip_GetOverRunFlag(const Emios_Pwm_Ip_HwAddrType *const Base,
606 uint8 Channel)
607 {
608 return (((Base->CH.UC[Channel].S & eMIOS_S_OVR_MASK) >> eMIOS_S_OVR_SHIFT) == 0U)? FALSE : TRUE;
609 }
610
611 /*!
612 * brief Write 1 to clear the overflow bit.
613 * param[in] Base The Emios Base address pointer
614 * param[in] Channel The Channel id for the given instance
615 */
Emios_Pwm_Ip_ClearOverFlowFlag(Emios_Pwm_Ip_HwAddrType * const Base,uint8 Channel)616 static inline void Emios_Pwm_Ip_ClearOverFlowFlag(Emios_Pwm_Ip_HwAddrType *const Base,
617 uint8 Channel)
618 {
619 /* OVR bit, OVFL bit & FLAG bit can be cleared when write 1 to them */
620 Base->CH.UC[Channel].S = (Base->CH.UC[Channel].S & ~((eMIOS_S_FLAG_MASK & eMIOS_S_OVFL_MASK) & eMIOS_S_OVR_MASK)) | eMIOS_S_OVFL(1UL);
621 }
622
623 /*!
624 * brief Get Overflow bit
625 * param[in] Base The Emios Base address pointer
626 * param[in] Channel The Channel id for the given instance
627 * return Value of Overflow bit in Unified Channels Control register
628 * The OVFL bit indicates that an overflow has occurred in the internal counter.
629 * The OVFL bit must be cleared by software writing a 1 to it.
630 * - 0 No overflow
631 * - 1 An overflow had occurred
632 */
Emios_Pwm_Ip_GetOverFlowFlag(const Emios_Pwm_Ip_HwAddrType * const Base,uint8 Channel)633 static inline boolean Emios_Pwm_Ip_GetOverFlowFlag(const Emios_Pwm_Ip_HwAddrType *const Base,
634 uint8 Channel)
635 {
636 return (((Base->CH.UC[Channel].S & eMIOS_S_OVFL_MASK) >> eMIOS_S_OVFL_SHIFT) == 0U)? FALSE : TRUE;
637 }
638
639 /*!
640 * brief Get Unified Channel Output pin bit
641 * param[in] Base The Emios Base address pointer
642 * param[in] Channel The Channel id for the given instance
643 * return Value of Unified Channel Output pin bit in Unified Channels Control register
644 */
Emios_Pwm_Ip_GetOutputPinState(const Emios_Pwm_Ip_HwAddrType * const Base,uint8 Channel)645 static inline boolean Emios_Pwm_Ip_GetOutputPinState(const Emios_Pwm_Ip_HwAddrType *const Base,
646 uint8 Channel)
647 {
648 return (((Base->CH.UC[Channel].S & eMIOS_S_UCOUT_MASK) >> eMIOS_S_UCOUT_SHIFT) == 0U)? FALSE : TRUE;
649 }
650
651 /*!
652 * brief Write 1 to clear the FLAG bit
653 * param[in] Base The Emios Base address pointer
654 * param[in] Channel The Channel id for the given instance
655 */
Emios_Pwm_Ip_ClearFlagEvent(Emios_Pwm_Ip_HwAddrType * const Base,uint8 Channel)656 static inline void Emios_Pwm_Ip_ClearFlagEvent(Emios_Pwm_Ip_HwAddrType *const Base,
657 uint8 Channel)
658 {
659 /* OVR bit, OVFL bit & FLAG bit can be cleared when write 1 to them */
660 Base->CH.UC[Channel].S = (Base->CH.UC[Channel].S & ~((eMIOS_S_FLAG_MASK & eMIOS_S_OVFL_MASK) & eMIOS_S_OVR_MASK)) | eMIOS_S_FLAG(1UL);
661 }
662
663 /*!
664 * brief Get FLAG bit
665 * param[in] Base The Emios Base address pointer
666 * param[in] Channel The Channel id for the given instance
667 * return Value of FLAG bit in Unified Channels Control register
668 * The FLAG bit indicates that a match event has occurred in the Channel.
669 * The FLAG bit must be cleared by software writing a 1 to it.
670 * - 0 No flag event
671 * - 1 A flag eventhad occurred
672 */
Emios_Pwm_Ip_GetOverFlagEvent(const Emios_Pwm_Ip_HwAddrType * const Base,uint8 Channel)673 static inline boolean Emios_Pwm_Ip_GetOverFlagEvent(const Emios_Pwm_Ip_HwAddrType *const Base,
674 uint8 Channel)
675 {
676 return (((Base->CH.UC[Channel].S & eMIOS_S_FLAG_MASK) >> eMIOS_S_FLAG_SHIFT) == 0U)? FALSE : TRUE;
677 }
678
679 /*-----------------------UC register ALTA-----------------------------*/
680 /*!
681 * brief Set A2 Channel registers Value
682 * param[in] Base The Emios Base address pointer
683 * param[in] Channel The Channel id for the given instance
684 * param[in] Value The Value to set
685 */
Emios_Pwm_Ip_SetTrigger(Emios_Pwm_Ip_HwAddrType * const Base,uint8 Channel,Emios_Pwm_Ip_PeriodType Value)686 static inline void Emios_Pwm_Ip_SetTrigger(Emios_Pwm_Ip_HwAddrType *const Base,
687 uint8 Channel,
688 Emios_Pwm_Ip_PeriodType Value)
689 {
690 Base->CH.UC[Channel].ALTA = (Base->CH.UC[Channel].ALTA & ~(eMIOS_ALTA_ALTA_MASK)) | eMIOS_ALTA_ALTA(Value);
691 }
692
693 /*!
694 * brief Get A2 Channel registers Value
695 * param[in] Base The Emios Base address pointer
696 * param[in] Channel The Channel id for the given instance
697 * return Value of A2 Channel registers in Unified Channels Control register
698 */
Emios_Pwm_Ip_GetTrigger(const Emios_Pwm_Ip_HwAddrType * const Base,uint8 Channel)699 static inline Emios_Pwm_Ip_PeriodType Emios_Pwm_Ip_GetTrigger(const Emios_Pwm_Ip_HwAddrType *const Base,
700 uint8 Channel)
701 {
702 return (Emios_Pwm_Ip_PeriodType)((Base->CH.UC[Channel].ALTA & eMIOS_ALTA_ALTA_MASK) >> eMIOS_ALTA_ALTA_SHIFT);
703 }
704
705 /*------------------UC register C2 --------------------------*/
706 /*!
707 * brief Set Extended Prescaler bits
708 * param[in] Base The Emios Base address pointer
709 * param[in] Channel The Channel id for the given instance
710 * param[in] Value The Value to set
711 */
712 #ifdef EMIOS_PWM_IP_PRESCALER_14BIT
Emios_Pwm_Ip_SetExtendedPrescaler(Emios_Pwm_Ip_HwAddrType * const Base,uint8 Channel,uint16 Value)713 static inline void Emios_Pwm_Ip_SetExtendedPrescaler(Emios_Pwm_Ip_HwAddrType *const Base,
714 uint8 Channel,
715 uint16 Value)
716 {
717 uint32 ClockDividerValue = (uint32)Value - 1U;
718 /* Set Extended Prescaler bits */
719 Base->CH.UC[Channel].C2 = (Base->CH.UC[Channel].C2 & ~(eMIOS_C2_UCEXTPRE_MASK)) | eMIOS_C2_UCEXTPRE(ClockDividerValue);
720 }
721 #else
722 /*!
723 * brief Set Extended Prescaler bits
724 */
Emios_Pwm_Ip_SetExtendedPrescaler(Emios_Pwm_Ip_HwAddrType * const Base,uint8 Channel,Emios_Pwm_Ip_InternalClkPsType Value)725 static inline void Emios_Pwm_Ip_SetExtendedPrescaler(Emios_Pwm_Ip_HwAddrType *const Base,
726 uint8 Channel,
727 Emios_Pwm_Ip_InternalClkPsType Value)
728 {
729 Base->CH.UC[Channel].C2 = (Base->CH.UC[Channel].C2 & ~(eMIOS_C2_UCEXTPRE_MASK)) | eMIOS_C2_UCEXTPRE(Value);
730 }
731 #endif
732
733 /*!
734 * brief Set Prescaler Clock select bit
735 * param[in] Base The Emios Base address pointer
736 * param[in] Channel The Channel id for the given instance
737 * param[in] Value The Value to set
738 * - 0 Prescaled Clock
739 * - 1 eMIOS module clock
740 */
Emios_Pwm_Ip_SetPrescalerSource(Emios_Pwm_Ip_HwAddrType * const Base,uint8 Channel,Emios_Pwm_Ip_InternalPsSrcType Value)741 static inline void Emios_Pwm_Ip_SetPrescalerSource(Emios_Pwm_Ip_HwAddrType *const Base,
742 uint8 Channel,
743 Emios_Pwm_Ip_InternalPsSrcType Value)
744 {
745 Base->CH.UC[Channel].C2 = (Base->CH.UC[Channel].C2 & ~(eMIOS_C2_UCPRECLK_MASK)) | eMIOS_C2_UCPRECLK(Value);
746 }
747
748 #define PWM_STOP_SEC_CODE
749 #include "Pwm_MemMap.h"
750
751
752 #ifdef __cplusplus
753 }
754 #endif
755
756 /** @} */
757
758 #endif /* EMIOS_PWM_IP_HWACCESS_H */
759
