1 /**************************************************************************//** 2 * @file emac.h 3 * @version V1.00 4 * @brief M480 EMAC driver header file 5 * 6 * SPDX-License-Identifier: Apache-2.0 7 * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. 8 *****************************************************************************/ 9 #ifndef __EMAC_H__ 10 #define __EMAC_H__ 11 12 #ifdef __cplusplus 13 extern "C" 14 { 15 #endif 16 17 #include <stdint.h> 18 19 /** @addtogroup Standard_Driver Standard Driver 20 @{ 21 */ 22 23 /** @addtogroup EMAC_Driver EMAC Driver 24 @{ 25 */ 26 27 /** @addtogroup EMAC_EXPORTED_CONSTANTS EMAC Exported Constants 28 @{ 29 */ 30 31 #define EMAC_PHY_ADDR 1UL /*!< PHY address, this address is board dependent \hideinitializer */ 32 #define EMAC_RX_DESC_SIZE 4UL /*!< Number of Rx Descriptors, should be 2 at least \hideinitializer */ 33 #define EMAC_TX_DESC_SIZE 4UL /*!< Number of Tx Descriptors, should be 2 at least \hideinitializer */ 34 #define EMAC_CAMENTRY_NB 16UL /*!< Number of CAM \hideinitializer */ 35 #define EMAC_MAX_PKT_SIZE 1524UL /*!< Number of HDR + EXTRA + VLAN_TAG + PAYLOAD + CRC \hideinitializer */ 36 37 #define EMAC_LINK_DOWN 0UL /*!< Ethernet link is down \hideinitializer */ 38 #define EMAC_LINK_100F 1UL /*!< Ethernet link is 100Mbps full duplex \hideinitializer */ 39 #define EMAC_LINK_100H 2UL /*!< Ethernet link is 100Mbps half duplex \hideinitializer */ 40 #define EMAC_LINK_10F 3UL /*!< Ethernet link is 10Mbps full duplex \hideinitializer */ 41 #define EMAC_LINK_10H 4UL /*!< Ethernet link is 10Mbps half duplex \hideinitializer */ 42 43 /*@}*/ /* end of group EMAC_EXPORTED_CONSTANTS */ 44 45 46 /** @addtogroup EMAC_EXPORTED_FUNCTIONS EMAC Exported Functions 47 @{ 48 */ 49 50 51 /** 52 * @brief Enable EMAC Tx function 53 * @param None 54 * @return None 55 * \hideinitializer 56 */ 57 #define EMAC_ENABLE_TX() (EMAC->CTL |= EMAC_CTL_TXON_Msk) 58 59 60 /** 61 * @brief Enable EMAC Rx function 62 * @param None 63 * @return None 64 * \hideinitializer 65 */ 66 #define EMAC_ENABLE_RX() do{EMAC->CTL |= EMAC_CTL_RXON_Msk; EMAC->RXST = 0;}while(0) 67 68 /** 69 * @brief Disable EMAC Tx function 70 * @param None 71 * @return None 72 * \hideinitializer 73 */ 74 #define EMAC_DISABLE_TX() (EMAC->CTL &= ~EMAC_CTL_TXON_Msk) 75 76 77 /** 78 * @brief Disable EMAC Rx function 79 * @param None 80 * @return None 81 * \hideinitializer 82 */ 83 #define EMAC_DISABLE_RX() (EMAC->CTL &= ~EMAC_CTL_RXON_Msk) 84 85 /** 86 * @brief Enable EMAC Magic Packet Wakeup function 87 * @param None 88 * @return None 89 * \hideinitializer 90 */ 91 #define EMAC_ENABLE_MAGIC_PKT_WAKEUP() (EMAC->CTL |= EMAC_CTL_WOLEN_Msk) 92 93 /** 94 * @brief Disable EMAC Magic Packet Wakeup function 95 * @param None 96 * @return None 97 * \hideinitializer 98 */ 99 #define EMAC_DISABLE_MAGIC_PKT_WAKEUP() (EMAC->CTL &= ~EMAC_CTL_WOLEN_Msk) 100 101 /** 102 * @brief Enable EMAC to receive broadcast packets 103 * @param None 104 * @return None 105 * \hideinitializer 106 */ 107 #define EMAC_ENABLE_RECV_BCASTPKT() (EMAC->CAMCTL |= EMAC_CAMCTL_ABP_Msk) 108 109 /** 110 * @brief Disable EMAC to receive broadcast packets 111 * @param None 112 * @return None 113 * \hideinitializer 114 */ 115 #define EMAC_DISABLE_RECV_BCASTPKT() (EMAC->CAMCTL &= ~EMAC_CAMCTL_ABP_Msk) 116 117 /** 118 * @brief Enable EMAC to receive multicast packets 119 * @param None 120 * @return None 121 * \hideinitializer 122 */ 123 #define EMAC_ENABLE_RECV_MCASTPKT() (EMAC->CAMCTL |= EMAC_CAMCTL_AMP_Msk) 124 125 /** 126 * @brief Disable EMAC Magic Packet Wakeup function 127 * @param None 128 * @return None 129 * \hideinitializer 130 */ 131 #define EMAC_DISABLE_RECV_MCASTPKT() (EMAC->CAMCTL &= ~EMAC_CAMCTL_AMP_Msk) 132 133 /** 134 * @brief Check if EMAC time stamp alarm interrupt occurred or not 135 * @param None 136 * @return If time stamp alarm interrupt occurred or not 137 * @retval 0 Alarm interrupt does not occur 138 * @retval 1 Alarm interrupt occurred 139 * \hideinitializer 140 */ 141 #define EMAC_GET_ALARM_FLAG() (EMAC->INTSTS & EMAC_INTSTS_TSALMIF_Msk ? 1 : 0) 142 143 /** 144 * @brief Clear EMAC time stamp alarm interrupt flag 145 * @param None 146 * @return None 147 * \hideinitializer 148 */ 149 #define EMAC_CLR_ALARM_FLAG() (EMAC->INTSTS = EMAC_INTSTS_TSALMIF_Msk) 150 151 /** 152 * @brief Trigger EMAC Rx function 153 * @param None 154 * @return None 155 */ 156 #define EMAC_TRIGGER_RX() do{EMAC->RXST = 0UL;}while(0) 157 158 /** 159 * @brief Trigger EMAC Tx function 160 * @param None 161 * @return None 162 */ 163 #define EMAC_TRIGGER_TX() do{EMAC->TXST = 0UL;}while(0) 164 165 /** 166 * @brief Enable specified EMAC interrupt 167 * 168 * @param[in] emac The pointer of the specified EMAC module 169 * @param[in] u32eIntSel Interrupt type select 170 * - \ref EMAC_INTEN_RXIEN_Msk : Receive 171 * - \ref EMAC_INTEN_CRCEIEN_Msk : CRC Error 172 * - \ref EMAC_INTEN_RXOVIEN_Msk : Receive FIFO Overflow 173 * - \ref EMAC_INTEN_LPIEN_Msk : Long Packet 174 * - \ref EMAC_INTEN_RXGDIEN_Msk : Receive Good 175 * - \ref EMAC_INTEN_ALIEIEN_Msk : Alignment Error 176 * - \ref EMAC_INTEN_RPIEN_Msk : Runt Packet 177 * - \ref EMAC_INTEN_MPCOVIEN_Msk : Miss Packet Counter Overrun 178 * - \ref EMAC_INTEN_MFLEIEN_Msk : Maximum Frame Length Exceed 179 * - \ref EMAC_INTEN_DENIEN_Msk : DMA Early Notification 180 * - \ref EMAC_INTEN_RDUIEN_Msk : Receive Descriptor Unavailable 181 * - \ref EMAC_INTEN_RXBEIEN_Msk : Receive Bus Error 182 * - \ref EMAC_INTEN_CFRIEN_Msk : Control Frame Receive 183 * - \ref EMAC_INTEN_WOLIEN_Msk : Wake on LAN Interrupt 184 * - \ref EMAC_INTEN_TXIEN_Msk : Transmit 185 * - \ref EMAC_INTEN_TXUDIEN_Msk : Transmit FIFO Underflow 186 * - \ref EMAC_INTEN_TXCPIEN_Msk : Transmit Completion 187 * - \ref EMAC_INTEN_EXDEFIEN_Msk : Defer Exceed 188 * - \ref EMAC_INTEN_NCSIEN_Msk : No Carrier Sense 189 * - \ref EMAC_INTEN_TXABTIEN_Msk : Transmit Abort 190 * - \ref EMAC_INTEN_LCIEN_Msk : Late Collision 191 * - \ref EMAC_INTEN_TDUIEN_Msk : Transmit Descriptor Unavailable 192 * - \ref EMAC_INTEN_TXBEIEN_Msk : Transmit Bus Error 193 * - \ref EMAC_INTEN_TSALMIEN_Msk : Time Stamp Alarm 194 * 195 * @return None 196 * 197 * @details This macro enable specified EMAC interrupt. 198 * \hideinitializer 199 */ 200 #define EMAC_ENABLE_INT(emac, u32eIntSel) ((emac)->INTEN |= (u32eIntSel)) 201 202 /** 203 * @brief Disable specified EMAC interrupt 204 * 205 * @param[in] emac The pointer of the specified EMAC module 206 * @param[in] u32eIntSel Interrupt type select 207 * - \ref EMAC_INTEN_RXIEN_Msk : Receive 208 * - \ref EMAC_INTEN_CRCEIEN_Msk : CRC Error 209 * - \ref EMAC_INTEN_RXOVIEN_Msk : Receive FIFO Overflow 210 * - \ref EMAC_INTEN_LPIEN_Msk : Long Packet 211 * - \ref EMAC_INTEN_RXGDIEN_Msk : Receive Good 212 * - \ref EMAC_INTEN_ALIEIEN_Msk : Alignment Error 213 * - \ref EMAC_INTEN_RPIEN_Msk : Runt Packet 214 * - \ref EMAC_INTEN_MPCOVIEN_Msk : Miss Packet Counter Overrun 215 * - \ref EMAC_INTEN_MFLEIEN_Msk : Maximum Frame Length Exceed 216 * - \ref EMAC_INTEN_DENIEN_Msk : DMA Early Notification 217 * - \ref EMAC_INTEN_RDUIEN_Msk : Receive Descriptor Unavailable 218 * - \ref EMAC_INTEN_RXBEIEN_Msk : Receive Bus Error 219 * - \ref EMAC_INTEN_CFRIEN_Msk : Control Frame Receive 220 * - \ref EMAC_INTEN_WOLIEN_Msk : Wake on LAN Interrupt 221 * - \ref EMAC_INTEN_TXIEN_Msk : Transmit 222 * - \ref EMAC_INTEN_TXUDIEN_Msk : Transmit FIFO Underflow 223 * - \ref EMAC_INTEN_TXCPIEN_Msk : Transmit Completion 224 * - \ref EMAC_INTEN_EXDEFIEN_Msk : Defer Exceed 225 * - \ref EMAC_INTEN_NCSIEN_Msk : No Carrier Sense 226 * - \ref EMAC_INTEN_TXABTIEN_Msk : Transmit Abort 227 * - \ref EMAC_INTEN_LCIEN_Msk : Late Collision 228 * - \ref EMAC_INTEN_TDUIEN_Msk : Transmit Descriptor Unavailable 229 * - \ref EMAC_INTEN_TXBEIEN_Msk : Transmit Bus Error 230 * - \ref EMAC_INTEN_TSALMIEN_Msk : Time Stamp Alarm 231 * 232 * @return None 233 * 234 * @details This macro disable specified EMAC interrupt. 235 * \hideinitializer 236 */ 237 #define EMAC_DISABLE_INT(emac, u32eIntSel) ((emac)->INTEN &= ~ (u32eIntSel)) 238 239 /** 240 * @brief Get specified interrupt flag/status 241 * 242 * @param[in] emac The pointer of the specified EMAC module 243 * @param[in] u32eIntTypeFlag Interrupt Type Flag, should be 244 * - \ref EMAC_INTSTS_RXIF_Msk : Receive 245 * - \ref EMAC_INTSTS_CRCEIF_Msk : CRC Error 246 * - \ref EMAC_INTSTS_RXOVIF_Msk : Receive FIFO Overflow 247 * - \ref EMAC_INTSTS_LPIF_Msk : Long Packet 248 * - \ref EMAC_INTSTS_RXGDIF_Msk : Receive Good 249 * - \ref EMAC_INTSTS_ALIEIF_Msk : Alignment Error 250 * - \ref EMAC_INTSTS_RPIF_Msk : Runt Packet 251 * - \ref EMAC_INTSTS_MPCOVIF_Msk : Missed Packet Counter 252 * - \ref EMAC_INTSTS_MFLEIF_Msk : Maximum Frame Length Exceed 253 * - \ref EMAC_INTSTS_DENIF_Msk : DMA Early Notification 254 * - \ref EMAC_INTSTS_RDUIF_Msk : Receive Descriptor Unavailable 255 * - \ref EMAC_INTSTS_RXBEIF_Msk : Receive Bus Error 256 * - \ref EMAC_INTSTS_CFRIF_Msk : Control Frame Receive 257 * - \ref EMAC_INTSTS_WOLIF_Msk : Wake on LAN 258 * - \ref EMAC_INTSTS_TXIF_Msk : Transmit 259 * - \ref EMAC_INTSTS_TXUDIF_Msk : Transmit FIFO Underflow 260 * - \ref EMAC_INTSTS_TXCPIF_Msk : Transmit Completion 261 * - \ref EMAC_INTSTS_EXDEFIF_Msk : Defer Exceed 262 * - \ref EMAC_INTSTS_NCSIF_Msk : No Carrier Sense 263 * - \ref EMAC_INTSTS_TXABTIF_Msk : Transmit Abort 264 * - \ref EMAC_INTSTS_LCIF_Msk : Late Collision 265 * - \ref EMAC_INTSTS_TDUIF_Msk : Transmit Descriptor Unavailable 266 * - \ref EMAC_INTSTS_TXBEIF_Msk : Transmit Bus Error 267 * - \ref EMAC_INTSTS_TSALMIF_Msk : Time Stamp Alarm 268 * 269 * @return None 270 * 271 * @details This macro get specified interrupt flag or interrupt indicator status. 272 * \hideinitializer 273 */ 274 #define EMAC_GET_INT_FLAG(emac, u32eIntTypeFlag) (((emac)->INTSTS & (u32eIntTypeFlag))?1:0) 275 276 /** 277 * @brief Clear specified interrupt flag/status 278 * 279 * @param[in] emac The pointer of the specified EMAC module 280 * @param[in] u32eIntTypeFlag Interrupt Type Flag, should be 281 * - \ref EMAC_INTSTS_RXIF_Msk : Receive 282 * - \ref EMAC_INTSTS_CRCEIF_Msk : CRC Error 283 * - \ref EMAC_INTSTS_RXOVIF_Msk : Receive FIFO Overflow 284 * - \ref EMAC_INTSTS_LPIF_Msk : Long Packet 285 * - \ref EMAC_INTSTS_RXGDIF_Msk : Receive Good 286 * - \ref EMAC_INTSTS_ALIEIF_Msk : Alignment Error 287 * - \ref EMAC_INTSTS_RPIF_Msk : Runt Packet 288 * - \ref EMAC_INTSTS_MPCOVIF_Msk : Missed Packet Counter 289 * - \ref EMAC_INTSTS_MFLEIF_Msk : Maximum Frame Length Exceed 290 * - \ref EMAC_INTSTS_DENIF_Msk : DMA Early Notification 291 * - \ref EMAC_INTSTS_RDUIF_Msk : Receive Descriptor Unavailable 292 * - \ref EMAC_INTSTS_RXBEIF_Msk : Receive Bus Error 293 * - \ref EMAC_INTSTS_CFRIF_Msk : Control Frame Receive 294 * - \ref EMAC_INTSTS_WOLIF_Msk : Wake on LAN 295 * - \ref EMAC_INTSTS_TXIF_Msk : Transmit 296 * - \ref EMAC_INTSTS_TXUDIF_Msk : Transmit FIFO Underflow 297 * - \ref EMAC_INTSTS_TXCPIF_Msk : Transmit Completion 298 * - \ref EMAC_INTSTS_EXDEFIF_Msk : Defer Exceed 299 * - \ref EMAC_INTSTS_NCSIF_Msk : No Carrier Sense 300 * - \ref EMAC_INTSTS_TXABTIF_Msk : Transmit Abort 301 * - \ref EMAC_INTSTS_LCIF_Msk : Late Collision 302 * - \ref EMAC_INTSTS_TDUIF_Msk : Transmit Descriptor Unavailable 303 * - \ref EMAC_INTSTS_TXBEIF_Msk : Transmit Bus Error 304 * - \ref EMAC_INTSTS_TSALMIF_Msk : Time Stamp Alarm 305 * 306 * @retval 0 The specified interrupt is not happened. 307 * 1 The specified interrupt is happened. 308 * 309 * @details This macro clear specified interrupt flag or interrupt indicator status. 310 * \hideinitializer 311 */ 312 #define EMAC_CLEAR_INT_FLAG(emac, u32eIntTypeFlag) ((emac)->INTSTS |= (u32eIntTypeFlag)) 313 314 void EMAC_Open(uint8_t *pu8MacAddr); 315 void EMAC_Close(void); 316 void EMAC_SetMacAddr(uint8_t *pu8MacAddr); 317 void EMAC_EnableCamEntry(uint32_t u32Entry, uint8_t pu8MacAddr[]); 318 void EMAC_DisableCamEntry(uint32_t u32Entry); 319 320 uint32_t EMAC_RecvPkt(uint8_t *pu8Data, uint32_t *pu32Size); 321 uint32_t EMAC_RecvPktTS(uint8_t *pu8Data, uint32_t *pu32Size, uint32_t *pu32Sec, uint32_t *pu32Nsec); 322 void EMAC_RecvPktDone(void); 323 324 uint32_t EMAC_SendPkt(uint8_t *pu8Data, uint32_t u32Size); 325 uint32_t EMAC_SendPktDone(void); 326 uint32_t EMAC_SendPktDoneTS(uint32_t *pu32Sec, uint32_t *pu32Nsec); 327 328 void EMAC_EnableTS(uint32_t u32Sec, uint32_t u32Nsec); 329 void EMAC_DisableTS(void); 330 void EMAC_GetTime(uint32_t *pu32Sec, uint32_t *pu32Nsec); 331 void EMAC_SetTime(uint32_t u32Sec, uint32_t u32Nsec); 332 void EMAC_UpdateTime(uint32_t u32Neg, uint32_t u32Sec, uint32_t u32Nsec); 333 void EMAC_EnableAlarm(uint32_t u32Sec, uint32_t u32Nsec); 334 void EMAC_DisableAlarm(void); 335 336 uint32_t EMAC_CheckLinkStatus(void); 337 338 void EMAC_PhyInit(void); 339 int32_t EMAC_FillCamEntry(uint8_t pu8MacAddr[]); 340 uint8_t *EMAC_ClaimFreeTXBuf(void); 341 uint32_t EMAC_GetAvailRXBufSize(void); 342 uint32_t EMAC_SendPktWoCopy(uint32_t u32Size); 343 void EMAC_RecvPktDoneWoRxTrigger(void); 344 345 /*@}*/ /* end of group EMAC_EXPORTED_FUNCTIONS */ 346 347 /*@}*/ /* end of group EMAC_Driver */ 348 349 /*@}*/ /* end of group Standard_Driver */ 350 351 #ifdef __cplusplus 352 } 353 #endif 354 355 #endif /* __NU_EMAC_H__ */ 356 357 /*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ 358
