1 /* 2 * Copyright (c) 2017 Oticon A/S 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #ifndef _NRF_HW_MODEL_PPI_H 7 #define _NRF_HW_MODEL_PPI_H 8 9 #ifdef __cplusplus 10 extern "C"{ 11 #endif 12 13 //Signals/Events types HW models may send to the PPI 14 typedef enum { //Note that, for performance, it is better to leave commented the unused ones 15 //0 0x40000000 CLOCK 16 //0 0x40000000 POWER 17 //CLOCK: 18 CLOCK_EVENTS_HFCLKSTARTED , 19 CLOCK_EVENTS_LFCLKSTARTED , 20 CLOCK_EVENTS_DONE , 21 CLOCK_EVENTS_CTTO , 22 CLOCK_EVENTS_CTSTARTED , 23 CLOCK_EVENTS_CTSTOPPED , 24 25 //POWER: 26 // POWER_EVENTS_POFWARN , 27 // POWER_EVENTS_SLEEPENTER , 28 // POWER_EVENTS_SLEEPEXIT , 29 // POWER_EVENTS_USBDETECTED , 30 // POWER_EVENTS_USBREMOVED , 31 // POWER_EVENTS_USBPWRRDY , 32 33 //1 0x40001000 RADIO 34 //RADIO: 35 RADIO_EVENTS_READY , 36 RADIO_EVENTS_ADDRESS , 37 RADIO_EVENTS_PAYLOAD , 38 RADIO_EVENTS_END , 39 RADIO_EVENTS_DISABLED , 40 RADIO_EVENTS_DEVMATCH , 41 RADIO_EVENTS_DEVMISS , 42 RADIO_EVENTS_RSSIEND , 43 RADIO_EVENTS_BCMATCH , 44 RADIO_EVENTS_CRCOK , 45 RADIO_EVENTS_CRCERROR , 46 RADIO_EVENTS_FRAMESTART , 47 RADIO_EVENTS_EDEND , 48 RADIO_EVENTS_EDSTOPPED , 49 RADIO_EVENTS_CCAIDLE , 50 RADIO_EVENTS_CCABUSY , 51 RADIO_EVENTS_CCASTOPPED , 52 RADIO_EVENTS_RATEBOOST , 53 RADIO_EVENTS_TXREADY , 54 RADIO_EVENTS_RXREADY , 55 RADIO_EVENTS_MHRMATCH , 56 RADIO_EVENTS_SYNC , 57 RADIO_EVENTS_PHYEND , 58 RADIO_EVENTS_CTEPRESENT , 59 60 // 2 0x40002000 UARTE 61 // 2 0x40002000 UART 62 UARTE0_EVENTS_CTS, 63 UARTE0_EVENTS_NCTS , 64 UARTE0_EVENTS_RXDRDY , 65 UARTE0_EVENTS_ENDRX , 66 UARTE0_EVENTS_TXDRDY , 67 UARTE0_EVENTS_ENDTX , 68 UARTE0_EVENTS_ERROR , 69 UARTE0_EVENTS_RXTO , 70 UARTE0_EVENTS_RXSTARTED , 71 UARTE0_EVENTS_TXSTARTED , 72 UARTE0_EVENTS_TXSTOPPED , 73 74 // 3 0x40003000 TWIM 75 // 3 0x40003000 SPIS 76 // 3 0x40003000 SPIM 77 // 3 0x40003000 SPI 78 // 3 0x40003000 TWIS 79 // 3 0x40003000 TWI 80 // 4 0x40004000 TWIS 81 // 4 0x40004000 SPIS 82 // 4 0x40004000 SPIM 83 // 4 0x40004000 TWI 84 // 4 0x40004000 TWIM 85 // 4 0x40004000 SPI 86 // 5 0x40005000 NFCT 87 // 6 0x40006000 GPIOTE 88 GPIOTE_EVENTS_IN_0, 89 GPIOTE_EVENTS_IN_1, 90 GPIOTE_EVENTS_IN_2, 91 GPIOTE_EVENTS_IN_3, 92 GPIOTE_EVENTS_IN_4, 93 GPIOTE_EVENTS_IN_5, 94 GPIOTE_EVENTS_IN_6, 95 GPIOTE_EVENTS_IN_7, 96 GPIOTE_EVENTS_PORT, 97 98 // 7 0x40007000 SAADC 99 100 //8 0x40008000 TIMER0 101 //TIMER 102 TIMER0_EVENTS_COMPARE_0 , 103 TIMER0_EVENTS_COMPARE_1 , 104 TIMER0_EVENTS_COMPARE_2 , 105 TIMER0_EVENTS_COMPARE_3 , 106 // TIMER0_EVENTS_COMPARE_4 , 107 // TIMER0_EVENTS_COMPARE_5 , 108 109 //9 0x40009000 Timer 1 110 TIMER1_EVENTS_COMPARE_0 , 111 TIMER1_EVENTS_COMPARE_1 , 112 TIMER1_EVENTS_COMPARE_2 , 113 TIMER1_EVENTS_COMPARE_3 , 114 // TIMER1_EVENTS_COMPARE_4 , 115 // TIMER1_EVENTS_COMPARE_5 , 116 117 //10 0x4000A000 Timer 2 118 TIMER2_EVENTS_COMPARE_0 , 119 TIMER2_EVENTS_COMPARE_1 , 120 TIMER2_EVENTS_COMPARE_2 , 121 TIMER2_EVENTS_COMPARE_3 , 122 // TIMER2_EVENTS_COMPARE_4 , 123 // TIMER2_EVENTS_COMPARE_5 , 124 125 126 //11 0x4000B000 RTC0 127 //RTC 128 RTC0_EVENTS_TICK , 129 RTC0_EVENTS_OVRFLW , 130 RTC0_EVENTS_COMPARE_0 , 131 RTC0_EVENTS_COMPARE_1 , 132 RTC0_EVENTS_COMPARE_2 , 133 RTC0_EVENTS_COMPARE_3 , 134 135 //12 0x4000C000 Temperature sensor 136 TEMP_EVENTS_DATARDY, 137 138 //13 0x4000D000 Random number generator 139 //RNG 140 RNG_EVENTS_VALRDY , 141 142 //14 0x4000E000 ECB AES 143 ECB_EVENTS_ENDECB, 144 ECB_EVENTS_ERRORECB, 145 146 //15 0x4000F000 AAR 147 AAR_EVENTS_END, 148 AAR_EVENTS_RESOLVED, 149 AAR_EVENTS_NOTRESOLVED, 150 151 //15 0x4000F000 CCM AES 152 CCM_EVENTS_ENDKSGEN, 153 CCM_EVENTS_ENDCRYPT, 154 CCM_EVENTS_ERROR, 155 156 //16 0x40010000 WDT 157 158 //17 0x40011000 RTC1 159 RTC1_EVENTS_TICK , 160 RTC1_EVENTS_OVRFLW , 161 RTC1_EVENTS_COMPARE_0 , 162 RTC1_EVENTS_COMPARE_1 , 163 RTC1_EVENTS_COMPARE_2 , 164 RTC1_EVENTS_COMPARE_3 , 165 166 // 18 0x40012000 QDEC 167 // 19 0x40013000 LPCOMP 168 // 19 0x40013000 COMP 169 // 20 0x40014000 EGU 170 EGU0_EVENTS_TRIGGERED_0, //Careful!: These EGU events (inside each instance) are assumed consecutive in the EGU model 171 EGU0_EVENTS_TRIGGERED_1, 172 EGU0_EVENTS_TRIGGERED_2, 173 EGU0_EVENTS_TRIGGERED_3, 174 EGU0_EVENTS_TRIGGERED_4, 175 EGU0_EVENTS_TRIGGERED_5, 176 EGU0_EVENTS_TRIGGERED_6, 177 EGU0_EVENTS_TRIGGERED_7, 178 EGU0_EVENTS_TRIGGERED_8, 179 EGU0_EVENTS_TRIGGERED_9, 180 EGU0_EVENTS_TRIGGERED_10, 181 EGU0_EVENTS_TRIGGERED_11, 182 EGU0_EVENTS_TRIGGERED_12, 183 EGU0_EVENTS_TRIGGERED_13, 184 EGU0_EVENTS_TRIGGERED_14, 185 EGU0_EVENTS_TRIGGERED_15, 186 // 20 0x40014000 SWI 187 // 21 0x40015000 EGU 188 EGU1_EVENTS_TRIGGERED_0, 189 EGU1_EVENTS_TRIGGERED_1, 190 EGU1_EVENTS_TRIGGERED_2, 191 EGU1_EVENTS_TRIGGERED_3, 192 EGU1_EVENTS_TRIGGERED_4, 193 EGU1_EVENTS_TRIGGERED_5, 194 EGU1_EVENTS_TRIGGERED_6, 195 EGU1_EVENTS_TRIGGERED_7, 196 EGU1_EVENTS_TRIGGERED_8, 197 EGU1_EVENTS_TRIGGERED_9, 198 EGU1_EVENTS_TRIGGERED_10, 199 EGU1_EVENTS_TRIGGERED_11, 200 EGU1_EVENTS_TRIGGERED_12, 201 EGU1_EVENTS_TRIGGERED_13, 202 EGU1_EVENTS_TRIGGERED_14, 203 EGU1_EVENTS_TRIGGERED_15, 204 // 21 0x40015000 SWI 205 // 22 0x40016000 EGU 206 EGU2_EVENTS_TRIGGERED_0, 207 EGU2_EVENTS_TRIGGERED_1, 208 EGU2_EVENTS_TRIGGERED_2, 209 EGU2_EVENTS_TRIGGERED_3, 210 EGU2_EVENTS_TRIGGERED_4, 211 EGU2_EVENTS_TRIGGERED_5, 212 EGU2_EVENTS_TRIGGERED_6, 213 EGU2_EVENTS_TRIGGERED_7, 214 EGU2_EVENTS_TRIGGERED_8, 215 EGU2_EVENTS_TRIGGERED_9, 216 EGU2_EVENTS_TRIGGERED_10, 217 EGU2_EVENTS_TRIGGERED_11, 218 EGU2_EVENTS_TRIGGERED_12, 219 EGU2_EVENTS_TRIGGERED_13, 220 EGU2_EVENTS_TRIGGERED_14, 221 EGU2_EVENTS_TRIGGERED_15, 222 // 22 0x40016000 SWI 223 // 23 0x40017000 EGU 224 EGU3_EVENTS_TRIGGERED_0, 225 EGU3_EVENTS_TRIGGERED_1, 226 EGU3_EVENTS_TRIGGERED_2, 227 EGU3_EVENTS_TRIGGERED_3, 228 EGU3_EVENTS_TRIGGERED_4, 229 EGU3_EVENTS_TRIGGERED_5, 230 EGU3_EVENTS_TRIGGERED_6, 231 EGU3_EVENTS_TRIGGERED_7, 232 EGU3_EVENTS_TRIGGERED_8, 233 EGU3_EVENTS_TRIGGERED_9, 234 EGU3_EVENTS_TRIGGERED_10, 235 EGU3_EVENTS_TRIGGERED_11, 236 EGU3_EVENTS_TRIGGERED_12, 237 EGU3_EVENTS_TRIGGERED_13, 238 EGU3_EVENTS_TRIGGERED_14, 239 EGU3_EVENTS_TRIGGERED_15, 240 // 23 0x40017000 SWI 241 // 24 0x40018000 SWI 242 // 24 0x40018000 EGU 243 EGU4_EVENTS_TRIGGERED_0, 244 EGU4_EVENTS_TRIGGERED_1, 245 EGU4_EVENTS_TRIGGERED_2, 246 EGU4_EVENTS_TRIGGERED_3, 247 EGU4_EVENTS_TRIGGERED_4, 248 EGU4_EVENTS_TRIGGERED_5, 249 EGU4_EVENTS_TRIGGERED_6, 250 EGU4_EVENTS_TRIGGERED_7, 251 EGU4_EVENTS_TRIGGERED_8, 252 EGU4_EVENTS_TRIGGERED_9, 253 EGU4_EVENTS_TRIGGERED_10, 254 EGU4_EVENTS_TRIGGERED_11, 255 EGU4_EVENTS_TRIGGERED_12, 256 EGU4_EVENTS_TRIGGERED_13, 257 EGU4_EVENTS_TRIGGERED_14, 258 EGU4_EVENTS_TRIGGERED_15, 259 // 25 0x40019000 SWI 260 // 25 0x40019000 EGU 261 EGU5_EVENTS_TRIGGERED_0, 262 EGU5_EVENTS_TRIGGERED_1, 263 EGU5_EVENTS_TRIGGERED_2, 264 EGU5_EVENTS_TRIGGERED_3, 265 EGU5_EVENTS_TRIGGERED_4, 266 EGU5_EVENTS_TRIGGERED_5, 267 EGU5_EVENTS_TRIGGERED_6, 268 EGU5_EVENTS_TRIGGERED_7, 269 EGU5_EVENTS_TRIGGERED_8, 270 EGU5_EVENTS_TRIGGERED_9, 271 EGU5_EVENTS_TRIGGERED_10, 272 EGU5_EVENTS_TRIGGERED_11, 273 EGU5_EVENTS_TRIGGERED_12, 274 EGU5_EVENTS_TRIGGERED_13, 275 EGU5_EVENTS_TRIGGERED_14, 276 EGU5_EVENTS_TRIGGERED_15, 277 278 // 26 0x4001A000 TIMER3 279 TIMER3_EVENTS_COMPARE_0 , 280 TIMER3_EVENTS_COMPARE_1 , 281 TIMER3_EVENTS_COMPARE_2 , 282 TIMER3_EVENTS_COMPARE_3 , 283 TIMER3_EVENTS_COMPARE_4 , 284 TIMER3_EVENTS_COMPARE_5 , 285 286 // 27 0x4001B000 TIMER4 287 TIMER4_EVENTS_COMPARE_0 , 288 TIMER4_EVENTS_COMPARE_1 , 289 TIMER4_EVENTS_COMPARE_2 , 290 TIMER4_EVENTS_COMPARE_3 , 291 TIMER4_EVENTS_COMPARE_4 , 292 TIMER4_EVENTS_COMPARE_5 , 293 294 // 28 0x4001C000 PWM 295 // 29 0x4001D000 PDM 296 // 30 0x4001E000 ACL 297 // 30 0x4001E000 NVMC 298 299 //31 0x4001F000 PPI 300 //PPI 301 //No events 302 303 // 32 0x40020000 MWU 304 // 33 0x40021000 PWM 305 // 34 0x40022000 PWM 306 // 35 0x40023000 SPIM 307 // 35 0x40023000 SPIS 308 // 35 0x40023000 SPI 309 // 36 0x40024000 RTC 310 RTC2_EVENTS_TICK , 311 RTC2_EVENTS_OVRFLW , 312 RTC2_EVENTS_COMPARE_0 , 313 RTC2_EVENTS_COMPARE_1 , 314 RTC2_EVENTS_COMPARE_2 , 315 RTC2_EVENTS_COMPARE_3 , 316 317 // 37 0x40025000 I2S 318 // 38 0x40026000 FPU 319 // 39 0x40027000 USBD 320 // 40 0x40028000 UARTE 321 UARTE1_EVENTS_CTS, 322 UARTE1_EVENTS_NCTS , 323 UARTE1_EVENTS_RXDRDY , 324 UARTE1_EVENTS_ENDRX , 325 UARTE1_EVENTS_TXDRDY , 326 UARTE1_EVENTS_ENDTX , 327 UARTE1_EVENTS_ERROR , 328 UARTE1_EVENTS_RXTO , 329 UARTE1_EVENTS_RXSTARTED , 330 UARTE1_EVENTS_TXSTARTED , 331 UARTE1_EVENTS_TXSTOPPED , 332 333 // 41 0x40029000 QSPI 334 // 45 0x4002D000 PWM 335 // 47 0x4002F000 SPIM 336 // 0 0x50000000 GPIO 337 // 0 0x50000000 GPIO 338 // 0 0x50000300 GPIO 339 // 42 0x5002A000 CRYPTOCELL 340 // N/A 0x10000000 FICR 341 // N/A 0x10001000 UICR 342 343 NUMBER_PPI_EVENTS 344 } ppi_event_types_t; 345 346 #define NUMBER_PPI_CHANNELS 32 347 348 void nrf_ppi_event(ppi_event_types_t event); 349 void nrf_ppi_regw_sideeffects_TEP(int ch_nbr); 350 void nrf_ppi_regw_sideeffects_EEP(int ch_nbr); 351 void nrf_ppi_regw_sideeffects_FORK_TEP(int ch_nbr); 352 void nrf_ppi_regw_sideeffects_TASKS_CHG_DIS(int i); 353 void nrf_ppi_regw_sideeffects_TASKS_CHG_EN(int i); 354 void nrf_ppi_regw_sideeffects_CHENSET(void); 355 void nrf_ppi_regw_sideeffects_CHENCLR(void); 356 357 #ifdef __cplusplus 358 } 359 #endif 360 361 #endif 362
