1# This file describes eFuses fields and registers for ESP32-C2 chip 2# 3# SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD 4# 5# SPDX-License-Identifier: GPL-2.0-or-later 6 7from ..mem_definition_base import EfuseBlocksBase, EfuseFieldsBase, EfuseRegistersBase 8 9 10# fmt: off 11class EfuseDefineRegisters(EfuseRegistersBase): 12 13 EFUSE_MEM_SIZE = (0x01FC + 4) 14 15 # EFUSE registers & command/conf values 16 DR_REG_EFUSE_BASE = 0x60008800 17 EFUSE_PGM_DATA0_REG = DR_REG_EFUSE_BASE 18 EFUSE_PGM_CHECK_VALUE0_REG = DR_REG_EFUSE_BASE + 0x020 19 EFUSE_CLK_REG = DR_REG_EFUSE_BASE + 0x88 20 EFUSE_CONF_REG = DR_REG_EFUSE_BASE + 0x8C 21 EFUSE_STATUS_REG = DR_REG_EFUSE_BASE + 0x90 22 EFUSE_CMD_REG = DR_REG_EFUSE_BASE + 0x94 23 EFUSE_RD_REPEAT_ERR_REG = DR_REG_EFUSE_BASE + 0x80 24 EFUSE_RD_RS_ERR_REG = DR_REG_EFUSE_BASE + 0x84 25 EFUSE_WRITE_OP_CODE = 0x5A5A 26 EFUSE_READ_OP_CODE = 0x5AA5 27 EFUSE_PGM_CMD_MASK = 0x3 28 EFUSE_PGM_CMD = 0x2 29 EFUSE_READ_CMD = 0x1 30 31 BLOCK_ERRORS = [ 32 # error_reg, err_num_mask, err_num_offs, fail_bit 33 (EFUSE_RD_REPEAT_ERR_REG, None, None, None), # BLOCK0 34 (EFUSE_RD_RS_ERR_REG, 0x7, 0, 3), # BLOCK1 35 (EFUSE_RD_RS_ERR_REG, 0x7, 4, 7), # BLOCK2 36 (EFUSE_RD_RS_ERR_REG, 0x7, 8, 11), # BLOCK3 37 ] 38 39 EFUSE_WR_TIM_CONF2_REG = DR_REG_EFUSE_BASE + 0x118 40 EFUSE_PWR_OFF_NUM_S = 0 41 EFUSE_PWR_OFF_NUM_M = 0xFFFF << EFUSE_PWR_OFF_NUM_S 42 43 EFUSE_WR_TIM_CONF0_REG = DR_REG_EFUSE_BASE + 0x110 44 EFUSE_TPGM_INACTIVE_S = 8 45 EFUSE_TPGM_INACTIVE_M = 0xFF << EFUSE_TPGM_INACTIVE_S 46 47 48class EfuseDefineBlocks(EfuseBlocksBase): 49 50 __base_rd_regs = EfuseDefineRegisters.DR_REG_EFUSE_BASE 51 __base_wr_regs = EfuseDefineRegisters.EFUSE_PGM_DATA0_REG 52 # List of efuse blocks 53 BLOCKS = [ 54 # Name, Alias, Index, Read address, Write address, Write protect bit, Read protect bit, Len, key_purpose 55 ("BLOCK0", ["BLOCK0"], 0, __base_rd_regs + 0x02C, __base_wr_regs, None, None, 2, None), 56 ("BLOCK1", ["BLOCK1"], 1, __base_rd_regs + 0x034, __base_wr_regs, 5, None, 3, None), 57 ("BLOCK2", ["BLOCK2"], 2, __base_rd_regs + 0x040, __base_wr_regs, 6, None, 8, None), 58 ("BLOCK_KEY0", ["BLOCK3"], 3, __base_rd_regs + 0x060, __base_wr_regs, 7, [0, 1], 8, None), 59 ] 60 61 def get_burn_block_data_names(self): 62 list_of_names = [] 63 for block in self.BLOCKS: 64 blk = self.get(block) 65 if blk.name: 66 list_of_names.append(blk.name) 67 if blk.alias: 68 for alias in blk.alias: 69 list_of_names.append(alias) 70 return list_of_names 71 72 def get_blocks_for_keys(self): 73 return ['BLOCK_KEY0'] 74 75 76class EfuseDefineFields(EfuseFieldsBase): 77 78 # List of efuse fields from TRM the chapter eFuse Controller. 79 EFUSES = [ 80 # 81 # Parameters in BLOCK0 82 # Name Category Block Word Pos Type:len WR_DIS RD_DIS Class Description Dictionary 83 ("WR_DIS", "efuse", 0, 0, 0, "uint:8", None, None, None, "Disables programming of individual eFuses", None), 84 ("RD_DIS", "efuse", 0, 1, 0, "uint:2", 0, None, None, "Disables software reading from BLOCK3", None), 85 ("WDT_DELAY_SEL", "WDT config", 0, 1, 2, "uint:2", 1, None, None, "RTC WDT timeout threshold", None), 86 ("DIS_PAD_JTAG", "jtag config", 0, 1, 4, "bool", 1, None, None, "Permanently disable JTAG access via pads" 87 "USB JTAG is controlled separately", None), 88 ("DIS_DOWNLOAD_ICACHE", "security", 0, 1, 5, "bool", 1, None, None, "Disables iCache in download mode", None), 89 ("DIS_DOWNLOAD_MANUAL_ENCRYPT", "security", 0, 1, 6, "bool", 2, None, None, "Disables flash encryption in Download boot modes", 90 None), 91 ("SPI_BOOT_CRYPT_CNT", "security", 0, 1, 7, "uint:3", 2, None, None, "Enables encryption and decryption, when an SPI boot" 92 "mode is set. Enabled when 1 or 3 bits are set," 93 "disabled otherwise", 94 {0: "Disable", 95 1: "Enable", 96 3: "Disable", 97 7: "Enable"}), 98 ("XTS_KEY_LENGTH_256", "security", 0, 1, 10, "bool", 2, None, None, "Flash encryption key length", 99 {0: "128 bits key", 100 1: "256 bits key"}), 101 ("UART_PRINT_CONTROL", "config", 0, 1, 11, "uint:2", 3, None, None, "Set UART boot message output mode", 102 {0: "Force print", 103 1: "Low-level print controlled by GPIO 8", 104 3: "High-level print controlled by GPIO 8", 105 7: "Print force disabled"}), 106 ("FORCE_SEND_RESUME", "config", 0, 1, 13, "bool", 3, None, None, "Force ROM code to send a resume cmd during SPI boot", 107 None), 108 ("DIS_DOWNLOAD_MODE", "security", 0, 1, 14, "bool", 3, None, None, "Disables all Download boot modes", None), 109 ("DIS_DIRECT_BOOT", "config", 0, 1, 15, "bool", 3, None, None, "Disable direct_boot mode", None), 110 ("ENABLE_SECURITY_DOWNLOAD", "security", 0, 1, 16, "bool", 3, None, None, "Enables secure UART download mode " 111 "(read/write flash only)", None), 112 ("FLASH_TPUW", "flash config", 0, 1, 17, "uint:4", 3, None, None, "Configures flash startup delay after SoC power-up, " 113 "unit is (ms/2). When the value is 15, delay is 7.5 ms", 114 None), 115 ("SECURE_BOOT_EN", "security", 0, 1, 21, "bool", 2, None, None, "Configures secure boot", None), 116 ("SECURE_VERSION", "identity", 0, 1, 22, "uint:4", 4, None, "bitcount", "Secure version (anti-rollback feature)", None), 117 ("CUSTOM_MAC_USED", "identity", 0, 1, 26, "bool", 4, None, None, "Enable CUSTOM_MAC programming", None), 118 ("DISABLE_WAFER_VERSION_MAJOR", "config", 0, 1, 27, "bool", 4, None, None, "Disables check of wafer version major", None), 119 ("DISABLE_BLK_VERSION_MAJOR", "config", 0, 1, 28, "bool", 4, None, None, "Disables check of blk version major", None), 120 121 # 122 # Parameters in BLOCK1 123 # Name Category Block Word Pos Type:len WR_DIS RD_DIS Class Description Dictionary 124 ("CUSTOM_MAC", "identity", 1, 0, 0, "bytes:6", 5, None, 'mac', "Custom MAC addr", None), 125 126 # 127 # Parameters in BLOCK2 128 # Name Category Block Word Pos Type:len WR_DIS RD_DIS Class Description Dictionary 129 ("MAC", "identity", 2, 0, 0, "bytes:6", 6, None, 'mac', "Factory MAC Address", None), 130 ("WAFER_VERSION_MINOR", "identity", 2, 1, 16, "uint:4", 6, None, None, "Minor WAFER version", None), 131 ("WAFER_VERSION_MAJOR", "identity", 2, 1, 20, "uint:2", 6, None, None, "Major WAFER version", None), 132 ("PKG_VERSION", "identity", 2, 1, 22, "uint:3", 6, None, None, "Package version", None), 133 ("BLK_VERSION_MINOR", "identity", 2, 1, 25, "uint:3", 6, None, None, "Minor version of BLOCK2", 134 {0: "No calibration", 1: "With calibration"}), 135 136 ("BLK_VERSION_MAJOR", "identity", 2, 1, 28, "uint:2", 6, None, None, "Major version of BLOCK2", None), 137 ("LDO_VOL_BIAS_CONFIG_HIGH", "ldo", 2, 2, 0, "uint:27", 6, None, None, "", None), 138 ("PVT_LOW", "pvt", 2, 2, 27, "uint:5", 6, None, None, "", None), 139 ("PVT_HIGH", "pvt", 2, 3, 0, "uint:10", 6, None, None, "", None), 140 ("ADC_CALIBRATION_0", "adc_calib", 2, 3, 10, "uint:22", 6, None, None, "", None), 141 ("ADC_CALIBRATION_1", "adc_calib", 2, 4, 0, "uint:32", 6, None, None, "", None), 142 ("ADC_CALIBRATION_2", "adc_calib", 2, 5, 0, "uint:32", 6, None, None, "", None), 143 ] 144 145 KEYBLOCKS = [ 146 # Name Category Block Word Pos Type:len WR_DIS RD_DIS Class Description Dictionary 147 ('BLOCK_KEY0', "security", 3, 0, 0, "bytes:32", 7, [0, 1], "keyblock", "BLOCK_KEY0 - 256-bits. 256-bit key of Flash Encryption", None), 148 ('BLOCK_KEY0_LOW_128', "security", 3, 0, 0, "bytes:16", 7, 0, "keyblock", "BLOCK_KEY0 - lower 128-bits. 128-bit key of Flash Encryption", None), 149 ('BLOCK_KEY0_HI_128', "security", 3, 4, 0, "bytes:16", 7, 1, "keyblock", "BLOCK_KEY0 - higher 128-bits. 128-bits key of Secure Boot.", None), 150 ] 151 152 # if BLK_VERSION_MINOR is 1, these efuse fields are in BLOCK2 153 BLOCK2_CALIBRATION_EFUSES = [ 154 # Name Category Block Word Pos Type:len WR_DIS RD_DIS Class Description Dictionary 155 ] 156# fmt: on 157
