1 /** 2 * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #pragma once 7 8 #include <stdint.h> 9 #include "soc/soc.h" 10 #include "efuse_defs.h" 11 #ifdef __cplusplus 12 extern "C" { 13 #endif 14 15 /** EFUSE_PGM_DATA0_REG register 16 * Register 0 that stores data to be programmed. 17 */ 18 #define EFUSE_PGM_DATA0_REG (DR_REG_EFUSE_BASE + 0x0) 19 /** EFUSE_PGM_DATA_0 : R/W; bitpos: [31:0]; default: 0; 20 * Configures the 0th 32-bit data to be programmed. 21 */ 22 #define EFUSE_PGM_DATA_0 0xFFFFFFFFU 23 #define EFUSE_PGM_DATA_0_M (EFUSE_PGM_DATA_0_V << EFUSE_PGM_DATA_0_S) 24 #define EFUSE_PGM_DATA_0_V 0xFFFFFFFFU 25 #define EFUSE_PGM_DATA_0_S 0 26 27 /** EFUSE_PGM_DATA1_REG register 28 * Register 1 that stores data to be programmed. 29 */ 30 #define EFUSE_PGM_DATA1_REG (DR_REG_EFUSE_BASE + 0x4) 31 /** EFUSE_PGM_DATA_1 : R/W; bitpos: [31:0]; default: 0; 32 * Configures the 1st 32-bit data to be programmed. 33 */ 34 #define EFUSE_PGM_DATA_1 0xFFFFFFFFU 35 #define EFUSE_PGM_DATA_1_M (EFUSE_PGM_DATA_1_V << EFUSE_PGM_DATA_1_S) 36 #define EFUSE_PGM_DATA_1_V 0xFFFFFFFFU 37 #define EFUSE_PGM_DATA_1_S 0 38 39 /** EFUSE_PGM_DATA2_REG register 40 * Register 2 that stores data to be programmed. 41 */ 42 #define EFUSE_PGM_DATA2_REG (DR_REG_EFUSE_BASE + 0x8) 43 /** EFUSE_PGM_DATA_2 : R/W; bitpos: [31:0]; default: 0; 44 * Configures the 2nd 32-bit data to be programmed. 45 */ 46 #define EFUSE_PGM_DATA_2 0xFFFFFFFFU 47 #define EFUSE_PGM_DATA_2_M (EFUSE_PGM_DATA_2_V << EFUSE_PGM_DATA_2_S) 48 #define EFUSE_PGM_DATA_2_V 0xFFFFFFFFU 49 #define EFUSE_PGM_DATA_2_S 0 50 51 /** EFUSE_PGM_DATA3_REG register 52 * Register 3 that stores data to be programmed. 53 */ 54 #define EFUSE_PGM_DATA3_REG (DR_REG_EFUSE_BASE + 0xc) 55 /** EFUSE_PGM_DATA_3 : R/W; bitpos: [31:0]; default: 0; 56 * Configures the 3rd 32-bit data to be programmed. 57 */ 58 #define EFUSE_PGM_DATA_3 0xFFFFFFFFU 59 #define EFUSE_PGM_DATA_3_M (EFUSE_PGM_DATA_3_V << EFUSE_PGM_DATA_3_S) 60 #define EFUSE_PGM_DATA_3_V 0xFFFFFFFFU 61 #define EFUSE_PGM_DATA_3_S 0 62 63 /** EFUSE_PGM_DATA4_REG register 64 * Register 4 that stores data to be programmed. 65 */ 66 #define EFUSE_PGM_DATA4_REG (DR_REG_EFUSE_BASE + 0x10) 67 /** EFUSE_PGM_DATA_4 : R/W; bitpos: [31:0]; default: 0; 68 * Configures the 4th 32-bit data to be programmed. 69 */ 70 #define EFUSE_PGM_DATA_4 0xFFFFFFFFU 71 #define EFUSE_PGM_DATA_4_M (EFUSE_PGM_DATA_4_V << EFUSE_PGM_DATA_4_S) 72 #define EFUSE_PGM_DATA_4_V 0xFFFFFFFFU 73 #define EFUSE_PGM_DATA_4_S 0 74 75 /** EFUSE_PGM_DATA5_REG register 76 * Register 5 that stores data to be programmed. 77 */ 78 #define EFUSE_PGM_DATA5_REG (DR_REG_EFUSE_BASE + 0x14) 79 /** EFUSE_PGM_DATA_5 : R/W; bitpos: [31:0]; default: 0; 80 * Configures the 5th 32-bit data to be programmed. 81 */ 82 #define EFUSE_PGM_DATA_5 0xFFFFFFFFU 83 #define EFUSE_PGM_DATA_5_M (EFUSE_PGM_DATA_5_V << EFUSE_PGM_DATA_5_S) 84 #define EFUSE_PGM_DATA_5_V 0xFFFFFFFFU 85 #define EFUSE_PGM_DATA_5_S 0 86 87 /** EFUSE_PGM_DATA6_REG register 88 * Register 6 that stores data to be programmed. 89 */ 90 #define EFUSE_PGM_DATA6_REG (DR_REG_EFUSE_BASE + 0x18) 91 /** EFUSE_PGM_DATA_6 : R/W; bitpos: [31:0]; default: 0; 92 * Configures the 6th 32-bit data to be programmed. 93 */ 94 #define EFUSE_PGM_DATA_6 0xFFFFFFFFU 95 #define EFUSE_PGM_DATA_6_M (EFUSE_PGM_DATA_6_V << EFUSE_PGM_DATA_6_S) 96 #define EFUSE_PGM_DATA_6_V 0xFFFFFFFFU 97 #define EFUSE_PGM_DATA_6_S 0 98 99 /** EFUSE_PGM_DATA7_REG register 100 * Register 7 that stores data to be programmed. 101 */ 102 #define EFUSE_PGM_DATA7_REG (DR_REG_EFUSE_BASE + 0x1c) 103 /** EFUSE_PGM_DATA_7 : R/W; bitpos: [31:0]; default: 0; 104 * Configures the 7th 32-bit data to be programmed. 105 */ 106 #define EFUSE_PGM_DATA_7 0xFFFFFFFFU 107 #define EFUSE_PGM_DATA_7_M (EFUSE_PGM_DATA_7_V << EFUSE_PGM_DATA_7_S) 108 #define EFUSE_PGM_DATA_7_V 0xFFFFFFFFU 109 #define EFUSE_PGM_DATA_7_S 0 110 111 /** EFUSE_PGM_CHECK_VALUE0_REG register 112 * Register 0 that stores the RS code to be programmed. 113 */ 114 #define EFUSE_PGM_CHECK_VALUE0_REG (DR_REG_EFUSE_BASE + 0x20) 115 /** EFUSE_PGM_RS_DATA_0 : R/W; bitpos: [31:0]; default: 0; 116 * Configures the 0th 32-bit RS code to be programmed. 117 */ 118 #define EFUSE_PGM_RS_DATA_0 0xFFFFFFFFU 119 #define EFUSE_PGM_RS_DATA_0_M (EFUSE_PGM_RS_DATA_0_V << EFUSE_PGM_RS_DATA_0_S) 120 #define EFUSE_PGM_RS_DATA_0_V 0xFFFFFFFFU 121 #define EFUSE_PGM_RS_DATA_0_S 0 122 123 /** EFUSE_PGM_CHECK_VALUE1_REG register 124 * Register 1 that stores the RS code to be programmed. 125 */ 126 #define EFUSE_PGM_CHECK_VALUE1_REG (DR_REG_EFUSE_BASE + 0x24) 127 /** EFUSE_PGM_RS_DATA_1 : R/W; bitpos: [31:0]; default: 0; 128 * Configures the 1st 32-bit RS code to be programmed. 129 */ 130 #define EFUSE_PGM_RS_DATA_1 0xFFFFFFFFU 131 #define EFUSE_PGM_RS_DATA_1_M (EFUSE_PGM_RS_DATA_1_V << EFUSE_PGM_RS_DATA_1_S) 132 #define EFUSE_PGM_RS_DATA_1_V 0xFFFFFFFFU 133 #define EFUSE_PGM_RS_DATA_1_S 0 134 135 /** EFUSE_PGM_CHECK_VALUE2_REG register 136 * Register 2 that stores the RS code to be programmed. 137 */ 138 #define EFUSE_PGM_CHECK_VALUE2_REG (DR_REG_EFUSE_BASE + 0x28) 139 /** EFUSE_PGM_RS_DATA_2 : R/W; bitpos: [31:0]; default: 0; 140 * Configures the 2nd 32-bit RS code to be programmed. 141 */ 142 #define EFUSE_PGM_RS_DATA_2 0xFFFFFFFFU 143 #define EFUSE_PGM_RS_DATA_2_M (EFUSE_PGM_RS_DATA_2_V << EFUSE_PGM_RS_DATA_2_S) 144 #define EFUSE_PGM_RS_DATA_2_V 0xFFFFFFFFU 145 #define EFUSE_PGM_RS_DATA_2_S 0 146 147 /** EFUSE_RD_WR_DIS_REG register 148 * BLOCK0 data register 0. 149 */ 150 #define EFUSE_RD_WR_DIS_REG (DR_REG_EFUSE_BASE + 0x2c) 151 /** EFUSE_WR_DIS : RO; bitpos: [31:0]; default: 0; 152 * Represents whether programming of individual eFuse memory bit is disabled or 153 * enabled. 1: Disabled. 0 Enabled. 154 */ 155 #define EFUSE_WR_DIS 0xFFFFFFFFU 156 #define EFUSE_WR_DIS_M (EFUSE_WR_DIS_V << EFUSE_WR_DIS_S) 157 #define EFUSE_WR_DIS_V 0xFFFFFFFFU 158 #define EFUSE_WR_DIS_S 0 159 160 /** EFUSE_RD_REPEAT_DATA0_REG register 161 * BLOCK0 data register 1. 162 */ 163 #define EFUSE_RD_REPEAT_DATA0_REG (DR_REG_EFUSE_BASE + 0x30) 164 /** EFUSE_RD_DIS : RO; bitpos: [6:0]; default: 0; 165 * Represents whether reading of individual eFuse block(block4~block10) is disabled or 166 * enabled. 1: disabled. 0: enabled. 167 */ 168 #define EFUSE_RD_DIS 0x0000007FU 169 #define EFUSE_RD_DIS_M (EFUSE_RD_DIS_V << EFUSE_RD_DIS_S) 170 #define EFUSE_RD_DIS_V 0x0000007FU 171 #define EFUSE_RD_DIS_S 0 172 /** EFUSE_RPT4_RESERVED0_4 : RO; bitpos: [7]; default: 0; 173 * Reserved. 174 */ 175 #define EFUSE_RPT4_RESERVED0_4 (BIT(7)) 176 #define EFUSE_RPT4_RESERVED0_4_M (EFUSE_RPT4_RESERVED0_4_V << EFUSE_RPT4_RESERVED0_4_S) 177 #define EFUSE_RPT4_RESERVED0_4_V 0x00000001U 178 #define EFUSE_RPT4_RESERVED0_4_S 7 179 /** EFUSE_DIS_ICACHE : RO; bitpos: [8]; default: 0; 180 * Represents whether icache is disabled or enabled. 1: disabled. 0: enabled. 181 */ 182 #define EFUSE_DIS_ICACHE (BIT(8)) 183 #define EFUSE_DIS_ICACHE_M (EFUSE_DIS_ICACHE_V << EFUSE_DIS_ICACHE_S) 184 #define EFUSE_DIS_ICACHE_V 0x00000001U 185 #define EFUSE_DIS_ICACHE_S 8 186 /** EFUSE_DIS_USB_JTAG : RO; bitpos: [9]; default: 0; 187 * Represents whether the function of usb switch to jtag is disabled or enabled. 1: 188 * disabled. 0: enabled. 189 */ 190 #define EFUSE_DIS_USB_JTAG (BIT(9)) 191 #define EFUSE_DIS_USB_JTAG_M (EFUSE_DIS_USB_JTAG_V << EFUSE_DIS_USB_JTAG_S) 192 #define EFUSE_DIS_USB_JTAG_V 0x00000001U 193 #define EFUSE_DIS_USB_JTAG_S 9 194 /** EFUSE_POWERGLITCH_EN : RO; bitpos: [10]; default: 0; 195 * Represents whether power glitch function is enabled. 1: enabled. 0: disabled. 196 */ 197 #define EFUSE_POWERGLITCH_EN (BIT(10)) 198 #define EFUSE_POWERGLITCH_EN_M (EFUSE_POWERGLITCH_EN_V << EFUSE_POWERGLITCH_EN_S) 199 #define EFUSE_POWERGLITCH_EN_V 0x00000001U 200 #define EFUSE_POWERGLITCH_EN_S 10 201 /** EFUSE_DIS_USB_SERIAL_JTAG : RO; bitpos: [11]; default: 0; 202 * Represents whether USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled. 203 */ 204 #define EFUSE_DIS_USB_SERIAL_JTAG (BIT(11)) 205 #define EFUSE_DIS_USB_SERIAL_JTAG_M (EFUSE_DIS_USB_SERIAL_JTAG_V << EFUSE_DIS_USB_SERIAL_JTAG_S) 206 #define EFUSE_DIS_USB_SERIAL_JTAG_V 0x00000001U 207 #define EFUSE_DIS_USB_SERIAL_JTAG_S 11 208 /** EFUSE_DIS_FORCE_DOWNLOAD : RO; bitpos: [12]; default: 0; 209 * Represents whether the function that forces chip into download mode is disabled or 210 * enabled. 1: disabled. 0: enabled. 211 */ 212 #define EFUSE_DIS_FORCE_DOWNLOAD (BIT(12)) 213 #define EFUSE_DIS_FORCE_DOWNLOAD_M (EFUSE_DIS_FORCE_DOWNLOAD_V << EFUSE_DIS_FORCE_DOWNLOAD_S) 214 #define EFUSE_DIS_FORCE_DOWNLOAD_V 0x00000001U 215 #define EFUSE_DIS_FORCE_DOWNLOAD_S 12 216 /** EFUSE_SPI_DOWNLOAD_MSPI_DIS : RO; bitpos: [13]; default: 0; 217 * Represents whether SPI0 controller during boot_mode_download is disabled or 218 * enabled. 1: disabled. 0: enabled. 219 */ 220 #define EFUSE_SPI_DOWNLOAD_MSPI_DIS (BIT(13)) 221 #define EFUSE_SPI_DOWNLOAD_MSPI_DIS_M (EFUSE_SPI_DOWNLOAD_MSPI_DIS_V << EFUSE_SPI_DOWNLOAD_MSPI_DIS_S) 222 #define EFUSE_SPI_DOWNLOAD_MSPI_DIS_V 0x00000001U 223 #define EFUSE_SPI_DOWNLOAD_MSPI_DIS_S 13 224 /** EFUSE_DIS_TWAI : RO; bitpos: [14]; default: 0; 225 * Represents whether TWAI function is disabled or enabled. 1: disabled. 0: enabled. 226 */ 227 #define EFUSE_DIS_TWAI (BIT(14)) 228 #define EFUSE_DIS_TWAI_M (EFUSE_DIS_TWAI_V << EFUSE_DIS_TWAI_S) 229 #define EFUSE_DIS_TWAI_V 0x00000001U 230 #define EFUSE_DIS_TWAI_S 14 231 /** EFUSE_JTAG_SEL_ENABLE : RO; bitpos: [15]; default: 0; 232 * Set this bit to enable selection between usb_to_jtag and pad_to_jtag through 233 * strapping gpio25 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 234 */ 235 #define EFUSE_JTAG_SEL_ENABLE (BIT(15)) 236 #define EFUSE_JTAG_SEL_ENABLE_M (EFUSE_JTAG_SEL_ENABLE_V << EFUSE_JTAG_SEL_ENABLE_S) 237 #define EFUSE_JTAG_SEL_ENABLE_V 0x00000001U 238 #define EFUSE_JTAG_SEL_ENABLE_S 15 239 /** EFUSE_SOFT_DIS_JTAG : RO; bitpos: [18:16]; default: 0; 240 * Represents whether JTAG is disabled in soft way. Odd number: disabled. Even number: 241 * enabled. 242 */ 243 #define EFUSE_SOFT_DIS_JTAG 0x00000007U 244 #define EFUSE_SOFT_DIS_JTAG_M (EFUSE_SOFT_DIS_JTAG_V << EFUSE_SOFT_DIS_JTAG_S) 245 #define EFUSE_SOFT_DIS_JTAG_V 0x00000007U 246 #define EFUSE_SOFT_DIS_JTAG_S 16 247 /** EFUSE_DIS_PAD_JTAG : RO; bitpos: [19]; default: 0; 248 * Represents whether JTAG is disabled in the hard way(permanently). 1: disabled. 0: 249 * enabled. 250 */ 251 #define EFUSE_DIS_PAD_JTAG (BIT(19)) 252 #define EFUSE_DIS_PAD_JTAG_M (EFUSE_DIS_PAD_JTAG_V << EFUSE_DIS_PAD_JTAG_S) 253 #define EFUSE_DIS_PAD_JTAG_V 0x00000001U 254 #define EFUSE_DIS_PAD_JTAG_S 19 255 /** EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT : RO; bitpos: [20]; default: 0; 256 * Represents whether flash encrypt function is disabled or enabled(except in SPI boot 257 * mode). 1: disabled. 0: enabled. 258 */ 259 #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT (BIT(20)) 260 #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_M (EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V << EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S) 261 #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V 0x00000001U 262 #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S 20 263 /** EFUSE_USB_DREFH : RO; bitpos: [22:21]; default: 0; 264 * Represents the single-end input threhold vrefh, 1.76 V to 2 V with step of 80 mV. 265 */ 266 #define EFUSE_USB_DREFH 0x00000003U 267 #define EFUSE_USB_DREFH_M (EFUSE_USB_DREFH_V << EFUSE_USB_DREFH_S) 268 #define EFUSE_USB_DREFH_V 0x00000003U 269 #define EFUSE_USB_DREFH_S 21 270 /** EFUSE_USB_DREFL : RO; bitpos: [24:23]; default: 0; 271 * Represents the single-end input threhold vrefl, 1.76 V to 2 V with step of 80 mV. 272 */ 273 #define EFUSE_USB_DREFL 0x00000003U 274 #define EFUSE_USB_DREFL_M (EFUSE_USB_DREFL_V << EFUSE_USB_DREFL_S) 275 #define EFUSE_USB_DREFL_V 0x00000003U 276 #define EFUSE_USB_DREFL_S 23 277 /** EFUSE_USB_EXCHG_PINS : RO; bitpos: [25]; default: 0; 278 * Represents whether the D+ and D- pins is exchanged. 1: exchanged. 0: not exchanged. 279 */ 280 #define EFUSE_USB_EXCHG_PINS (BIT(25)) 281 #define EFUSE_USB_EXCHG_PINS_M (EFUSE_USB_EXCHG_PINS_V << EFUSE_USB_EXCHG_PINS_S) 282 #define EFUSE_USB_EXCHG_PINS_V 0x00000001U 283 #define EFUSE_USB_EXCHG_PINS_S 25 284 /** EFUSE_VDD_SPI_AS_GPIO : RO; bitpos: [26]; default: 0; 285 * Represents whether vdd spi pin is functioned as gpio. 1: functioned. 0: not 286 * functioned. 287 */ 288 #define EFUSE_VDD_SPI_AS_GPIO (BIT(26)) 289 #define EFUSE_VDD_SPI_AS_GPIO_M (EFUSE_VDD_SPI_AS_GPIO_V << EFUSE_VDD_SPI_AS_GPIO_S) 290 #define EFUSE_VDD_SPI_AS_GPIO_V 0x00000001U 291 #define EFUSE_VDD_SPI_AS_GPIO_S 26 292 /** EFUSE_ECDSA_CURVE_MODE : R; bitpos: [28:27]; default: 0; 293 * Configures the curve of ECDSA calculation: 0: only enable P256. 1: only enable 294 * P192. 2: both enable P256 and P192. 3: only enable P256 295 */ 296 #define EFUSE_ECDSA_CURVE_MODE 0x00000003U 297 #define EFUSE_ECDSA_CURVE_MODE_M (EFUSE_ECDSA_CURVE_MODE_V << EFUSE_ECDSA_CURVE_MODE_S) 298 #define EFUSE_ECDSA_CURVE_MODE_V 0x00000003U 299 #define EFUSE_ECDSA_CURVE_MODE_S 27 300 /** EFUSE_ECC_FORCE_CONST_TIME : R; bitpos: [29]; default: 0; 301 * Set this bit to permanently turn on ECC const-time mode 302 */ 303 #define EFUSE_ECC_FORCE_CONST_TIME (BIT(29)) 304 #define EFUSE_ECC_FORCE_CONST_TIME_M (EFUSE_ECC_FORCE_CONST_TIME_V << EFUSE_ECC_FORCE_CONST_TIME_S) 305 #define EFUSE_ECC_FORCE_CONST_TIME_V 0x00000001U 306 #define EFUSE_ECC_FORCE_CONST_TIME_S 29 307 /** EFUSE_XTS_DPA_PSEUDO_LEVEL : R; bitpos: [31:30]; default: 0; 308 * Set this bit to control the xts pseudo-round anti-dpa attack function: 0: 309 * controlled by register. 1-3: the higher the value is, the more pseudo-rounds are 310 * inserted to the xts-aes calculation 311 */ 312 #define EFUSE_XTS_DPA_PSEUDO_LEVEL 0x00000003U 313 #define EFUSE_XTS_DPA_PSEUDO_LEVEL_M (EFUSE_XTS_DPA_PSEUDO_LEVEL_V << EFUSE_XTS_DPA_PSEUDO_LEVEL_S) 314 #define EFUSE_XTS_DPA_PSEUDO_LEVEL_V 0x00000003U 315 #define EFUSE_XTS_DPA_PSEUDO_LEVEL_S 30 316 317 /** EFUSE_RD_REPEAT_DATA1_REG register 318 * BLOCK0 data register 2. 319 */ 320 #define EFUSE_RD_REPEAT_DATA1_REG (DR_REG_EFUSE_BASE + 0x34) 321 /** EFUSE_RPT4_RESERVED1_1 : RO; bitpos: [15:0]; default: 0; 322 * Reserved. 323 */ 324 #define EFUSE_RPT4_RESERVED1_1 0x0000FFFFU 325 #define EFUSE_RPT4_RESERVED1_1_M (EFUSE_RPT4_RESERVED1_1_V << EFUSE_RPT4_RESERVED1_1_S) 326 #define EFUSE_RPT4_RESERVED1_1_V 0x0000FFFFU 327 #define EFUSE_RPT4_RESERVED1_1_S 0 328 /** EFUSE_WDT_DELAY_SEL : RO; bitpos: [17:16]; default: 0; 329 * Represents whether RTC watchdog timeout threshold is selected at startup. 1: 330 * selected. 0: not selected. 331 */ 332 #define EFUSE_WDT_DELAY_SEL 0x00000003U 333 #define EFUSE_WDT_DELAY_SEL_M (EFUSE_WDT_DELAY_SEL_V << EFUSE_WDT_DELAY_SEL_S) 334 #define EFUSE_WDT_DELAY_SEL_V 0x00000003U 335 #define EFUSE_WDT_DELAY_SEL_S 16 336 /** EFUSE_SPI_BOOT_CRYPT_CNT : RO; bitpos: [20:18]; default: 0; 337 * Represents whether SPI boot encrypt/decrypt is disabled or enabled. Odd number of 338 * 1: enabled. Even number of 1: disabled. 339 */ 340 #define EFUSE_SPI_BOOT_CRYPT_CNT 0x00000007U 341 #define EFUSE_SPI_BOOT_CRYPT_CNT_M (EFUSE_SPI_BOOT_CRYPT_CNT_V << EFUSE_SPI_BOOT_CRYPT_CNT_S) 342 #define EFUSE_SPI_BOOT_CRYPT_CNT_V 0x00000007U 343 #define EFUSE_SPI_BOOT_CRYPT_CNT_S 18 344 /** EFUSE_SECURE_BOOT_KEY_REVOKE0 : RO; bitpos: [21]; default: 0; 345 * Represents whether revoking first secure boot key is enabled or disabled. 1: 346 * enabled. 0: disabled. 347 */ 348 #define EFUSE_SECURE_BOOT_KEY_REVOKE0 (BIT(21)) 349 #define EFUSE_SECURE_BOOT_KEY_REVOKE0_M (EFUSE_SECURE_BOOT_KEY_REVOKE0_V << EFUSE_SECURE_BOOT_KEY_REVOKE0_S) 350 #define EFUSE_SECURE_BOOT_KEY_REVOKE0_V 0x00000001U 351 #define EFUSE_SECURE_BOOT_KEY_REVOKE0_S 21 352 /** EFUSE_SECURE_BOOT_KEY_REVOKE1 : RO; bitpos: [22]; default: 0; 353 * Represents whether revoking second secure boot key is enabled or disabled. 1: 354 * enabled. 0: disabled. 355 */ 356 #define EFUSE_SECURE_BOOT_KEY_REVOKE1 (BIT(22)) 357 #define EFUSE_SECURE_BOOT_KEY_REVOKE1_M (EFUSE_SECURE_BOOT_KEY_REVOKE1_V << EFUSE_SECURE_BOOT_KEY_REVOKE1_S) 358 #define EFUSE_SECURE_BOOT_KEY_REVOKE1_V 0x00000001U 359 #define EFUSE_SECURE_BOOT_KEY_REVOKE1_S 22 360 /** EFUSE_SECURE_BOOT_KEY_REVOKE2 : RO; bitpos: [23]; default: 0; 361 * Represents whether revoking third secure boot key is enabled or disabled. 1: 362 * enabled. 0: disabled. 363 */ 364 #define EFUSE_SECURE_BOOT_KEY_REVOKE2 (BIT(23)) 365 #define EFUSE_SECURE_BOOT_KEY_REVOKE2_M (EFUSE_SECURE_BOOT_KEY_REVOKE2_V << EFUSE_SECURE_BOOT_KEY_REVOKE2_S) 366 #define EFUSE_SECURE_BOOT_KEY_REVOKE2_V 0x00000001U 367 #define EFUSE_SECURE_BOOT_KEY_REVOKE2_S 23 368 /** EFUSE_KEY_PURPOSE_0 : RO; bitpos: [27:24]; default: 0; 369 * Represents the purpose of Key0. 370 */ 371 #define EFUSE_KEY_PURPOSE_0 0x0000000FU 372 #define EFUSE_KEY_PURPOSE_0_M (EFUSE_KEY_PURPOSE_0_V << EFUSE_KEY_PURPOSE_0_S) 373 #define EFUSE_KEY_PURPOSE_0_V 0x0000000FU 374 #define EFUSE_KEY_PURPOSE_0_S 24 375 /** EFUSE_KEY_PURPOSE_1 : RO; bitpos: [31:28]; default: 0; 376 * Represents the purpose of Key1. 377 */ 378 #define EFUSE_KEY_PURPOSE_1 0x0000000FU 379 #define EFUSE_KEY_PURPOSE_1_M (EFUSE_KEY_PURPOSE_1_V << EFUSE_KEY_PURPOSE_1_S) 380 #define EFUSE_KEY_PURPOSE_1_V 0x0000000FU 381 #define EFUSE_KEY_PURPOSE_1_S 28 382 383 /** EFUSE_RD_REPEAT_DATA2_REG register 384 * BLOCK0 data register 3. 385 */ 386 #define EFUSE_RD_REPEAT_DATA2_REG (DR_REG_EFUSE_BASE + 0x38) 387 /** EFUSE_KEY_PURPOSE_2 : RO; bitpos: [3:0]; default: 0; 388 * Represents the purpose of Key2. 389 */ 390 #define EFUSE_KEY_PURPOSE_2 0x0000000FU 391 #define EFUSE_KEY_PURPOSE_2_M (EFUSE_KEY_PURPOSE_2_V << EFUSE_KEY_PURPOSE_2_S) 392 #define EFUSE_KEY_PURPOSE_2_V 0x0000000FU 393 #define EFUSE_KEY_PURPOSE_2_S 0 394 /** EFUSE_KEY_PURPOSE_3 : RO; bitpos: [7:4]; default: 0; 395 * Represents the purpose of Key3. 396 */ 397 #define EFUSE_KEY_PURPOSE_3 0x0000000FU 398 #define EFUSE_KEY_PURPOSE_3_M (EFUSE_KEY_PURPOSE_3_V << EFUSE_KEY_PURPOSE_3_S) 399 #define EFUSE_KEY_PURPOSE_3_V 0x0000000FU 400 #define EFUSE_KEY_PURPOSE_3_S 4 401 /** EFUSE_KEY_PURPOSE_4 : RO; bitpos: [11:8]; default: 0; 402 * Represents the purpose of Key4. 403 */ 404 #define EFUSE_KEY_PURPOSE_4 0x0000000FU 405 #define EFUSE_KEY_PURPOSE_4_M (EFUSE_KEY_PURPOSE_4_V << EFUSE_KEY_PURPOSE_4_S) 406 #define EFUSE_KEY_PURPOSE_4_V 0x0000000FU 407 #define EFUSE_KEY_PURPOSE_4_S 8 408 /** EFUSE_KEY_PURPOSE_5 : RO; bitpos: [15:12]; default: 0; 409 * Represents the purpose of Key5. 410 */ 411 #define EFUSE_KEY_PURPOSE_5 0x0000000FU 412 #define EFUSE_KEY_PURPOSE_5_M (EFUSE_KEY_PURPOSE_5_V << EFUSE_KEY_PURPOSE_5_S) 413 #define EFUSE_KEY_PURPOSE_5_V 0x0000000FU 414 #define EFUSE_KEY_PURPOSE_5_S 12 415 /** EFUSE_SEC_DPA_LEVEL : RO; bitpos: [17:16]; default: 0; 416 * Represents the spa secure level by configuring the clock random divide mode. 417 */ 418 #define EFUSE_SEC_DPA_LEVEL 0x00000003U 419 #define EFUSE_SEC_DPA_LEVEL_M (EFUSE_SEC_DPA_LEVEL_V << EFUSE_SEC_DPA_LEVEL_S) 420 #define EFUSE_SEC_DPA_LEVEL_V 0x00000003U 421 #define EFUSE_SEC_DPA_LEVEL_S 16 422 /** EFUSE_RESERVE_0_114 : RO; bitpos: [18]; default: 1; 423 * Reserved 424 */ 425 #define EFUSE_RESERVE_0_114 (BIT(18)) 426 #define EFUSE_RESERVE_0_114_M (EFUSE_RESERVE_0_114_V << EFUSE_RESERVE_0_114_S) 427 #define EFUSE_RESERVE_0_114_V 0x00000001U 428 #define EFUSE_RESERVE_0_114_S 18 429 /** EFUSE_CRYPT_DPA_ENABLE : RO; bitpos: [19]; default: 1; 430 * Represents whether anti-dpa attack is enabled. 1:enabled. 0: disabled. 431 */ 432 #define EFUSE_CRYPT_DPA_ENABLE (BIT(19)) 433 #define EFUSE_CRYPT_DPA_ENABLE_M (EFUSE_CRYPT_DPA_ENABLE_V << EFUSE_CRYPT_DPA_ENABLE_S) 434 #define EFUSE_CRYPT_DPA_ENABLE_V 0x00000001U 435 #define EFUSE_CRYPT_DPA_ENABLE_S 19 436 /** EFUSE_SECURE_BOOT_EN : RO; bitpos: [20]; default: 0; 437 * Represents whether secure boot is enabled or disabled. 1: enabled. 0: disabled. 438 */ 439 #define EFUSE_SECURE_BOOT_EN (BIT(20)) 440 #define EFUSE_SECURE_BOOT_EN_M (EFUSE_SECURE_BOOT_EN_V << EFUSE_SECURE_BOOT_EN_S) 441 #define EFUSE_SECURE_BOOT_EN_V 0x00000001U 442 #define EFUSE_SECURE_BOOT_EN_S 20 443 /** EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE : RO; bitpos: [21]; default: 0; 444 * Represents whether revoking aggressive secure boot is enabled or disabled. 1: 445 * enabled. 0: disabled. 446 */ 447 #define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE (BIT(21)) 448 #define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_M (EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V << EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S) 449 #define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V 0x00000001U 450 #define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S 21 451 /** EFUSE_POWERGLITCH_EN1 : R; bitpos: [26:22]; default: 0; 452 * Set these bits to enable power glitch function when chip power on 453 */ 454 #define EFUSE_POWERGLITCH_EN1 0x0000001FU 455 #define EFUSE_POWERGLITCH_EN1_M (EFUSE_POWERGLITCH_EN1_V << EFUSE_POWERGLITCH_EN1_S) 456 #define EFUSE_POWERGLITCH_EN1_V 0x0000001FU 457 #define EFUSE_POWERGLITCH_EN1_S 22 458 /** EFUSE_RESERVED_0_123 : R; bitpos: [27]; default: 0; 459 * reserved 460 */ 461 #define EFUSE_RESERVED_0_123 (BIT(27)) 462 #define EFUSE_RESERVED_0_123_M (EFUSE_RESERVED_0_123_V << EFUSE_RESERVED_0_123_S) 463 #define EFUSE_RESERVED_0_123_V 0x00000001U 464 #define EFUSE_RESERVED_0_123_S 27 465 /** EFUSE_FLASH_TPUW : RO; bitpos: [31:28]; default: 0; 466 * Represents the flash waiting time after power-up, in unit of ms. When the value 467 * less than 15, the waiting time is the programmed value. Otherwise, the waiting time 468 * is 2 times the programmed value. 469 */ 470 #define EFUSE_FLASH_TPUW 0x0000000FU 471 #define EFUSE_FLASH_TPUW_M (EFUSE_FLASH_TPUW_V << EFUSE_FLASH_TPUW_S) 472 #define EFUSE_FLASH_TPUW_V 0x0000000FU 473 #define EFUSE_FLASH_TPUW_S 28 474 475 /** EFUSE_RD_REPEAT_DATA3_REG register 476 * BLOCK0 data register 4. 477 */ 478 #define EFUSE_RD_REPEAT_DATA3_REG (DR_REG_EFUSE_BASE + 0x3c) 479 /** EFUSE_DIS_DOWNLOAD_MODE : RO; bitpos: [0]; default: 0; 480 * Represents whether Download mode is disabled or enabled. 1: disabled. 0: enabled. 481 */ 482 #define EFUSE_DIS_DOWNLOAD_MODE (BIT(0)) 483 #define EFUSE_DIS_DOWNLOAD_MODE_M (EFUSE_DIS_DOWNLOAD_MODE_V << EFUSE_DIS_DOWNLOAD_MODE_S) 484 #define EFUSE_DIS_DOWNLOAD_MODE_V 0x00000001U 485 #define EFUSE_DIS_DOWNLOAD_MODE_S 0 486 /** EFUSE_DIS_DIRECT_BOOT : RO; bitpos: [1]; default: 0; 487 * Represents whether direct boot mode is disabled or enabled. 1: disabled. 0: enabled. 488 */ 489 #define EFUSE_DIS_DIRECT_BOOT (BIT(1)) 490 #define EFUSE_DIS_DIRECT_BOOT_M (EFUSE_DIS_DIRECT_BOOT_V << EFUSE_DIS_DIRECT_BOOT_S) 491 #define EFUSE_DIS_DIRECT_BOOT_V 0x00000001U 492 #define EFUSE_DIS_DIRECT_BOOT_S 1 493 /** EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT : RO; bitpos: [2]; default: 0; 494 * Set this bit to disable USB-Serial-JTAG print during rom boot. 495 */ 496 #define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT (BIT(2)) 497 #define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_M (EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_V << EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_S) 498 #define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_V 0x00000001U 499 #define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_S 2 500 /** EFUSE_RPT4_RESERVED3_5 : RO; bitpos: [3]; default: 0; 501 * Reserved. 502 */ 503 #define EFUSE_RPT4_RESERVED3_5 (BIT(3)) 504 #define EFUSE_RPT4_RESERVED3_5_M (EFUSE_RPT4_RESERVED3_5_V << EFUSE_RPT4_RESERVED3_5_S) 505 #define EFUSE_RPT4_RESERVED3_5_V 0x00000001U 506 #define EFUSE_RPT4_RESERVED3_5_S 3 507 /** EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE : RO; bitpos: [4]; default: 0; 508 * Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1: 509 * disabled. 0: enabled. 510 */ 511 #define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE (BIT(4)) 512 #define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_M (EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_V << EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_S) 513 #define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_V 0x00000001U 514 #define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_S 4 515 /** EFUSE_ENABLE_SECURITY_DOWNLOAD : RO; bitpos: [5]; default: 0; 516 * Represents whether security download is enabled or disabled. 1: enabled. 0: 517 * disabled. 518 */ 519 #define EFUSE_ENABLE_SECURITY_DOWNLOAD (BIT(5)) 520 #define EFUSE_ENABLE_SECURITY_DOWNLOAD_M (EFUSE_ENABLE_SECURITY_DOWNLOAD_V << EFUSE_ENABLE_SECURITY_DOWNLOAD_S) 521 #define EFUSE_ENABLE_SECURITY_DOWNLOAD_V 0x00000001U 522 #define EFUSE_ENABLE_SECURITY_DOWNLOAD_S 5 523 /** EFUSE_UART_PRINT_CONTROL : RO; bitpos: [7:6]; default: 0; 524 * Represents the type of UART printing. 00: force enable printing. 01: enable 525 * printing when GPIO8 is reset at low level. 10: enable printing when GPIO8 is reset 526 * at high level. 11: force disable printing. 527 */ 528 #define EFUSE_UART_PRINT_CONTROL 0x00000003U 529 #define EFUSE_UART_PRINT_CONTROL_M (EFUSE_UART_PRINT_CONTROL_V << EFUSE_UART_PRINT_CONTROL_S) 530 #define EFUSE_UART_PRINT_CONTROL_V 0x00000003U 531 #define EFUSE_UART_PRINT_CONTROL_S 6 532 /** EFUSE_FORCE_SEND_RESUME : RO; bitpos: [8]; default: 0; 533 * Represents whether ROM code is forced to send a resume command during SPI boot. 1: 534 * forced. 0:not forced. 535 */ 536 #define EFUSE_FORCE_SEND_RESUME (BIT(8)) 537 #define EFUSE_FORCE_SEND_RESUME_M (EFUSE_FORCE_SEND_RESUME_V << EFUSE_FORCE_SEND_RESUME_S) 538 #define EFUSE_FORCE_SEND_RESUME_V 0x00000001U 539 #define EFUSE_FORCE_SEND_RESUME_S 8 540 /** EFUSE_SECURE_VERSION : RO; bitpos: [24:9]; default: 0; 541 * Represents the version used by ESP-IDF anti-rollback feature. 542 */ 543 #define EFUSE_SECURE_VERSION 0x0000FFFFU 544 #define EFUSE_SECURE_VERSION_M (EFUSE_SECURE_VERSION_V << EFUSE_SECURE_VERSION_S) 545 #define EFUSE_SECURE_VERSION_V 0x0000FFFFU 546 #define EFUSE_SECURE_VERSION_S 9 547 /** EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE : RO; bitpos: [25]; default: 0; 548 * Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is 549 * enabled. 1: disabled. 0: enabled. 550 */ 551 #define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE (BIT(25)) 552 #define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_M (EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_V << EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_S) 553 #define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_V 0x00000001U 554 #define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_S 25 555 /** EFUSE_HYS_EN_PAD0 : RO; bitpos: [31:26]; default: 0; 556 * Set bits to enable hysteresis function of PAD0~5 557 */ 558 #define EFUSE_HYS_EN_PAD0 0x0000003FU 559 #define EFUSE_HYS_EN_PAD0_M (EFUSE_HYS_EN_PAD0_V << EFUSE_HYS_EN_PAD0_S) 560 #define EFUSE_HYS_EN_PAD0_V 0x0000003FU 561 #define EFUSE_HYS_EN_PAD0_S 26 562 563 /** EFUSE_RD_REPEAT_DATA4_REG register 564 * BLOCK0 data register 5. 565 */ 566 #define EFUSE_RD_REPEAT_DATA4_REG (DR_REG_EFUSE_BASE + 0x40) 567 /** EFUSE_HYS_EN_PAD1 : RO; bitpos: [21:0]; default: 0; 568 * Set bits to enable hysteresis function of PAD6~27 569 */ 570 #define EFUSE_HYS_EN_PAD1 0x003FFFFFU 571 #define EFUSE_HYS_EN_PAD1_M (EFUSE_HYS_EN_PAD1_V << EFUSE_HYS_EN_PAD1_S) 572 #define EFUSE_HYS_EN_PAD1_V 0x003FFFFFU 573 #define EFUSE_HYS_EN_PAD1_S 0 574 /** EFUSE_RPT4_RESERVED4_1 : RO; bitpos: [23:22]; default: 0; 575 * Reserved. 576 */ 577 #define EFUSE_RPT4_RESERVED4_1 0x00000003U 578 #define EFUSE_RPT4_RESERVED4_1_M (EFUSE_RPT4_RESERVED4_1_V << EFUSE_RPT4_RESERVED4_1_S) 579 #define EFUSE_RPT4_RESERVED4_1_V 0x00000003U 580 #define EFUSE_RPT4_RESERVED4_1_S 22 581 /** EFUSE_RPT4_RESERVED4_0 : RO; bitpos: [31:24]; default: 0; 582 * Reserved. 583 */ 584 #define EFUSE_RPT4_RESERVED4_0 0x000000FFU 585 #define EFUSE_RPT4_RESERVED4_0_M (EFUSE_RPT4_RESERVED4_0_V << EFUSE_RPT4_RESERVED4_0_S) 586 #define EFUSE_RPT4_RESERVED4_0_V 0x000000FFU 587 #define EFUSE_RPT4_RESERVED4_0_S 24 588 589 /** EFUSE_RD_MAC_SYS_0_REG register 590 * BLOCK1 data register $n. 591 */ 592 #define EFUSE_RD_MAC_SYS_0_REG (DR_REG_EFUSE_BASE + 0x44) 593 /** EFUSE_MAC_0 : RO; bitpos: [31:0]; default: 0; 594 * Stores the low 32 bits of MAC address. 595 */ 596 #define EFUSE_MAC_0 0xFFFFFFFFU 597 #define EFUSE_MAC_0_M (EFUSE_MAC_0_V << EFUSE_MAC_0_S) 598 #define EFUSE_MAC_0_V 0xFFFFFFFFU 599 #define EFUSE_MAC_0_S 0 600 601 /** EFUSE_RD_MAC_SYS_1_REG register 602 * BLOCK1 data register $n. 603 */ 604 #define EFUSE_RD_MAC_SYS_1_REG (DR_REG_EFUSE_BASE + 0x48) 605 /** EFUSE_MAC_1 : RO; bitpos: [15:0]; default: 0; 606 * Stores the high 16 bits of MAC address. 607 */ 608 #define EFUSE_MAC_1 0x0000FFFFU 609 #define EFUSE_MAC_1_M (EFUSE_MAC_1_V << EFUSE_MAC_1_S) 610 #define EFUSE_MAC_1_V 0x0000FFFFU 611 #define EFUSE_MAC_1_S 0 612 /** EFUSE_MAC_EXT : RO; bitpos: [31:16]; default: 0; 613 * Stores the extended bits of MAC address. 614 */ 615 #define EFUSE_MAC_EXT 0x0000FFFFU 616 #define EFUSE_MAC_EXT_M (EFUSE_MAC_EXT_V << EFUSE_MAC_EXT_S) 617 #define EFUSE_MAC_EXT_V 0x0000FFFFU 618 #define EFUSE_MAC_EXT_S 16 619 620 /** EFUSE_RD_MAC_SYS_2_REG register 621 * BLOCK1 data register $n. 622 */ 623 #define EFUSE_RD_MAC_SYS_2_REG (DR_REG_EFUSE_BASE + 0x4c) 624 /** EFUSE_RXIQ_VERSION : RO; bitpos: [2:0]; default: 0; 625 * Stores RF Calibration data. RXIQ version. 626 */ 627 #define EFUSE_RXIQ_VERSION 0x00000007U 628 #define EFUSE_RXIQ_VERSION_M (EFUSE_RXIQ_VERSION_V << EFUSE_RXIQ_VERSION_S) 629 #define EFUSE_RXIQ_VERSION_V 0x00000007U 630 #define EFUSE_RXIQ_VERSION_S 0 631 /** EFUSE_RXIQ_0 : RO; bitpos: [9:3]; default: 0; 632 * Stores RF Calibration data. RXIQ data 0. 633 */ 634 #define EFUSE_RXIQ_0 0x0000007FU 635 #define EFUSE_RXIQ_0_M (EFUSE_RXIQ_0_V << EFUSE_RXIQ_0_S) 636 #define EFUSE_RXIQ_0_V 0x0000007FU 637 #define EFUSE_RXIQ_0_S 3 638 /** EFUSE_RXIQ_1 : RO; bitpos: [16:10]; default: 0; 639 * Stores RF Calibration data. RXIQ data 1. 640 */ 641 #define EFUSE_RXIQ_1 0x0000007FU 642 #define EFUSE_RXIQ_1_M (EFUSE_RXIQ_1_V << EFUSE_RXIQ_1_S) 643 #define EFUSE_RXIQ_1_V 0x0000007FU 644 #define EFUSE_RXIQ_1_S 10 645 /** EFUSE_ACTIVE_HP_DBIAS : RO; bitpos: [21:17]; default: 0; 646 * Stores the PMU active hp dbias. 647 */ 648 #define EFUSE_ACTIVE_HP_DBIAS 0x0000001FU 649 #define EFUSE_ACTIVE_HP_DBIAS_M (EFUSE_ACTIVE_HP_DBIAS_V << EFUSE_ACTIVE_HP_DBIAS_S) 650 #define EFUSE_ACTIVE_HP_DBIAS_V 0x0000001FU 651 #define EFUSE_ACTIVE_HP_DBIAS_S 17 652 /** EFUSE_ACTIVE_LP_DBIAS : RO; bitpos: [26:22]; default: 0; 653 * Stores the PMU active lp dbias. 654 */ 655 #define EFUSE_ACTIVE_LP_DBIAS 0x0000001FU 656 #define EFUSE_ACTIVE_LP_DBIAS_M (EFUSE_ACTIVE_LP_DBIAS_V << EFUSE_ACTIVE_LP_DBIAS_S) 657 #define EFUSE_ACTIVE_LP_DBIAS_V 0x0000001FU 658 #define EFUSE_ACTIVE_LP_DBIAS_S 22 659 /** EFUSE_DSLP_DBIAS : RO; bitpos: [30:27]; default: 0; 660 * Stores the PMU sleep dbias. 661 */ 662 #define EFUSE_DSLP_DBIAS 0x0000000FU 663 #define EFUSE_DSLP_DBIAS_M (EFUSE_DSLP_DBIAS_V << EFUSE_DSLP_DBIAS_S) 664 #define EFUSE_DSLP_DBIAS_V 0x0000000FU 665 #define EFUSE_DSLP_DBIAS_S 27 666 /** EFUSE_DBIAS_VOL_GAP_VALUE1 : RO; bitpos: [31]; default: 0; 667 * Stores the low 1 bit of dbias_vol_gap. 668 */ 669 #define EFUSE_DBIAS_VOL_GAP_VALUE1 (BIT(31)) 670 #define EFUSE_DBIAS_VOL_GAP_VALUE1_M (EFUSE_DBIAS_VOL_GAP_VALUE1_V << EFUSE_DBIAS_VOL_GAP_VALUE1_S) 671 #define EFUSE_DBIAS_VOL_GAP_VALUE1_V 0x00000001U 672 #define EFUSE_DBIAS_VOL_GAP_VALUE1_S 31 673 674 /** EFUSE_RD_MAC_SYS_3_REG register 675 * BLOCK1 data register $n. 676 */ 677 #define EFUSE_RD_MAC_SYS_3_REG (DR_REG_EFUSE_BASE + 0x50) 678 /** EFUSE_DBIAS_VOL_GAP_VALUE2 : RO; bitpos: [2:0]; default: 0; 679 * Stores the high 3 bits of dbias_vol_gap. 680 */ 681 #define EFUSE_DBIAS_VOL_GAP_VALUE2 0x00000007U 682 #define EFUSE_DBIAS_VOL_GAP_VALUE2_M (EFUSE_DBIAS_VOL_GAP_VALUE2_V << EFUSE_DBIAS_VOL_GAP_VALUE2_S) 683 #define EFUSE_DBIAS_VOL_GAP_VALUE2_V 0x00000007U 684 #define EFUSE_DBIAS_VOL_GAP_VALUE2_S 0 685 /** EFUSE_DBIAS_VOL_GAP_SIGN : RO; bitpos: [3]; default: 0; 686 * Stores the sign bit of dbias_vol_gap. 687 */ 688 #define EFUSE_DBIAS_VOL_GAP_SIGN (BIT(3)) 689 #define EFUSE_DBIAS_VOL_GAP_SIGN_M (EFUSE_DBIAS_VOL_GAP_SIGN_V << EFUSE_DBIAS_VOL_GAP_SIGN_S) 690 #define EFUSE_DBIAS_VOL_GAP_SIGN_V 0x00000001U 691 #define EFUSE_DBIAS_VOL_GAP_SIGN_S 3 692 /** EFUSE_MAC_RESERVED_2 : RO; bitpos: [17:4]; default: 0; 693 * Reserved. 694 */ 695 #define EFUSE_MAC_RESERVED_2 0x00003FFFU 696 #define EFUSE_MAC_RESERVED_2_M (EFUSE_MAC_RESERVED_2_V << EFUSE_MAC_RESERVED_2_S) 697 #define EFUSE_MAC_RESERVED_2_V 0x00003FFFU 698 #define EFUSE_MAC_RESERVED_2_S 4 699 /** EFUSE_WAFER_VERSION_MINOR : RO; bitpos: [20:18]; default: 0; 700 * Stores the wafer version minor. 701 */ 702 #define EFUSE_WAFER_VERSION_MINOR 0x00000007U 703 #define EFUSE_WAFER_VERSION_MINOR_M (EFUSE_WAFER_VERSION_MINOR_V << EFUSE_WAFER_VERSION_MINOR_S) 704 #define EFUSE_WAFER_VERSION_MINOR_V 0x00000007U 705 #define EFUSE_WAFER_VERSION_MINOR_S 18 706 /** EFUSE_WAFER_VERSION_MAJOR : RO; bitpos: [22:21]; default: 0; 707 * Stores the wafer version major. 708 */ 709 #define EFUSE_WAFER_VERSION_MAJOR 0x00000003U 710 #define EFUSE_WAFER_VERSION_MAJOR_M (EFUSE_WAFER_VERSION_MAJOR_V << EFUSE_WAFER_VERSION_MAJOR_S) 711 #define EFUSE_WAFER_VERSION_MAJOR_V 0x00000003U 712 #define EFUSE_WAFER_VERSION_MAJOR_S 21 713 /** EFUSE_DISABLE_WAFER_VERSION_MAJOR : RO; bitpos: [23]; default: 0; 714 * Disables check of wafer version major. 715 */ 716 #define EFUSE_DISABLE_WAFER_VERSION_MAJOR (BIT(23)) 717 #define EFUSE_DISABLE_WAFER_VERSION_MAJOR_M (EFUSE_DISABLE_WAFER_VERSION_MAJOR_V << EFUSE_DISABLE_WAFER_VERSION_MAJOR_S) 718 #define EFUSE_DISABLE_WAFER_VERSION_MAJOR_V 0x00000001U 719 #define EFUSE_DISABLE_WAFER_VERSION_MAJOR_S 23 720 /** EFUSE_FLASH_CAP : RO; bitpos: [26:24]; default: 0; 721 * Stores the flash cap. 722 */ 723 #define EFUSE_FLASH_CAP 0x00000007U 724 #define EFUSE_FLASH_CAP_M (EFUSE_FLASH_CAP_V << EFUSE_FLASH_CAP_S) 725 #define EFUSE_FLASH_CAP_V 0x00000007U 726 #define EFUSE_FLASH_CAP_S 24 727 /** EFUSE_FLASH_TEMP : RO; bitpos: [28:27]; default: 0; 728 * Stores the flash temp. 729 */ 730 #define EFUSE_FLASH_TEMP 0x00000003U 731 #define EFUSE_FLASH_TEMP_M (EFUSE_FLASH_TEMP_V << EFUSE_FLASH_TEMP_S) 732 #define EFUSE_FLASH_TEMP_V 0x00000003U 733 #define EFUSE_FLASH_TEMP_S 27 734 /** EFUSE_FLASH_VENDOR : RO; bitpos: [31:29]; default: 0; 735 * Stores the flash vendor. 736 */ 737 #define EFUSE_FLASH_VENDOR 0x00000007U 738 #define EFUSE_FLASH_VENDOR_M (EFUSE_FLASH_VENDOR_V << EFUSE_FLASH_VENDOR_S) 739 #define EFUSE_FLASH_VENDOR_V 0x00000007U 740 #define EFUSE_FLASH_VENDOR_S 29 741 742 /** EFUSE_RD_MAC_SYS_4_REG register 743 * BLOCK1 data register $n. 744 */ 745 #define EFUSE_RD_MAC_SYS_4_REG (DR_REG_EFUSE_BASE + 0x54) 746 /** EFUSE_PKG_VERSION : R; bitpos: [2:0]; default: 0; 747 * Package version 748 */ 749 #define EFUSE_PKG_VERSION 0x00000007U 750 #define EFUSE_PKG_VERSION_M (EFUSE_PKG_VERSION_V << EFUSE_PKG_VERSION_S) 751 #define EFUSE_PKG_VERSION_V 0x00000007U 752 #define EFUSE_PKG_VERSION_S 0 753 /** EFUSE_RESERVED_1_131 : R; bitpos: [31:3]; default: 0; 754 * reserved 755 */ 756 #define EFUSE_RESERVED_1_131 0x1FFFFFFFU 757 #define EFUSE_RESERVED_1_131_M (EFUSE_RESERVED_1_131_V << EFUSE_RESERVED_1_131_S) 758 #define EFUSE_RESERVED_1_131_V 0x1FFFFFFFU 759 #define EFUSE_RESERVED_1_131_S 3 760 761 /** EFUSE_RD_MAC_SYS_5_REG register 762 * BLOCK1 data register $n. 763 */ 764 #define EFUSE_RD_MAC_SYS_5_REG (DR_REG_EFUSE_BASE + 0x58) 765 /** EFUSE_SYS_DATA_PART0_2 : RO; bitpos: [31:0]; default: 0; 766 * Stores the second 32 bits of the zeroth part of system data. 767 */ 768 #define EFUSE_SYS_DATA_PART0_2 0xFFFFFFFFU 769 #define EFUSE_SYS_DATA_PART0_2_M (EFUSE_SYS_DATA_PART0_2_V << EFUSE_SYS_DATA_PART0_2_S) 770 #define EFUSE_SYS_DATA_PART0_2_V 0xFFFFFFFFU 771 #define EFUSE_SYS_DATA_PART0_2_S 0 772 773 /** EFUSE_RD_SYS_PART1_DATA0_REG register 774 * Register $n of BLOCK2 (system). 775 */ 776 #define EFUSE_RD_SYS_PART1_DATA0_REG (DR_REG_EFUSE_BASE + 0x5c) 777 /** EFUSE_OPTIONAL_UNIQUE_ID : R; bitpos: [31:0]; default: 0; 778 * Optional unique 128-bit ID 779 */ 780 #define EFUSE_OPTIONAL_UNIQUE_ID 0xFFFFFFFFU 781 #define EFUSE_OPTIONAL_UNIQUE_ID_M (EFUSE_OPTIONAL_UNIQUE_ID_V << EFUSE_OPTIONAL_UNIQUE_ID_S) 782 #define EFUSE_OPTIONAL_UNIQUE_ID_V 0xFFFFFFFFU 783 #define EFUSE_OPTIONAL_UNIQUE_ID_S 0 784 785 /** EFUSE_RD_SYS_PART1_DATA1_REG register 786 * Register $n of BLOCK2 (system). 787 */ 788 #define EFUSE_RD_SYS_PART1_DATA1_REG (DR_REG_EFUSE_BASE + 0x60) 789 /** EFUSE_OPTIONAL_UNIQUE_ID_1 : R; bitpos: [31:0]; default: 0; 790 * Optional unique 128-bit ID 791 */ 792 #define EFUSE_OPTIONAL_UNIQUE_ID_1 0xFFFFFFFFU 793 #define EFUSE_OPTIONAL_UNIQUE_ID_1_M (EFUSE_OPTIONAL_UNIQUE_ID_1_V << EFUSE_OPTIONAL_UNIQUE_ID_1_S) 794 #define EFUSE_OPTIONAL_UNIQUE_ID_1_V 0xFFFFFFFFU 795 #define EFUSE_OPTIONAL_UNIQUE_ID_1_S 0 796 797 /** EFUSE_RD_SYS_PART1_DATA2_REG register 798 * Register $n of BLOCK2 (system). 799 */ 800 #define EFUSE_RD_SYS_PART1_DATA2_REG (DR_REG_EFUSE_BASE + 0x64) 801 /** EFUSE_OPTIONAL_UNIQUE_ID_2 : R; bitpos: [31:0]; default: 0; 802 * Optional unique 128-bit ID 803 */ 804 #define EFUSE_OPTIONAL_UNIQUE_ID_2 0xFFFFFFFFU 805 #define EFUSE_OPTIONAL_UNIQUE_ID_2_M (EFUSE_OPTIONAL_UNIQUE_ID_2_V << EFUSE_OPTIONAL_UNIQUE_ID_2_S) 806 #define EFUSE_OPTIONAL_UNIQUE_ID_2_V 0xFFFFFFFFU 807 #define EFUSE_OPTIONAL_UNIQUE_ID_2_S 0 808 809 /** EFUSE_RD_SYS_PART1_DATA3_REG register 810 * Register $n of BLOCK2 (system). 811 */ 812 #define EFUSE_RD_SYS_PART1_DATA3_REG (DR_REG_EFUSE_BASE + 0x68) 813 /** EFUSE_OPTIONAL_UNIQUE_ID_3 : R; bitpos: [31:0]; default: 0; 814 * Optional unique 128-bit ID 815 */ 816 #define EFUSE_OPTIONAL_UNIQUE_ID_3 0xFFFFFFFFU 817 #define EFUSE_OPTIONAL_UNIQUE_ID_3_M (EFUSE_OPTIONAL_UNIQUE_ID_3_V << EFUSE_OPTIONAL_UNIQUE_ID_3_S) 818 #define EFUSE_OPTIONAL_UNIQUE_ID_3_V 0xFFFFFFFFU 819 #define EFUSE_OPTIONAL_UNIQUE_ID_3_S 0 820 821 /** EFUSE_RD_SYS_PART1_DATA4_REG register 822 * Register $n of BLOCK2 (system). 823 */ 824 #define EFUSE_RD_SYS_PART1_DATA4_REG (DR_REG_EFUSE_BASE + 0x6c) 825 /** EFUSE_RESERVED_2_128 : R; bitpos: [1:0]; default: 0; 826 * reserved 827 */ 828 #define EFUSE_RESERVED_2_128 0x00000003U 829 #define EFUSE_RESERVED_2_128_M (EFUSE_RESERVED_2_128_V << EFUSE_RESERVED_2_128_S) 830 #define EFUSE_RESERVED_2_128_V 0x00000003U 831 #define EFUSE_RESERVED_2_128_S 0 832 /** EFUSE_BLK_VERSION_MINOR : R; bitpos: [4:2]; default: 0; 833 * BLK_VERSION_MINOR of BLOCK2. 1: RF Calibration data in BLOCK1 834 */ 835 #define EFUSE_BLK_VERSION_MINOR 0x00000007U 836 #define EFUSE_BLK_VERSION_MINOR_M (EFUSE_BLK_VERSION_MINOR_V << EFUSE_BLK_VERSION_MINOR_S) 837 #define EFUSE_BLK_VERSION_MINOR_V 0x00000007U 838 #define EFUSE_BLK_VERSION_MINOR_S 2 839 /** EFUSE_BLK_VERSION_MAJOR : R; bitpos: [6:5]; default: 0; 840 * BLK_VERSION_MAJOR of BLOCK2 841 */ 842 #define EFUSE_BLK_VERSION_MAJOR 0x00000003U 843 #define EFUSE_BLK_VERSION_MAJOR_M (EFUSE_BLK_VERSION_MAJOR_V << EFUSE_BLK_VERSION_MAJOR_S) 844 #define EFUSE_BLK_VERSION_MAJOR_V 0x00000003U 845 #define EFUSE_BLK_VERSION_MAJOR_S 5 846 /** EFUSE_DISABLE_BLK_VERSION_MAJOR : R; bitpos: [7]; default: 0; 847 * Disables check of blk version major 848 */ 849 #define EFUSE_DISABLE_BLK_VERSION_MAJOR (BIT(7)) 850 #define EFUSE_DISABLE_BLK_VERSION_MAJOR_M (EFUSE_DISABLE_BLK_VERSION_MAJOR_V << EFUSE_DISABLE_BLK_VERSION_MAJOR_S) 851 #define EFUSE_DISABLE_BLK_VERSION_MAJOR_V 0x00000001U 852 #define EFUSE_DISABLE_BLK_VERSION_MAJOR_S 7 853 /** EFUSE_TEMP_CALIB : R; bitpos: [16:8]; default: 0; 854 * Temperature calibration data 855 */ 856 #define EFUSE_TEMP_CALIB 0x000001FFU 857 #define EFUSE_TEMP_CALIB_M (EFUSE_TEMP_CALIB_V << EFUSE_TEMP_CALIB_S) 858 #define EFUSE_TEMP_CALIB_V 0x000001FFU 859 #define EFUSE_TEMP_CALIB_S 8 860 /** EFUSE_ADC1_AVE_INITCODE_ATTEN0 : R; bitpos: [26:17]; default: 0; 861 * ADC1 calibration data 862 */ 863 #define EFUSE_ADC1_AVE_INITCODE_ATTEN0 0x000003FFU 864 #define EFUSE_ADC1_AVE_INITCODE_ATTEN0_M (EFUSE_ADC1_AVE_INITCODE_ATTEN0_V << EFUSE_ADC1_AVE_INITCODE_ATTEN0_S) 865 #define EFUSE_ADC1_AVE_INITCODE_ATTEN0_V 0x000003FFU 866 #define EFUSE_ADC1_AVE_INITCODE_ATTEN0_S 17 867 /** EFUSE_ADC1_AVE_INITCODE_ATTEN1 : R; bitpos: [31:27]; default: 0; 868 * ADC1 calibration data 869 */ 870 #define EFUSE_ADC1_AVE_INITCODE_ATTEN1 0x0000001FU 871 #define EFUSE_ADC1_AVE_INITCODE_ATTEN1_M (EFUSE_ADC1_AVE_INITCODE_ATTEN1_V << EFUSE_ADC1_AVE_INITCODE_ATTEN1_S) 872 #define EFUSE_ADC1_AVE_INITCODE_ATTEN1_V 0x0000001FU 873 #define EFUSE_ADC1_AVE_INITCODE_ATTEN1_S 27 874 875 /** EFUSE_RD_SYS_PART1_DATA5_REG register 876 * Register $n of BLOCK2 (system). 877 */ 878 #define EFUSE_RD_SYS_PART1_DATA5_REG (DR_REG_EFUSE_BASE + 0x70) 879 /** EFUSE_ADC1_AVE_INITCODE_ATTEN1_1 : R; bitpos: [4:0]; default: 0; 880 * ADC1 calibration data 881 */ 882 #define EFUSE_ADC1_AVE_INITCODE_ATTEN1_1 0x0000001FU 883 #define EFUSE_ADC1_AVE_INITCODE_ATTEN1_1_M (EFUSE_ADC1_AVE_INITCODE_ATTEN1_1_V << EFUSE_ADC1_AVE_INITCODE_ATTEN1_1_S) 884 #define EFUSE_ADC1_AVE_INITCODE_ATTEN1_1_V 0x0000001FU 885 #define EFUSE_ADC1_AVE_INITCODE_ATTEN1_1_S 0 886 /** EFUSE_ADC1_AVE_INITCODE_ATTEN2 : R; bitpos: [14:5]; default: 0; 887 * ADC1 calibration data 888 */ 889 #define EFUSE_ADC1_AVE_INITCODE_ATTEN2 0x000003FFU 890 #define EFUSE_ADC1_AVE_INITCODE_ATTEN2_M (EFUSE_ADC1_AVE_INITCODE_ATTEN2_V << EFUSE_ADC1_AVE_INITCODE_ATTEN2_S) 891 #define EFUSE_ADC1_AVE_INITCODE_ATTEN2_V 0x000003FFU 892 #define EFUSE_ADC1_AVE_INITCODE_ATTEN2_S 5 893 /** EFUSE_ADC1_AVE_INITCODE_ATTEN3 : R; bitpos: [24:15]; default: 0; 894 * ADC1 calibration data 895 */ 896 #define EFUSE_ADC1_AVE_INITCODE_ATTEN3 0x000003FFU 897 #define EFUSE_ADC1_AVE_INITCODE_ATTEN3_M (EFUSE_ADC1_AVE_INITCODE_ATTEN3_V << EFUSE_ADC1_AVE_INITCODE_ATTEN3_S) 898 #define EFUSE_ADC1_AVE_INITCODE_ATTEN3_V 0x000003FFU 899 #define EFUSE_ADC1_AVE_INITCODE_ATTEN3_S 15 900 /** EFUSE_ADC1_HI_DOUT_ATTEN0 : R; bitpos: [31:25]; default: 0; 901 * ADC1 calibration data 902 */ 903 #define EFUSE_ADC1_HI_DOUT_ATTEN0 0x0000007FU 904 #define EFUSE_ADC1_HI_DOUT_ATTEN0_M (EFUSE_ADC1_HI_DOUT_ATTEN0_V << EFUSE_ADC1_HI_DOUT_ATTEN0_S) 905 #define EFUSE_ADC1_HI_DOUT_ATTEN0_V 0x0000007FU 906 #define EFUSE_ADC1_HI_DOUT_ATTEN0_S 25 907 908 /** EFUSE_RD_SYS_PART1_DATA6_REG register 909 * Register $n of BLOCK2 (system). 910 */ 911 #define EFUSE_RD_SYS_PART1_DATA6_REG (DR_REG_EFUSE_BASE + 0x74) 912 /** EFUSE_ADC1_HI_DOUT_ATTEN0_1 : R; bitpos: [2:0]; default: 0; 913 * ADC1 calibration data 914 */ 915 #define EFUSE_ADC1_HI_DOUT_ATTEN0_1 0x00000007U 916 #define EFUSE_ADC1_HI_DOUT_ATTEN0_1_M (EFUSE_ADC1_HI_DOUT_ATTEN0_1_V << EFUSE_ADC1_HI_DOUT_ATTEN0_1_S) 917 #define EFUSE_ADC1_HI_DOUT_ATTEN0_1_V 0x00000007U 918 #define EFUSE_ADC1_HI_DOUT_ATTEN0_1_S 0 919 /** EFUSE_ADC1_HI_DOUT_ATTEN1 : R; bitpos: [12:3]; default: 0; 920 * ADC1 calibration data 921 */ 922 #define EFUSE_ADC1_HI_DOUT_ATTEN1 0x000003FFU 923 #define EFUSE_ADC1_HI_DOUT_ATTEN1_M (EFUSE_ADC1_HI_DOUT_ATTEN1_V << EFUSE_ADC1_HI_DOUT_ATTEN1_S) 924 #define EFUSE_ADC1_HI_DOUT_ATTEN1_V 0x000003FFU 925 #define EFUSE_ADC1_HI_DOUT_ATTEN1_S 3 926 /** EFUSE_ADC1_HI_DOUT_ATTEN2 : R; bitpos: [22:13]; default: 0; 927 * ADC1 calibration data 928 */ 929 #define EFUSE_ADC1_HI_DOUT_ATTEN2 0x000003FFU 930 #define EFUSE_ADC1_HI_DOUT_ATTEN2_M (EFUSE_ADC1_HI_DOUT_ATTEN2_V << EFUSE_ADC1_HI_DOUT_ATTEN2_S) 931 #define EFUSE_ADC1_HI_DOUT_ATTEN2_V 0x000003FFU 932 #define EFUSE_ADC1_HI_DOUT_ATTEN2_S 13 933 /** EFUSE_ADC1_HI_DOUT_ATTEN3 : R; bitpos: [31:23]; default: 0; 934 * ADC1 calibration data 935 */ 936 #define EFUSE_ADC1_HI_DOUT_ATTEN3 0x000001FFU 937 #define EFUSE_ADC1_HI_DOUT_ATTEN3_M (EFUSE_ADC1_HI_DOUT_ATTEN3_V << EFUSE_ADC1_HI_DOUT_ATTEN3_S) 938 #define EFUSE_ADC1_HI_DOUT_ATTEN3_V 0x000001FFU 939 #define EFUSE_ADC1_HI_DOUT_ATTEN3_S 23 940 941 /** EFUSE_RD_SYS_PART1_DATA7_REG register 942 * Register $n of BLOCK2 (system). 943 */ 944 #define EFUSE_RD_SYS_PART1_DATA7_REG (DR_REG_EFUSE_BASE + 0x78) 945 /** EFUSE_ADC1_HI_DOUT_ATTEN3_1 : R; bitpos: [0]; default: 0; 946 * ADC1 calibration data 947 */ 948 #define EFUSE_ADC1_HI_DOUT_ATTEN3_1 (BIT(0)) 949 #define EFUSE_ADC1_HI_DOUT_ATTEN3_1_M (EFUSE_ADC1_HI_DOUT_ATTEN3_1_V << EFUSE_ADC1_HI_DOUT_ATTEN3_1_S) 950 #define EFUSE_ADC1_HI_DOUT_ATTEN3_1_V 0x00000001U 951 #define EFUSE_ADC1_HI_DOUT_ATTEN3_1_S 0 952 /** EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF : R; bitpos: [4:1]; default: 0; 953 * ADC1 calibration data 954 */ 955 #define EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF 0x0000000FU 956 #define EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF_M (EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF_S) 957 #define EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF_V 0x0000000FU 958 #define EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF_S 1 959 /** EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF : R; bitpos: [8:5]; default: 0; 960 * ADC1 calibration data 961 */ 962 #define EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF 0x0000000FU 963 #define EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF_M (EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF_S) 964 #define EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF_V 0x0000000FU 965 #define EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF_S 5 966 /** EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF : R; bitpos: [12:9]; default: 0; 967 * ADC1 calibration data 968 */ 969 #define EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF 0x0000000FU 970 #define EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF_M (EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF_S) 971 #define EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF_V 0x0000000FU 972 #define EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF_S 9 973 /** EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF : R; bitpos: [16:13]; default: 0; 974 * ADC1 calibration data 975 */ 976 #define EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF 0x0000000FU 977 #define EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF_M (EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF_S) 978 #define EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF_V 0x0000000FU 979 #define EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF_S 13 980 /** EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF : R; bitpos: [20:17]; default: 0; 981 * ADC1 calibration data 982 */ 983 #define EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF 0x0000000FU 984 #define EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF_M (EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF_S) 985 #define EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF_V 0x0000000FU 986 #define EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF_S 17 987 /** EFUSE_RESERVED_2_245 : R; bitpos: [31:21]; default: 0; 988 * reserved 989 */ 990 #define EFUSE_RESERVED_2_245 0x000007FFU 991 #define EFUSE_RESERVED_2_245_M (EFUSE_RESERVED_2_245_V << EFUSE_RESERVED_2_245_S) 992 #define EFUSE_RESERVED_2_245_V 0x000007FFU 993 #define EFUSE_RESERVED_2_245_S 21 994 995 /** EFUSE_RD_USR_DATA0_REG register 996 * Register $n of BLOCK3 (user). 997 */ 998 #define EFUSE_RD_USR_DATA0_REG (DR_REG_EFUSE_BASE + 0x7c) 999 /** EFUSE_USR_DATA0 : RO; bitpos: [31:0]; default: 0; 1000 * Stores the zeroth 32 bits of BLOCK3 (user). 1001 */ 1002 #define EFUSE_USR_DATA0 0xFFFFFFFFU 1003 #define EFUSE_USR_DATA0_M (EFUSE_USR_DATA0_V << EFUSE_USR_DATA0_S) 1004 #define EFUSE_USR_DATA0_V 0xFFFFFFFFU 1005 #define EFUSE_USR_DATA0_S 0 1006 1007 /** EFUSE_RD_USR_DATA1_REG register 1008 * Register $n of BLOCK3 (user). 1009 */ 1010 #define EFUSE_RD_USR_DATA1_REG (DR_REG_EFUSE_BASE + 0x80) 1011 /** EFUSE_USR_DATA1 : RO; bitpos: [31:0]; default: 0; 1012 * Stores the first 32 bits of BLOCK3 (user). 1013 */ 1014 #define EFUSE_USR_DATA1 0xFFFFFFFFU 1015 #define EFUSE_USR_DATA1_M (EFUSE_USR_DATA1_V << EFUSE_USR_DATA1_S) 1016 #define EFUSE_USR_DATA1_V 0xFFFFFFFFU 1017 #define EFUSE_USR_DATA1_S 0 1018 1019 /** EFUSE_RD_USR_DATA2_REG register 1020 * Register $n of BLOCK3 (user). 1021 */ 1022 #define EFUSE_RD_USR_DATA2_REG (DR_REG_EFUSE_BASE + 0x84) 1023 /** EFUSE_USR_DATA2 : RO; bitpos: [31:0]; default: 0; 1024 * Stores the second 32 bits of BLOCK3 (user). 1025 */ 1026 #define EFUSE_USR_DATA2 0xFFFFFFFFU 1027 #define EFUSE_USR_DATA2_M (EFUSE_USR_DATA2_V << EFUSE_USR_DATA2_S) 1028 #define EFUSE_USR_DATA2_V 0xFFFFFFFFU 1029 #define EFUSE_USR_DATA2_S 0 1030 1031 /** EFUSE_RD_USR_DATA3_REG register 1032 * Register $n of BLOCK3 (user). 1033 */ 1034 #define EFUSE_RD_USR_DATA3_REG (DR_REG_EFUSE_BASE + 0x88) 1035 /** EFUSE_USR_DATA3 : RO; bitpos: [31:0]; default: 0; 1036 * Stores the third 32 bits of BLOCK3 (user). 1037 */ 1038 #define EFUSE_USR_DATA3 0xFFFFFFFFU 1039 #define EFUSE_USR_DATA3_M (EFUSE_USR_DATA3_V << EFUSE_USR_DATA3_S) 1040 #define EFUSE_USR_DATA3_V 0xFFFFFFFFU 1041 #define EFUSE_USR_DATA3_S 0 1042 1043 /** EFUSE_RD_USR_DATA4_REG register 1044 * Register $n of BLOCK3 (user). 1045 */ 1046 #define EFUSE_RD_USR_DATA4_REG (DR_REG_EFUSE_BASE + 0x8c) 1047 /** EFUSE_USR_DATA4 : RO; bitpos: [31:0]; default: 0; 1048 * Stores the fourth 32 bits of BLOCK3 (user). 1049 */ 1050 #define EFUSE_USR_DATA4 0xFFFFFFFFU 1051 #define EFUSE_USR_DATA4_M (EFUSE_USR_DATA4_V << EFUSE_USR_DATA4_S) 1052 #define EFUSE_USR_DATA4_V 0xFFFFFFFFU 1053 #define EFUSE_USR_DATA4_S 0 1054 1055 /** EFUSE_RD_USR_DATA5_REG register 1056 * Register $n of BLOCK3 (user). 1057 */ 1058 #define EFUSE_RD_USR_DATA5_REG (DR_REG_EFUSE_BASE + 0x90) 1059 /** EFUSE_USR_DATA5 : RO; bitpos: [31:0]; default: 0; 1060 * Stores the fifth 32 bits of BLOCK3 (user). 1061 */ 1062 #define EFUSE_USR_DATA5 0xFFFFFFFFU 1063 #define EFUSE_USR_DATA5_M (EFUSE_USR_DATA5_V << EFUSE_USR_DATA5_S) 1064 #define EFUSE_USR_DATA5_V 0xFFFFFFFFU 1065 #define EFUSE_USR_DATA5_S 0 1066 1067 /** EFUSE_RD_USR_DATA6_REG register 1068 * Register $n of BLOCK3 (user). 1069 */ 1070 #define EFUSE_RD_USR_DATA6_REG (DR_REG_EFUSE_BASE + 0x94) 1071 /** EFUSE_RESERVED_3_192 : R; bitpos: [7:0]; default: 0; 1072 * reserved 1073 */ 1074 #define EFUSE_RESERVED_3_192 0x000000FFU 1075 #define EFUSE_RESERVED_3_192_M (EFUSE_RESERVED_3_192_V << EFUSE_RESERVED_3_192_S) 1076 #define EFUSE_RESERVED_3_192_V 0x000000FFU 1077 #define EFUSE_RESERVED_3_192_S 0 1078 /** EFUSE_CUSTOM_MAC : R; bitpos: [31:8]; default: 0; 1079 * Custom MAC 1080 */ 1081 #define EFUSE_CUSTOM_MAC 0x00FFFFFFU 1082 #define EFUSE_CUSTOM_MAC_M (EFUSE_CUSTOM_MAC_V << EFUSE_CUSTOM_MAC_S) 1083 #define EFUSE_CUSTOM_MAC_V 0x00FFFFFFU 1084 #define EFUSE_CUSTOM_MAC_S 8 1085 1086 /** EFUSE_RD_USR_DATA7_REG register 1087 * Register $n of BLOCK3 (user). 1088 */ 1089 #define EFUSE_RD_USR_DATA7_REG (DR_REG_EFUSE_BASE + 0x98) 1090 /** EFUSE_CUSTOM_MAC_1 : R; bitpos: [23:0]; default: 0; 1091 * Custom MAC 1092 */ 1093 #define EFUSE_CUSTOM_MAC_1 0x00FFFFFFU 1094 #define EFUSE_CUSTOM_MAC_1_M (EFUSE_CUSTOM_MAC_1_V << EFUSE_CUSTOM_MAC_1_S) 1095 #define EFUSE_CUSTOM_MAC_1_V 0x00FFFFFFU 1096 #define EFUSE_CUSTOM_MAC_1_S 0 1097 /** EFUSE_RESERVED_3_248 : R; bitpos: [31:24]; default: 0; 1098 * reserved 1099 */ 1100 #define EFUSE_RESERVED_3_248 0x000000FFU 1101 #define EFUSE_RESERVED_3_248_M (EFUSE_RESERVED_3_248_V << EFUSE_RESERVED_3_248_S) 1102 #define EFUSE_RESERVED_3_248_V 0x000000FFU 1103 #define EFUSE_RESERVED_3_248_S 24 1104 1105 /** EFUSE_RD_KEY0_DATA0_REG register 1106 * Register $n of BLOCK4 (KEY0). 1107 */ 1108 #define EFUSE_RD_KEY0_DATA0_REG (DR_REG_EFUSE_BASE + 0x9c) 1109 /** EFUSE_KEY0_DATA0 : RO; bitpos: [31:0]; default: 0; 1110 * Stores the zeroth 32 bits of KEY0. 1111 */ 1112 #define EFUSE_KEY0_DATA0 0xFFFFFFFFU 1113 #define EFUSE_KEY0_DATA0_M (EFUSE_KEY0_DATA0_V << EFUSE_KEY0_DATA0_S) 1114 #define EFUSE_KEY0_DATA0_V 0xFFFFFFFFU 1115 #define EFUSE_KEY0_DATA0_S 0 1116 1117 /** EFUSE_RD_KEY0_DATA1_REG register 1118 * Register $n of BLOCK4 (KEY0). 1119 */ 1120 #define EFUSE_RD_KEY0_DATA1_REG (DR_REG_EFUSE_BASE + 0xa0) 1121 /** EFUSE_KEY0_DATA1 : RO; bitpos: [31:0]; default: 0; 1122 * Stores the first 32 bits of KEY0. 1123 */ 1124 #define EFUSE_KEY0_DATA1 0xFFFFFFFFU 1125 #define EFUSE_KEY0_DATA1_M (EFUSE_KEY0_DATA1_V << EFUSE_KEY0_DATA1_S) 1126 #define EFUSE_KEY0_DATA1_V 0xFFFFFFFFU 1127 #define EFUSE_KEY0_DATA1_S 0 1128 1129 /** EFUSE_RD_KEY0_DATA2_REG register 1130 * Register $n of BLOCK4 (KEY0). 1131 */ 1132 #define EFUSE_RD_KEY0_DATA2_REG (DR_REG_EFUSE_BASE + 0xa4) 1133 /** EFUSE_KEY0_DATA2 : RO; bitpos: [31:0]; default: 0; 1134 * Stores the second 32 bits of KEY0. 1135 */ 1136 #define EFUSE_KEY0_DATA2 0xFFFFFFFFU 1137 #define EFUSE_KEY0_DATA2_M (EFUSE_KEY0_DATA2_V << EFUSE_KEY0_DATA2_S) 1138 #define EFUSE_KEY0_DATA2_V 0xFFFFFFFFU 1139 #define EFUSE_KEY0_DATA2_S 0 1140 1141 /** EFUSE_RD_KEY0_DATA3_REG register 1142 * Register $n of BLOCK4 (KEY0). 1143 */ 1144 #define EFUSE_RD_KEY0_DATA3_REG (DR_REG_EFUSE_BASE + 0xa8) 1145 /** EFUSE_KEY0_DATA3 : RO; bitpos: [31:0]; default: 0; 1146 * Stores the third 32 bits of KEY0. 1147 */ 1148 #define EFUSE_KEY0_DATA3 0xFFFFFFFFU 1149 #define EFUSE_KEY0_DATA3_M (EFUSE_KEY0_DATA3_V << EFUSE_KEY0_DATA3_S) 1150 #define EFUSE_KEY0_DATA3_V 0xFFFFFFFFU 1151 #define EFUSE_KEY0_DATA3_S 0 1152 1153 /** EFUSE_RD_KEY0_DATA4_REG register 1154 * Register $n of BLOCK4 (KEY0). 1155 */ 1156 #define EFUSE_RD_KEY0_DATA4_REG (DR_REG_EFUSE_BASE + 0xac) 1157 /** EFUSE_KEY0_DATA4 : RO; bitpos: [31:0]; default: 0; 1158 * Stores the fourth 32 bits of KEY0. 1159 */ 1160 #define EFUSE_KEY0_DATA4 0xFFFFFFFFU 1161 #define EFUSE_KEY0_DATA4_M (EFUSE_KEY0_DATA4_V << EFUSE_KEY0_DATA4_S) 1162 #define EFUSE_KEY0_DATA4_V 0xFFFFFFFFU 1163 #define EFUSE_KEY0_DATA4_S 0 1164 1165 /** EFUSE_RD_KEY0_DATA5_REG register 1166 * Register $n of BLOCK4 (KEY0). 1167 */ 1168 #define EFUSE_RD_KEY0_DATA5_REG (DR_REG_EFUSE_BASE + 0xb0) 1169 /** EFUSE_KEY0_DATA5 : RO; bitpos: [31:0]; default: 0; 1170 * Stores the fifth 32 bits of KEY0. 1171 */ 1172 #define EFUSE_KEY0_DATA5 0xFFFFFFFFU 1173 #define EFUSE_KEY0_DATA5_M (EFUSE_KEY0_DATA5_V << EFUSE_KEY0_DATA5_S) 1174 #define EFUSE_KEY0_DATA5_V 0xFFFFFFFFU 1175 #define EFUSE_KEY0_DATA5_S 0 1176 1177 /** EFUSE_RD_KEY0_DATA6_REG register 1178 * Register $n of BLOCK4 (KEY0). 1179 */ 1180 #define EFUSE_RD_KEY0_DATA6_REG (DR_REG_EFUSE_BASE + 0xb4) 1181 /** EFUSE_KEY0_DATA6 : RO; bitpos: [31:0]; default: 0; 1182 * Stores the sixth 32 bits of KEY0. 1183 */ 1184 #define EFUSE_KEY0_DATA6 0xFFFFFFFFU 1185 #define EFUSE_KEY0_DATA6_M (EFUSE_KEY0_DATA6_V << EFUSE_KEY0_DATA6_S) 1186 #define EFUSE_KEY0_DATA6_V 0xFFFFFFFFU 1187 #define EFUSE_KEY0_DATA6_S 0 1188 1189 /** EFUSE_RD_KEY0_DATA7_REG register 1190 * Register $n of BLOCK4 (KEY0). 1191 */ 1192 #define EFUSE_RD_KEY0_DATA7_REG (DR_REG_EFUSE_BASE + 0xb8) 1193 /** EFUSE_KEY0_DATA7 : RO; bitpos: [31:0]; default: 0; 1194 * Stores the seventh 32 bits of KEY0. 1195 */ 1196 #define EFUSE_KEY0_DATA7 0xFFFFFFFFU 1197 #define EFUSE_KEY0_DATA7_M (EFUSE_KEY0_DATA7_V << EFUSE_KEY0_DATA7_S) 1198 #define EFUSE_KEY0_DATA7_V 0xFFFFFFFFU 1199 #define EFUSE_KEY0_DATA7_S 0 1200 1201 /** EFUSE_RD_KEY1_DATA0_REG register 1202 * Register $n of BLOCK5 (KEY1). 1203 */ 1204 #define EFUSE_RD_KEY1_DATA0_REG (DR_REG_EFUSE_BASE + 0xbc) 1205 /** EFUSE_KEY1_DATA0 : RO; bitpos: [31:0]; default: 0; 1206 * Stores the zeroth 32 bits of KEY1. 1207 */ 1208 #define EFUSE_KEY1_DATA0 0xFFFFFFFFU 1209 #define EFUSE_KEY1_DATA0_M (EFUSE_KEY1_DATA0_V << EFUSE_KEY1_DATA0_S) 1210 #define EFUSE_KEY1_DATA0_V 0xFFFFFFFFU 1211 #define EFUSE_KEY1_DATA0_S 0 1212 1213 /** EFUSE_RD_KEY1_DATA1_REG register 1214 * Register $n of BLOCK5 (KEY1). 1215 */ 1216 #define EFUSE_RD_KEY1_DATA1_REG (DR_REG_EFUSE_BASE + 0xc0) 1217 /** EFUSE_KEY1_DATA1 : RO; bitpos: [31:0]; default: 0; 1218 * Stores the first 32 bits of KEY1. 1219 */ 1220 #define EFUSE_KEY1_DATA1 0xFFFFFFFFU 1221 #define EFUSE_KEY1_DATA1_M (EFUSE_KEY1_DATA1_V << EFUSE_KEY1_DATA1_S) 1222 #define EFUSE_KEY1_DATA1_V 0xFFFFFFFFU 1223 #define EFUSE_KEY1_DATA1_S 0 1224 1225 /** EFUSE_RD_KEY1_DATA2_REG register 1226 * Register $n of BLOCK5 (KEY1). 1227 */ 1228 #define EFUSE_RD_KEY1_DATA2_REG (DR_REG_EFUSE_BASE + 0xc4) 1229 /** EFUSE_KEY1_DATA2 : RO; bitpos: [31:0]; default: 0; 1230 * Stores the second 32 bits of KEY1. 1231 */ 1232 #define EFUSE_KEY1_DATA2 0xFFFFFFFFU 1233 #define EFUSE_KEY1_DATA2_M (EFUSE_KEY1_DATA2_V << EFUSE_KEY1_DATA2_S) 1234 #define EFUSE_KEY1_DATA2_V 0xFFFFFFFFU 1235 #define EFUSE_KEY1_DATA2_S 0 1236 1237 /** EFUSE_RD_KEY1_DATA3_REG register 1238 * Register $n of BLOCK5 (KEY1). 1239 */ 1240 #define EFUSE_RD_KEY1_DATA3_REG (DR_REG_EFUSE_BASE + 0xc8) 1241 /** EFUSE_KEY1_DATA3 : RO; bitpos: [31:0]; default: 0; 1242 * Stores the third 32 bits of KEY1. 1243 */ 1244 #define EFUSE_KEY1_DATA3 0xFFFFFFFFU 1245 #define EFUSE_KEY1_DATA3_M (EFUSE_KEY1_DATA3_V << EFUSE_KEY1_DATA3_S) 1246 #define EFUSE_KEY1_DATA3_V 0xFFFFFFFFU 1247 #define EFUSE_KEY1_DATA3_S 0 1248 1249 /** EFUSE_RD_KEY1_DATA4_REG register 1250 * Register $n of BLOCK5 (KEY1). 1251 */ 1252 #define EFUSE_RD_KEY1_DATA4_REG (DR_REG_EFUSE_BASE + 0xcc) 1253 /** EFUSE_KEY1_DATA4 : RO; bitpos: [31:0]; default: 0; 1254 * Stores the fourth 32 bits of KEY1. 1255 */ 1256 #define EFUSE_KEY1_DATA4 0xFFFFFFFFU 1257 #define EFUSE_KEY1_DATA4_M (EFUSE_KEY1_DATA4_V << EFUSE_KEY1_DATA4_S) 1258 #define EFUSE_KEY1_DATA4_V 0xFFFFFFFFU 1259 #define EFUSE_KEY1_DATA4_S 0 1260 1261 /** EFUSE_RD_KEY1_DATA5_REG register 1262 * Register $n of BLOCK5 (KEY1). 1263 */ 1264 #define EFUSE_RD_KEY1_DATA5_REG (DR_REG_EFUSE_BASE + 0xd0) 1265 /** EFUSE_KEY1_DATA5 : RO; bitpos: [31:0]; default: 0; 1266 * Stores the fifth 32 bits of KEY1. 1267 */ 1268 #define EFUSE_KEY1_DATA5 0xFFFFFFFFU 1269 #define EFUSE_KEY1_DATA5_M (EFUSE_KEY1_DATA5_V << EFUSE_KEY1_DATA5_S) 1270 #define EFUSE_KEY1_DATA5_V 0xFFFFFFFFU 1271 #define EFUSE_KEY1_DATA5_S 0 1272 1273 /** EFUSE_RD_KEY1_DATA6_REG register 1274 * Register $n of BLOCK5 (KEY1). 1275 */ 1276 #define EFUSE_RD_KEY1_DATA6_REG (DR_REG_EFUSE_BASE + 0xd4) 1277 /** EFUSE_KEY1_DATA6 : RO; bitpos: [31:0]; default: 0; 1278 * Stores the sixth 32 bits of KEY1. 1279 */ 1280 #define EFUSE_KEY1_DATA6 0xFFFFFFFFU 1281 #define EFUSE_KEY1_DATA6_M (EFUSE_KEY1_DATA6_V << EFUSE_KEY1_DATA6_S) 1282 #define EFUSE_KEY1_DATA6_V 0xFFFFFFFFU 1283 #define EFUSE_KEY1_DATA6_S 0 1284 1285 /** EFUSE_RD_KEY1_DATA7_REG register 1286 * Register $n of BLOCK5 (KEY1). 1287 */ 1288 #define EFUSE_RD_KEY1_DATA7_REG (DR_REG_EFUSE_BASE + 0xd8) 1289 /** EFUSE_KEY1_DATA7 : RO; bitpos: [31:0]; default: 0; 1290 * Stores the seventh 32 bits of KEY1. 1291 */ 1292 #define EFUSE_KEY1_DATA7 0xFFFFFFFFU 1293 #define EFUSE_KEY1_DATA7_M (EFUSE_KEY1_DATA7_V << EFUSE_KEY1_DATA7_S) 1294 #define EFUSE_KEY1_DATA7_V 0xFFFFFFFFU 1295 #define EFUSE_KEY1_DATA7_S 0 1296 1297 /** EFUSE_RD_KEY2_DATA0_REG register 1298 * Register $n of BLOCK6 (KEY2). 1299 */ 1300 #define EFUSE_RD_KEY2_DATA0_REG (DR_REG_EFUSE_BASE + 0xdc) 1301 /** EFUSE_KEY2_DATA0 : RO; bitpos: [31:0]; default: 0; 1302 * Stores the zeroth 32 bits of KEY2. 1303 */ 1304 #define EFUSE_KEY2_DATA0 0xFFFFFFFFU 1305 #define EFUSE_KEY2_DATA0_M (EFUSE_KEY2_DATA0_V << EFUSE_KEY2_DATA0_S) 1306 #define EFUSE_KEY2_DATA0_V 0xFFFFFFFFU 1307 #define EFUSE_KEY2_DATA0_S 0 1308 1309 /** EFUSE_RD_KEY2_DATA1_REG register 1310 * Register $n of BLOCK6 (KEY2). 1311 */ 1312 #define EFUSE_RD_KEY2_DATA1_REG (DR_REG_EFUSE_BASE + 0xe0) 1313 /** EFUSE_KEY2_DATA1 : RO; bitpos: [31:0]; default: 0; 1314 * Stores the first 32 bits of KEY2. 1315 */ 1316 #define EFUSE_KEY2_DATA1 0xFFFFFFFFU 1317 #define EFUSE_KEY2_DATA1_M (EFUSE_KEY2_DATA1_V << EFUSE_KEY2_DATA1_S) 1318 #define EFUSE_KEY2_DATA1_V 0xFFFFFFFFU 1319 #define EFUSE_KEY2_DATA1_S 0 1320 1321 /** EFUSE_RD_KEY2_DATA2_REG register 1322 * Register $n of BLOCK6 (KEY2). 1323 */ 1324 #define EFUSE_RD_KEY2_DATA2_REG (DR_REG_EFUSE_BASE + 0xe4) 1325 /** EFUSE_KEY2_DATA2 : RO; bitpos: [31:0]; default: 0; 1326 * Stores the second 32 bits of KEY2. 1327 */ 1328 #define EFUSE_KEY2_DATA2 0xFFFFFFFFU 1329 #define EFUSE_KEY2_DATA2_M (EFUSE_KEY2_DATA2_V << EFUSE_KEY2_DATA2_S) 1330 #define EFUSE_KEY2_DATA2_V 0xFFFFFFFFU 1331 #define EFUSE_KEY2_DATA2_S 0 1332 1333 /** EFUSE_RD_KEY2_DATA3_REG register 1334 * Register $n of BLOCK6 (KEY2). 1335 */ 1336 #define EFUSE_RD_KEY2_DATA3_REG (DR_REG_EFUSE_BASE + 0xe8) 1337 /** EFUSE_KEY2_DATA3 : RO; bitpos: [31:0]; default: 0; 1338 * Stores the third 32 bits of KEY2. 1339 */ 1340 #define EFUSE_KEY2_DATA3 0xFFFFFFFFU 1341 #define EFUSE_KEY2_DATA3_M (EFUSE_KEY2_DATA3_V << EFUSE_KEY2_DATA3_S) 1342 #define EFUSE_KEY2_DATA3_V 0xFFFFFFFFU 1343 #define EFUSE_KEY2_DATA3_S 0 1344 1345 /** EFUSE_RD_KEY2_DATA4_REG register 1346 * Register $n of BLOCK6 (KEY2). 1347 */ 1348 #define EFUSE_RD_KEY2_DATA4_REG (DR_REG_EFUSE_BASE + 0xec) 1349 /** EFUSE_KEY2_DATA4 : RO; bitpos: [31:0]; default: 0; 1350 * Stores the fourth 32 bits of KEY2. 1351 */ 1352 #define EFUSE_KEY2_DATA4 0xFFFFFFFFU 1353 #define EFUSE_KEY2_DATA4_M (EFUSE_KEY2_DATA4_V << EFUSE_KEY2_DATA4_S) 1354 #define EFUSE_KEY2_DATA4_V 0xFFFFFFFFU 1355 #define EFUSE_KEY2_DATA4_S 0 1356 1357 /** EFUSE_RD_KEY2_DATA5_REG register 1358 * Register $n of BLOCK6 (KEY2). 1359 */ 1360 #define EFUSE_RD_KEY2_DATA5_REG (DR_REG_EFUSE_BASE + 0xf0) 1361 /** EFUSE_KEY2_DATA5 : RO; bitpos: [31:0]; default: 0; 1362 * Stores the fifth 32 bits of KEY2. 1363 */ 1364 #define EFUSE_KEY2_DATA5 0xFFFFFFFFU 1365 #define EFUSE_KEY2_DATA5_M (EFUSE_KEY2_DATA5_V << EFUSE_KEY2_DATA5_S) 1366 #define EFUSE_KEY2_DATA5_V 0xFFFFFFFFU 1367 #define EFUSE_KEY2_DATA5_S 0 1368 1369 /** EFUSE_RD_KEY2_DATA6_REG register 1370 * Register $n of BLOCK6 (KEY2). 1371 */ 1372 #define EFUSE_RD_KEY2_DATA6_REG (DR_REG_EFUSE_BASE + 0xf4) 1373 /** EFUSE_KEY2_DATA6 : RO; bitpos: [31:0]; default: 0; 1374 * Stores the sixth 32 bits of KEY2. 1375 */ 1376 #define EFUSE_KEY2_DATA6 0xFFFFFFFFU 1377 #define EFUSE_KEY2_DATA6_M (EFUSE_KEY2_DATA6_V << EFUSE_KEY2_DATA6_S) 1378 #define EFUSE_KEY2_DATA6_V 0xFFFFFFFFU 1379 #define EFUSE_KEY2_DATA6_S 0 1380 1381 /** EFUSE_RD_KEY2_DATA7_REG register 1382 * Register $n of BLOCK6 (KEY2). 1383 */ 1384 #define EFUSE_RD_KEY2_DATA7_REG (DR_REG_EFUSE_BASE + 0xf8) 1385 /** EFUSE_KEY2_DATA7 : RO; bitpos: [31:0]; default: 0; 1386 * Stores the seventh 32 bits of KEY2. 1387 */ 1388 #define EFUSE_KEY2_DATA7 0xFFFFFFFFU 1389 #define EFUSE_KEY2_DATA7_M (EFUSE_KEY2_DATA7_V << EFUSE_KEY2_DATA7_S) 1390 #define EFUSE_KEY2_DATA7_V 0xFFFFFFFFU 1391 #define EFUSE_KEY2_DATA7_S 0 1392 1393 /** EFUSE_RD_KEY3_DATA0_REG register 1394 * Register $n of BLOCK7 (KEY3). 1395 */ 1396 #define EFUSE_RD_KEY3_DATA0_REG (DR_REG_EFUSE_BASE + 0xfc) 1397 /** EFUSE_KEY3_DATA0 : RO; bitpos: [31:0]; default: 0; 1398 * Stores the zeroth 32 bits of KEY3. 1399 */ 1400 #define EFUSE_KEY3_DATA0 0xFFFFFFFFU 1401 #define EFUSE_KEY3_DATA0_M (EFUSE_KEY3_DATA0_V << EFUSE_KEY3_DATA0_S) 1402 #define EFUSE_KEY3_DATA0_V 0xFFFFFFFFU 1403 #define EFUSE_KEY3_DATA0_S 0 1404 1405 /** EFUSE_RD_KEY3_DATA1_REG register 1406 * Register $n of BLOCK7 (KEY3). 1407 */ 1408 #define EFUSE_RD_KEY3_DATA1_REG (DR_REG_EFUSE_BASE + 0x100) 1409 /** EFUSE_KEY3_DATA1 : RO; bitpos: [31:0]; default: 0; 1410 * Stores the first 32 bits of KEY3. 1411 */ 1412 #define EFUSE_KEY3_DATA1 0xFFFFFFFFU 1413 #define EFUSE_KEY3_DATA1_M (EFUSE_KEY3_DATA1_V << EFUSE_KEY3_DATA1_S) 1414 #define EFUSE_KEY3_DATA1_V 0xFFFFFFFFU 1415 #define EFUSE_KEY3_DATA1_S 0 1416 1417 /** EFUSE_RD_KEY3_DATA2_REG register 1418 * Register $n of BLOCK7 (KEY3). 1419 */ 1420 #define EFUSE_RD_KEY3_DATA2_REG (DR_REG_EFUSE_BASE + 0x104) 1421 /** EFUSE_KEY3_DATA2 : RO; bitpos: [31:0]; default: 0; 1422 * Stores the second 32 bits of KEY3. 1423 */ 1424 #define EFUSE_KEY3_DATA2 0xFFFFFFFFU 1425 #define EFUSE_KEY3_DATA2_M (EFUSE_KEY3_DATA2_V << EFUSE_KEY3_DATA2_S) 1426 #define EFUSE_KEY3_DATA2_V 0xFFFFFFFFU 1427 #define EFUSE_KEY3_DATA2_S 0 1428 1429 /** EFUSE_RD_KEY3_DATA3_REG register 1430 * Register $n of BLOCK7 (KEY3). 1431 */ 1432 #define EFUSE_RD_KEY3_DATA3_REG (DR_REG_EFUSE_BASE + 0x108) 1433 /** EFUSE_KEY3_DATA3 : RO; bitpos: [31:0]; default: 0; 1434 * Stores the third 32 bits of KEY3. 1435 */ 1436 #define EFUSE_KEY3_DATA3 0xFFFFFFFFU 1437 #define EFUSE_KEY3_DATA3_M (EFUSE_KEY3_DATA3_V << EFUSE_KEY3_DATA3_S) 1438 #define EFUSE_KEY3_DATA3_V 0xFFFFFFFFU 1439 #define EFUSE_KEY3_DATA3_S 0 1440 1441 /** EFUSE_RD_KEY3_DATA4_REG register 1442 * Register $n of BLOCK7 (KEY3). 1443 */ 1444 #define EFUSE_RD_KEY3_DATA4_REG (DR_REG_EFUSE_BASE + 0x10c) 1445 /** EFUSE_KEY3_DATA4 : RO; bitpos: [31:0]; default: 0; 1446 * Stores the fourth 32 bits of KEY3. 1447 */ 1448 #define EFUSE_KEY3_DATA4 0xFFFFFFFFU 1449 #define EFUSE_KEY3_DATA4_M (EFUSE_KEY3_DATA4_V << EFUSE_KEY3_DATA4_S) 1450 #define EFUSE_KEY3_DATA4_V 0xFFFFFFFFU 1451 #define EFUSE_KEY3_DATA4_S 0 1452 1453 /** EFUSE_RD_KEY3_DATA5_REG register 1454 * Register $n of BLOCK7 (KEY3). 1455 */ 1456 #define EFUSE_RD_KEY3_DATA5_REG (DR_REG_EFUSE_BASE + 0x110) 1457 /** EFUSE_KEY3_DATA5 : RO; bitpos: [31:0]; default: 0; 1458 * Stores the fifth 32 bits of KEY3. 1459 */ 1460 #define EFUSE_KEY3_DATA5 0xFFFFFFFFU 1461 #define EFUSE_KEY3_DATA5_M (EFUSE_KEY3_DATA5_V << EFUSE_KEY3_DATA5_S) 1462 #define EFUSE_KEY3_DATA5_V 0xFFFFFFFFU 1463 #define EFUSE_KEY3_DATA5_S 0 1464 1465 /** EFUSE_RD_KEY3_DATA6_REG register 1466 * Register $n of BLOCK7 (KEY3). 1467 */ 1468 #define EFUSE_RD_KEY3_DATA6_REG (DR_REG_EFUSE_BASE + 0x114) 1469 /** EFUSE_KEY3_DATA6 : RO; bitpos: [31:0]; default: 0; 1470 * Stores the sixth 32 bits of KEY3. 1471 */ 1472 #define EFUSE_KEY3_DATA6 0xFFFFFFFFU 1473 #define EFUSE_KEY3_DATA6_M (EFUSE_KEY3_DATA6_V << EFUSE_KEY3_DATA6_S) 1474 #define EFUSE_KEY3_DATA6_V 0xFFFFFFFFU 1475 #define EFUSE_KEY3_DATA6_S 0 1476 1477 /** EFUSE_RD_KEY3_DATA7_REG register 1478 * Register $n of BLOCK7 (KEY3). 1479 */ 1480 #define EFUSE_RD_KEY3_DATA7_REG (DR_REG_EFUSE_BASE + 0x118) 1481 /** EFUSE_KEY3_DATA7 : RO; bitpos: [31:0]; default: 0; 1482 * Stores the seventh 32 bits of KEY3. 1483 */ 1484 #define EFUSE_KEY3_DATA7 0xFFFFFFFFU 1485 #define EFUSE_KEY3_DATA7_M (EFUSE_KEY3_DATA7_V << EFUSE_KEY3_DATA7_S) 1486 #define EFUSE_KEY3_DATA7_V 0xFFFFFFFFU 1487 #define EFUSE_KEY3_DATA7_S 0 1488 1489 /** EFUSE_RD_KEY4_DATA0_REG register 1490 * Register $n of BLOCK8 (KEY4). 1491 */ 1492 #define EFUSE_RD_KEY4_DATA0_REG (DR_REG_EFUSE_BASE + 0x11c) 1493 /** EFUSE_KEY4_DATA0 : RO; bitpos: [31:0]; default: 0; 1494 * Stores the zeroth 32 bits of KEY4. 1495 */ 1496 #define EFUSE_KEY4_DATA0 0xFFFFFFFFU 1497 #define EFUSE_KEY4_DATA0_M (EFUSE_KEY4_DATA0_V << EFUSE_KEY4_DATA0_S) 1498 #define EFUSE_KEY4_DATA0_V 0xFFFFFFFFU 1499 #define EFUSE_KEY4_DATA0_S 0 1500 1501 /** EFUSE_RD_KEY4_DATA1_REG register 1502 * Register $n of BLOCK8 (KEY4). 1503 */ 1504 #define EFUSE_RD_KEY4_DATA1_REG (DR_REG_EFUSE_BASE + 0x120) 1505 /** EFUSE_KEY4_DATA1 : RO; bitpos: [31:0]; default: 0; 1506 * Stores the first 32 bits of KEY4. 1507 */ 1508 #define EFUSE_KEY4_DATA1 0xFFFFFFFFU 1509 #define EFUSE_KEY4_DATA1_M (EFUSE_KEY4_DATA1_V << EFUSE_KEY4_DATA1_S) 1510 #define EFUSE_KEY4_DATA1_V 0xFFFFFFFFU 1511 #define EFUSE_KEY4_DATA1_S 0 1512 1513 /** EFUSE_RD_KEY4_DATA2_REG register 1514 * Register $n of BLOCK8 (KEY4). 1515 */ 1516 #define EFUSE_RD_KEY4_DATA2_REG (DR_REG_EFUSE_BASE + 0x124) 1517 /** EFUSE_KEY4_DATA2 : RO; bitpos: [31:0]; default: 0; 1518 * Stores the second 32 bits of KEY4. 1519 */ 1520 #define EFUSE_KEY4_DATA2 0xFFFFFFFFU 1521 #define EFUSE_KEY4_DATA2_M (EFUSE_KEY4_DATA2_V << EFUSE_KEY4_DATA2_S) 1522 #define EFUSE_KEY4_DATA2_V 0xFFFFFFFFU 1523 #define EFUSE_KEY4_DATA2_S 0 1524 1525 /** EFUSE_RD_KEY4_DATA3_REG register 1526 * Register $n of BLOCK8 (KEY4). 1527 */ 1528 #define EFUSE_RD_KEY4_DATA3_REG (DR_REG_EFUSE_BASE + 0x128) 1529 /** EFUSE_KEY4_DATA3 : RO; bitpos: [31:0]; default: 0; 1530 * Stores the third 32 bits of KEY4. 1531 */ 1532 #define EFUSE_KEY4_DATA3 0xFFFFFFFFU 1533 #define EFUSE_KEY4_DATA3_M (EFUSE_KEY4_DATA3_V << EFUSE_KEY4_DATA3_S) 1534 #define EFUSE_KEY4_DATA3_V 0xFFFFFFFFU 1535 #define EFUSE_KEY4_DATA3_S 0 1536 1537 /** EFUSE_RD_KEY4_DATA4_REG register 1538 * Register $n of BLOCK8 (KEY4). 1539 */ 1540 #define EFUSE_RD_KEY4_DATA4_REG (DR_REG_EFUSE_BASE + 0x12c) 1541 /** EFUSE_KEY4_DATA4 : RO; bitpos: [31:0]; default: 0; 1542 * Stores the fourth 32 bits of KEY4. 1543 */ 1544 #define EFUSE_KEY4_DATA4 0xFFFFFFFFU 1545 #define EFUSE_KEY4_DATA4_M (EFUSE_KEY4_DATA4_V << EFUSE_KEY4_DATA4_S) 1546 #define EFUSE_KEY4_DATA4_V 0xFFFFFFFFU 1547 #define EFUSE_KEY4_DATA4_S 0 1548 1549 /** EFUSE_RD_KEY4_DATA5_REG register 1550 * Register $n of BLOCK8 (KEY4). 1551 */ 1552 #define EFUSE_RD_KEY4_DATA5_REG (DR_REG_EFUSE_BASE + 0x130) 1553 /** EFUSE_KEY4_DATA5 : RO; bitpos: [31:0]; default: 0; 1554 * Stores the fifth 32 bits of KEY4. 1555 */ 1556 #define EFUSE_KEY4_DATA5 0xFFFFFFFFU 1557 #define EFUSE_KEY4_DATA5_M (EFUSE_KEY4_DATA5_V << EFUSE_KEY4_DATA5_S) 1558 #define EFUSE_KEY4_DATA5_V 0xFFFFFFFFU 1559 #define EFUSE_KEY4_DATA5_S 0 1560 1561 /** EFUSE_RD_KEY4_DATA6_REG register 1562 * Register $n of BLOCK8 (KEY4). 1563 */ 1564 #define EFUSE_RD_KEY4_DATA6_REG (DR_REG_EFUSE_BASE + 0x134) 1565 /** EFUSE_KEY4_DATA6 : RO; bitpos: [31:0]; default: 0; 1566 * Stores the sixth 32 bits of KEY4. 1567 */ 1568 #define EFUSE_KEY4_DATA6 0xFFFFFFFFU 1569 #define EFUSE_KEY4_DATA6_M (EFUSE_KEY4_DATA6_V << EFUSE_KEY4_DATA6_S) 1570 #define EFUSE_KEY4_DATA6_V 0xFFFFFFFFU 1571 #define EFUSE_KEY4_DATA6_S 0 1572 1573 /** EFUSE_RD_KEY4_DATA7_REG register 1574 * Register $n of BLOCK8 (KEY4). 1575 */ 1576 #define EFUSE_RD_KEY4_DATA7_REG (DR_REG_EFUSE_BASE + 0x138) 1577 /** EFUSE_KEY4_DATA7 : RO; bitpos: [31:0]; default: 0; 1578 * Stores the seventh 32 bits of KEY4. 1579 */ 1580 #define EFUSE_KEY4_DATA7 0xFFFFFFFFU 1581 #define EFUSE_KEY4_DATA7_M (EFUSE_KEY4_DATA7_V << EFUSE_KEY4_DATA7_S) 1582 #define EFUSE_KEY4_DATA7_V 0xFFFFFFFFU 1583 #define EFUSE_KEY4_DATA7_S 0 1584 1585 /** EFUSE_RD_KEY5_DATA0_REG register 1586 * Register $n of BLOCK9 (KEY5). 1587 */ 1588 #define EFUSE_RD_KEY5_DATA0_REG (DR_REG_EFUSE_BASE + 0x13c) 1589 /** EFUSE_KEY5_DATA0 : RO; bitpos: [31:0]; default: 0; 1590 * Stores the zeroth 32 bits of KEY5. 1591 */ 1592 #define EFUSE_KEY5_DATA0 0xFFFFFFFFU 1593 #define EFUSE_KEY5_DATA0_M (EFUSE_KEY5_DATA0_V << EFUSE_KEY5_DATA0_S) 1594 #define EFUSE_KEY5_DATA0_V 0xFFFFFFFFU 1595 #define EFUSE_KEY5_DATA0_S 0 1596 1597 /** EFUSE_RD_KEY5_DATA1_REG register 1598 * Register $n of BLOCK9 (KEY5). 1599 */ 1600 #define EFUSE_RD_KEY5_DATA1_REG (DR_REG_EFUSE_BASE + 0x140) 1601 /** EFUSE_KEY5_DATA1 : RO; bitpos: [31:0]; default: 0; 1602 * Stores the first 32 bits of KEY5. 1603 */ 1604 #define EFUSE_KEY5_DATA1 0xFFFFFFFFU 1605 #define EFUSE_KEY5_DATA1_M (EFUSE_KEY5_DATA1_V << EFUSE_KEY5_DATA1_S) 1606 #define EFUSE_KEY5_DATA1_V 0xFFFFFFFFU 1607 #define EFUSE_KEY5_DATA1_S 0 1608 1609 /** EFUSE_RD_KEY5_DATA2_REG register 1610 * Register $n of BLOCK9 (KEY5). 1611 */ 1612 #define EFUSE_RD_KEY5_DATA2_REG (DR_REG_EFUSE_BASE + 0x144) 1613 /** EFUSE_KEY5_DATA2 : RO; bitpos: [31:0]; default: 0; 1614 * Stores the second 32 bits of KEY5. 1615 */ 1616 #define EFUSE_KEY5_DATA2 0xFFFFFFFFU 1617 #define EFUSE_KEY5_DATA2_M (EFUSE_KEY5_DATA2_V << EFUSE_KEY5_DATA2_S) 1618 #define EFUSE_KEY5_DATA2_V 0xFFFFFFFFU 1619 #define EFUSE_KEY5_DATA2_S 0 1620 1621 /** EFUSE_RD_KEY5_DATA3_REG register 1622 * Register $n of BLOCK9 (KEY5). 1623 */ 1624 #define EFUSE_RD_KEY5_DATA3_REG (DR_REG_EFUSE_BASE + 0x148) 1625 /** EFUSE_KEY5_DATA3 : RO; bitpos: [31:0]; default: 0; 1626 * Stores the third 32 bits of KEY5. 1627 */ 1628 #define EFUSE_KEY5_DATA3 0xFFFFFFFFU 1629 #define EFUSE_KEY5_DATA3_M (EFUSE_KEY5_DATA3_V << EFUSE_KEY5_DATA3_S) 1630 #define EFUSE_KEY5_DATA3_V 0xFFFFFFFFU 1631 #define EFUSE_KEY5_DATA3_S 0 1632 1633 /** EFUSE_RD_KEY5_DATA4_REG register 1634 * Register $n of BLOCK9 (KEY5). 1635 */ 1636 #define EFUSE_RD_KEY5_DATA4_REG (DR_REG_EFUSE_BASE + 0x14c) 1637 /** EFUSE_KEY5_DATA4 : RO; bitpos: [31:0]; default: 0; 1638 * Stores the fourth 32 bits of KEY5. 1639 */ 1640 #define EFUSE_KEY5_DATA4 0xFFFFFFFFU 1641 #define EFUSE_KEY5_DATA4_M (EFUSE_KEY5_DATA4_V << EFUSE_KEY5_DATA4_S) 1642 #define EFUSE_KEY5_DATA4_V 0xFFFFFFFFU 1643 #define EFUSE_KEY5_DATA4_S 0 1644 1645 /** EFUSE_RD_KEY5_DATA5_REG register 1646 * Register $n of BLOCK9 (KEY5). 1647 */ 1648 #define EFUSE_RD_KEY5_DATA5_REG (DR_REG_EFUSE_BASE + 0x150) 1649 /** EFUSE_KEY5_DATA5 : RO; bitpos: [31:0]; default: 0; 1650 * Stores the fifth 32 bits of KEY5. 1651 */ 1652 #define EFUSE_KEY5_DATA5 0xFFFFFFFFU 1653 #define EFUSE_KEY5_DATA5_M (EFUSE_KEY5_DATA5_V << EFUSE_KEY5_DATA5_S) 1654 #define EFUSE_KEY5_DATA5_V 0xFFFFFFFFU 1655 #define EFUSE_KEY5_DATA5_S 0 1656 1657 /** EFUSE_RD_KEY5_DATA6_REG register 1658 * Register $n of BLOCK9 (KEY5). 1659 */ 1660 #define EFUSE_RD_KEY5_DATA6_REG (DR_REG_EFUSE_BASE + 0x154) 1661 /** EFUSE_KEY5_DATA6 : RO; bitpos: [31:0]; default: 0; 1662 * Stores the sixth 32 bits of KEY5. 1663 */ 1664 #define EFUSE_KEY5_DATA6 0xFFFFFFFFU 1665 #define EFUSE_KEY5_DATA6_M (EFUSE_KEY5_DATA6_V << EFUSE_KEY5_DATA6_S) 1666 #define EFUSE_KEY5_DATA6_V 0xFFFFFFFFU 1667 #define EFUSE_KEY5_DATA6_S 0 1668 1669 /** EFUSE_RD_KEY5_DATA7_REG register 1670 * Register $n of BLOCK9 (KEY5). 1671 */ 1672 #define EFUSE_RD_KEY5_DATA7_REG (DR_REG_EFUSE_BASE + 0x158) 1673 /** EFUSE_KEY5_DATA7 : RO; bitpos: [31:0]; default: 0; 1674 * Stores the seventh 32 bits of KEY5. 1675 */ 1676 #define EFUSE_KEY5_DATA7 0xFFFFFFFFU 1677 #define EFUSE_KEY5_DATA7_M (EFUSE_KEY5_DATA7_V << EFUSE_KEY5_DATA7_S) 1678 #define EFUSE_KEY5_DATA7_V 0xFFFFFFFFU 1679 #define EFUSE_KEY5_DATA7_S 0 1680 1681 /** EFUSE_RD_SYS_PART2_DATA0_REG register 1682 * Register $n of BLOCK10 (system). 1683 */ 1684 #define EFUSE_RD_SYS_PART2_DATA0_REG (DR_REG_EFUSE_BASE + 0x15c) 1685 /** EFUSE_SYS_DATA_PART2_0 : RO; bitpos: [31:0]; default: 0; 1686 * Stores the $nth 32 bits of the 2nd part of system data. 1687 */ 1688 #define EFUSE_SYS_DATA_PART2_0 0xFFFFFFFFU 1689 #define EFUSE_SYS_DATA_PART2_0_M (EFUSE_SYS_DATA_PART2_0_V << EFUSE_SYS_DATA_PART2_0_S) 1690 #define EFUSE_SYS_DATA_PART2_0_V 0xFFFFFFFFU 1691 #define EFUSE_SYS_DATA_PART2_0_S 0 1692 1693 /** EFUSE_RD_SYS_PART2_DATA1_REG register 1694 * Register $n of BLOCK9 (KEY5). 1695 */ 1696 #define EFUSE_RD_SYS_PART2_DATA1_REG (DR_REG_EFUSE_BASE + 0x160) 1697 /** EFUSE_SYS_DATA_PART2_1 : RO; bitpos: [31:0]; default: 0; 1698 * Stores the $nth 32 bits of the 2nd part of system data. 1699 */ 1700 #define EFUSE_SYS_DATA_PART2_1 0xFFFFFFFFU 1701 #define EFUSE_SYS_DATA_PART2_1_M (EFUSE_SYS_DATA_PART2_1_V << EFUSE_SYS_DATA_PART2_1_S) 1702 #define EFUSE_SYS_DATA_PART2_1_V 0xFFFFFFFFU 1703 #define EFUSE_SYS_DATA_PART2_1_S 0 1704 1705 /** EFUSE_RD_SYS_PART2_DATA2_REG register 1706 * Register $n of BLOCK10 (system). 1707 */ 1708 #define EFUSE_RD_SYS_PART2_DATA2_REG (DR_REG_EFUSE_BASE + 0x164) 1709 /** EFUSE_SYS_DATA_PART2_2 : RO; bitpos: [31:0]; default: 0; 1710 * Stores the $nth 32 bits of the 2nd part of system data. 1711 */ 1712 #define EFUSE_SYS_DATA_PART2_2 0xFFFFFFFFU 1713 #define EFUSE_SYS_DATA_PART2_2_M (EFUSE_SYS_DATA_PART2_2_V << EFUSE_SYS_DATA_PART2_2_S) 1714 #define EFUSE_SYS_DATA_PART2_2_V 0xFFFFFFFFU 1715 #define EFUSE_SYS_DATA_PART2_2_S 0 1716 1717 /** EFUSE_RD_SYS_PART2_DATA3_REG register 1718 * Register $n of BLOCK10 (system). 1719 */ 1720 #define EFUSE_RD_SYS_PART2_DATA3_REG (DR_REG_EFUSE_BASE + 0x168) 1721 /** EFUSE_SYS_DATA_PART2_3 : RO; bitpos: [31:0]; default: 0; 1722 * Stores the $nth 32 bits of the 2nd part of system data. 1723 */ 1724 #define EFUSE_SYS_DATA_PART2_3 0xFFFFFFFFU 1725 #define EFUSE_SYS_DATA_PART2_3_M (EFUSE_SYS_DATA_PART2_3_V << EFUSE_SYS_DATA_PART2_3_S) 1726 #define EFUSE_SYS_DATA_PART2_3_V 0xFFFFFFFFU 1727 #define EFUSE_SYS_DATA_PART2_3_S 0 1728 1729 /** EFUSE_RD_SYS_PART2_DATA4_REG register 1730 * Register $n of BLOCK10 (system). 1731 */ 1732 #define EFUSE_RD_SYS_PART2_DATA4_REG (DR_REG_EFUSE_BASE + 0x16c) 1733 /** EFUSE_SYS_DATA_PART2_4 : RO; bitpos: [31:0]; default: 0; 1734 * Stores the $nth 32 bits of the 2nd part of system data. 1735 */ 1736 #define EFUSE_SYS_DATA_PART2_4 0xFFFFFFFFU 1737 #define EFUSE_SYS_DATA_PART2_4_M (EFUSE_SYS_DATA_PART2_4_V << EFUSE_SYS_DATA_PART2_4_S) 1738 #define EFUSE_SYS_DATA_PART2_4_V 0xFFFFFFFFU 1739 #define EFUSE_SYS_DATA_PART2_4_S 0 1740 1741 /** EFUSE_RD_SYS_PART2_DATA5_REG register 1742 * Register $n of BLOCK10 (system). 1743 */ 1744 #define EFUSE_RD_SYS_PART2_DATA5_REG (DR_REG_EFUSE_BASE + 0x170) 1745 /** EFUSE_SYS_DATA_PART2_5 : RO; bitpos: [31:0]; default: 0; 1746 * Stores the $nth 32 bits of the 2nd part of system data. 1747 */ 1748 #define EFUSE_SYS_DATA_PART2_5 0xFFFFFFFFU 1749 #define EFUSE_SYS_DATA_PART2_5_M (EFUSE_SYS_DATA_PART2_5_V << EFUSE_SYS_DATA_PART2_5_S) 1750 #define EFUSE_SYS_DATA_PART2_5_V 0xFFFFFFFFU 1751 #define EFUSE_SYS_DATA_PART2_5_S 0 1752 1753 /** EFUSE_RD_SYS_PART2_DATA6_REG register 1754 * Register $n of BLOCK10 (system). 1755 */ 1756 #define EFUSE_RD_SYS_PART2_DATA6_REG (DR_REG_EFUSE_BASE + 0x174) 1757 /** EFUSE_SYS_DATA_PART2_6 : RO; bitpos: [31:0]; default: 0; 1758 * Stores the $nth 32 bits of the 2nd part of system data. 1759 */ 1760 #define EFUSE_SYS_DATA_PART2_6 0xFFFFFFFFU 1761 #define EFUSE_SYS_DATA_PART2_6_M (EFUSE_SYS_DATA_PART2_6_V << EFUSE_SYS_DATA_PART2_6_S) 1762 #define EFUSE_SYS_DATA_PART2_6_V 0xFFFFFFFFU 1763 #define EFUSE_SYS_DATA_PART2_6_S 0 1764 1765 /** EFUSE_RD_SYS_PART2_DATA7_REG register 1766 * Register $n of BLOCK10 (system). 1767 */ 1768 #define EFUSE_RD_SYS_PART2_DATA7_REG (DR_REG_EFUSE_BASE + 0x178) 1769 /** EFUSE_SYS_DATA_PART2_7 : RO; bitpos: [31:0]; default: 0; 1770 * Stores the $nth 32 bits of the 2nd part of system data. 1771 */ 1772 #define EFUSE_SYS_DATA_PART2_7 0xFFFFFFFFU 1773 #define EFUSE_SYS_DATA_PART2_7_M (EFUSE_SYS_DATA_PART2_7_V << EFUSE_SYS_DATA_PART2_7_S) 1774 #define EFUSE_SYS_DATA_PART2_7_V 0xFFFFFFFFU 1775 #define EFUSE_SYS_DATA_PART2_7_S 0 1776 1777 /** EFUSE_RD_REPEAT_ERR0_REG register 1778 * Programming error record register 0 of BLOCK0. 1779 */ 1780 #define EFUSE_RD_REPEAT_ERR0_REG (DR_REG_EFUSE_BASE + 0x17c) 1781 /** EFUSE_RD_DIS_ERR : RO; bitpos: [6:0]; default: 0; 1782 * Indicates a programming error of RD_DIS. 1783 */ 1784 #define EFUSE_RD_DIS_ERR 0x0000007FU 1785 #define EFUSE_RD_DIS_ERR_M (EFUSE_RD_DIS_ERR_V << EFUSE_RD_DIS_ERR_S) 1786 #define EFUSE_RD_DIS_ERR_V 0x0000007FU 1787 #define EFUSE_RD_DIS_ERR_S 0 1788 /** EFUSE_RPT4_RESERVED0_ERR_4 : RO; bitpos: [7]; default: 0; 1789 * Reserved. 1790 */ 1791 #define EFUSE_RPT4_RESERVED0_ERR_4 (BIT(7)) 1792 #define EFUSE_RPT4_RESERVED0_ERR_4_M (EFUSE_RPT4_RESERVED0_ERR_4_V << EFUSE_RPT4_RESERVED0_ERR_4_S) 1793 #define EFUSE_RPT4_RESERVED0_ERR_4_V 0x00000001U 1794 #define EFUSE_RPT4_RESERVED0_ERR_4_S 7 1795 /** EFUSE_DIS_ICACHE_ERR : RO; bitpos: [8]; default: 0; 1796 * Indicates a programming error of DIS_ICACHE. 1797 */ 1798 #define EFUSE_DIS_ICACHE_ERR (BIT(8)) 1799 #define EFUSE_DIS_ICACHE_ERR_M (EFUSE_DIS_ICACHE_ERR_V << EFUSE_DIS_ICACHE_ERR_S) 1800 #define EFUSE_DIS_ICACHE_ERR_V 0x00000001U 1801 #define EFUSE_DIS_ICACHE_ERR_S 8 1802 /** EFUSE_DIS_USB_JTAG_ERR : RO; bitpos: [9]; default: 0; 1803 * Indicates a programming error of DIS_USB_JTAG. 1804 */ 1805 #define EFUSE_DIS_USB_JTAG_ERR (BIT(9)) 1806 #define EFUSE_DIS_USB_JTAG_ERR_M (EFUSE_DIS_USB_JTAG_ERR_V << EFUSE_DIS_USB_JTAG_ERR_S) 1807 #define EFUSE_DIS_USB_JTAG_ERR_V 0x00000001U 1808 #define EFUSE_DIS_USB_JTAG_ERR_S 9 1809 /** EFUSE_POWERGLITCH_EN_ERR : RO; bitpos: [10]; default: 0; 1810 * Indicates a programming error of POWERGLITCH_EN. 1811 */ 1812 #define EFUSE_POWERGLITCH_EN_ERR (BIT(10)) 1813 #define EFUSE_POWERGLITCH_EN_ERR_M (EFUSE_POWERGLITCH_EN_ERR_V << EFUSE_POWERGLITCH_EN_ERR_S) 1814 #define EFUSE_POWERGLITCH_EN_ERR_V 0x00000001U 1815 #define EFUSE_POWERGLITCH_EN_ERR_S 10 1816 /** EFUSE_DIS_USB_SERIAL_JTAG_ERR : RO; bitpos: [11]; default: 0; 1817 * Indicates a programming error of DIS_USB_DEVICE. 1818 */ 1819 #define EFUSE_DIS_USB_SERIAL_JTAG_ERR (BIT(11)) 1820 #define EFUSE_DIS_USB_SERIAL_JTAG_ERR_M (EFUSE_DIS_USB_SERIAL_JTAG_ERR_V << EFUSE_DIS_USB_SERIAL_JTAG_ERR_S) 1821 #define EFUSE_DIS_USB_SERIAL_JTAG_ERR_V 0x00000001U 1822 #define EFUSE_DIS_USB_SERIAL_JTAG_ERR_S 11 1823 /** EFUSE_DIS_FORCE_DOWNLOAD_ERR : RO; bitpos: [12]; default: 0; 1824 * Indicates a programming error of DIS_FORCE_DOWNLOAD. 1825 */ 1826 #define EFUSE_DIS_FORCE_DOWNLOAD_ERR (BIT(12)) 1827 #define EFUSE_DIS_FORCE_DOWNLOAD_ERR_M (EFUSE_DIS_FORCE_DOWNLOAD_ERR_V << EFUSE_DIS_FORCE_DOWNLOAD_ERR_S) 1828 #define EFUSE_DIS_FORCE_DOWNLOAD_ERR_V 0x00000001U 1829 #define EFUSE_DIS_FORCE_DOWNLOAD_ERR_S 12 1830 /** EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR : RO; bitpos: [13]; default: 0; 1831 * Indicates a programming error of SPI_DOWNLOAD_MSPI_DIS. 1832 */ 1833 #define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR (BIT(13)) 1834 #define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_M (EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_V << EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_S) 1835 #define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_V 0x00000001U 1836 #define EFUSE_SPI_DOWNLOAD_MSPI_DIS_ERR_S 13 1837 /** EFUSE_DIS_TWAI_ERR : RO; bitpos: [14]; default: 0; 1838 * Indicates a programming error of DIS_CAN. 1839 */ 1840 #define EFUSE_DIS_TWAI_ERR (BIT(14)) 1841 #define EFUSE_DIS_TWAI_ERR_M (EFUSE_DIS_TWAI_ERR_V << EFUSE_DIS_TWAI_ERR_S) 1842 #define EFUSE_DIS_TWAI_ERR_V 0x00000001U 1843 #define EFUSE_DIS_TWAI_ERR_S 14 1844 /** EFUSE_JTAG_SEL_ENABLE_ERR : RO; bitpos: [15]; default: 0; 1845 * Indicates a programming error of JTAG_SEL_ENABLE. 1846 */ 1847 #define EFUSE_JTAG_SEL_ENABLE_ERR (BIT(15)) 1848 #define EFUSE_JTAG_SEL_ENABLE_ERR_M (EFUSE_JTAG_SEL_ENABLE_ERR_V << EFUSE_JTAG_SEL_ENABLE_ERR_S) 1849 #define EFUSE_JTAG_SEL_ENABLE_ERR_V 0x00000001U 1850 #define EFUSE_JTAG_SEL_ENABLE_ERR_S 15 1851 /** EFUSE_SOFT_DIS_JTAG_ERR : RO; bitpos: [18:16]; default: 0; 1852 * Indicates a programming error of SOFT_DIS_JTAG. 1853 */ 1854 #define EFUSE_SOFT_DIS_JTAG_ERR 0x00000007U 1855 #define EFUSE_SOFT_DIS_JTAG_ERR_M (EFUSE_SOFT_DIS_JTAG_ERR_V << EFUSE_SOFT_DIS_JTAG_ERR_S) 1856 #define EFUSE_SOFT_DIS_JTAG_ERR_V 0x00000007U 1857 #define EFUSE_SOFT_DIS_JTAG_ERR_S 16 1858 /** EFUSE_DIS_PAD_JTAG_ERR : RO; bitpos: [19]; default: 0; 1859 * Indicates a programming error of DIS_PAD_JTAG. 1860 */ 1861 #define EFUSE_DIS_PAD_JTAG_ERR (BIT(19)) 1862 #define EFUSE_DIS_PAD_JTAG_ERR_M (EFUSE_DIS_PAD_JTAG_ERR_V << EFUSE_DIS_PAD_JTAG_ERR_S) 1863 #define EFUSE_DIS_PAD_JTAG_ERR_V 0x00000001U 1864 #define EFUSE_DIS_PAD_JTAG_ERR_S 19 1865 /** EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR : RO; bitpos: [20]; default: 0; 1866 * Indicates a programming error of DIS_DOWNLOAD_MANUAL_ENCRYPT. 1867 */ 1868 #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR (BIT(20)) 1869 #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_M (EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V << EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S) 1870 #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V 0x00000001U 1871 #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S 20 1872 /** EFUSE_USB_DREFH_ERR : RO; bitpos: [22:21]; default: 0; 1873 * Indicates a programming error of USB_DREFH. 1874 */ 1875 #define EFUSE_USB_DREFH_ERR 0x00000003U 1876 #define EFUSE_USB_DREFH_ERR_M (EFUSE_USB_DREFH_ERR_V << EFUSE_USB_DREFH_ERR_S) 1877 #define EFUSE_USB_DREFH_ERR_V 0x00000003U 1878 #define EFUSE_USB_DREFH_ERR_S 21 1879 /** EFUSE_USB_DREFL_ERR : RO; bitpos: [24:23]; default: 0; 1880 * Indicates a programming error of USB_DREFL. 1881 */ 1882 #define EFUSE_USB_DREFL_ERR 0x00000003U 1883 #define EFUSE_USB_DREFL_ERR_M (EFUSE_USB_DREFL_ERR_V << EFUSE_USB_DREFL_ERR_S) 1884 #define EFUSE_USB_DREFL_ERR_V 0x00000003U 1885 #define EFUSE_USB_DREFL_ERR_S 23 1886 /** EFUSE_USB_EXCHG_PINS_ERR : RO; bitpos: [25]; default: 0; 1887 * Indicates a programming error of USB_EXCHG_PINS. 1888 */ 1889 #define EFUSE_USB_EXCHG_PINS_ERR (BIT(25)) 1890 #define EFUSE_USB_EXCHG_PINS_ERR_M (EFUSE_USB_EXCHG_PINS_ERR_V << EFUSE_USB_EXCHG_PINS_ERR_S) 1891 #define EFUSE_USB_EXCHG_PINS_ERR_V 0x00000001U 1892 #define EFUSE_USB_EXCHG_PINS_ERR_S 25 1893 /** EFUSE_VDD_SPI_AS_GPIO_ERR : RO; bitpos: [26]; default: 0; 1894 * Indicates a programming error of VDD_SPI_AS_GPIO. 1895 */ 1896 #define EFUSE_VDD_SPI_AS_GPIO_ERR (BIT(26)) 1897 #define EFUSE_VDD_SPI_AS_GPIO_ERR_M (EFUSE_VDD_SPI_AS_GPIO_ERR_V << EFUSE_VDD_SPI_AS_GPIO_ERR_S) 1898 #define EFUSE_VDD_SPI_AS_GPIO_ERR_V 0x00000001U 1899 #define EFUSE_VDD_SPI_AS_GPIO_ERR_S 26 1900 /** EFUSE_RPT4_RESERVED0_ERR_2 : RO; bitpos: [28:27]; default: 0; 1901 * Reserved. 1902 */ 1903 #define EFUSE_RPT4_RESERVED0_ERR_2 0x00000003U 1904 #define EFUSE_RPT4_RESERVED0_ERR_2_M (EFUSE_RPT4_RESERVED0_ERR_2_V << EFUSE_RPT4_RESERVED0_ERR_2_S) 1905 #define EFUSE_RPT4_RESERVED0_ERR_2_V 0x00000003U 1906 #define EFUSE_RPT4_RESERVED0_ERR_2_S 27 1907 /** EFUSE_RPT4_RESERVED0_ERR_1 : RO; bitpos: [29]; default: 0; 1908 * Reserved. 1909 */ 1910 #define EFUSE_RPT4_RESERVED0_ERR_1 (BIT(29)) 1911 #define EFUSE_RPT4_RESERVED0_ERR_1_M (EFUSE_RPT4_RESERVED0_ERR_1_V << EFUSE_RPT4_RESERVED0_ERR_1_S) 1912 #define EFUSE_RPT4_RESERVED0_ERR_1_V 0x00000001U 1913 #define EFUSE_RPT4_RESERVED0_ERR_1_S 29 1914 /** EFUSE_RPT4_RESERVED0_ERR_0 : RO; bitpos: [31:30]; default: 0; 1915 * Reserved. 1916 */ 1917 #define EFUSE_RPT4_RESERVED0_ERR_0 0x00000003U 1918 #define EFUSE_RPT4_RESERVED0_ERR_0_M (EFUSE_RPT4_RESERVED0_ERR_0_V << EFUSE_RPT4_RESERVED0_ERR_0_S) 1919 #define EFUSE_RPT4_RESERVED0_ERR_0_V 0x00000003U 1920 #define EFUSE_RPT4_RESERVED0_ERR_0_S 30 1921 1922 /** EFUSE_RD_REPEAT_ERR1_REG register 1923 * Programming error record register 1 of BLOCK0. 1924 */ 1925 #define EFUSE_RD_REPEAT_ERR1_REG (DR_REG_EFUSE_BASE + 0x180) 1926 /** EFUSE_RPT4_RESERVED1_ERR_0 : RO; bitpos: [15:0]; default: 0; 1927 * Reserved. 1928 */ 1929 #define EFUSE_RPT4_RESERVED1_ERR_0 0x0000FFFFU 1930 #define EFUSE_RPT4_RESERVED1_ERR_0_M (EFUSE_RPT4_RESERVED1_ERR_0_V << EFUSE_RPT4_RESERVED1_ERR_0_S) 1931 #define EFUSE_RPT4_RESERVED1_ERR_0_V 0x0000FFFFU 1932 #define EFUSE_RPT4_RESERVED1_ERR_0_S 0 1933 /** EFUSE_WDT_DELAY_SEL_ERR : RO; bitpos: [17:16]; default: 0; 1934 * Indicates a programming error of WDT_DELAY_SEL. 1935 */ 1936 #define EFUSE_WDT_DELAY_SEL_ERR 0x00000003U 1937 #define EFUSE_WDT_DELAY_SEL_ERR_M (EFUSE_WDT_DELAY_SEL_ERR_V << EFUSE_WDT_DELAY_SEL_ERR_S) 1938 #define EFUSE_WDT_DELAY_SEL_ERR_V 0x00000003U 1939 #define EFUSE_WDT_DELAY_SEL_ERR_S 16 1940 /** EFUSE_SPI_BOOT_CRYPT_CNT_ERR : RO; bitpos: [20:18]; default: 0; 1941 * Indicates a programming error of SPI_BOOT_CRYPT_CNT. 1942 */ 1943 #define EFUSE_SPI_BOOT_CRYPT_CNT_ERR 0x00000007U 1944 #define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_M (EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V << EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S) 1945 #define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V 0x00000007U 1946 #define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S 18 1947 /** EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR : RO; bitpos: [21]; default: 0; 1948 * Indicates a programming error of SECURE_BOOT_KEY_REVOKE0. 1949 */ 1950 #define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR (BIT(21)) 1951 #define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_M (EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_S) 1952 #define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_V 0x00000001U 1953 #define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_S 21 1954 /** EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR : RO; bitpos: [22]; default: 0; 1955 * Indicates a programming error of SECURE_BOOT_KEY_REVOKE1. 1956 */ 1957 #define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR (BIT(22)) 1958 #define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_M (EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_S) 1959 #define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_V 0x00000001U 1960 #define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_S 22 1961 /** EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR : RO; bitpos: [23]; default: 0; 1962 * Indicates a programming error of SECURE_BOOT_KEY_REVOKE2. 1963 */ 1964 #define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR (BIT(23)) 1965 #define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_M (EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_S) 1966 #define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_V 0x00000001U 1967 #define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_S 23 1968 /** EFUSE_KEY_PURPOSE_0_ERR : RO; bitpos: [27:24]; default: 0; 1969 * Indicates a programming error of KEY_PURPOSE_0. 1970 */ 1971 #define EFUSE_KEY_PURPOSE_0_ERR 0x0000000FU 1972 #define EFUSE_KEY_PURPOSE_0_ERR_M (EFUSE_KEY_PURPOSE_0_ERR_V << EFUSE_KEY_PURPOSE_0_ERR_S) 1973 #define EFUSE_KEY_PURPOSE_0_ERR_V 0x0000000FU 1974 #define EFUSE_KEY_PURPOSE_0_ERR_S 24 1975 /** EFUSE_KEY_PURPOSE_1_ERR : RO; bitpos: [31:28]; default: 0; 1976 * Indicates a programming error of KEY_PURPOSE_1. 1977 */ 1978 #define EFUSE_KEY_PURPOSE_1_ERR 0x0000000FU 1979 #define EFUSE_KEY_PURPOSE_1_ERR_M (EFUSE_KEY_PURPOSE_1_ERR_V << EFUSE_KEY_PURPOSE_1_ERR_S) 1980 #define EFUSE_KEY_PURPOSE_1_ERR_V 0x0000000FU 1981 #define EFUSE_KEY_PURPOSE_1_ERR_S 28 1982 1983 /** EFUSE_RD_REPEAT_ERR2_REG register 1984 * Programming error record register 2 of BLOCK0. 1985 */ 1986 #define EFUSE_RD_REPEAT_ERR2_REG (DR_REG_EFUSE_BASE + 0x184) 1987 /** EFUSE_KEY_PURPOSE_2_ERR : RO; bitpos: [3:0]; default: 0; 1988 * Indicates a programming error of KEY_PURPOSE_2. 1989 */ 1990 #define EFUSE_KEY_PURPOSE_2_ERR 0x0000000FU 1991 #define EFUSE_KEY_PURPOSE_2_ERR_M (EFUSE_KEY_PURPOSE_2_ERR_V << EFUSE_KEY_PURPOSE_2_ERR_S) 1992 #define EFUSE_KEY_PURPOSE_2_ERR_V 0x0000000FU 1993 #define EFUSE_KEY_PURPOSE_2_ERR_S 0 1994 /** EFUSE_KEY_PURPOSE_3_ERR : RO; bitpos: [7:4]; default: 0; 1995 * Indicates a programming error of KEY_PURPOSE_3. 1996 */ 1997 #define EFUSE_KEY_PURPOSE_3_ERR 0x0000000FU 1998 #define EFUSE_KEY_PURPOSE_3_ERR_M (EFUSE_KEY_PURPOSE_3_ERR_V << EFUSE_KEY_PURPOSE_3_ERR_S) 1999 #define EFUSE_KEY_PURPOSE_3_ERR_V 0x0000000FU 2000 #define EFUSE_KEY_PURPOSE_3_ERR_S 4 2001 /** EFUSE_KEY_PURPOSE_4_ERR : RO; bitpos: [11:8]; default: 0; 2002 * Indicates a programming error of KEY_PURPOSE_4. 2003 */ 2004 #define EFUSE_KEY_PURPOSE_4_ERR 0x0000000FU 2005 #define EFUSE_KEY_PURPOSE_4_ERR_M (EFUSE_KEY_PURPOSE_4_ERR_V << EFUSE_KEY_PURPOSE_4_ERR_S) 2006 #define EFUSE_KEY_PURPOSE_4_ERR_V 0x0000000FU 2007 #define EFUSE_KEY_PURPOSE_4_ERR_S 8 2008 /** EFUSE_KEY_PURPOSE_5_ERR : RO; bitpos: [15:12]; default: 0; 2009 * Indicates a programming error of KEY_PURPOSE_5. 2010 */ 2011 #define EFUSE_KEY_PURPOSE_5_ERR 0x0000000FU 2012 #define EFUSE_KEY_PURPOSE_5_ERR_M (EFUSE_KEY_PURPOSE_5_ERR_V << EFUSE_KEY_PURPOSE_5_ERR_S) 2013 #define EFUSE_KEY_PURPOSE_5_ERR_V 0x0000000FU 2014 #define EFUSE_KEY_PURPOSE_5_ERR_S 12 2015 /** EFUSE_SEC_DPA_LEVEL_ERR : RO; bitpos: [17:16]; default: 0; 2016 * Indicates a programming error of SEC_DPA_LEVEL. 2017 */ 2018 #define EFUSE_SEC_DPA_LEVEL_ERR 0x00000003U 2019 #define EFUSE_SEC_DPA_LEVEL_ERR_M (EFUSE_SEC_DPA_LEVEL_ERR_V << EFUSE_SEC_DPA_LEVEL_ERR_S) 2020 #define EFUSE_SEC_DPA_LEVEL_ERR_V 0x00000003U 2021 #define EFUSE_SEC_DPA_LEVEL_ERR_S 16 2022 /** EFUSE_RPT4_RESERVED2_ERR_1 : RO; bitpos: [18]; default: 0; 2023 * Reserved. 2024 */ 2025 #define EFUSE_RPT4_RESERVED2_ERR_1 (BIT(18)) 2026 #define EFUSE_RPT4_RESERVED2_ERR_1_M (EFUSE_RPT4_RESERVED2_ERR_1_V << EFUSE_RPT4_RESERVED2_ERR_1_S) 2027 #define EFUSE_RPT4_RESERVED2_ERR_1_V 0x00000001U 2028 #define EFUSE_RPT4_RESERVED2_ERR_1_S 18 2029 /** EFUSE_CRYPT_DPA_ENABLE_ERR : RO; bitpos: [19]; default: 0; 2030 * Indicates a programming error of CRYPT_DPA_ENABLE. 2031 */ 2032 #define EFUSE_CRYPT_DPA_ENABLE_ERR (BIT(19)) 2033 #define EFUSE_CRYPT_DPA_ENABLE_ERR_M (EFUSE_CRYPT_DPA_ENABLE_ERR_V << EFUSE_CRYPT_DPA_ENABLE_ERR_S) 2034 #define EFUSE_CRYPT_DPA_ENABLE_ERR_V 0x00000001U 2035 #define EFUSE_CRYPT_DPA_ENABLE_ERR_S 19 2036 /** EFUSE_SECURE_BOOT_EN_ERR : RO; bitpos: [20]; default: 0; 2037 * Indicates a programming error of SECURE_BOOT_EN. 2038 */ 2039 #define EFUSE_SECURE_BOOT_EN_ERR (BIT(20)) 2040 #define EFUSE_SECURE_BOOT_EN_ERR_M (EFUSE_SECURE_BOOT_EN_ERR_V << EFUSE_SECURE_BOOT_EN_ERR_S) 2041 #define EFUSE_SECURE_BOOT_EN_ERR_V 0x00000001U 2042 #define EFUSE_SECURE_BOOT_EN_ERR_S 20 2043 /** EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR : RO; bitpos: [21]; default: 0; 2044 * Indicates a programming error of SECURE_BOOT_AGGRESSIVE_REVOKE. 2045 */ 2046 #define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR (BIT(21)) 2047 #define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_M (EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_V << EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_S) 2048 #define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_V 0x00000001U 2049 #define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_S 21 2050 /** EFUSE_RPT4_RESERVED2_ERR_0 : RO; bitpos: [27:22]; default: 0; 2051 * Reserved. 2052 */ 2053 #define EFUSE_RPT4_RESERVED2_ERR_0 0x0000003FU 2054 #define EFUSE_RPT4_RESERVED2_ERR_0_M (EFUSE_RPT4_RESERVED2_ERR_0_V << EFUSE_RPT4_RESERVED2_ERR_0_S) 2055 #define EFUSE_RPT4_RESERVED2_ERR_0_V 0x0000003FU 2056 #define EFUSE_RPT4_RESERVED2_ERR_0_S 22 2057 /** EFUSE_FLASH_TPUW_ERR : RO; bitpos: [31:28]; default: 0; 2058 * Indicates a programming error of FLASH_TPUW. 2059 */ 2060 #define EFUSE_FLASH_TPUW_ERR 0x0000000FU 2061 #define EFUSE_FLASH_TPUW_ERR_M (EFUSE_FLASH_TPUW_ERR_V << EFUSE_FLASH_TPUW_ERR_S) 2062 #define EFUSE_FLASH_TPUW_ERR_V 0x0000000FU 2063 #define EFUSE_FLASH_TPUW_ERR_S 28 2064 2065 /** EFUSE_RD_REPEAT_ERR3_REG register 2066 * Programming error record register 3 of BLOCK0. 2067 */ 2068 #define EFUSE_RD_REPEAT_ERR3_REG (DR_REG_EFUSE_BASE + 0x188) 2069 /** EFUSE_DIS_DOWNLOAD_MODE_ERR : RO; bitpos: [0]; default: 0; 2070 * Indicates a programming error of DIS_DOWNLOAD_MODE. 2071 */ 2072 #define EFUSE_DIS_DOWNLOAD_MODE_ERR (BIT(0)) 2073 #define EFUSE_DIS_DOWNLOAD_MODE_ERR_M (EFUSE_DIS_DOWNLOAD_MODE_ERR_V << EFUSE_DIS_DOWNLOAD_MODE_ERR_S) 2074 #define EFUSE_DIS_DOWNLOAD_MODE_ERR_V 0x00000001U 2075 #define EFUSE_DIS_DOWNLOAD_MODE_ERR_S 0 2076 /** EFUSE_DIS_DIRECT_BOOT_ERR : RO; bitpos: [1]; default: 0; 2077 * Indicates a programming error of DIS_DIRECT_BOOT. 2078 */ 2079 #define EFUSE_DIS_DIRECT_BOOT_ERR (BIT(1)) 2080 #define EFUSE_DIS_DIRECT_BOOT_ERR_M (EFUSE_DIS_DIRECT_BOOT_ERR_V << EFUSE_DIS_DIRECT_BOOT_ERR_S) 2081 #define EFUSE_DIS_DIRECT_BOOT_ERR_V 0x00000001U 2082 #define EFUSE_DIS_DIRECT_BOOT_ERR_S 1 2083 /** EFUSE_USB_PRINT_ERR : RO; bitpos: [2]; default: 0; 2084 * Indicates a programming error of UART_PRINT_CHANNEL. 2085 */ 2086 #define EFUSE_USB_PRINT_ERR (BIT(2)) 2087 #define EFUSE_USB_PRINT_ERR_M (EFUSE_USB_PRINT_ERR_V << EFUSE_USB_PRINT_ERR_S) 2088 #define EFUSE_USB_PRINT_ERR_V 0x00000001U 2089 #define EFUSE_USB_PRINT_ERR_S 2 2090 /** EFUSE_RPT4_RESERVED3_ERR_5 : RO; bitpos: [3]; default: 0; 2091 * Reserved. 2092 */ 2093 #define EFUSE_RPT4_RESERVED3_ERR_5 (BIT(3)) 2094 #define EFUSE_RPT4_RESERVED3_ERR_5_M (EFUSE_RPT4_RESERVED3_ERR_5_V << EFUSE_RPT4_RESERVED3_ERR_5_S) 2095 #define EFUSE_RPT4_RESERVED3_ERR_5_V 0x00000001U 2096 #define EFUSE_RPT4_RESERVED3_ERR_5_S 3 2097 /** EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR : RO; bitpos: [4]; default: 0; 2098 * Indicates a programming error of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE. 2099 */ 2100 #define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR (BIT(4)) 2101 #define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_M (EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_V << EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_S) 2102 #define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_V 0x00000001U 2103 #define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_S 4 2104 /** EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR : RO; bitpos: [5]; default: 0; 2105 * Indicates a programming error of ENABLE_SECURITY_DOWNLOAD. 2106 */ 2107 #define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR (BIT(5)) 2108 #define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_M (EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_V << EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_S) 2109 #define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_V 0x00000001U 2110 #define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_S 5 2111 /** EFUSE_UART_PRINT_CONTROL_ERR : RO; bitpos: [7:6]; default: 0; 2112 * Indicates a programming error of UART_PRINT_CONTROL. 2113 */ 2114 #define EFUSE_UART_PRINT_CONTROL_ERR 0x00000003U 2115 #define EFUSE_UART_PRINT_CONTROL_ERR_M (EFUSE_UART_PRINT_CONTROL_ERR_V << EFUSE_UART_PRINT_CONTROL_ERR_S) 2116 #define EFUSE_UART_PRINT_CONTROL_ERR_V 0x00000003U 2117 #define EFUSE_UART_PRINT_CONTROL_ERR_S 6 2118 /** EFUSE_FORCE_SEND_RESUME_ERR : RO; bitpos: [8]; default: 0; 2119 * Indicates a programming error of FORCE_SEND_RESUME. 2120 */ 2121 #define EFUSE_FORCE_SEND_RESUME_ERR (BIT(8)) 2122 #define EFUSE_FORCE_SEND_RESUME_ERR_M (EFUSE_FORCE_SEND_RESUME_ERR_V << EFUSE_FORCE_SEND_RESUME_ERR_S) 2123 #define EFUSE_FORCE_SEND_RESUME_ERR_V 0x00000001U 2124 #define EFUSE_FORCE_SEND_RESUME_ERR_S 8 2125 /** EFUSE_SECURE_VERSION_ERR : RO; bitpos: [24:9]; default: 0; 2126 * Indicates a programming error of SECURE VERSION. 2127 */ 2128 #define EFUSE_SECURE_VERSION_ERR 0x0000FFFFU 2129 #define EFUSE_SECURE_VERSION_ERR_M (EFUSE_SECURE_VERSION_ERR_V << EFUSE_SECURE_VERSION_ERR_S) 2130 #define EFUSE_SECURE_VERSION_ERR_V 0x0000FFFFU 2131 #define EFUSE_SECURE_VERSION_ERR_S 9 2132 /** EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR : RO; bitpos: [25]; default: 0; 2133 * Indicates a programming error of SECURE_BOOT_DISABLE_FAST_WAKE. 2134 */ 2135 #define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR (BIT(25)) 2136 #define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_M (EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_V << EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_S) 2137 #define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_V 0x00000001U 2138 #define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_ERR_S 25 2139 /** EFUSE_HYS_EN_PAD0_ERR : RO; bitpos: [31:26]; default: 0; 2140 * Indicates a programming error of HYS_EN_PAD0. 2141 */ 2142 #define EFUSE_HYS_EN_PAD0_ERR 0x0000003FU 2143 #define EFUSE_HYS_EN_PAD0_ERR_M (EFUSE_HYS_EN_PAD0_ERR_V << EFUSE_HYS_EN_PAD0_ERR_S) 2144 #define EFUSE_HYS_EN_PAD0_ERR_V 0x0000003FU 2145 #define EFUSE_HYS_EN_PAD0_ERR_S 26 2146 2147 /** EFUSE_RD_REPEAT_ERR4_REG register 2148 * Programming error record register 4 of BLOCK0. 2149 */ 2150 #define EFUSE_RD_REPEAT_ERR4_REG (DR_REG_EFUSE_BASE + 0x18c) 2151 /** EFUSE_HYS_EN_PAD1_ERR : RO; bitpos: [21:0]; default: 0; 2152 * Indicates a programming error of HYS_EN_PAD1. 2153 */ 2154 #define EFUSE_HYS_EN_PAD1_ERR 0x003FFFFFU 2155 #define EFUSE_HYS_EN_PAD1_ERR_M (EFUSE_HYS_EN_PAD1_ERR_V << EFUSE_HYS_EN_PAD1_ERR_S) 2156 #define EFUSE_HYS_EN_PAD1_ERR_V 0x003FFFFFU 2157 #define EFUSE_HYS_EN_PAD1_ERR_S 0 2158 /** EFUSE_RPT4_RESERVED4_ERR_1 : RO; bitpos: [23:22]; default: 0; 2159 * Reserved. 2160 */ 2161 #define EFUSE_RPT4_RESERVED4_ERR_1 0x00000003U 2162 #define EFUSE_RPT4_RESERVED4_ERR_1_M (EFUSE_RPT4_RESERVED4_ERR_1_V << EFUSE_RPT4_RESERVED4_ERR_1_S) 2163 #define EFUSE_RPT4_RESERVED4_ERR_1_V 0x00000003U 2164 #define EFUSE_RPT4_RESERVED4_ERR_1_S 22 2165 /** EFUSE_RPT4_RESERVED4_ERR_0 : RO; bitpos: [31:24]; default: 0; 2166 * Reserved. 2167 */ 2168 #define EFUSE_RPT4_RESERVED4_ERR_0 0x000000FFU 2169 #define EFUSE_RPT4_RESERVED4_ERR_0_M (EFUSE_RPT4_RESERVED4_ERR_0_V << EFUSE_RPT4_RESERVED4_ERR_0_S) 2170 #define EFUSE_RPT4_RESERVED4_ERR_0_V 0x000000FFU 2171 #define EFUSE_RPT4_RESERVED4_ERR_0_S 24 2172 2173 /** EFUSE_RD_RS_ERR0_REG register 2174 * Programming error record register 0 of BLOCK1-10. 2175 */ 2176 #define EFUSE_RD_RS_ERR0_REG (DR_REG_EFUSE_BASE + 0x1c0) 2177 /** EFUSE_MAC_SPI_8M_ERR_NUM : RO; bitpos: [2:0]; default: 0; 2178 * The value of this signal means the number of error bytes. 2179 */ 2180 #define EFUSE_MAC_SPI_8M_ERR_NUM 0x00000007U 2181 #define EFUSE_MAC_SPI_8M_ERR_NUM_M (EFUSE_MAC_SPI_8M_ERR_NUM_V << EFUSE_MAC_SPI_8M_ERR_NUM_S) 2182 #define EFUSE_MAC_SPI_8M_ERR_NUM_V 0x00000007U 2183 #define EFUSE_MAC_SPI_8M_ERR_NUM_S 0 2184 /** EFUSE_MAC_SPI_8M_FAIL : RO; bitpos: [3]; default: 0; 2185 * 0: Means no failure and that the data of MAC_SPI_8M is reliable 1: Means that 2186 * programming user data failed and the number of error bytes is over 6. 2187 */ 2188 #define EFUSE_MAC_SPI_8M_FAIL (BIT(3)) 2189 #define EFUSE_MAC_SPI_8M_FAIL_M (EFUSE_MAC_SPI_8M_FAIL_V << EFUSE_MAC_SPI_8M_FAIL_S) 2190 #define EFUSE_MAC_SPI_8M_FAIL_V 0x00000001U 2191 #define EFUSE_MAC_SPI_8M_FAIL_S 3 2192 /** EFUSE_SYS_PART1_NUM : RO; bitpos: [6:4]; default: 0; 2193 * The value of this signal means the number of error bytes. 2194 */ 2195 #define EFUSE_SYS_PART1_NUM 0x00000007U 2196 #define EFUSE_SYS_PART1_NUM_M (EFUSE_SYS_PART1_NUM_V << EFUSE_SYS_PART1_NUM_S) 2197 #define EFUSE_SYS_PART1_NUM_V 0x00000007U 2198 #define EFUSE_SYS_PART1_NUM_S 4 2199 /** EFUSE_SYS_PART1_FAIL : RO; bitpos: [7]; default: 0; 2200 * 0: Means no failure and that the data of system part1 is reliable 1: Means that 2201 * programming user data failed and the number of error bytes is over 6. 2202 */ 2203 #define EFUSE_SYS_PART1_FAIL (BIT(7)) 2204 #define EFUSE_SYS_PART1_FAIL_M (EFUSE_SYS_PART1_FAIL_V << EFUSE_SYS_PART1_FAIL_S) 2205 #define EFUSE_SYS_PART1_FAIL_V 0x00000001U 2206 #define EFUSE_SYS_PART1_FAIL_S 7 2207 /** EFUSE_USR_DATA_ERR_NUM : RO; bitpos: [10:8]; default: 0; 2208 * The value of this signal means the number of error bytes. 2209 */ 2210 #define EFUSE_USR_DATA_ERR_NUM 0x00000007U 2211 #define EFUSE_USR_DATA_ERR_NUM_M (EFUSE_USR_DATA_ERR_NUM_V << EFUSE_USR_DATA_ERR_NUM_S) 2212 #define EFUSE_USR_DATA_ERR_NUM_V 0x00000007U 2213 #define EFUSE_USR_DATA_ERR_NUM_S 8 2214 /** EFUSE_USR_DATA_FAIL : RO; bitpos: [11]; default: 0; 2215 * 0: Means no failure and that the user data is reliable 1: Means that programming 2216 * user data failed and the number of error bytes is over 6. 2217 */ 2218 #define EFUSE_USR_DATA_FAIL (BIT(11)) 2219 #define EFUSE_USR_DATA_FAIL_M (EFUSE_USR_DATA_FAIL_V << EFUSE_USR_DATA_FAIL_S) 2220 #define EFUSE_USR_DATA_FAIL_V 0x00000001U 2221 #define EFUSE_USR_DATA_FAIL_S 11 2222 /** EFUSE_KEY0_ERR_NUM : RO; bitpos: [14:12]; default: 0; 2223 * The value of this signal means the number of error bytes. 2224 */ 2225 #define EFUSE_KEY0_ERR_NUM 0x00000007U 2226 #define EFUSE_KEY0_ERR_NUM_M (EFUSE_KEY0_ERR_NUM_V << EFUSE_KEY0_ERR_NUM_S) 2227 #define EFUSE_KEY0_ERR_NUM_V 0x00000007U 2228 #define EFUSE_KEY0_ERR_NUM_S 12 2229 /** EFUSE_KEY0_FAIL : RO; bitpos: [15]; default: 0; 2230 * 0: Means no failure and that the data of key0 is reliable 1: Means that programming 2231 * key0 failed and the number of error bytes is over 6. 2232 */ 2233 #define EFUSE_KEY0_FAIL (BIT(15)) 2234 #define EFUSE_KEY0_FAIL_M (EFUSE_KEY0_FAIL_V << EFUSE_KEY0_FAIL_S) 2235 #define EFUSE_KEY0_FAIL_V 0x00000001U 2236 #define EFUSE_KEY0_FAIL_S 15 2237 /** EFUSE_KEY1_ERR_NUM : RO; bitpos: [18:16]; default: 0; 2238 * The value of this signal means the number of error bytes. 2239 */ 2240 #define EFUSE_KEY1_ERR_NUM 0x00000007U 2241 #define EFUSE_KEY1_ERR_NUM_M (EFUSE_KEY1_ERR_NUM_V << EFUSE_KEY1_ERR_NUM_S) 2242 #define EFUSE_KEY1_ERR_NUM_V 0x00000007U 2243 #define EFUSE_KEY1_ERR_NUM_S 16 2244 /** EFUSE_KEY1_FAIL : RO; bitpos: [19]; default: 0; 2245 * 0: Means no failure and that the data of key1 is reliable 1: Means that programming 2246 * key1 failed and the number of error bytes is over 6. 2247 */ 2248 #define EFUSE_KEY1_FAIL (BIT(19)) 2249 #define EFUSE_KEY1_FAIL_M (EFUSE_KEY1_FAIL_V << EFUSE_KEY1_FAIL_S) 2250 #define EFUSE_KEY1_FAIL_V 0x00000001U 2251 #define EFUSE_KEY1_FAIL_S 19 2252 /** EFUSE_KEY2_ERR_NUM : RO; bitpos: [22:20]; default: 0; 2253 * The value of this signal means the number of error bytes. 2254 */ 2255 #define EFUSE_KEY2_ERR_NUM 0x00000007U 2256 #define EFUSE_KEY2_ERR_NUM_M (EFUSE_KEY2_ERR_NUM_V << EFUSE_KEY2_ERR_NUM_S) 2257 #define EFUSE_KEY2_ERR_NUM_V 0x00000007U 2258 #define EFUSE_KEY2_ERR_NUM_S 20 2259 /** EFUSE_KEY2_FAIL : RO; bitpos: [23]; default: 0; 2260 * 0: Means no failure and that the data of key2 is reliable 1: Means that programming 2261 * key2 failed and the number of error bytes is over 6. 2262 */ 2263 #define EFUSE_KEY2_FAIL (BIT(23)) 2264 #define EFUSE_KEY2_FAIL_M (EFUSE_KEY2_FAIL_V << EFUSE_KEY2_FAIL_S) 2265 #define EFUSE_KEY2_FAIL_V 0x00000001U 2266 #define EFUSE_KEY2_FAIL_S 23 2267 /** EFUSE_KEY3_ERR_NUM : RO; bitpos: [26:24]; default: 0; 2268 * The value of this signal means the number of error bytes. 2269 */ 2270 #define EFUSE_KEY3_ERR_NUM 0x00000007U 2271 #define EFUSE_KEY3_ERR_NUM_M (EFUSE_KEY3_ERR_NUM_V << EFUSE_KEY3_ERR_NUM_S) 2272 #define EFUSE_KEY3_ERR_NUM_V 0x00000007U 2273 #define EFUSE_KEY3_ERR_NUM_S 24 2274 /** EFUSE_KEY3_FAIL : RO; bitpos: [27]; default: 0; 2275 * 0: Means no failure and that the data of key3 is reliable 1: Means that programming 2276 * key3 failed and the number of error bytes is over 6. 2277 */ 2278 #define EFUSE_KEY3_FAIL (BIT(27)) 2279 #define EFUSE_KEY3_FAIL_M (EFUSE_KEY3_FAIL_V << EFUSE_KEY3_FAIL_S) 2280 #define EFUSE_KEY3_FAIL_V 0x00000001U 2281 #define EFUSE_KEY3_FAIL_S 27 2282 /** EFUSE_KEY4_ERR_NUM : RO; bitpos: [30:28]; default: 0; 2283 * The value of this signal means the number of error bytes. 2284 */ 2285 #define EFUSE_KEY4_ERR_NUM 0x00000007U 2286 #define EFUSE_KEY4_ERR_NUM_M (EFUSE_KEY4_ERR_NUM_V << EFUSE_KEY4_ERR_NUM_S) 2287 #define EFUSE_KEY4_ERR_NUM_V 0x00000007U 2288 #define EFUSE_KEY4_ERR_NUM_S 28 2289 /** EFUSE_KEY4_FAIL : RO; bitpos: [31]; default: 0; 2290 * 0: Means no failure and that the data of key4 is reliable 1: Means that programming 2291 * key4 failed and the number of error bytes is over 6. 2292 */ 2293 #define EFUSE_KEY4_FAIL (BIT(31)) 2294 #define EFUSE_KEY4_FAIL_M (EFUSE_KEY4_FAIL_V << EFUSE_KEY4_FAIL_S) 2295 #define EFUSE_KEY4_FAIL_V 0x00000001U 2296 #define EFUSE_KEY4_FAIL_S 31 2297 2298 /** EFUSE_RD_RS_ERR1_REG register 2299 * Programming error record register 1 of BLOCK1-10. 2300 */ 2301 #define EFUSE_RD_RS_ERR1_REG (DR_REG_EFUSE_BASE + 0x1c4) 2302 /** EFUSE_KEY5_ERR_NUM : RO; bitpos: [2:0]; default: 0; 2303 * The value of this signal means the number of error bytes. 2304 */ 2305 #define EFUSE_KEY5_ERR_NUM 0x00000007U 2306 #define EFUSE_KEY5_ERR_NUM_M (EFUSE_KEY5_ERR_NUM_V << EFUSE_KEY5_ERR_NUM_S) 2307 #define EFUSE_KEY5_ERR_NUM_V 0x00000007U 2308 #define EFUSE_KEY5_ERR_NUM_S 0 2309 /** EFUSE_KEY5_FAIL : RO; bitpos: [3]; default: 0; 2310 * 0: Means no failure and that the data of key5 is reliable 1: Means that programming 2311 * key5 failed and the number of error bytes is over 6. 2312 */ 2313 #define EFUSE_KEY5_FAIL (BIT(3)) 2314 #define EFUSE_KEY5_FAIL_M (EFUSE_KEY5_FAIL_V << EFUSE_KEY5_FAIL_S) 2315 #define EFUSE_KEY5_FAIL_V 0x00000001U 2316 #define EFUSE_KEY5_FAIL_S 3 2317 /** EFUSE_SYS_PART2_ERR_NUM : RO; bitpos: [6:4]; default: 0; 2318 * The value of this signal means the number of error bytes. 2319 */ 2320 #define EFUSE_SYS_PART2_ERR_NUM 0x00000007U 2321 #define EFUSE_SYS_PART2_ERR_NUM_M (EFUSE_SYS_PART2_ERR_NUM_V << EFUSE_SYS_PART2_ERR_NUM_S) 2322 #define EFUSE_SYS_PART2_ERR_NUM_V 0x00000007U 2323 #define EFUSE_SYS_PART2_ERR_NUM_S 4 2324 /** EFUSE_SYS_PART2_FAIL : RO; bitpos: [7]; default: 0; 2325 * 0: Means no failure and that the data of system part2 is reliable 1: Means that 2326 * programming user data failed and the number of error bytes is over 6. 2327 */ 2328 #define EFUSE_SYS_PART2_FAIL (BIT(7)) 2329 #define EFUSE_SYS_PART2_FAIL_M (EFUSE_SYS_PART2_FAIL_V << EFUSE_SYS_PART2_FAIL_S) 2330 #define EFUSE_SYS_PART2_FAIL_V 0x00000001U 2331 #define EFUSE_SYS_PART2_FAIL_S 7 2332 2333 /** EFUSE_CLK_REG register 2334 * eFuse clcok configuration register. 2335 */ 2336 #define EFUSE_CLK_REG (DR_REG_EFUSE_BASE + 0x1c8) 2337 /** EFUSE_MEM_FORCE_PD : R/W; bitpos: [0]; default: 0; 2338 * Set this bit to force eFuse SRAM into power-saving mode. 2339 */ 2340 #define EFUSE_MEM_FORCE_PD (BIT(0)) 2341 #define EFUSE_MEM_FORCE_PD_M (EFUSE_MEM_FORCE_PD_V << EFUSE_MEM_FORCE_PD_S) 2342 #define EFUSE_MEM_FORCE_PD_V 0x00000001U 2343 #define EFUSE_MEM_FORCE_PD_S 0 2344 /** EFUSE_MEM_CLK_FORCE_ON : R/W; bitpos: [1]; default: 1; 2345 * Set this bit and force to activate clock signal of eFuse SRAM. 2346 */ 2347 #define EFUSE_MEM_CLK_FORCE_ON (BIT(1)) 2348 #define EFUSE_MEM_CLK_FORCE_ON_M (EFUSE_MEM_CLK_FORCE_ON_V << EFUSE_MEM_CLK_FORCE_ON_S) 2349 #define EFUSE_MEM_CLK_FORCE_ON_V 0x00000001U 2350 #define EFUSE_MEM_CLK_FORCE_ON_S 1 2351 /** EFUSE_MEM_FORCE_PU : R/W; bitpos: [2]; default: 0; 2352 * Set this bit to force eFuse SRAM into working mode. 2353 */ 2354 #define EFUSE_MEM_FORCE_PU (BIT(2)) 2355 #define EFUSE_MEM_FORCE_PU_M (EFUSE_MEM_FORCE_PU_V << EFUSE_MEM_FORCE_PU_S) 2356 #define EFUSE_MEM_FORCE_PU_V 0x00000001U 2357 #define EFUSE_MEM_FORCE_PU_S 2 2358 /** EFUSE_CLK_EN : R/W; bitpos: [16]; default: 0; 2359 * Set this bit to force enable eFuse register configuration clock signal. 2360 */ 2361 #define EFUSE_CLK_EN (BIT(16)) 2362 #define EFUSE_CLK_EN_M (EFUSE_CLK_EN_V << EFUSE_CLK_EN_S) 2363 #define EFUSE_CLK_EN_V 0x00000001U 2364 #define EFUSE_CLK_EN_S 16 2365 2366 /** EFUSE_CONF_REG register 2367 * eFuse operation mode configuraiton register 2368 */ 2369 #define EFUSE_CONF_REG (DR_REG_EFUSE_BASE + 0x1cc) 2370 /** EFUSE_OP_CODE : R/W; bitpos: [15:0]; default: 0; 2371 * 0x5A5A: programming operation command 0x5AA5: read operation command. 2372 */ 2373 #define EFUSE_OP_CODE 0x0000FFFFU 2374 #define EFUSE_OP_CODE_M (EFUSE_OP_CODE_V << EFUSE_OP_CODE_S) 2375 #define EFUSE_OP_CODE_V 0x0000FFFFU 2376 #define EFUSE_OP_CODE_S 0 2377 /** EFUSE_CFG_ECDSA_BLK : R/W; bitpos: [19:16]; default: 0; 2378 * Configures which block to use for ECDSA key output. 2379 */ 2380 #define EFUSE_CFG_ECDSA_BLK 0x0000000FU 2381 #define EFUSE_CFG_ECDSA_BLK_M (EFUSE_CFG_ECDSA_BLK_V << EFUSE_CFG_ECDSA_BLK_S) 2382 #define EFUSE_CFG_ECDSA_BLK_V 0x0000000FU 2383 #define EFUSE_CFG_ECDSA_BLK_S 16 2384 2385 /** EFUSE_STATUS_REG register 2386 * eFuse status register. 2387 */ 2388 #define EFUSE_STATUS_REG (DR_REG_EFUSE_BASE + 0x1d0) 2389 /** EFUSE_STATE : RO; bitpos: [3:0]; default: 0; 2390 * Indicates the state of the eFuse state machine. 2391 */ 2392 #define EFUSE_STATE 0x0000000FU 2393 #define EFUSE_STATE_M (EFUSE_STATE_V << EFUSE_STATE_S) 2394 #define EFUSE_STATE_V 0x0000000FU 2395 #define EFUSE_STATE_S 0 2396 /** EFUSE_OTP_LOAD_SW : RO; bitpos: [4]; default: 0; 2397 * The value of OTP_LOAD_SW. 2398 */ 2399 #define EFUSE_OTP_LOAD_SW (BIT(4)) 2400 #define EFUSE_OTP_LOAD_SW_M (EFUSE_OTP_LOAD_SW_V << EFUSE_OTP_LOAD_SW_S) 2401 #define EFUSE_OTP_LOAD_SW_V 0x00000001U 2402 #define EFUSE_OTP_LOAD_SW_S 4 2403 /** EFUSE_OTP_VDDQ_C_SYNC2 : RO; bitpos: [5]; default: 0; 2404 * The value of OTP_VDDQ_C_SYNC2. 2405 */ 2406 #define EFUSE_OTP_VDDQ_C_SYNC2 (BIT(5)) 2407 #define EFUSE_OTP_VDDQ_C_SYNC2_M (EFUSE_OTP_VDDQ_C_SYNC2_V << EFUSE_OTP_VDDQ_C_SYNC2_S) 2408 #define EFUSE_OTP_VDDQ_C_SYNC2_V 0x00000001U 2409 #define EFUSE_OTP_VDDQ_C_SYNC2_S 5 2410 /** EFUSE_OTP_STROBE_SW : RO; bitpos: [6]; default: 0; 2411 * The value of OTP_STROBE_SW. 2412 */ 2413 #define EFUSE_OTP_STROBE_SW (BIT(6)) 2414 #define EFUSE_OTP_STROBE_SW_M (EFUSE_OTP_STROBE_SW_V << EFUSE_OTP_STROBE_SW_S) 2415 #define EFUSE_OTP_STROBE_SW_V 0x00000001U 2416 #define EFUSE_OTP_STROBE_SW_S 6 2417 /** EFUSE_OTP_CSB_SW : RO; bitpos: [7]; default: 0; 2418 * The value of OTP_CSB_SW. 2419 */ 2420 #define EFUSE_OTP_CSB_SW (BIT(7)) 2421 #define EFUSE_OTP_CSB_SW_M (EFUSE_OTP_CSB_SW_V << EFUSE_OTP_CSB_SW_S) 2422 #define EFUSE_OTP_CSB_SW_V 0x00000001U 2423 #define EFUSE_OTP_CSB_SW_S 7 2424 /** EFUSE_OTP_PGENB_SW : RO; bitpos: [8]; default: 0; 2425 * The value of OTP_PGENB_SW. 2426 */ 2427 #define EFUSE_OTP_PGENB_SW (BIT(8)) 2428 #define EFUSE_OTP_PGENB_SW_M (EFUSE_OTP_PGENB_SW_V << EFUSE_OTP_PGENB_SW_S) 2429 #define EFUSE_OTP_PGENB_SW_V 0x00000001U 2430 #define EFUSE_OTP_PGENB_SW_S 8 2431 /** EFUSE_OTP_VDDQ_IS_SW : RO; bitpos: [9]; default: 0; 2432 * The value of OTP_VDDQ_IS_SW. 2433 */ 2434 #define EFUSE_OTP_VDDQ_IS_SW (BIT(9)) 2435 #define EFUSE_OTP_VDDQ_IS_SW_M (EFUSE_OTP_VDDQ_IS_SW_V << EFUSE_OTP_VDDQ_IS_SW_S) 2436 #define EFUSE_OTP_VDDQ_IS_SW_V 0x00000001U 2437 #define EFUSE_OTP_VDDQ_IS_SW_S 9 2438 /** EFUSE_BLK0_VALID_BIT_CNT : RO; bitpos: [19:10]; default: 0; 2439 * Indicates the number of block valid bit. 2440 */ 2441 #define EFUSE_BLK0_VALID_BIT_CNT 0x000003FFU 2442 #define EFUSE_BLK0_VALID_BIT_CNT_M (EFUSE_BLK0_VALID_BIT_CNT_V << EFUSE_BLK0_VALID_BIT_CNT_S) 2443 #define EFUSE_BLK0_VALID_BIT_CNT_V 0x000003FFU 2444 #define EFUSE_BLK0_VALID_BIT_CNT_S 10 2445 /** EFUSE_CUR_ECDSA_BLK : RO; bitpos: [23:20]; default: 0; 2446 * Indicates which block is used for ECDSA key output. 2447 */ 2448 #define EFUSE_CUR_ECDSA_BLK 0x0000000FU 2449 #define EFUSE_CUR_ECDSA_BLK_M (EFUSE_CUR_ECDSA_BLK_V << EFUSE_CUR_ECDSA_BLK_S) 2450 #define EFUSE_CUR_ECDSA_BLK_V 0x0000000FU 2451 #define EFUSE_CUR_ECDSA_BLK_S 20 2452 2453 /** EFUSE_CMD_REG register 2454 * eFuse command register. 2455 */ 2456 #define EFUSE_CMD_REG (DR_REG_EFUSE_BASE + 0x1d4) 2457 /** EFUSE_READ_CMD : R/W/SC; bitpos: [0]; default: 0; 2458 * Set this bit to send read command. 2459 */ 2460 #define EFUSE_READ_CMD (BIT(0)) 2461 #define EFUSE_READ_CMD_M (EFUSE_READ_CMD_V << EFUSE_READ_CMD_S) 2462 #define EFUSE_READ_CMD_V 0x00000001U 2463 #define EFUSE_READ_CMD_S 0 2464 /** EFUSE_PGM_CMD : R/W/SC; bitpos: [1]; default: 0; 2465 * Set this bit to send programming command. 2466 */ 2467 #define EFUSE_PGM_CMD (BIT(1)) 2468 #define EFUSE_PGM_CMD_M (EFUSE_PGM_CMD_V << EFUSE_PGM_CMD_S) 2469 #define EFUSE_PGM_CMD_V 0x00000001U 2470 #define EFUSE_PGM_CMD_S 1 2471 /** EFUSE_BLK_NUM : R/W; bitpos: [5:2]; default: 0; 2472 * The serial number of the block to be programmed. Value 0-10 corresponds to block 2473 * number 0-10, respectively. 2474 */ 2475 #define EFUSE_BLK_NUM 0x0000000FU 2476 #define EFUSE_BLK_NUM_M (EFUSE_BLK_NUM_V << EFUSE_BLK_NUM_S) 2477 #define EFUSE_BLK_NUM_V 0x0000000FU 2478 #define EFUSE_BLK_NUM_S 2 2479 2480 /** EFUSE_INT_RAW_REG register 2481 * eFuse raw interrupt register. 2482 */ 2483 #define EFUSE_INT_RAW_REG (DR_REG_EFUSE_BASE + 0x1d8) 2484 /** EFUSE_READ_DONE_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0; 2485 * The raw bit signal for read_done interrupt. 2486 */ 2487 #define EFUSE_READ_DONE_INT_RAW (BIT(0)) 2488 #define EFUSE_READ_DONE_INT_RAW_M (EFUSE_READ_DONE_INT_RAW_V << EFUSE_READ_DONE_INT_RAW_S) 2489 #define EFUSE_READ_DONE_INT_RAW_V 0x00000001U 2490 #define EFUSE_READ_DONE_INT_RAW_S 0 2491 /** EFUSE_PGM_DONE_INT_RAW : R/SS/WTC; bitpos: [1]; default: 0; 2492 * The raw bit signal for pgm_done interrupt. 2493 */ 2494 #define EFUSE_PGM_DONE_INT_RAW (BIT(1)) 2495 #define EFUSE_PGM_DONE_INT_RAW_M (EFUSE_PGM_DONE_INT_RAW_V << EFUSE_PGM_DONE_INT_RAW_S) 2496 #define EFUSE_PGM_DONE_INT_RAW_V 0x00000001U 2497 #define EFUSE_PGM_DONE_INT_RAW_S 1 2498 2499 /** EFUSE_INT_ST_REG register 2500 * eFuse interrupt status register. 2501 */ 2502 #define EFUSE_INT_ST_REG (DR_REG_EFUSE_BASE + 0x1dc) 2503 /** EFUSE_READ_DONE_INT_ST : RO; bitpos: [0]; default: 0; 2504 * The status signal for read_done interrupt. 2505 */ 2506 #define EFUSE_READ_DONE_INT_ST (BIT(0)) 2507 #define EFUSE_READ_DONE_INT_ST_M (EFUSE_READ_DONE_INT_ST_V << EFUSE_READ_DONE_INT_ST_S) 2508 #define EFUSE_READ_DONE_INT_ST_V 0x00000001U 2509 #define EFUSE_READ_DONE_INT_ST_S 0 2510 /** EFUSE_PGM_DONE_INT_ST : RO; bitpos: [1]; default: 0; 2511 * The status signal for pgm_done interrupt. 2512 */ 2513 #define EFUSE_PGM_DONE_INT_ST (BIT(1)) 2514 #define EFUSE_PGM_DONE_INT_ST_M (EFUSE_PGM_DONE_INT_ST_V << EFUSE_PGM_DONE_INT_ST_S) 2515 #define EFUSE_PGM_DONE_INT_ST_V 0x00000001U 2516 #define EFUSE_PGM_DONE_INT_ST_S 1 2517 2518 /** EFUSE_INT_ENA_REG register 2519 * eFuse interrupt enable register. 2520 */ 2521 #define EFUSE_INT_ENA_REG (DR_REG_EFUSE_BASE + 0x1e0) 2522 /** EFUSE_READ_DONE_INT_ENA : R/W; bitpos: [0]; default: 0; 2523 * The enable signal for read_done interrupt. 2524 */ 2525 #define EFUSE_READ_DONE_INT_ENA (BIT(0)) 2526 #define EFUSE_READ_DONE_INT_ENA_M (EFUSE_READ_DONE_INT_ENA_V << EFUSE_READ_DONE_INT_ENA_S) 2527 #define EFUSE_READ_DONE_INT_ENA_V 0x00000001U 2528 #define EFUSE_READ_DONE_INT_ENA_S 0 2529 /** EFUSE_PGM_DONE_INT_ENA : R/W; bitpos: [1]; default: 0; 2530 * The enable signal for pgm_done interrupt. 2531 */ 2532 #define EFUSE_PGM_DONE_INT_ENA (BIT(1)) 2533 #define EFUSE_PGM_DONE_INT_ENA_M (EFUSE_PGM_DONE_INT_ENA_V << EFUSE_PGM_DONE_INT_ENA_S) 2534 #define EFUSE_PGM_DONE_INT_ENA_V 0x00000001U 2535 #define EFUSE_PGM_DONE_INT_ENA_S 1 2536 2537 /** EFUSE_INT_CLR_REG register 2538 * eFuse interrupt clear register. 2539 */ 2540 #define EFUSE_INT_CLR_REG (DR_REG_EFUSE_BASE + 0x1e4) 2541 /** EFUSE_READ_DONE_INT_CLR : WT; bitpos: [0]; default: 0; 2542 * The clear signal for read_done interrupt. 2543 */ 2544 #define EFUSE_READ_DONE_INT_CLR (BIT(0)) 2545 #define EFUSE_READ_DONE_INT_CLR_M (EFUSE_READ_DONE_INT_CLR_V << EFUSE_READ_DONE_INT_CLR_S) 2546 #define EFUSE_READ_DONE_INT_CLR_V 0x00000001U 2547 #define EFUSE_READ_DONE_INT_CLR_S 0 2548 /** EFUSE_PGM_DONE_INT_CLR : WT; bitpos: [1]; default: 0; 2549 * The clear signal for pgm_done interrupt. 2550 */ 2551 #define EFUSE_PGM_DONE_INT_CLR (BIT(1)) 2552 #define EFUSE_PGM_DONE_INT_CLR_M (EFUSE_PGM_DONE_INT_CLR_V << EFUSE_PGM_DONE_INT_CLR_S) 2553 #define EFUSE_PGM_DONE_INT_CLR_V 0x00000001U 2554 #define EFUSE_PGM_DONE_INT_CLR_S 1 2555 2556 /** EFUSE_DAC_CONF_REG register 2557 * Controls the eFuse programming voltage. 2558 */ 2559 #define EFUSE_DAC_CONF_REG (DR_REG_EFUSE_BASE + 0x1e8) 2560 /** EFUSE_DAC_CLK_DIV : R/W; bitpos: [7:0]; default: 23; 2561 * Controls the division factor of the rising clock of the programming voltage. 2562 */ 2563 #define EFUSE_DAC_CLK_DIV 0x000000FFU 2564 #define EFUSE_DAC_CLK_DIV_M (EFUSE_DAC_CLK_DIV_V << EFUSE_DAC_CLK_DIV_S) 2565 #define EFUSE_DAC_CLK_DIV_V 0x000000FFU 2566 #define EFUSE_DAC_CLK_DIV_S 0 2567 /** EFUSE_DAC_CLK_PAD_SEL : R/W; bitpos: [8]; default: 0; 2568 * Don't care. 2569 */ 2570 #define EFUSE_DAC_CLK_PAD_SEL (BIT(8)) 2571 #define EFUSE_DAC_CLK_PAD_SEL_M (EFUSE_DAC_CLK_PAD_SEL_V << EFUSE_DAC_CLK_PAD_SEL_S) 2572 #define EFUSE_DAC_CLK_PAD_SEL_V 0x00000001U 2573 #define EFUSE_DAC_CLK_PAD_SEL_S 8 2574 /** EFUSE_DAC_NUM : R/W; bitpos: [16:9]; default: 255; 2575 * Controls the rising period of the programming voltage. 2576 */ 2577 #define EFUSE_DAC_NUM 0x000000FFU 2578 #define EFUSE_DAC_NUM_M (EFUSE_DAC_NUM_V << EFUSE_DAC_NUM_S) 2579 #define EFUSE_DAC_NUM_V 0x000000FFU 2580 #define EFUSE_DAC_NUM_S 9 2581 /** EFUSE_OE_CLR : R/W; bitpos: [17]; default: 0; 2582 * Reduces the power supply of the programming voltage. 2583 */ 2584 #define EFUSE_OE_CLR (BIT(17)) 2585 #define EFUSE_OE_CLR_M (EFUSE_OE_CLR_V << EFUSE_OE_CLR_S) 2586 #define EFUSE_OE_CLR_V 0x00000001U 2587 #define EFUSE_OE_CLR_S 17 2588 2589 /** EFUSE_RD_TIM_CONF_REG register 2590 * Configures read timing parameters. 2591 */ 2592 #define EFUSE_RD_TIM_CONF_REG (DR_REG_EFUSE_BASE + 0x1ec) 2593 /** EFUSE_THR_A : R/W; bitpos: [7:0]; default: 1; 2594 * Configures the read hold time. 2595 */ 2596 #define EFUSE_THR_A 0x000000FFU 2597 #define EFUSE_THR_A_M (EFUSE_THR_A_V << EFUSE_THR_A_S) 2598 #define EFUSE_THR_A_V 0x000000FFU 2599 #define EFUSE_THR_A_S 0 2600 /** EFUSE_TRD : R/W; bitpos: [15:8]; default: 2; 2601 * Configures the read time. 2602 */ 2603 #define EFUSE_TRD 0x000000FFU 2604 #define EFUSE_TRD_M (EFUSE_TRD_V << EFUSE_TRD_S) 2605 #define EFUSE_TRD_V 0x000000FFU 2606 #define EFUSE_TRD_S 8 2607 /** EFUSE_TSUR_A : R/W; bitpos: [23:16]; default: 1; 2608 * Configures the read setup time. 2609 */ 2610 #define EFUSE_TSUR_A 0x000000FFU 2611 #define EFUSE_TSUR_A_M (EFUSE_TSUR_A_V << EFUSE_TSUR_A_S) 2612 #define EFUSE_TSUR_A_V 0x000000FFU 2613 #define EFUSE_TSUR_A_S 16 2614 /** EFUSE_READ_INIT_NUM : R/W; bitpos: [31:24]; default: 15; 2615 * Configures the waiting time of reading eFuse memory. 2616 */ 2617 #define EFUSE_READ_INIT_NUM 0x000000FFU 2618 #define EFUSE_READ_INIT_NUM_M (EFUSE_READ_INIT_NUM_V << EFUSE_READ_INIT_NUM_S) 2619 #define EFUSE_READ_INIT_NUM_V 0x000000FFU 2620 #define EFUSE_READ_INIT_NUM_S 24 2621 2622 /** EFUSE_WR_TIM_CONF1_REG register 2623 * Configurarion register 1 of eFuse programming timing parameters. 2624 */ 2625 #define EFUSE_WR_TIM_CONF1_REG (DR_REG_EFUSE_BASE + 0x1f0) 2626 /** EFUSE_TSUP_A : R/W; bitpos: [7:0]; default: 1; 2627 * Configures the programming setup time. 2628 */ 2629 #define EFUSE_TSUP_A 0x000000FFU 2630 #define EFUSE_TSUP_A_M (EFUSE_TSUP_A_V << EFUSE_TSUP_A_S) 2631 #define EFUSE_TSUP_A_V 0x000000FFU 2632 #define EFUSE_TSUP_A_S 0 2633 /** EFUSE_PWR_ON_NUM : R/W; bitpos: [23:8]; default: 9831; 2634 * Configures the power up time for VDDQ. 2635 */ 2636 #define EFUSE_PWR_ON_NUM 0x0000FFFFU 2637 #define EFUSE_PWR_ON_NUM_M (EFUSE_PWR_ON_NUM_V << EFUSE_PWR_ON_NUM_S) 2638 #define EFUSE_PWR_ON_NUM_V 0x0000FFFFU 2639 #define EFUSE_PWR_ON_NUM_S 8 2640 /** EFUSE_THP_A : R/W; bitpos: [31:24]; default: 1; 2641 * Configures the programming hold time. 2642 */ 2643 #define EFUSE_THP_A 0x000000FFU 2644 #define EFUSE_THP_A_M (EFUSE_THP_A_V << EFUSE_THP_A_S) 2645 #define EFUSE_THP_A_V 0x000000FFU 2646 #define EFUSE_THP_A_S 24 2647 2648 /** EFUSE_WR_TIM_CONF2_REG register 2649 * Configurarion register 2 of eFuse programming timing parameters. 2650 */ 2651 #define EFUSE_WR_TIM_CONF2_REG (DR_REG_EFUSE_BASE + 0x1f4) 2652 /** EFUSE_PWR_OFF_NUM : R/W; bitpos: [15:0]; default: 320; 2653 * Configures the power outage time for VDDQ. 2654 */ 2655 #define EFUSE_PWR_OFF_NUM 0x0000FFFFU 2656 #define EFUSE_PWR_OFF_NUM_M (EFUSE_PWR_OFF_NUM_V << EFUSE_PWR_OFF_NUM_S) 2657 #define EFUSE_PWR_OFF_NUM_V 0x0000FFFFU 2658 #define EFUSE_PWR_OFF_NUM_S 0 2659 /** EFUSE_TPGM : R/W; bitpos: [31:16]; default: 160; 2660 * Configures the active programming time. 2661 */ 2662 #define EFUSE_TPGM 0x0000FFFFU 2663 #define EFUSE_TPGM_M (EFUSE_TPGM_V << EFUSE_TPGM_S) 2664 #define EFUSE_TPGM_V 0x0000FFFFU 2665 #define EFUSE_TPGM_S 16 2666 2667 /** EFUSE_WR_TIM_CONF0_RS_BYPASS_REG register 2668 * Configurarion register0 of eFuse programming time parameters and rs bypass 2669 * operation. 2670 */ 2671 #define EFUSE_WR_TIM_CONF0_RS_BYPASS_REG (DR_REG_EFUSE_BASE + 0x1f8) 2672 /** EFUSE_BYPASS_RS_CORRECTION : R/W; bitpos: [0]; default: 0; 2673 * Set this bit to bypass reed solomon correction step. 2674 */ 2675 #define EFUSE_BYPASS_RS_CORRECTION (BIT(0)) 2676 #define EFUSE_BYPASS_RS_CORRECTION_M (EFUSE_BYPASS_RS_CORRECTION_V << EFUSE_BYPASS_RS_CORRECTION_S) 2677 #define EFUSE_BYPASS_RS_CORRECTION_V 0x00000001U 2678 #define EFUSE_BYPASS_RS_CORRECTION_S 0 2679 /** EFUSE_BYPASS_RS_BLK_NUM : R/W; bitpos: [11:1]; default: 0; 2680 * Configures block number of programming twice operation. 2681 */ 2682 #define EFUSE_BYPASS_RS_BLK_NUM 0x000007FFU 2683 #define EFUSE_BYPASS_RS_BLK_NUM_M (EFUSE_BYPASS_RS_BLK_NUM_V << EFUSE_BYPASS_RS_BLK_NUM_S) 2684 #define EFUSE_BYPASS_RS_BLK_NUM_V 0x000007FFU 2685 #define EFUSE_BYPASS_RS_BLK_NUM_S 1 2686 /** EFUSE_UPDATE : WT; bitpos: [12]; default: 0; 2687 * Set this bit to update multi-bit register signals. 2688 */ 2689 #define EFUSE_UPDATE (BIT(12)) 2690 #define EFUSE_UPDATE_M (EFUSE_UPDATE_V << EFUSE_UPDATE_S) 2691 #define EFUSE_UPDATE_V 0x00000001U 2692 #define EFUSE_UPDATE_S 12 2693 /** EFUSE_TPGM_INACTIVE : R/W; bitpos: [20:13]; default: 1; 2694 * Configures the inactive programming time. 2695 */ 2696 #define EFUSE_TPGM_INACTIVE 0x000000FFU 2697 #define EFUSE_TPGM_INACTIVE_M (EFUSE_TPGM_INACTIVE_V << EFUSE_TPGM_INACTIVE_S) 2698 #define EFUSE_TPGM_INACTIVE_V 0x000000FFU 2699 #define EFUSE_TPGM_INACTIVE_S 13 2700 2701 /** EFUSE_DATE_REG register 2702 * eFuse version register. 2703 */ 2704 #define EFUSE_DATE_REG (DR_REG_EFUSE_BASE + 0x1fc) 2705 /** EFUSE_DATE : R/W; bitpos: [27:0]; default: 35684640; 2706 * Stores eFuse version. 2707 */ 2708 #define EFUSE_DATE 0x0FFFFFFFU 2709 #define EFUSE_DATE_M (EFUSE_DATE_V << EFUSE_DATE_S) 2710 #define EFUSE_DATE_V 0x0FFFFFFFU 2711 #define EFUSE_DATE_S 0 2712 2713 #ifdef __cplusplus 2714 } 2715 #endif 2716
