1# This file describes eFuses fields and registers for ESP32 chip 2# 3# SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD 4# 5# SPDX-License-Identifier: GPL-2.0-or-later 6 7from ..mem_definition_base import EfuseBlocksBase, EfuseFieldsBase, EfuseRegistersBase 8 9 10class EfuseDefineRegisters(EfuseRegistersBase): 11 EFUSE_MEM_SIZE = 0x011C + 4 12 13 # EFUSE registers & command/conf values 14 DR_REG_EFUSE_BASE = 0x3FF5A000 15 EFUSE_REG_CONF = DR_REG_EFUSE_BASE + 0x0FC 16 EFUSE_CONF_WRITE = 0x5A5A 17 EFUSE_CONF_READ = 0x5AA5 18 EFUSE_REG_CMD = DR_REG_EFUSE_BASE + 0x104 19 EFUSE_CMD_OP_MASK = 0x3 20 EFUSE_CMD_WRITE = 0x2 21 EFUSE_CMD_READ = 0x1 22 23 # 3/4 Coding scheme warnings registers 24 EFUSE_REG_DEC_STATUS = DR_REG_EFUSE_BASE + 0x11C 25 EFUSE_REG_DEC_STATUS_MASK = 0xFFF 26 27 # Coding Scheme 28 EFUSE_CODING_SCHEME_WORD = 6 29 EFUSE_CODING_SCHEME_MASK = 0x3 30 31 # Efuse clock control 32 EFUSE_DAC_CONF_REG = DR_REG_EFUSE_BASE + 0x118 33 EFUSE_CLK_REG = DR_REG_EFUSE_BASE + 0x0F8 34 EFUSE_DAC_CLK_DIV_MASK = 0xFF 35 EFUSE_CLK_SEL0_MASK = 0x00FF 36 EFUSE_CLK_SEL1_MASK = 0xFF00 37 38 EFUSE_CLK_SETTINGS = { 39 # APB freq: clk_sel0, clk_sel1, dac_clk_div 40 # Taken from TRM chapter "eFuse Controller": Timing Configuration 41 # 80 is here for completeness only as esptool never sets an 80MHz APB clock 42 26: (250, 255, 52), 43 40: (160, 255, 80), 44 80: (80, 128, 100), 45 } 46 47 DR_REG_SYSCON_BASE = 0x3FF66000 48 APB_CTL_DATE_ADDR = DR_REG_SYSCON_BASE + 0x7C 49 APB_CTL_DATE_V = 0x1 50 APB_CTL_DATE_S = 31 51 52 EFUSE_BLK0_RDATA3_REG = DR_REG_EFUSE_BASE + 0x00C 53 EFUSE_RD_CHIP_VER_REV1 = 1 << 15 54 55 EFUSE_BLK0_RDATA5_REG = DR_REG_EFUSE_BASE + 0x014 56 EFUSE_RD_CHIP_VER_REV2 = 1 << 20 57 58 59# fmt: off 60class EfuseDefineBlocks(EfuseBlocksBase): 61 62 __base_regs = EfuseDefineRegisters.DR_REG_EFUSE_BASE 63 # List of efuse blocks 64 BLOCKS = [ 65 # Name, Alias, Index, Read address, Write address, Write protect bit, Read protect bit, Len, key_purpose 66 ("BLOCK0", [], 0, __base_regs + 0x000, __base_regs + 0x01C, None, None, 7, None), 67 ("BLOCK1", ["flash_encryption"], 1, __base_regs + 0x038, __base_regs + 0x098, 7, 0, 8, None), 68 ("BLOCK2", ["secure_boot_v1", "secure_boot_v2"], 2, __base_regs + 0x058, __base_regs + 0x0B8, 8, 1, 8, None), 69 ("BLOCK3", [], 3, __base_regs + 0x078, __base_regs + 0x0D8, 9, 2, 8, None), 70 ] 71 72 def get_burn_block_data_names(self): 73 list_of_names = [] 74 for block in self.BLOCKS: 75 blk = self.get(block) 76 if blk.name: 77 list_of_names.append(blk.name) 78 return list_of_names 79 80 81class EfuseDefineFields(EfuseFieldsBase): 82 83 # Lists of efuse fields 84 EFUSES = [ 85 # Name Category Block Word Pos Type:len WR_DIS RD_DIS Class Description Dictionary 86 ('WR_DIS', "efuse", 0, 0, 0, "uint:16", 1, None, None, "Efuse write disable mask", None), 87 ('RD_DIS', "efuse", 0, 0, 16, "uint:4", 0, None, None, "Efuse read disable mask", None), 88 ('CODING_SCHEME', "efuse", 0, 6, 0, "uint:2", 10, 3, None, "Efuse variable block length scheme", 89 {0: "NONE (BLK1-3 len=256 bits)", 90 1: "3/4 (BLK1-3 len=192 bits)", 91 2: "REPEAT (BLK1-3 len=128 bits) not supported", 92 3: "NONE (BLK1-3 len=256 bits)"}), 93 ('KEY_STATUS', "efuse", 0, 6, 10, "bool", 10, 3, None, "Usage of efuse block 3 (reserved)", None), 94 ('MAC', "identity", 0, 1, 0, "bytes:6", 3, None, "mac", "Factory MAC Address", None), 95 ('MAC_CRC', "identity", 0, 2, 16, "uint:8", 3, None, None, "CRC8 for factory MAC address", None), 96 ('CHIP_VER_REV1', "identity", 0, 3, 15, "bool", 3, None, None, "Silicon Revision 1", None), 97 ('CHIP_VER_REV2', "identity", 0, 5, 20, "bool", 6, None, None, "Silicon Revision 2", None), 98 ("WAFER_VERSION_MINOR", "identity", 0, 5, 24, "uint:2", 6, None, None, "WAFER VERSION MINOR", None), 99 ('CHIP_PACKAGE', "identity", 0, 3, 9, "uint:3", 3, None, None, "Chip package identifier", None), 100 ('CHIP_PACKAGE_4BIT', "identity", 0, 3, 2, "uint:1", 3, None, None, "Chip package identifier #4bit", None), 101 ('XPD_SDIO_FORCE', "config", 0, 4, 16, "bool", 5, None, None, "Ignore MTDI pin (GPIO12) for VDD_SDIO on reset", None), 102 ('XPD_SDIO_REG', "config", 0, 4, 14, "bool", 5, None, None, "If XPD_SDIO_FORCE, enable VDD_SDIO reg on reset", None), 103 ('XPD_SDIO_TIEH', "config", 0, 4, 15, "bool", 5, None, None, "If XPD_SDIO_FORCE & XPD_SDIO_REG", 104 {1: "3.3V", 105 0: "1.8V"}), 106 ('CLK8M_FREQ', "config", 0, 4, 0, "uint:8", None, None, None, "8MHz clock freq override", None), 107 ('SPI_PAD_CONFIG_CLK', "config", 0, 5, 0, "uint:5", 6, None, "spipin", "Override SD_CLK pad (GPIO6/SPICLK)", None), 108 ('SPI_PAD_CONFIG_Q', "config", 0, 5, 5, "uint:5", 6, None, "spipin", "Override SD_DATA_0 pad (GPIO7/SPIQ)", None), 109 ('SPI_PAD_CONFIG_D', "config", 0, 5, 10, "uint:5", 6, None, "spipin", "Override SD_DATA_1 pad (GPIO8/SPID)", None), 110 ('SPI_PAD_CONFIG_HD', "config", 0, 3, 4, "uint:5", 6, None, "spipin", "Override SD_DATA_2 pad (GPIO9/SPIHD)", None), 111 ('SPI_PAD_CONFIG_CS0', "config", 0, 5, 15, "uint:5", 6, None, "spipin", "Override SD_CMD pad (GPIO11/SPICS0)", None), 112 ('DISABLE_SDIO_HOST', "config", 0, 6, 3, "bool", None, None, None, "Disable SDIO host", None), 113 ('FLASH_CRYPT_CNT', "security", 0, 0, 20, "uint:7", 2, None, "bitcount", "Flash encryption mode counter", None), 114 ('UART_DOWNLOAD_DIS', "security", 0, 0, 27, "bool", 2, None, None, "Disable UART download mode (ESP32 rev3 only)", None), 115 ('FLASH_CRYPT_CONFIG', "security", 0, 5, 28, "uint:4", 10, 3, None, "Flash encryption config (key tweak bits)", None), 116 ('CONSOLE_DEBUG_DISABLE', "security", 0, 6, 2, "bool", 15, None, None, "Disable ROM BASIC interpreter fallback", None), 117 ('ABS_DONE_0', "security", 0, 6, 4, "bool", 12, None, None, "Secure boot V1 is enabled for bootloader image", None), 118 ('ABS_DONE_1', "security", 0, 6, 5, "bool", 13, None, None, "Secure boot V2 is enabled for bootloader image", None), 119 ('JTAG_DISABLE', "security", 0, 6, 6, "bool", 14, None, None, "Disable JTAG", None), 120 ('DISABLE_DL_ENCRYPT', "security", 0, 6, 7, "bool", 15, None, None, "Disable flash encryption in UART bootloader", None), 121 ('DISABLE_DL_DECRYPT', "security", 0, 6, 8, "bool", 15, None, None, "Disable flash decryption in UART bootloader", None), 122 ('DISABLE_DL_CACHE', "security", 0, 6, 9, "bool", 15, None, None, "Disable flash cache in UART bootloader", None), 123 ('BLK3_PART_RESERVE', "calibration", 0, 3, 14, "bool", 10, 3, None, "BLOCK3 partially served for ADC calibration data", None), 124 ('ADC_VREF', "calibration", 0, 4, 8, "uint:5", 0, None, "vref", "Voltage reference calibration", None), 125 ('MAC_VERSION', "identity", 3, 5, 24, "uint:8", 9, 2, None, "Version of the MAC field", 126 {1: "Custom MAC in BLOCK3"}), 127 ] 128 129 # if MAC_VERSION is set "1", these efuse fields are in BLOCK3: 130 CUSTOM_MAC = [ 131 # Name Category Block Word Pos Type:len WR_DIS RD_DIS Class Description Dictionary 132 ('CUSTOM_MAC', "identity", 3, 0, 8, "bytes:6", 9, 2, "mac", "Custom MAC", None), 133 ('CUSTOM_MAC_CRC', "identity", 3, 0, 0, "uint:8", 9, 2, None, "CRC of custom MAC", None), 134 ] 135 136 # The len of fields depends on coding scheme: for CODING_SCHEME_NONE 137 KEYBLOCKS_256 = [ 138 # Name Category Block Word Pos Type:len WR_DIS RD_DIS Class Description Dictionary 139 ('BLOCK1', "security", 1, 0, 0, "bytes:32", 7, 0, "keyblock", "Flash encryption key", None), 140 ('BLOCK2', "security", 2, 0, 0, "bytes:32", 8, 1, "keyblock", "Secure boot key", None), 141 ('BLOCK3', "security", 3, 0, 0, "bytes:32", 9, 2, "keyblock", "Variable Block 3", None), 142 ] 143 144 # The len of fields depends on coding scheme: for CODING_SCHEME_34 145 KEYBLOCKS_192 = [ 146 # Name Category Block Word Pos Type:len WR_DIS RD_DIS Class Description Dictionary 147 ('BLOCK1', "security", 1, 0, 0, "bytes:24", 7, 0, "keyblock", "Flash encryption key", None), 148 ('BLOCK2', "security", 2, 0, 0, "bytes:24", 8, 1, "keyblock", "Secure boot key", None), 149 ('BLOCK3', "security", 3, 0, 0, "bytes:24", 9, 2, "keyblock", "Variable Block 3", None), 150 ] 151 152 # if BLK3_PART_RESERVE is set, these efuse fields are in BLOCK3: 153 ADC_CALIBRATION = [ 154 # Name Category Block Word Pos Type:len WR_DIS RD_DIS Class Description Dictionary 155 ('ADC1_TP_LOW', "calibration", 3, 3, 0, "uint:7", 9, 2, "adc_tp", "ADC1 150mV reading", None), 156 ('ADC1_TP_HIGH', "calibration", 3, 3, 7, "uint:9", 9, 2, "adc_tp", "ADC1 850mV reading", None), 157 ('ADC2_TP_LOW', "calibration", 3, 3, 16, "uint:7", 9, 2, "adc_tp", "ADC2 150mV reading", None), 158 ('ADC2_TP_HIGH', "calibration", 3, 3, 23, "uint:9", 9, 2, "adc_tp", "ADC2 850mV reading", None), 159 ] 160 161 CALC = [ 162 ("WAFER_VERSION_MAJOR", "identity", 0, None, None, "uint:3", None, None, "wafer", "calc WAFER VERSION MAJOR from CHIP_VER_REV1 and CHIP_VER_REV2 and apb_ctl_date (read only)", None), 163 ('PKG_VERSION', "identity", 0, None, None, "uint:4", None, None, "pkg", "calc Chip package = CHIP_PACKAGE_4BIT << 3 + CHIP_PACKAGE (read only)", None), 164 ] 165# fmt: on 166
