1 /* 2 * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #pragma once 8 9 #include <stdint.h> 10 #include <stdlib.h> 11 #include <esp_types.h> 12 #include "soc/pmu_struct.h" 13 #include "hal/pmu_hal.h" 14 15 #ifdef __cplusplus 16 extern "C" { 17 #endif 18 19 #define HP_CALI_DBIAS_DEFAULT 25 20 #define LP_CALI_DBIAS_DEFAULT 26 21 22 // FOR XTAL FORCE PU IN SLEEP 23 #define PMU_PD_CUR_SLEEP_ON 0 24 #define PMU_BIASSLP_SLEEP_ON 0 25 26 // FOR BOTH LIGHTSLEEP & DEEPSLEEP 27 #define PMU_PD_CUR_SLEEP_DEFAULT 1 28 #define PMU_BIASSLP_SLEEP_DEFAULT 1 29 #define PMU_LP_XPD_SLEEP_DEFAULT 1 30 #define PMU_LP_SLP_XPD_SLEEP_DEFAULT 0 31 #define PMU_LP_SLP_DBIAS_SLEEP_DEFAULT 0 32 33 // FOR LIGHTSLEEP 34 #define PMU_HP_DRVB_LIGHTSLEEP 0 35 #define PMU_LP_DRVB_LIGHTSLEEP 0 36 #define PMU_HP_XPD_LIGHTSLEEP 1 37 38 #define PMU_DBG_ATTEN_LIGHTSLEEP_NODROP 0 39 #define PMU_DBG_ATTEN_LIGHTSLEEP_DEFAULT 0 40 #define PMU_HP_DBIAS_LIGHTSLEEP_0V6_DEFAULT 1 41 #define PMU_LP_DBIAS_LIGHTSLEEP_0V7_DEFAULT 12 42 43 // FOR LIGHTSLEEP: XTAL FORCE PU 44 #define PMU_DBG_ATTEN_ACTIVE_DEFAULT 0 45 46 // FOR DEEPSLEEP 47 #define PMU_DBG_HP_DEEPSLEEP 0 48 #define PMU_HP_XPD_DEEPSLEEP 0 49 #define PMU_LP_DRVB_DEEPSLEEP 0 50 51 #define PMU_REGDMA_S2A_WORK_TIME_US 480 52 53 #define PMU_DBG_ATTEN_DEEPSLEEP_DEFAULT 12 54 #define PMU_LP_DBIAS_DEEPSLEEP_0V7_DEFAULT 23 55 56 #define EFUSE_BURN_OFFSET_DSLP_DBG 8 57 #define EFUSE_BURN_OFFSET_DSLP_LP_DBIAS 23 58 59 uint32_t get_act_hp_dbias(void); 60 uint32_t get_act_lp_dbias(void); 61 62 typedef struct { 63 pmu_hp_dig_power_reg_t dig_power; 64 pmu_hp_clk_power_reg_t clk_power; 65 pmu_hp_xtal_reg_t xtal; 66 } pmu_hp_system_power_param_t; 67 68 const pmu_hp_system_power_param_t* pmu_hp_system_power_param_default(pmu_hp_mode_t mode); 69 70 typedef struct { 71 uint32_t icg_func; 72 uint32_t icg_apb; 73 pmu_hp_icg_modem_reg_t icg_modem; 74 pmu_hp_sysclk_reg_t sysclk; 75 } pmu_hp_system_clock_param_t; 76 77 const pmu_hp_system_clock_param_t* pmu_hp_system_clock_param_default(pmu_hp_mode_t mode); 78 79 typedef struct { 80 pmu_hp_sys_cntl_reg_t syscntl; 81 } pmu_hp_system_digital_param_t; 82 83 const pmu_hp_system_digital_param_t* pmu_hp_system_digital_param_default(pmu_hp_mode_t mode); 84 85 typedef struct { 86 pmu_hp_bias_reg_t bias; 87 pmu_hp_regulator0_reg_t regulator0; 88 pmu_hp_regulator1_reg_t regulator1; 89 } pmu_hp_system_analog_param_t; 90 91 const pmu_hp_system_analog_param_t* pmu_hp_system_analog_param_default(pmu_hp_mode_t mode); 92 93 typedef struct { 94 pmu_hp_backup_reg_t retention; 95 uint32_t backup_clk; 96 } pmu_hp_system_retention_param_t; 97 98 const pmu_hp_system_retention_param_t* pmu_hp_system_retention_param_default(pmu_hp_mode_t mode); 99 100 typedef struct { 101 pmu_lp_dig_power_reg_t dig_power; 102 pmu_lp_clk_power_reg_t clk_power; 103 pmu_lp_xtal_reg_t xtal; 104 } pmu_lp_system_power_param_t; 105 106 const pmu_lp_system_power_param_t* pmu_lp_system_power_param_default(pmu_lp_mode_t mode); 107 108 109 110 typedef struct { 111 pmu_lp_bias_reg_t bias; 112 pmu_lp_regulator0_reg_t regulator0; 113 pmu_lp_regulator1_reg_t regulator1; 114 } pmu_lp_system_analog_param_t; 115 116 const pmu_lp_system_analog_param_t* pmu_lp_system_analog_param_default(pmu_lp_mode_t mode); 117 118 119 120 /* Following software configuration instance type from pmu_struct.h used for the PMU state machine in sleep flow*/ 121 typedef union { 122 struct { 123 uint32_t reserved0 : 21; 124 uint32_t vdd_spi_pd_en: 1; 125 uint32_t mem_dslp : 1; 126 uint32_t mem_pd_en : 4; 127 uint32_t wifi_pd_en : 1; 128 uint32_t reserved1 : 1; 129 uint32_t cpu_pd_en : 1; 130 uint32_t aon_pd_en : 1; 131 uint32_t top_pd_en : 1; 132 }; 133 struct { 134 uint32_t reserved2 : 26; 135 uint32_t i2c_iso_en : 1; 136 uint32_t i2c_retention: 1; 137 uint32_t xpd_bb_i2c : 1; 138 uint32_t xpd_bbpll_i2c: 1; 139 uint32_t xpd_bbpll : 1; 140 uint32_t reserved3 : 1; 141 }; 142 struct { 143 uint32_t reserved4 : 31; 144 uint32_t xpd_xtal : 1; 145 }; 146 uint32_t val; 147 } pmu_hp_power_t; 148 149 typedef union { 150 struct { 151 uint32_t reserved0 : 30; 152 uint32_t mem_dslp : 1; 153 uint32_t peri_pd_en: 1; 154 }; 155 struct { 156 uint32_t reserved1 : 28; 157 uint32_t xpd_xtal32k: 1; 158 uint32_t xpd_rc32k : 1; 159 uint32_t xpd_fosc : 1; 160 uint32_t pd_osc : 1; 161 }; 162 struct { 163 uint32_t reserved2 : 31; 164 uint32_t xpd_xtal : 1; 165 }; 166 uint32_t val; 167 } pmu_lp_power_t; 168 169 typedef struct { 170 struct { 171 uint32_t reserved0 : 25; 172 uint32_t xpd_bias : 1; 173 uint32_t dbg_atten : 4; 174 uint32_t pd_cur : 1; 175 uint32_t bias_sleep: 1; 176 }; 177 struct { 178 uint32_t reserved1 : 16; 179 uint32_t slp_mem_xpd : 1; 180 uint32_t slp_logic_xpd : 1; 181 uint32_t xpd : 1; 182 uint32_t slp_mem_dbias : 4; 183 uint32_t slp_logic_dbias: 4; 184 uint32_t dbias : 5; 185 }; 186 struct { 187 uint32_t reserved2: 8; 188 uint32_t drv_b : 24; 189 }; 190 } pmu_hp_analog_t; 191 192 typedef struct { 193 struct { 194 uint32_t reserved0 : 25; 195 uint32_t xpd_bias : 1; 196 uint32_t dbg_atten : 4; 197 uint32_t pd_cur : 1; 198 uint32_t bias_sleep: 1; 199 }; 200 struct { 201 uint32_t reserved1: 21; 202 uint32_t slp_xpd : 1; 203 uint32_t xpd : 1; 204 uint32_t slp_dbias: 4; 205 uint32_t dbias : 5; 206 }; 207 struct { 208 uint32_t reserved2: 28; 209 uint32_t drv_b : 4; 210 }; 211 } pmu_lp_analog_t; 212 213 typedef struct { 214 uint32_t modem_wakeup_wait_cycle; 215 uint16_t analog_wait_target_cycle; 216 uint16_t digital_power_down_wait_cycle; 217 uint16_t digital_power_supply_wait_cycle; 218 uint16_t digital_power_up_wait_cycle; 219 uint16_t pll_stable_wait_cycle; 220 uint8_t modify_icg_cntl_wait_cycle; 221 uint8_t switch_icg_cntl_wait_cycle; 222 uint8_t min_slp_slow_clk_cycle; 223 } pmu_hp_param_t; 224 225 typedef struct { 226 uint16_t digital_power_supply_wait_cycle; 227 uint8_t min_slp_slow_clk_cycle; 228 uint8_t analog_wait_target_cycle; 229 uint8_t digital_power_down_wait_cycle; 230 uint8_t digital_power_up_wait_cycle; 231 } pmu_lp_param_t; 232 233 typedef struct { 234 union { 235 uint16_t xtal_stable_wait_slow_clk_cycle; 236 uint16_t xtal_stable_wait_cycle; 237 }; 238 } pmu_hp_lp_param_t; 239 240 #define PMU_HP_SLEEP_MIN_SLOW_CLK_CYCLES (10) 241 #define PMU_LP_SLEEP_MIN_SLOW_CLK_CYCLES (10) 242 243 #define PMU_HP_WAKEUP_DELAY_CYCLES (0) 244 #define PMU_HP_XTAL_STABLE_WAIT_CYCLES (3155) /* Not used, Fast OSC as PMU work clock source is about 201 us, corresponding to PMU_LP_XTAL_STABLE_WAIT_SLOW_CLK_CYCLES */ 245 #define PMU_HP_PLL_STABLE_WAIT_CYCLES (2) 246 #define PMU_HP_ANALOG_WAIT_TARGET_CYCLES (2419) /* Fast OSC as PMU work clock source is about 154 us */ 247 #define PMU_HP_DIGITAL_POWER_SUPPLY_WAIT_CYCLES (32) 248 #define PMU_HP_DIGITAL_POWER_UP_WAIT_CYCLES (32) 249 #define PMU_HP_MODEM_WAKEUP_WAIT_CYCLES (20700) /* Fast OSC as PMU work clock source is about 1318.6 us */ 250 251 #define PMU_LP_WAKEUP_DELAY_CYCLES (0) 252 #define PMU_LP_XTAL_STABLE_WAIT_SLOW_CLK_CYCLES (30) /* Slow OSC as PMU slow clock source is about 201 us */ 253 #define PMU_LP_ANALOG_WAIT_TARGET_CYCLES (23) /* Slow OSC as PMU slow clock source is about 154 us */ 254 #define PMU_LP_DIGITAL_POWER_SUPPLY_WAIT_CYCLES (32) /* Fast OSC as PMU work clock source is about 2 us */ 255 #define PMU_LP_DIGITAL_POWER_UP_WAIT_CYCLES (32) /* Fast OSC as PMU work clock source is about 2 us */ 256 257 #define PMU_LP_ANALOG_WAIT_TARGET_TIME_DSLP_US (500) /* Slow OSC as PMU slow clock source in deepsleep is about 500 us */ 258 259 typedef struct { 260 struct { 261 pmu_hp_power_t dig_power; 262 pmu_hp_power_t clk_power; 263 pmu_hp_power_t xtal; 264 } hp_sys; 265 struct { 266 pmu_lp_power_t dig_power; 267 pmu_lp_power_t clk_power; 268 pmu_lp_power_t xtal; 269 } lp_sys[PMU_MODE_LP_MAX]; 270 } pmu_sleep_power_config_t; 271 272 #define PMU_SLEEP_POWER_CONFIG_DEFAULT(pd_flags) { \ 273 .hp_sys = { \ 274 .dig_power = { \ 275 .vdd_spi_pd_en = ((pd_flags) & PMU_SLEEP_PD_VDDSDIO) ? 1 : 0, \ 276 .wifi_pd_en = ((pd_flags) & PMU_SLEEP_PD_MODEM) ? 1 : 0, \ 277 .cpu_pd_en = ((pd_flags) & PMU_SLEEP_PD_CPU) ? 1 : 0, \ 278 .aon_pd_en = ((pd_flags) & PMU_SLEEP_PD_HP_AON) ? 1 : 0, \ 279 .top_pd_en = ((pd_flags) & PMU_SLEEP_PD_TOP) ? 1 : 0, \ 280 .mem_pd_en = 0, \ 281 .mem_dslp = 0 \ 282 }, \ 283 .clk_power = { \ 284 .i2c_iso_en = 1, \ 285 .i2c_retention = 1, \ 286 .xpd_bb_i2c = 0, \ 287 .xpd_bbpll_i2c = 0, \ 288 .xpd_bbpll = 0 \ 289 }, \ 290 .xtal = { \ 291 .xpd_xtal = ((pd_flags) & PMU_SLEEP_PD_XTAL) ? 0 : 1, \ 292 } \ 293 }, \ 294 .lp_sys[PMU_MODE_LP_ACTIVE] = { \ 295 .dig_power = { \ 296 .peri_pd_en = 0, \ 297 .mem_dslp = 0 \ 298 }, \ 299 .clk_power = { \ 300 .xpd_xtal32k = ((pd_flags) & PMU_SLEEP_PD_XTAL32K) ? 0 : 1, \ 301 .xpd_rc32k = ((pd_flags) & PMU_SLEEP_PD_RC32K) ? 0 : 1, \ 302 .xpd_fosc = 1 \ 303 } \ 304 }, \ 305 .lp_sys[PMU_MODE_LP_SLEEP] = { \ 306 .dig_power = { \ 307 .peri_pd_en = ((pd_flags) & PMU_SLEEP_PD_LP_PERIPH) ? 1 : 0, \ 308 .mem_dslp = 1 \ 309 }, \ 310 .clk_power = { \ 311 .xpd_xtal32k = ((pd_flags) & PMU_SLEEP_PD_XTAL32K) ? 0 : 1, \ 312 .xpd_rc32k = ((pd_flags) & PMU_SLEEP_PD_RC32K) ? 0 : 1, \ 313 .xpd_fosc = ((pd_flags) & PMU_SLEEP_PD_RC_FAST) ? 0 : 1 \ 314 }, \ 315 .xtal = { \ 316 .xpd_xtal = ((pd_flags) & PMU_SLEEP_PD_XTAL) ? 0 : 1, \ 317 } \ 318 } \ 319 } 320 321 typedef struct { 322 pmu_hp_sys_cntl_reg_t syscntl; 323 } pmu_sleep_digital_config_t; 324 325 #define PMU_SLEEP_DIGITAL_LSLP_CONFIG_DEFAULT(pd_flags) { \ 326 .syscntl = { \ 327 .dig_pad_slp_sel = ((pd_flags) & PMU_SLEEP_PD_TOP) ? 0 : 1, \ 328 } \ 329 } 330 331 typedef struct { 332 struct { 333 pmu_hp_analog_t analog; 334 } hp_sys; 335 struct { 336 pmu_lp_analog_t analog; 337 } lp_sys[PMU_MODE_LP_MAX]; 338 } pmu_sleep_analog_config_t; 339 340 #define PMU_SLEEP_ANALOG_LSLP_CONFIG_DEFAULT(pd_flags) { \ 341 .hp_sys = { \ 342 .analog = { \ 343 .drv_b = PMU_HP_DRVB_LIGHTSLEEP, \ 344 .pd_cur = PMU_PD_CUR_SLEEP_DEFAULT, \ 345 .bias_sleep = PMU_BIASSLP_SLEEP_DEFAULT, \ 346 .xpd = PMU_HP_XPD_LIGHTSLEEP, \ 347 .dbg_atten = PMU_DBG_ATTEN_LIGHTSLEEP_DEFAULT, \ 348 .dbias = PMU_HP_DBIAS_LIGHTSLEEP_0V6_DEFAULT \ 349 } \ 350 }, \ 351 .lp_sys[PMU_MODE_LP_SLEEP] = { \ 352 .analog = { \ 353 .drv_b = PMU_LP_DRVB_DEEPSLEEP, \ 354 .pd_cur = PMU_PD_CUR_SLEEP_DEFAULT, \ 355 .bias_sleep = PMU_BIASSLP_SLEEP_DEFAULT, \ 356 .slp_xpd = PMU_LP_SLP_XPD_SLEEP_DEFAULT, \ 357 .slp_dbias = PMU_LP_SLP_DBIAS_SLEEP_DEFAULT, \ 358 .xpd = PMU_LP_XPD_SLEEP_DEFAULT, \ 359 .dbg_atten = PMU_DBG_ATTEN_LIGHTSLEEP_DEFAULT, \ 360 .dbias = PMU_LP_DBIAS_LIGHTSLEEP_0V7_DEFAULT \ 361 } \ 362 } \ 363 } 364 365 #define PMU_SLEEP_ANALOG_DSLP_CONFIG_DEFAULT(pd_flags) { \ 366 .hp_sys = { \ 367 .analog = { \ 368 .pd_cur = PMU_PD_CUR_SLEEP_DEFAULT, \ 369 .bias_sleep = PMU_BIASSLP_SLEEP_DEFAULT, \ 370 .xpd = PMU_HP_XPD_DEEPSLEEP, \ 371 .dbg_atten = PMU_DBG_HP_DEEPSLEEP \ 372 } \ 373 }, \ 374 .lp_sys[PMU_MODE_LP_SLEEP] = { \ 375 .analog = { \ 376 .drv_b = PMU_LP_DRVB_DEEPSLEEP, \ 377 .pd_cur = PMU_PD_CUR_SLEEP_DEFAULT, \ 378 .bias_sleep = PMU_BIASSLP_SLEEP_DEFAULT, \ 379 .slp_xpd = PMU_LP_SLP_XPD_SLEEP_DEFAULT, \ 380 .slp_dbias = PMU_LP_SLP_DBIAS_SLEEP_DEFAULT, \ 381 .xpd = PMU_LP_XPD_SLEEP_DEFAULT, \ 382 .dbg_atten = PMU_DBG_ATTEN_DEEPSLEEP_DEFAULT, \ 383 .dbias = PMU_LP_DBIAS_DEEPSLEEP_0V7_DEFAULT \ 384 } \ 385 } \ 386 } 387 388 typedef struct { 389 pmu_hp_param_t hp_sys; 390 pmu_lp_param_t lp_sys; 391 pmu_hp_lp_param_t hp_lp; 392 } pmu_sleep_param_config_t; 393 394 #define PMU_SLEEP_PARAM_CONFIG_DEFAULT(pd_flags) { \ 395 .hp_sys = { \ 396 .min_slp_slow_clk_cycle = PMU_HP_SLEEP_MIN_SLOW_CLK_CYCLES, \ 397 .analog_wait_target_cycle = PMU_HP_ANALOG_WAIT_TARGET_CYCLES, \ 398 .digital_power_supply_wait_cycle = PMU_HP_DIGITAL_POWER_SUPPLY_WAIT_CYCLES, \ 399 .digital_power_up_wait_cycle = PMU_HP_DIGITAL_POWER_UP_WAIT_CYCLES, \ 400 .modem_wakeup_wait_cycle = PMU_HP_MODEM_WAKEUP_WAIT_CYCLES, \ 401 .pll_stable_wait_cycle = PMU_HP_PLL_STABLE_WAIT_CYCLES \ 402 }, \ 403 .lp_sys = { \ 404 .min_slp_slow_clk_cycle = PMU_LP_SLEEP_MIN_SLOW_CLK_CYCLES, \ 405 .analog_wait_target_cycle = PMU_LP_ANALOG_WAIT_TARGET_CYCLES, \ 406 .digital_power_supply_wait_cycle = PMU_LP_DIGITAL_POWER_SUPPLY_WAIT_CYCLES, \ 407 .digital_power_up_wait_cycle = PMU_LP_DIGITAL_POWER_UP_WAIT_CYCLES \ 408 }, \ 409 .hp_lp = { \ 410 .xtal_stable_wait_slow_clk_cycle = PMU_LP_XTAL_STABLE_WAIT_SLOW_CLK_CYCLES \ 411 } \ 412 } 413 414 typedef struct { 415 pmu_sleep_power_config_t power; 416 pmu_sleep_digital_config_t digital; 417 pmu_sleep_analog_config_t analog; 418 pmu_sleep_param_config_t param; 419 } pmu_sleep_config_t; 420 421 typedef struct pmu_sleep_machine_constant { 422 struct { 423 uint16_t min_slp_time_us; /* Mininum sleep protection time (unit: microsecond) */ 424 uint8_t wakeup_wait_cycle; /* Modem wakeup signal (WiFi MAC and BEACON wakeup) waits for the slow & fast clock domain synchronization and the wakeup signal triggers the PMU FSM switching wait cycle (unit: slow clock cycle) */ 425 uint8_t reserved0; 426 uint16_t reserved1; 427 uint16_t analog_wait_time_us; /* LP LDO power up wait time (unit: microsecond) */ 428 uint16_t xtal_wait_stable_time_us; /* Main XTAL stabilization wait time (unit: microsecond) */ 429 uint8_t clk_switch_cycle; /* Clock switch to FOSC (unit: slow clock cycle) */ 430 uint8_t clk_power_on_wait_cycle; /* Clock power on wait cycle (unit: slow clock cycle) */ 431 uint16_t power_supply_wait_time_us; /* (unit: microsecond) */ 432 uint16_t power_up_wait_time_us; /* (unit: microsecond) */ 433 } lp; 434 struct { 435 uint16_t min_slp_time_us; /* Mininum sleep protection time (unit: microsecond) */ 436 uint16_t clock_domain_sync_time_us; /* The Slow OSC clock domain synchronizes time with the Fast OSC domain, at least 4 slow clock cycles (unit: microsecond) */ 437 uint16_t system_dfs_up_work_time_us; /* System DFS up scaling work time (unit: microsecond) */ 438 uint16_t analog_wait_time_us; /* HP LDO power up wait time (unit: microsecond) */ 439 uint16_t power_supply_wait_time_us; /* (unit: microsecond) */ 440 uint16_t power_up_wait_time_us; /* (unit: microsecond) */ 441 uint16_t regdma_s2m_work_time_us; /* Modem Subsystem (S2M switch) REGDMA restore time (unit: microsecond) */ 442 uint16_t regdma_s2a_work_time_us; /* SOC System (Digital Peripheral + Modem Subsystem) REGDMA (S2A switch) restore time (unit: microsecond) */ 443 uint16_t regdma_m2a_work_time_us; /* Digital Peripheral (M2A switch) REGDMA restore time (unit: microsecond) */ 444 uint16_t regdma_a2s_work_time_us; /* SOC System (Digital Peripheral + Modem Subsystem) REGDMA (A2S switch) backup time (unit: microsecond) */ 445 uint16_t regdma_rf_on_work_time_us; /* The REGDMA work time of RF enable (unit: microsecond) */ 446 uint16_t regdma_rf_off_work_time_us; /* The REGDMA work time of RF disable (unit: microsecond) */ 447 uint16_t xtal_wait_stable_time_us; /* Main XTAL stabilization wait time (unit: microsecond) */ 448 uint16_t pll_wait_stable_time_us; /* PLL stabilization wait time (unit: microsecond) */ 449 } hp; 450 } pmu_sleep_machine_constant_t; 451 452 #define PMU_SLEEP_MC_DEFAULT() { \ 453 .lp = { \ 454 .min_slp_time_us = 450, \ 455 .wakeup_wait_cycle = 4, \ 456 .analog_wait_time_us = 154, \ 457 .xtal_wait_stable_time_us = 250, \ 458 .clk_switch_cycle = 1, \ 459 .clk_power_on_wait_cycle = 1, \ 460 .power_supply_wait_time_us = 2, \ 461 .power_up_wait_time_us = 2 \ 462 }, \ 463 .hp = { \ 464 .min_slp_time_us = 450, \ 465 .clock_domain_sync_time_us = 150, \ 466 .system_dfs_up_work_time_us = 124, \ 467 .analog_wait_time_us = 154, \ 468 .power_supply_wait_time_us = 2, \ 469 .power_up_wait_time_us = 2, \ 470 .regdma_s2m_work_time_us = 172, \ 471 .regdma_s2a_work_time_us = PMU_REGDMA_S2A_WORK_TIME_US, \ 472 .regdma_m2a_work_time_us = 278, \ 473 .regdma_a2s_work_time_us = 382, \ 474 .regdma_rf_on_work_time_us = 70, \ 475 .regdma_rf_off_work_time_us = 23, \ 476 .xtal_wait_stable_time_us = 250, \ 477 .pll_wait_stable_time_us = 1 \ 478 } \ 479 } 480 481 #ifdef __cplusplus 482 } 483 #endif 484
