1 /** 2 * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #pragma once 7 8 #include <stdint.h> 9 #include "soc/soc.h" 10 #include "efuse_defs.h" 11 #ifdef __cplusplus 12 extern "C" { 13 #endif 14 15 /** EFUSE_BLK0_RDATA0_REG register */ 16 #define EFUSE_BLK0_RDATA0_REG (DR_REG_EFUSE_BASE + 0x0) 17 /** EFUSE_RD_EFUSE_WR_DIS : R; bitpos: [15:0]; default: 0; 18 * read for efuse_wr_disable 19 */ 20 #define EFUSE_RD_EFUSE_WR_DIS 0x0000FFFFU 21 #define EFUSE_RD_EFUSE_WR_DIS_M (EFUSE_RD_EFUSE_WR_DIS_V << EFUSE_RD_EFUSE_WR_DIS_S) 22 #define EFUSE_RD_EFUSE_WR_DIS_V 0x0000FFFFU 23 #define EFUSE_RD_EFUSE_WR_DIS_S 0 24 /** EFUSE_RD_EFUSE_RD_DIS : R; bitpos: [19:16]; default: 0; 25 * read for efuse_rd_disable 26 */ 27 #define EFUSE_RD_EFUSE_RD_DIS 0x0000000FU 28 #define EFUSE_RD_EFUSE_RD_DIS_M (EFUSE_RD_EFUSE_RD_DIS_V << EFUSE_RD_EFUSE_RD_DIS_S) 29 #define EFUSE_RD_EFUSE_RD_DIS_V 0x0000000FU 30 #define EFUSE_RD_EFUSE_RD_DIS_S 16 31 /** EFUSE_RD_FLASH_CRYPT_CNT : R; bitpos: [26:20]; default: 0; 32 * read for flash_crypt_cnt 33 */ 34 #define EFUSE_RD_FLASH_CRYPT_CNT 0x0000007FU 35 #define EFUSE_RD_FLASH_CRYPT_CNT_M (EFUSE_RD_FLASH_CRYPT_CNT_V << EFUSE_RD_FLASH_CRYPT_CNT_S) 36 #define EFUSE_RD_FLASH_CRYPT_CNT_V 0x0000007FU 37 #define EFUSE_RD_FLASH_CRYPT_CNT_S 20 38 /** EFUSE_RD_UART_DOWNLOAD_DIS : R; bitpos: [27]; default: 0; 39 * Disable UART download mode. Valid for ESP32 V3 and newer, only 40 */ 41 #define EFUSE_RD_UART_DOWNLOAD_DIS (BIT(27)) 42 #define EFUSE_RD_UART_DOWNLOAD_DIS_M (EFUSE_RD_UART_DOWNLOAD_DIS_V << EFUSE_RD_UART_DOWNLOAD_DIS_S) 43 #define EFUSE_RD_UART_DOWNLOAD_DIS_V 0x00000001U 44 #define EFUSE_RD_UART_DOWNLOAD_DIS_S 27 45 /** EFUSE_RESERVED_0_28 : R; bitpos: [31:28]; default: 0; 46 * reserved 47 */ 48 #define EFUSE_RESERVED_0_28 0x0000000FU 49 #define EFUSE_RESERVED_0_28_M (EFUSE_RESERVED_0_28_V << EFUSE_RESERVED_0_28_S) 50 #define EFUSE_RESERVED_0_28_V 0x0000000FU 51 #define EFUSE_RESERVED_0_28_S 28 52 53 /** EFUSE_BLK0_RDATA1_REG register */ 54 #define EFUSE_BLK0_RDATA1_REG (DR_REG_EFUSE_BASE + 0x4) 55 /** EFUSE_RD_MAC : R; bitpos: [31:0]; default: 0; 56 * MAC address 57 */ 58 #define EFUSE_RD_MAC 0xFFFFFFFFU 59 #define EFUSE_RD_MAC_M (EFUSE_RD_MAC_V << EFUSE_RD_MAC_S) 60 #define EFUSE_RD_MAC_V 0xFFFFFFFFU 61 #define EFUSE_RD_MAC_S 0 62 63 /** EFUSE_BLK0_RDATA2_REG register */ 64 #define EFUSE_BLK0_RDATA2_REG (DR_REG_EFUSE_BASE + 0x8) 65 /** EFUSE_RD_MAC_1 : R; bitpos: [15:0]; default: 0; 66 * MAC address 67 */ 68 #define EFUSE_RD_MAC_1 0x0000FFFFU 69 #define EFUSE_RD_MAC_1_M (EFUSE_RD_MAC_1_V << EFUSE_RD_MAC_1_S) 70 #define EFUSE_RD_MAC_1_V 0x0000FFFFU 71 #define EFUSE_RD_MAC_1_S 0 72 /** EFUSE_RD_MAC_CRC : R; bitpos: [23:16]; default: 0; 73 * CRC8 for MAC address 74 */ 75 #define EFUSE_RD_MAC_CRC 0x000000FFU 76 #define EFUSE_RD_MAC_CRC_M (EFUSE_RD_MAC_CRC_V << EFUSE_RD_MAC_CRC_S) 77 #define EFUSE_RD_MAC_CRC_V 0x000000FFU 78 #define EFUSE_RD_MAC_CRC_S 16 79 /** EFUSE_RD_RESERVE_0_88 : RW; bitpos: [31:24]; default: 0; 80 * Reserved, it was created by set_missed_fields_in_regs func 81 */ 82 #define EFUSE_RD_RESERVE_0_88 0x000000FFU 83 #define EFUSE_RD_RESERVE_0_88_M (EFUSE_RD_RESERVE_0_88_V << EFUSE_RD_RESERVE_0_88_S) 84 #define EFUSE_RD_RESERVE_0_88_V 0x000000FFU 85 #define EFUSE_RD_RESERVE_0_88_S 24 86 87 /** EFUSE_BLK0_RDATA3_REG register */ 88 #define EFUSE_BLK0_RDATA3_REG (DR_REG_EFUSE_BASE + 0xc) 89 /** EFUSE_RD_DISABLE_APP_CPU : R; bitpos: [0]; default: 0; 90 * Disables APP CPU 91 */ 92 #define EFUSE_RD_DISABLE_APP_CPU (BIT(0)) 93 #define EFUSE_RD_DISABLE_APP_CPU_M (EFUSE_RD_DISABLE_APP_CPU_V << EFUSE_RD_DISABLE_APP_CPU_S) 94 #define EFUSE_RD_DISABLE_APP_CPU_V 0x00000001U 95 #define EFUSE_RD_DISABLE_APP_CPU_S 0 96 /** EFUSE_RD_DISABLE_BT : R; bitpos: [1]; default: 0; 97 * Disables Bluetooth 98 */ 99 #define EFUSE_RD_DISABLE_BT (BIT(1)) 100 #define EFUSE_RD_DISABLE_BT_M (EFUSE_RD_DISABLE_BT_V << EFUSE_RD_DISABLE_BT_S) 101 #define EFUSE_RD_DISABLE_BT_V 0x00000001U 102 #define EFUSE_RD_DISABLE_BT_S 1 103 /** EFUSE_RD_CHIP_PACKAGE_4BIT : R; bitpos: [2]; default: 0; 104 * Chip package identifier #4bit 105 */ 106 #define EFUSE_RD_CHIP_PACKAGE_4BIT (BIT(2)) 107 #define EFUSE_RD_CHIP_PACKAGE_4BIT_M (EFUSE_RD_CHIP_PACKAGE_4BIT_V << EFUSE_RD_CHIP_PACKAGE_4BIT_S) 108 #define EFUSE_RD_CHIP_PACKAGE_4BIT_V 0x00000001U 109 #define EFUSE_RD_CHIP_PACKAGE_4BIT_S 2 110 /** EFUSE_RD_DIS_CACHE : R; bitpos: [3]; default: 0; 111 * Disables cache 112 */ 113 #define EFUSE_RD_DIS_CACHE (BIT(3)) 114 #define EFUSE_RD_DIS_CACHE_M (EFUSE_RD_DIS_CACHE_V << EFUSE_RD_DIS_CACHE_S) 115 #define EFUSE_RD_DIS_CACHE_V 0x00000001U 116 #define EFUSE_RD_DIS_CACHE_S 3 117 /** EFUSE_RD_SPI_PAD_CONFIG_HD : R; bitpos: [8:4]; default: 0; 118 * read for SPI_pad_config_hd 119 */ 120 #define EFUSE_RD_SPI_PAD_CONFIG_HD 0x0000001FU 121 #define EFUSE_RD_SPI_PAD_CONFIG_HD_M (EFUSE_RD_SPI_PAD_CONFIG_HD_V << EFUSE_RD_SPI_PAD_CONFIG_HD_S) 122 #define EFUSE_RD_SPI_PAD_CONFIG_HD_V 0x0000001FU 123 #define EFUSE_RD_SPI_PAD_CONFIG_HD_S 4 124 /** EFUSE_RD_CHIP_PACKAGE : RW; bitpos: [11:9]; default: 0; 125 * Chip package identifier 126 */ 127 #define EFUSE_RD_CHIP_PACKAGE 0x00000007U 128 #define EFUSE_RD_CHIP_PACKAGE_M (EFUSE_RD_CHIP_PACKAGE_V << EFUSE_RD_CHIP_PACKAGE_S) 129 #define EFUSE_RD_CHIP_PACKAGE_V 0x00000007U 130 #define EFUSE_RD_CHIP_PACKAGE_S 9 131 /** EFUSE_RD_CHIP_CPU_FREQ_LOW : RW; bitpos: [12]; default: 0; 132 * If set alongside EFUSE_RD_CHIP_CPU_FREQ_RATED, the ESP32's max CPU frequency is 133 * rated for 160MHz. 240MHz otherwise 134 */ 135 #define EFUSE_RD_CHIP_CPU_FREQ_LOW (BIT(12)) 136 #define EFUSE_RD_CHIP_CPU_FREQ_LOW_M (EFUSE_RD_CHIP_CPU_FREQ_LOW_V << EFUSE_RD_CHIP_CPU_FREQ_LOW_S) 137 #define EFUSE_RD_CHIP_CPU_FREQ_LOW_V 0x00000001U 138 #define EFUSE_RD_CHIP_CPU_FREQ_LOW_S 12 139 /** EFUSE_RD_CHIP_CPU_FREQ_RATED : RW; bitpos: [13]; default: 0; 140 * If set, the ESP32's maximum CPU frequency has been rated 141 */ 142 #define EFUSE_RD_CHIP_CPU_FREQ_RATED (BIT(13)) 143 #define EFUSE_RD_CHIP_CPU_FREQ_RATED_M (EFUSE_RD_CHIP_CPU_FREQ_RATED_V << EFUSE_RD_CHIP_CPU_FREQ_RATED_S) 144 #define EFUSE_RD_CHIP_CPU_FREQ_RATED_V 0x00000001U 145 #define EFUSE_RD_CHIP_CPU_FREQ_RATED_S 13 146 /** EFUSE_RD_BLK3_PART_RESERVE : RW; bitpos: [14]; default: 0; 147 * If set, this bit indicates that BLOCK3[143:96] is reserved for internal use 148 */ 149 #define EFUSE_RD_BLK3_PART_RESERVE (BIT(14)) 150 #define EFUSE_RD_BLK3_PART_RESERVE_M (EFUSE_RD_BLK3_PART_RESERVE_V << EFUSE_RD_BLK3_PART_RESERVE_S) 151 #define EFUSE_RD_BLK3_PART_RESERVE_V 0x00000001U 152 #define EFUSE_RD_BLK3_PART_RESERVE_S 14 153 /** EFUSE_RD_CHIP_VER_REV1 : RW; bitpos: [15]; default: 0; 154 * bit is set to 1 for rev1 silicon 155 */ 156 #define EFUSE_RD_CHIP_VER_REV1 (BIT(15)) 157 #define EFUSE_RD_CHIP_VER_REV1_M (EFUSE_RD_CHIP_VER_REV1_V << EFUSE_RD_CHIP_VER_REV1_S) 158 #define EFUSE_RD_CHIP_VER_REV1_V 0x00000001U 159 #define EFUSE_RD_CHIP_VER_REV1_S 15 160 /** EFUSE_RD_RESERVE_0_112 : RW; bitpos: [31:16]; default: 0; 161 * Reserved, it was created by set_missed_fields_in_regs func 162 */ 163 #define EFUSE_RD_RESERVE_0_112 0x0000FFFFU 164 #define EFUSE_RD_RESERVE_0_112_M (EFUSE_RD_RESERVE_0_112_V << EFUSE_RD_RESERVE_0_112_S) 165 #define EFUSE_RD_RESERVE_0_112_V 0x0000FFFFU 166 #define EFUSE_RD_RESERVE_0_112_S 16 167 168 /** EFUSE_BLK0_RDATA4_REG register */ 169 #define EFUSE_BLK0_RDATA4_REG (DR_REG_EFUSE_BASE + 0x10) 170 /** EFUSE_RD_CLK8M_FREQ : R; bitpos: [7:0]; default: 0; 171 * 8MHz clock freq override 172 */ 173 #define EFUSE_RD_CLK8M_FREQ 0x000000FFU 174 #define EFUSE_RD_CLK8M_FREQ_M (EFUSE_RD_CLK8M_FREQ_V << EFUSE_RD_CLK8M_FREQ_S) 175 #define EFUSE_RD_CLK8M_FREQ_V 0x000000FFU 176 #define EFUSE_RD_CLK8M_FREQ_S 0 177 /** EFUSE_RD_ADC_VREF : RW; bitpos: [12:8]; default: 0; 178 * True ADC reference voltage 179 */ 180 #define EFUSE_RD_ADC_VREF 0x0000001FU 181 #define EFUSE_RD_ADC_VREF_M (EFUSE_RD_ADC_VREF_V << EFUSE_RD_ADC_VREF_S) 182 #define EFUSE_RD_ADC_VREF_V 0x0000001FU 183 #define EFUSE_RD_ADC_VREF_S 8 184 /** EFUSE_RD_RESERVE_0_141 : RW; bitpos: [13]; default: 0; 185 * Reserved, it was created by set_missed_fields_in_regs func 186 */ 187 #define EFUSE_RD_RESERVE_0_141 (BIT(13)) 188 #define EFUSE_RD_RESERVE_0_141_M (EFUSE_RD_RESERVE_0_141_V << EFUSE_RD_RESERVE_0_141_S) 189 #define EFUSE_RD_RESERVE_0_141_V 0x00000001U 190 #define EFUSE_RD_RESERVE_0_141_S 13 191 /** EFUSE_RD_XPD_SDIO_REG : R; bitpos: [14]; default: 0; 192 * read for XPD_SDIO_REG 193 */ 194 #define EFUSE_RD_XPD_SDIO_REG (BIT(14)) 195 #define EFUSE_RD_XPD_SDIO_REG_M (EFUSE_RD_XPD_SDIO_REG_V << EFUSE_RD_XPD_SDIO_REG_S) 196 #define EFUSE_RD_XPD_SDIO_REG_V 0x00000001U 197 #define EFUSE_RD_XPD_SDIO_REG_S 14 198 /** EFUSE_RD_XPD_SDIO_TIEH : R; bitpos: [15]; default: 0; 199 * If XPD_SDIO_FORCE & XPD_SDIO_REG 200 */ 201 #define EFUSE_RD_XPD_SDIO_TIEH (BIT(15)) 202 #define EFUSE_RD_XPD_SDIO_TIEH_M (EFUSE_RD_XPD_SDIO_TIEH_V << EFUSE_RD_XPD_SDIO_TIEH_S) 203 #define EFUSE_RD_XPD_SDIO_TIEH_V 0x00000001U 204 #define EFUSE_RD_XPD_SDIO_TIEH_S 15 205 /** EFUSE_RD_XPD_SDIO_FORCE : R; bitpos: [16]; default: 0; 206 * Ignore MTDI pin (GPIO12) for VDD_SDIO on reset 207 */ 208 #define EFUSE_RD_XPD_SDIO_FORCE (BIT(16)) 209 #define EFUSE_RD_XPD_SDIO_FORCE_M (EFUSE_RD_XPD_SDIO_FORCE_V << EFUSE_RD_XPD_SDIO_FORCE_S) 210 #define EFUSE_RD_XPD_SDIO_FORCE_V 0x00000001U 211 #define EFUSE_RD_XPD_SDIO_FORCE_S 16 212 /** EFUSE_RD_RESERVE_0_145 : RW; bitpos: [31:17]; default: 0; 213 * Reserved, it was created by set_missed_fields_in_regs func 214 */ 215 #define EFUSE_RD_RESERVE_0_145 0x00007FFFU 216 #define EFUSE_RD_RESERVE_0_145_M (EFUSE_RD_RESERVE_0_145_V << EFUSE_RD_RESERVE_0_145_S) 217 #define EFUSE_RD_RESERVE_0_145_V 0x00007FFFU 218 #define EFUSE_RD_RESERVE_0_145_S 17 219 220 /** EFUSE_BLK0_RDATA5_REG register */ 221 #define EFUSE_BLK0_RDATA5_REG (DR_REG_EFUSE_BASE + 0x14) 222 /** EFUSE_RD_SPI_PAD_CONFIG_CLK : R; bitpos: [4:0]; default: 0; 223 * read for SPI_pad_config_clk 224 */ 225 #define EFUSE_RD_SPI_PAD_CONFIG_CLK 0x0000001FU 226 #define EFUSE_RD_SPI_PAD_CONFIG_CLK_M (EFUSE_RD_SPI_PAD_CONFIG_CLK_V << EFUSE_RD_SPI_PAD_CONFIG_CLK_S) 227 #define EFUSE_RD_SPI_PAD_CONFIG_CLK_V 0x0000001FU 228 #define EFUSE_RD_SPI_PAD_CONFIG_CLK_S 0 229 /** EFUSE_RD_SPI_PAD_CONFIG_Q : R; bitpos: [9:5]; default: 0; 230 * read for SPI_pad_config_q 231 */ 232 #define EFUSE_RD_SPI_PAD_CONFIG_Q 0x0000001FU 233 #define EFUSE_RD_SPI_PAD_CONFIG_Q_M (EFUSE_RD_SPI_PAD_CONFIG_Q_V << EFUSE_RD_SPI_PAD_CONFIG_Q_S) 234 #define EFUSE_RD_SPI_PAD_CONFIG_Q_V 0x0000001FU 235 #define EFUSE_RD_SPI_PAD_CONFIG_Q_S 5 236 /** EFUSE_RD_SPI_PAD_CONFIG_D : R; bitpos: [14:10]; default: 0; 237 * read for SPI_pad_config_d 238 */ 239 #define EFUSE_RD_SPI_PAD_CONFIG_D 0x0000001FU 240 #define EFUSE_RD_SPI_PAD_CONFIG_D_M (EFUSE_RD_SPI_PAD_CONFIG_D_V << EFUSE_RD_SPI_PAD_CONFIG_D_S) 241 #define EFUSE_RD_SPI_PAD_CONFIG_D_V 0x0000001FU 242 #define EFUSE_RD_SPI_PAD_CONFIG_D_S 10 243 /** EFUSE_RD_SPI_PAD_CONFIG_CS0 : R; bitpos: [19:15]; default: 0; 244 * read for SPI_pad_config_cs0 245 */ 246 #define EFUSE_RD_SPI_PAD_CONFIG_CS0 0x0000001FU 247 #define EFUSE_RD_SPI_PAD_CONFIG_CS0_M (EFUSE_RD_SPI_PAD_CONFIG_CS0_V << EFUSE_RD_SPI_PAD_CONFIG_CS0_S) 248 #define EFUSE_RD_SPI_PAD_CONFIG_CS0_V 0x0000001FU 249 #define EFUSE_RD_SPI_PAD_CONFIG_CS0_S 15 250 /** EFUSE_RD_CHIP_VER_REV2 : R; bitpos: [20]; default: 0; */ 251 #define EFUSE_RD_CHIP_VER_REV2 (BIT(20)) 252 #define EFUSE_RD_CHIP_VER_REV2_M (EFUSE_RD_CHIP_VER_REV2_V << EFUSE_RD_CHIP_VER_REV2_S) 253 #define EFUSE_RD_CHIP_VER_REV2_V 0x00000001U 254 #define EFUSE_RD_CHIP_VER_REV2_S 20 255 /** EFUSE_RD_RESERVE_0_181 : RW; bitpos: [21]; default: 0; 256 * Reserved, it was created by set_missed_fields_in_regs func 257 */ 258 #define EFUSE_RD_RESERVE_0_181 (BIT(21)) 259 #define EFUSE_RD_RESERVE_0_181_M (EFUSE_RD_RESERVE_0_181_V << EFUSE_RD_RESERVE_0_181_S) 260 #define EFUSE_RD_RESERVE_0_181_V 0x00000001U 261 #define EFUSE_RD_RESERVE_0_181_S 21 262 /** EFUSE_RD_VOL_LEVEL_HP_INV : R; bitpos: [23:22]; default: 0; 263 * This field stores the voltage level for CPU to run at 240 MHz, or for flash/PSRAM 264 * to run at 80 MHz.0x0: level 7; 0x1: level 6; 0x2: level 5; 0x3: level 4. (RO) 265 */ 266 #define EFUSE_RD_VOL_LEVEL_HP_INV 0x00000003U 267 #define EFUSE_RD_VOL_LEVEL_HP_INV_M (EFUSE_RD_VOL_LEVEL_HP_INV_V << EFUSE_RD_VOL_LEVEL_HP_INV_S) 268 #define EFUSE_RD_VOL_LEVEL_HP_INV_V 0x00000003U 269 #define EFUSE_RD_VOL_LEVEL_HP_INV_S 22 270 /** EFUSE_RD_WAFER_VERSION_MINOR : R; bitpos: [25:24]; default: 0; */ 271 #define EFUSE_RD_WAFER_VERSION_MINOR 0x00000003U 272 #define EFUSE_RD_WAFER_VERSION_MINOR_M (EFUSE_RD_WAFER_VERSION_MINOR_V << EFUSE_RD_WAFER_VERSION_MINOR_S) 273 #define EFUSE_RD_WAFER_VERSION_MINOR_V 0x00000003U 274 #define EFUSE_RD_WAFER_VERSION_MINOR_S 24 275 /** EFUSE_RD_RESERVE_0_186 : RW; bitpos: [27:26]; default: 0; 276 * Reserved, it was created by set_missed_fields_in_regs func 277 */ 278 #define EFUSE_RD_RESERVE_0_186 0x00000003U 279 #define EFUSE_RD_RESERVE_0_186_M (EFUSE_RD_RESERVE_0_186_V << EFUSE_RD_RESERVE_0_186_S) 280 #define EFUSE_RD_RESERVE_0_186_V 0x00000003U 281 #define EFUSE_RD_RESERVE_0_186_S 26 282 /** EFUSE_RD_FLASH_CRYPT_CONFIG : R; bitpos: [31:28]; default: 0; 283 * read for flash_crypt_config 284 */ 285 #define EFUSE_RD_FLASH_CRYPT_CONFIG 0x0000000FU 286 #define EFUSE_RD_FLASH_CRYPT_CONFIG_M (EFUSE_RD_FLASH_CRYPT_CONFIG_V << EFUSE_RD_FLASH_CRYPT_CONFIG_S) 287 #define EFUSE_RD_FLASH_CRYPT_CONFIG_V 0x0000000FU 288 #define EFUSE_RD_FLASH_CRYPT_CONFIG_S 28 289 290 /** EFUSE_BLK0_RDATA6_REG register */ 291 #define EFUSE_BLK0_RDATA6_REG (DR_REG_EFUSE_BASE + 0x18) 292 /** EFUSE_RD_CODING_SCHEME : R; bitpos: [1:0]; default: 0; 293 * read for coding_scheme 294 */ 295 #define EFUSE_RD_CODING_SCHEME 0x00000003U 296 #define EFUSE_RD_CODING_SCHEME_M (EFUSE_RD_CODING_SCHEME_V << EFUSE_RD_CODING_SCHEME_S) 297 #define EFUSE_RD_CODING_SCHEME_V 0x00000003U 298 #define EFUSE_RD_CODING_SCHEME_S 0 299 /** EFUSE_RD_CONSOLE_DEBUG_DISABLE : R; bitpos: [2]; default: 0; 300 * read for console_debug_disable 301 */ 302 #define EFUSE_RD_CONSOLE_DEBUG_DISABLE (BIT(2)) 303 #define EFUSE_RD_CONSOLE_DEBUG_DISABLE_M (EFUSE_RD_CONSOLE_DEBUG_DISABLE_V << EFUSE_RD_CONSOLE_DEBUG_DISABLE_S) 304 #define EFUSE_RD_CONSOLE_DEBUG_DISABLE_V 0x00000001U 305 #define EFUSE_RD_CONSOLE_DEBUG_DISABLE_S 2 306 /** EFUSE_RD_DISABLE_SDIO_HOST : R; bitpos: [3]; default: 0; */ 307 #define EFUSE_RD_DISABLE_SDIO_HOST (BIT(3)) 308 #define EFUSE_RD_DISABLE_SDIO_HOST_M (EFUSE_RD_DISABLE_SDIO_HOST_V << EFUSE_RD_DISABLE_SDIO_HOST_S) 309 #define EFUSE_RD_DISABLE_SDIO_HOST_V 0x00000001U 310 #define EFUSE_RD_DISABLE_SDIO_HOST_S 3 311 /** EFUSE_RD_ABS_DONE_0 : R; bitpos: [4]; default: 0; 312 * read for abstract_done_0 313 */ 314 #define EFUSE_RD_ABS_DONE_0 (BIT(4)) 315 #define EFUSE_RD_ABS_DONE_0_M (EFUSE_RD_ABS_DONE_0_V << EFUSE_RD_ABS_DONE_0_S) 316 #define EFUSE_RD_ABS_DONE_0_V 0x00000001U 317 #define EFUSE_RD_ABS_DONE_0_S 4 318 /** EFUSE_RD_ABS_DONE_1 : R; bitpos: [5]; default: 0; 319 * read for abstract_done_1 320 */ 321 #define EFUSE_RD_ABS_DONE_1 (BIT(5)) 322 #define EFUSE_RD_ABS_DONE_1_M (EFUSE_RD_ABS_DONE_1_V << EFUSE_RD_ABS_DONE_1_S) 323 #define EFUSE_RD_ABS_DONE_1_V 0x00000001U 324 #define EFUSE_RD_ABS_DONE_1_S 5 325 /** EFUSE_RD_JTAG_DISABLE : R; bitpos: [6]; default: 0; 326 * Disable JTAG 327 */ 328 #define EFUSE_RD_JTAG_DISABLE (BIT(6)) 329 #define EFUSE_RD_JTAG_DISABLE_M (EFUSE_RD_JTAG_DISABLE_V << EFUSE_RD_JTAG_DISABLE_S) 330 #define EFUSE_RD_JTAG_DISABLE_V 0x00000001U 331 #define EFUSE_RD_JTAG_DISABLE_S 6 332 /** EFUSE_RD_DISABLE_DL_ENCRYPT : R; bitpos: [7]; default: 0; 333 * read for download_dis_encrypt 334 */ 335 #define EFUSE_RD_DISABLE_DL_ENCRYPT (BIT(7)) 336 #define EFUSE_RD_DISABLE_DL_ENCRYPT_M (EFUSE_RD_DISABLE_DL_ENCRYPT_V << EFUSE_RD_DISABLE_DL_ENCRYPT_S) 337 #define EFUSE_RD_DISABLE_DL_ENCRYPT_V 0x00000001U 338 #define EFUSE_RD_DISABLE_DL_ENCRYPT_S 7 339 /** EFUSE_RD_DISABLE_DL_DECRYPT : R; bitpos: [8]; default: 0; 340 * read for download_dis_decrypt 341 */ 342 #define EFUSE_RD_DISABLE_DL_DECRYPT (BIT(8)) 343 #define EFUSE_RD_DISABLE_DL_DECRYPT_M (EFUSE_RD_DISABLE_DL_DECRYPT_V << EFUSE_RD_DISABLE_DL_DECRYPT_S) 344 #define EFUSE_RD_DISABLE_DL_DECRYPT_V 0x00000001U 345 #define EFUSE_RD_DISABLE_DL_DECRYPT_S 8 346 /** EFUSE_RD_DISABLE_DL_CACHE : R; bitpos: [9]; default: 0; 347 * read for download_dis_cache 348 */ 349 #define EFUSE_RD_DISABLE_DL_CACHE (BIT(9)) 350 #define EFUSE_RD_DISABLE_DL_CACHE_M (EFUSE_RD_DISABLE_DL_CACHE_V << EFUSE_RD_DISABLE_DL_CACHE_S) 351 #define EFUSE_RD_DISABLE_DL_CACHE_V 0x00000001U 352 #define EFUSE_RD_DISABLE_DL_CACHE_S 9 353 /** EFUSE_RD_KEY_STATUS : R; bitpos: [10]; default: 0; 354 * read for key_status 355 */ 356 #define EFUSE_RD_KEY_STATUS (BIT(10)) 357 #define EFUSE_RD_KEY_STATUS_M (EFUSE_RD_KEY_STATUS_V << EFUSE_RD_KEY_STATUS_S) 358 #define EFUSE_RD_KEY_STATUS_V 0x00000001U 359 #define EFUSE_RD_KEY_STATUS_S 10 360 /** EFUSE_RD_RESERVE_0_203 : RW; bitpos: [31:11]; default: 0; 361 * Reserved, it was created by set_missed_fields_in_regs func 362 */ 363 #define EFUSE_RD_RESERVE_0_203 0x001FFFFFU 364 #define EFUSE_RD_RESERVE_0_203_M (EFUSE_RD_RESERVE_0_203_V << EFUSE_RD_RESERVE_0_203_S) 365 #define EFUSE_RD_RESERVE_0_203_V 0x001FFFFFU 366 #define EFUSE_RD_RESERVE_0_203_S 11 367 368 /** EFUSE_BLK0_WDATA0_REG register */ 369 #define EFUSE_BLK0_WDATA0_REG (DR_REG_EFUSE_BASE + 0x1c) 370 /** EFUSE_WR_DIS : RW; bitpos: [15:0]; default: 0; 371 * program for efuse_wr_disable 372 */ 373 #define EFUSE_WR_DIS 0x0000FFFFU 374 #define EFUSE_WR_DIS_M (EFUSE_WR_DIS_V << EFUSE_WR_DIS_S) 375 #define EFUSE_WR_DIS_V 0x0000FFFFU 376 #define EFUSE_WR_DIS_S 0 377 /** EFUSE_RD_DIS : RW; bitpos: [19:16]; default: 0; 378 * program for efuse_rd_disable 379 */ 380 #define EFUSE_RD_DIS 0x0000000FU 381 #define EFUSE_RD_DIS_M (EFUSE_RD_DIS_V << EFUSE_RD_DIS_S) 382 #define EFUSE_RD_DIS_V 0x0000000FU 383 #define EFUSE_RD_DIS_S 16 384 /** EFUSE_FLASH_CRYPT_CNT : RW; bitpos: [26:20]; default: 0; 385 * program for flash_crypt_cnt 386 */ 387 #define EFUSE_FLASH_CRYPT_CNT 0x0000007FU 388 #define EFUSE_FLASH_CRYPT_CNT_M (EFUSE_FLASH_CRYPT_CNT_V << EFUSE_FLASH_CRYPT_CNT_S) 389 #define EFUSE_FLASH_CRYPT_CNT_V 0x0000007FU 390 #define EFUSE_FLASH_CRYPT_CNT_S 20 391 392 /** EFUSE_BLK0_WDATA1_REG register */ 393 #define EFUSE_BLK0_WDATA1_REG (DR_REG_EFUSE_BASE + 0x20) 394 /** EFUSE_WIFI_MAC_CRC_LOW : RW; bitpos: [31:0]; default: 0; 395 * program for low 32bit WIFI_MAC_Address 396 */ 397 #define EFUSE_WIFI_MAC_CRC_LOW 0xFFFFFFFFU 398 #define EFUSE_WIFI_MAC_CRC_LOW_M (EFUSE_WIFI_MAC_CRC_LOW_V << EFUSE_WIFI_MAC_CRC_LOW_S) 399 #define EFUSE_WIFI_MAC_CRC_LOW_V 0xFFFFFFFFU 400 #define EFUSE_WIFI_MAC_CRC_LOW_S 0 401 402 /** EFUSE_BLK0_WDATA2_REG register */ 403 #define EFUSE_BLK0_WDATA2_REG (DR_REG_EFUSE_BASE + 0x24) 404 /** EFUSE_WIFI_MAC_CRC_HIGH : RW; bitpos: [23:0]; default: 0; 405 * program for high 24bit WIFI_MAC_Address 406 */ 407 #define EFUSE_WIFI_MAC_CRC_HIGH 0x00FFFFFFU 408 #define EFUSE_WIFI_MAC_CRC_HIGH_M (EFUSE_WIFI_MAC_CRC_HIGH_V << EFUSE_WIFI_MAC_CRC_HIGH_S) 409 #define EFUSE_WIFI_MAC_CRC_HIGH_V 0x00FFFFFFU 410 #define EFUSE_WIFI_MAC_CRC_HIGH_S 0 411 412 /** EFUSE_BLK0_WDATA3_REG register */ 413 #define EFUSE_BLK0_WDATA3_REG (DR_REG_EFUSE_BASE + 0x28) 414 /** EFUSE_DISABLE_APP_CPU : R; bitpos: [0]; default: 0; 415 * Disables APP CPU 416 */ 417 #define EFUSE_DISABLE_APP_CPU (BIT(0)) 418 #define EFUSE_DISABLE_APP_CPU_M (EFUSE_DISABLE_APP_CPU_V << EFUSE_DISABLE_APP_CPU_S) 419 #define EFUSE_DISABLE_APP_CPU_V 0x00000001U 420 #define EFUSE_DISABLE_APP_CPU_S 0 421 /** EFUSE_DISABLE_BT : R; bitpos: [1]; default: 0; 422 * Disables Bluetooth 423 */ 424 #define EFUSE_DISABLE_BT (BIT(1)) 425 #define EFUSE_DISABLE_BT_M (EFUSE_DISABLE_BT_V << EFUSE_DISABLE_BT_S) 426 #define EFUSE_DISABLE_BT_V 0x00000001U 427 #define EFUSE_DISABLE_BT_S 1 428 /** EFUSE_CHIP_PACKAGE_4BIT : R; bitpos: [2]; default: 0; 429 * Chip package identifier #4bit 430 */ 431 #define EFUSE_CHIP_PACKAGE_4BIT (BIT(2)) 432 #define EFUSE_CHIP_PACKAGE_4BIT_M (EFUSE_CHIP_PACKAGE_4BIT_V << EFUSE_CHIP_PACKAGE_4BIT_S) 433 #define EFUSE_CHIP_PACKAGE_4BIT_V 0x00000001U 434 #define EFUSE_CHIP_PACKAGE_4BIT_S 2 435 /** EFUSE_DIS_CACHE : R; bitpos: [3]; default: 0; 436 * Disables cache 437 */ 438 #define EFUSE_DIS_CACHE (BIT(3)) 439 #define EFUSE_DIS_CACHE_M (EFUSE_DIS_CACHE_V << EFUSE_DIS_CACHE_S) 440 #define EFUSE_DIS_CACHE_V 0x00000001U 441 #define EFUSE_DIS_CACHE_S 3 442 /** EFUSE_SPI_PAD_CONFIG_HD : R; bitpos: [8:4]; default: 0; 443 * program for SPI_pad_config_hd 444 */ 445 #define EFUSE_SPI_PAD_CONFIG_HD 0x0000001FU 446 #define EFUSE_SPI_PAD_CONFIG_HD_M (EFUSE_SPI_PAD_CONFIG_HD_V << EFUSE_SPI_PAD_CONFIG_HD_S) 447 #define EFUSE_SPI_PAD_CONFIG_HD_V 0x0000001FU 448 #define EFUSE_SPI_PAD_CONFIG_HD_S 4 449 /** EFUSE_CHIP_PACKAGE : RW; bitpos: [11:9]; default: 0; 450 * Chip package identifier 451 */ 452 #define EFUSE_CHIP_PACKAGE 0x00000007U 453 #define EFUSE_CHIP_PACKAGE_M (EFUSE_CHIP_PACKAGE_V << EFUSE_CHIP_PACKAGE_S) 454 #define EFUSE_CHIP_PACKAGE_V 0x00000007U 455 #define EFUSE_CHIP_PACKAGE_S 9 456 /** EFUSE_CHIP_CPU_FREQ_LOW : RW; bitpos: [12]; default: 0; 457 * If set alongside EFUSE_RD_CHIP_CPU_FREQ_RATED, the ESP32's max CPU frequency is 458 * rated for 160MHz. 240MHz otherwise 459 */ 460 #define EFUSE_CHIP_CPU_FREQ_LOW (BIT(12)) 461 #define EFUSE_CHIP_CPU_FREQ_LOW_M (EFUSE_CHIP_CPU_FREQ_LOW_V << EFUSE_CHIP_CPU_FREQ_LOW_S) 462 #define EFUSE_CHIP_CPU_FREQ_LOW_V 0x00000001U 463 #define EFUSE_CHIP_CPU_FREQ_LOW_S 12 464 /** EFUSE_CHIP_CPU_FREQ_RATED : RW; bitpos: [13]; default: 0; 465 * If set, the ESP32's maximum CPU frequency has been rated 466 */ 467 #define EFUSE_CHIP_CPU_FREQ_RATED (BIT(13)) 468 #define EFUSE_CHIP_CPU_FREQ_RATED_M (EFUSE_CHIP_CPU_FREQ_RATED_V << EFUSE_CHIP_CPU_FREQ_RATED_S) 469 #define EFUSE_CHIP_CPU_FREQ_RATED_V 0x00000001U 470 #define EFUSE_CHIP_CPU_FREQ_RATED_S 13 471 /** EFUSE_BLK3_PART_RESERVE : RW; bitpos: [14]; default: 0; 472 * If set, this bit indicates that BLOCK3[143:96] is reserved for internal use 473 */ 474 #define EFUSE_BLK3_PART_RESERVE (BIT(14)) 475 #define EFUSE_BLK3_PART_RESERVE_M (EFUSE_BLK3_PART_RESERVE_V << EFUSE_BLK3_PART_RESERVE_S) 476 #define EFUSE_BLK3_PART_RESERVE_V 0x00000001U 477 #define EFUSE_BLK3_PART_RESERVE_S 14 478 /** EFUSE_CHIP_VER_REV1 : RW; bitpos: [15]; default: 0; 479 * bit is set to 1 for rev1 silicon 480 */ 481 #define EFUSE_CHIP_VER_REV1 (BIT(15)) 482 #define EFUSE_CHIP_VER_REV1_M (EFUSE_CHIP_VER_REV1_V << EFUSE_CHIP_VER_REV1_S) 483 #define EFUSE_CHIP_VER_REV1_V 0x00000001U 484 #define EFUSE_CHIP_VER_REV1_S 15 485 /** EFUSE_RESERVE_0_112 : RW; bitpos: [31:16]; default: 0; 486 * Reserved, it was created by set_missed_fields_in_regs func 487 */ 488 #define EFUSE_RESERVE_0_112 0x0000FFFFU 489 #define EFUSE_RESERVE_0_112_M (EFUSE_RESERVE_0_112_V << EFUSE_RESERVE_0_112_S) 490 #define EFUSE_RESERVE_0_112_V 0x0000FFFFU 491 #define EFUSE_RESERVE_0_112_S 16 492 493 /** EFUSE_BLK0_WDATA4_REG register */ 494 #define EFUSE_BLK0_WDATA4_REG (DR_REG_EFUSE_BASE + 0x2c) 495 /** EFUSE_CLK8M_FREQ : R; bitpos: [7:0]; default: 0; 496 * 8MHz clock freq override 497 */ 498 #define EFUSE_CLK8M_FREQ 0x000000FFU 499 #define EFUSE_CLK8M_FREQ_M (EFUSE_CLK8M_FREQ_V << EFUSE_CLK8M_FREQ_S) 500 #define EFUSE_CLK8M_FREQ_V 0x000000FFU 501 #define EFUSE_CLK8M_FREQ_S 0 502 /** EFUSE_ADC_VREF : RW; bitpos: [12:8]; default: 0; 503 * True ADC reference voltage 504 */ 505 #define EFUSE_ADC_VREF 0x0000001FU 506 #define EFUSE_ADC_VREF_M (EFUSE_ADC_VREF_V << EFUSE_ADC_VREF_S) 507 #define EFUSE_ADC_VREF_V 0x0000001FU 508 #define EFUSE_ADC_VREF_S 8 509 /** EFUSE_RESERVE_0_141 : RW; bitpos: [13]; default: 0; 510 * Reserved, it was created by set_missed_fields_in_regs func 511 */ 512 #define EFUSE_RESERVE_0_141 (BIT(13)) 513 #define EFUSE_RESERVE_0_141_M (EFUSE_RESERVE_0_141_V << EFUSE_RESERVE_0_141_S) 514 #define EFUSE_RESERVE_0_141_V 0x00000001U 515 #define EFUSE_RESERVE_0_141_S 13 516 /** EFUSE_XPD_SDIO_REG : R; bitpos: [14]; default: 0; 517 * program for XPD_SDIO_REG 518 */ 519 #define EFUSE_XPD_SDIO_REG (BIT(14)) 520 #define EFUSE_XPD_SDIO_REG_M (EFUSE_XPD_SDIO_REG_V << EFUSE_XPD_SDIO_REG_S) 521 #define EFUSE_XPD_SDIO_REG_V 0x00000001U 522 #define EFUSE_XPD_SDIO_REG_S 14 523 /** EFUSE_XPD_SDIO_TIEH : R; bitpos: [15]; default: 0; 524 * If XPD_SDIO_FORCE & XPD_SDIO_REG 525 */ 526 #define EFUSE_XPD_SDIO_TIEH (BIT(15)) 527 #define EFUSE_XPD_SDIO_TIEH_M (EFUSE_XPD_SDIO_TIEH_V << EFUSE_XPD_SDIO_TIEH_S) 528 #define EFUSE_XPD_SDIO_TIEH_V 0x00000001U 529 #define EFUSE_XPD_SDIO_TIEH_S 15 530 /** EFUSE_XPD_SDIO_FORCE : R; bitpos: [16]; default: 0; 531 * Ignore MTDI pin (GPIO12) for VDD_SDIO on reset 532 */ 533 #define EFUSE_XPD_SDIO_FORCE (BIT(16)) 534 #define EFUSE_XPD_SDIO_FORCE_M (EFUSE_XPD_SDIO_FORCE_V << EFUSE_XPD_SDIO_FORCE_S) 535 #define EFUSE_XPD_SDIO_FORCE_V 0x00000001U 536 #define EFUSE_XPD_SDIO_FORCE_S 16 537 /** EFUSE_RESERVE_0_145 : RW; bitpos: [31:17]; default: 0; 538 * Reserved, it was created by set_missed_fields_in_regs func 539 */ 540 #define EFUSE_RESERVE_0_145 0x00007FFFU 541 #define EFUSE_RESERVE_0_145_M (EFUSE_RESERVE_0_145_V << EFUSE_RESERVE_0_145_S) 542 #define EFUSE_RESERVE_0_145_V 0x00007FFFU 543 #define EFUSE_RESERVE_0_145_S 17 544 545 /** EFUSE_BLK0_WDATA5_REG register */ 546 #define EFUSE_BLK0_WDATA5_REG (DR_REG_EFUSE_BASE + 0x30) 547 /** EFUSE_SPI_PAD_CONFIG_CLK : R; bitpos: [4:0]; default: 0; 548 * program for SPI_pad_config_clk 549 */ 550 #define EFUSE_SPI_PAD_CONFIG_CLK 0x0000001FU 551 #define EFUSE_SPI_PAD_CONFIG_CLK_M (EFUSE_SPI_PAD_CONFIG_CLK_V << EFUSE_SPI_PAD_CONFIG_CLK_S) 552 #define EFUSE_SPI_PAD_CONFIG_CLK_V 0x0000001FU 553 #define EFUSE_SPI_PAD_CONFIG_CLK_S 0 554 /** EFUSE_SPI_PAD_CONFIG_Q : R; bitpos: [9:5]; default: 0; 555 * program for SPI_pad_config_q 556 */ 557 #define EFUSE_SPI_PAD_CONFIG_Q 0x0000001FU 558 #define EFUSE_SPI_PAD_CONFIG_Q_M (EFUSE_SPI_PAD_CONFIG_Q_V << EFUSE_SPI_PAD_CONFIG_Q_S) 559 #define EFUSE_SPI_PAD_CONFIG_Q_V 0x0000001FU 560 #define EFUSE_SPI_PAD_CONFIG_Q_S 5 561 /** EFUSE_SPI_PAD_CONFIG_D : R; bitpos: [14:10]; default: 0; 562 * program for SPI_pad_config_d 563 */ 564 #define EFUSE_SPI_PAD_CONFIG_D 0x0000001FU 565 #define EFUSE_SPI_PAD_CONFIG_D_M (EFUSE_SPI_PAD_CONFIG_D_V << EFUSE_SPI_PAD_CONFIG_D_S) 566 #define EFUSE_SPI_PAD_CONFIG_D_V 0x0000001FU 567 #define EFUSE_SPI_PAD_CONFIG_D_S 10 568 /** EFUSE_SPI_PAD_CONFIG_CS0 : R; bitpos: [19:15]; default: 0; 569 * program for SPI_pad_config_cs0 570 */ 571 #define EFUSE_SPI_PAD_CONFIG_CS0 0x0000001FU 572 #define EFUSE_SPI_PAD_CONFIG_CS0_M (EFUSE_SPI_PAD_CONFIG_CS0_V << EFUSE_SPI_PAD_CONFIG_CS0_S) 573 #define EFUSE_SPI_PAD_CONFIG_CS0_V 0x0000001FU 574 #define EFUSE_SPI_PAD_CONFIG_CS0_S 15 575 /** EFUSE_CHIP_VER_REV2 : R; bitpos: [20]; default: 0; */ 576 #define EFUSE_CHIP_VER_REV2 (BIT(20)) 577 #define EFUSE_CHIP_VER_REV2_M (EFUSE_CHIP_VER_REV2_V << EFUSE_CHIP_VER_REV2_S) 578 #define EFUSE_CHIP_VER_REV2_V 0x00000001U 579 #define EFUSE_CHIP_VER_REV2_S 20 580 /** EFUSE_RESERVE_0_181 : RW; bitpos: [21]; default: 0; 581 * Reserved, it was created by set_missed_fields_in_regs func 582 */ 583 #define EFUSE_RESERVE_0_181 (BIT(21)) 584 #define EFUSE_RESERVE_0_181_M (EFUSE_RESERVE_0_181_V << EFUSE_RESERVE_0_181_S) 585 #define EFUSE_RESERVE_0_181_V 0x00000001U 586 #define EFUSE_RESERVE_0_181_S 21 587 /** EFUSE_VOL_LEVEL_HP_INV : R; bitpos: [23:22]; default: 0; 588 * This field stores the voltage level for CPU to run at 240 MHz, or for flash/PSRAM 589 * to run at 80 MHz.0x0: level 7; 0x1: level 6; 0x2: level 5; 0x3: level 4. (RO) 590 */ 591 #define EFUSE_VOL_LEVEL_HP_INV 0x00000003U 592 #define EFUSE_VOL_LEVEL_HP_INV_M (EFUSE_VOL_LEVEL_HP_INV_V << EFUSE_VOL_LEVEL_HP_INV_S) 593 #define EFUSE_VOL_LEVEL_HP_INV_V 0x00000003U 594 #define EFUSE_VOL_LEVEL_HP_INV_S 22 595 /** EFUSE_WAFER_VERSION_MINOR : R; bitpos: [25:24]; default: 0; */ 596 #define EFUSE_WAFER_VERSION_MINOR 0x00000003U 597 #define EFUSE_WAFER_VERSION_MINOR_M (EFUSE_WAFER_VERSION_MINOR_V << EFUSE_WAFER_VERSION_MINOR_S) 598 #define EFUSE_WAFER_VERSION_MINOR_V 0x00000003U 599 #define EFUSE_WAFER_VERSION_MINOR_S 24 600 /** EFUSE_RESERVE_0_186 : RW; bitpos: [27:26]; default: 0; 601 * Reserved, it was created by set_missed_fields_in_regs func 602 */ 603 #define EFUSE_RESERVE_0_186 0x00000003U 604 #define EFUSE_RESERVE_0_186_M (EFUSE_RESERVE_0_186_V << EFUSE_RESERVE_0_186_S) 605 #define EFUSE_RESERVE_0_186_V 0x00000003U 606 #define EFUSE_RESERVE_0_186_S 26 607 /** EFUSE_FLASH_CRYPT_CONFIG : R; bitpos: [31:28]; default: 0; 608 * program for flash_crypt_config 609 */ 610 #define EFUSE_FLASH_CRYPT_CONFIG 0x0000000FU 611 #define EFUSE_FLASH_CRYPT_CONFIG_M (EFUSE_FLASH_CRYPT_CONFIG_V << EFUSE_FLASH_CRYPT_CONFIG_S) 612 #define EFUSE_FLASH_CRYPT_CONFIG_V 0x0000000FU 613 #define EFUSE_FLASH_CRYPT_CONFIG_S 28 614 615 /** EFUSE_BLK0_WDATA6_REG register */ 616 #define EFUSE_BLK0_WDATA6_REG (DR_REG_EFUSE_BASE + 0x34) 617 /** EFUSE_CODING_SCHEME : RW; bitpos: [1:0]; default: 0; 618 * program for coding_scheme 619 */ 620 #define EFUSE_CODING_SCHEME 0x00000003U 621 #define EFUSE_CODING_SCHEME_M (EFUSE_CODING_SCHEME_V << EFUSE_CODING_SCHEME_S) 622 #define EFUSE_CODING_SCHEME_V 0x00000003U 623 #define EFUSE_CODING_SCHEME_S 0 624 /** EFUSE_CONSOLE_DEBUG_DISABLE : RW; bitpos: [2]; default: 0; 625 * program for console_debug_disable 626 */ 627 #define EFUSE_CONSOLE_DEBUG_DISABLE (BIT(2)) 628 #define EFUSE_CONSOLE_DEBUG_DISABLE_M (EFUSE_CONSOLE_DEBUG_DISABLE_V << EFUSE_CONSOLE_DEBUG_DISABLE_S) 629 #define EFUSE_CONSOLE_DEBUG_DISABLE_V 0x00000001U 630 #define EFUSE_CONSOLE_DEBUG_DISABLE_S 2 631 /** EFUSE_DISABLE_SDIO_HOST : RW; bitpos: [3]; default: 0; */ 632 #define EFUSE_DISABLE_SDIO_HOST (BIT(3)) 633 #define EFUSE_DISABLE_SDIO_HOST_M (EFUSE_DISABLE_SDIO_HOST_V << EFUSE_DISABLE_SDIO_HOST_S) 634 #define EFUSE_DISABLE_SDIO_HOST_V 0x00000001U 635 #define EFUSE_DISABLE_SDIO_HOST_S 3 636 /** EFUSE_ABS_DONE_0 : RW; bitpos: [4]; default: 0; 637 * program for abstract_done_0 638 */ 639 #define EFUSE_ABS_DONE_0 (BIT(4)) 640 #define EFUSE_ABS_DONE_0_M (EFUSE_ABS_DONE_0_V << EFUSE_ABS_DONE_0_S) 641 #define EFUSE_ABS_DONE_0_V 0x00000001U 642 #define EFUSE_ABS_DONE_0_S 4 643 /** EFUSE_ABS_DONE_1 : RW; bitpos: [5]; default: 0; 644 * program for abstract_done_1 645 */ 646 #define EFUSE_ABS_DONE_1 (BIT(5)) 647 #define EFUSE_ABS_DONE_1_M (EFUSE_ABS_DONE_1_V << EFUSE_ABS_DONE_1_S) 648 #define EFUSE_ABS_DONE_1_V 0x00000001U 649 #define EFUSE_ABS_DONE_1_S 5 650 /** EFUSE_DISABLE_JTAG : RW; bitpos: [6]; default: 0; 651 * program for JTAG_disable 652 */ 653 #define EFUSE_DISABLE_JTAG (BIT(6)) 654 #define EFUSE_DISABLE_JTAG_M (EFUSE_DISABLE_JTAG_V << EFUSE_DISABLE_JTAG_S) 655 #define EFUSE_DISABLE_JTAG_V 0x00000001U 656 #define EFUSE_DISABLE_JTAG_S 6 657 /** EFUSE_DISABLE_DL_ENCRYPT : RW; bitpos: [7]; default: 0; 658 * program for download_dis_encrypt 659 */ 660 #define EFUSE_DISABLE_DL_ENCRYPT (BIT(7)) 661 #define EFUSE_DISABLE_DL_ENCRYPT_M (EFUSE_DISABLE_DL_ENCRYPT_V << EFUSE_DISABLE_DL_ENCRYPT_S) 662 #define EFUSE_DISABLE_DL_ENCRYPT_V 0x00000001U 663 #define EFUSE_DISABLE_DL_ENCRYPT_S 7 664 /** EFUSE_DISABLE_DL_DECRYPT : RW; bitpos: [8]; default: 0; 665 * program for download_dis_decrypt 666 */ 667 #define EFUSE_DISABLE_DL_DECRYPT (BIT(8)) 668 #define EFUSE_DISABLE_DL_DECRYPT_M (EFUSE_DISABLE_DL_DECRYPT_V << EFUSE_DISABLE_DL_DECRYPT_S) 669 #define EFUSE_DISABLE_DL_DECRYPT_V 0x00000001U 670 #define EFUSE_DISABLE_DL_DECRYPT_S 8 671 /** EFUSE_DISABLE_DL_CACHE : RW; bitpos: [9]; default: 0; 672 * program for download_dis_cache 673 */ 674 #define EFUSE_DISABLE_DL_CACHE (BIT(9)) 675 #define EFUSE_DISABLE_DL_CACHE_M (EFUSE_DISABLE_DL_CACHE_V << EFUSE_DISABLE_DL_CACHE_S) 676 #define EFUSE_DISABLE_DL_CACHE_V 0x00000001U 677 #define EFUSE_DISABLE_DL_CACHE_S 9 678 /** EFUSE_KEY_STATUS : RW; bitpos: [10]; default: 0; 679 * program for key_status 680 */ 681 #define EFUSE_KEY_STATUS (BIT(10)) 682 #define EFUSE_KEY_STATUS_M (EFUSE_KEY_STATUS_V << EFUSE_KEY_STATUS_S) 683 #define EFUSE_KEY_STATUS_V 0x00000001U 684 #define EFUSE_KEY_STATUS_S 10 685 686 /** EFUSE_BLK1_RDATA0_REG register */ 687 #define EFUSE_BLK1_RDATA0_REG (DR_REG_EFUSE_BASE + 0x38) 688 /** EFUSE_RD_BLOCK1 : R; bitpos: [31:0]; default: 0; 689 * Flash encryption key 690 */ 691 #define EFUSE_RD_BLOCK1 0xFFFFFFFFU 692 #define EFUSE_RD_BLOCK1_M (EFUSE_RD_BLOCK1_V << EFUSE_RD_BLOCK1_S) 693 #define EFUSE_RD_BLOCK1_V 0xFFFFFFFFU 694 #define EFUSE_RD_BLOCK1_S 0 695 696 /** EFUSE_BLK1_RDATA1_REG register */ 697 #define EFUSE_BLK1_RDATA1_REG (DR_REG_EFUSE_BASE + 0x3c) 698 /** EFUSE_RD_BLOCK1_1 : R; bitpos: [31:0]; default: 0; 699 * Flash encryption key 700 */ 701 #define EFUSE_RD_BLOCK1_1 0xFFFFFFFFU 702 #define EFUSE_RD_BLOCK1_1_M (EFUSE_RD_BLOCK1_1_V << EFUSE_RD_BLOCK1_1_S) 703 #define EFUSE_RD_BLOCK1_1_V 0xFFFFFFFFU 704 #define EFUSE_RD_BLOCK1_1_S 0 705 706 /** EFUSE_BLK1_RDATA2_REG register */ 707 #define EFUSE_BLK1_RDATA2_REG (DR_REG_EFUSE_BASE + 0x40) 708 /** EFUSE_RD_BLOCK1_2 : R; bitpos: [31:0]; default: 0; 709 * Flash encryption key 710 */ 711 #define EFUSE_RD_BLOCK1_2 0xFFFFFFFFU 712 #define EFUSE_RD_BLOCK1_2_M (EFUSE_RD_BLOCK1_2_V << EFUSE_RD_BLOCK1_2_S) 713 #define EFUSE_RD_BLOCK1_2_V 0xFFFFFFFFU 714 #define EFUSE_RD_BLOCK1_2_S 0 715 716 /** EFUSE_BLK1_RDATA3_REG register */ 717 #define EFUSE_BLK1_RDATA3_REG (DR_REG_EFUSE_BASE + 0x44) 718 /** EFUSE_RD_BLOCK1_3 : R; bitpos: [31:0]; default: 0; 719 * Flash encryption key 720 */ 721 #define EFUSE_RD_BLOCK1_3 0xFFFFFFFFU 722 #define EFUSE_RD_BLOCK1_3_M (EFUSE_RD_BLOCK1_3_V << EFUSE_RD_BLOCK1_3_S) 723 #define EFUSE_RD_BLOCK1_3_V 0xFFFFFFFFU 724 #define EFUSE_RD_BLOCK1_3_S 0 725 726 /** EFUSE_BLK1_RDATA4_REG register */ 727 #define EFUSE_BLK1_RDATA4_REG (DR_REG_EFUSE_BASE + 0x48) 728 /** EFUSE_RD_BLOCK1_4 : R; bitpos: [31:0]; default: 0; 729 * Flash encryption key 730 */ 731 #define EFUSE_RD_BLOCK1_4 0xFFFFFFFFU 732 #define EFUSE_RD_BLOCK1_4_M (EFUSE_RD_BLOCK1_4_V << EFUSE_RD_BLOCK1_4_S) 733 #define EFUSE_RD_BLOCK1_4_V 0xFFFFFFFFU 734 #define EFUSE_RD_BLOCK1_4_S 0 735 736 /** EFUSE_BLK1_RDATA5_REG register */ 737 #define EFUSE_BLK1_RDATA5_REG (DR_REG_EFUSE_BASE + 0x4c) 738 /** EFUSE_RD_BLOCK1_5 : R; bitpos: [31:0]; default: 0; 739 * Flash encryption key 740 */ 741 #define EFUSE_RD_BLOCK1_5 0xFFFFFFFFU 742 #define EFUSE_RD_BLOCK1_5_M (EFUSE_RD_BLOCK1_5_V << EFUSE_RD_BLOCK1_5_S) 743 #define EFUSE_RD_BLOCK1_5_V 0xFFFFFFFFU 744 #define EFUSE_RD_BLOCK1_5_S 0 745 746 /** EFUSE_BLK1_RDATA6_REG register */ 747 #define EFUSE_BLK1_RDATA6_REG (DR_REG_EFUSE_BASE + 0x50) 748 /** EFUSE_RD_BLOCK1_6 : R; bitpos: [31:0]; default: 0; 749 * Flash encryption key 750 */ 751 #define EFUSE_RD_BLOCK1_6 0xFFFFFFFFU 752 #define EFUSE_RD_BLOCK1_6_M (EFUSE_RD_BLOCK1_6_V << EFUSE_RD_BLOCK1_6_S) 753 #define EFUSE_RD_BLOCK1_6_V 0xFFFFFFFFU 754 #define EFUSE_RD_BLOCK1_6_S 0 755 756 /** EFUSE_BLK1_RDATA7_REG register */ 757 #define EFUSE_BLK1_RDATA7_REG (DR_REG_EFUSE_BASE + 0x54) 758 /** EFUSE_RD_BLOCK1_7 : R; bitpos: [31:0]; default: 0; 759 * Flash encryption key 760 */ 761 #define EFUSE_RD_BLOCK1_7 0xFFFFFFFFU 762 #define EFUSE_RD_BLOCK1_7_M (EFUSE_RD_BLOCK1_7_V << EFUSE_RD_BLOCK1_7_S) 763 #define EFUSE_RD_BLOCK1_7_V 0xFFFFFFFFU 764 #define EFUSE_RD_BLOCK1_7_S 0 765 766 /** EFUSE_BLK2_RDATA0_REG register */ 767 #define EFUSE_BLK2_RDATA0_REG (DR_REG_EFUSE_BASE + 0x58) 768 /** EFUSE_RD_BLOCK2 : R; bitpos: [31:0]; default: 0; 769 * Security boot key 770 */ 771 #define EFUSE_RD_BLOCK2 0xFFFFFFFFU 772 #define EFUSE_RD_BLOCK2_M (EFUSE_RD_BLOCK2_V << EFUSE_RD_BLOCK2_S) 773 #define EFUSE_RD_BLOCK2_V 0xFFFFFFFFU 774 #define EFUSE_RD_BLOCK2_S 0 775 776 /** EFUSE_BLK2_RDATA1_REG register */ 777 #define EFUSE_BLK2_RDATA1_REG (DR_REG_EFUSE_BASE + 0x5c) 778 /** EFUSE_RD_BLOCK2_1 : R; bitpos: [31:0]; default: 0; 779 * Security boot key 780 */ 781 #define EFUSE_RD_BLOCK2_1 0xFFFFFFFFU 782 #define EFUSE_RD_BLOCK2_1_M (EFUSE_RD_BLOCK2_1_V << EFUSE_RD_BLOCK2_1_S) 783 #define EFUSE_RD_BLOCK2_1_V 0xFFFFFFFFU 784 #define EFUSE_RD_BLOCK2_1_S 0 785 786 /** EFUSE_BLK2_RDATA2_REG register */ 787 #define EFUSE_BLK2_RDATA2_REG (DR_REG_EFUSE_BASE + 0x60) 788 /** EFUSE_RD_BLOCK2_2 : R; bitpos: [31:0]; default: 0; 789 * Security boot key 790 */ 791 #define EFUSE_RD_BLOCK2_2 0xFFFFFFFFU 792 #define EFUSE_RD_BLOCK2_2_M (EFUSE_RD_BLOCK2_2_V << EFUSE_RD_BLOCK2_2_S) 793 #define EFUSE_RD_BLOCK2_2_V 0xFFFFFFFFU 794 #define EFUSE_RD_BLOCK2_2_S 0 795 796 /** EFUSE_BLK2_RDATA3_REG register */ 797 #define EFUSE_BLK2_RDATA3_REG (DR_REG_EFUSE_BASE + 0x64) 798 /** EFUSE_RD_BLOCK2_3 : R; bitpos: [31:0]; default: 0; 799 * Security boot key 800 */ 801 #define EFUSE_RD_BLOCK2_3 0xFFFFFFFFU 802 #define EFUSE_RD_BLOCK2_3_M (EFUSE_RD_BLOCK2_3_V << EFUSE_RD_BLOCK2_3_S) 803 #define EFUSE_RD_BLOCK2_3_V 0xFFFFFFFFU 804 #define EFUSE_RD_BLOCK2_3_S 0 805 806 /** EFUSE_BLK2_RDATA4_REG register */ 807 #define EFUSE_BLK2_RDATA4_REG (DR_REG_EFUSE_BASE + 0x68) 808 /** EFUSE_RD_BLOCK2_4 : R; bitpos: [31:0]; default: 0; 809 * Security boot key 810 */ 811 #define EFUSE_RD_BLOCK2_4 0xFFFFFFFFU 812 #define EFUSE_RD_BLOCK2_4_M (EFUSE_RD_BLOCK2_4_V << EFUSE_RD_BLOCK2_4_S) 813 #define EFUSE_RD_BLOCK2_4_V 0xFFFFFFFFU 814 #define EFUSE_RD_BLOCK2_4_S 0 815 816 /** EFUSE_BLK2_RDATA5_REG register */ 817 #define EFUSE_BLK2_RDATA5_REG (DR_REG_EFUSE_BASE + 0x6c) 818 /** EFUSE_RD_BLOCK2_5 : R; bitpos: [31:0]; default: 0; 819 * Security boot key 820 */ 821 #define EFUSE_RD_BLOCK2_5 0xFFFFFFFFU 822 #define EFUSE_RD_BLOCK2_5_M (EFUSE_RD_BLOCK2_5_V << EFUSE_RD_BLOCK2_5_S) 823 #define EFUSE_RD_BLOCK2_5_V 0xFFFFFFFFU 824 #define EFUSE_RD_BLOCK2_5_S 0 825 826 /** EFUSE_BLK2_RDATA6_REG register */ 827 #define EFUSE_BLK2_RDATA6_REG (DR_REG_EFUSE_BASE + 0x70) 828 /** EFUSE_RD_BLOCK2_6 : R; bitpos: [31:0]; default: 0; 829 * Security boot key 830 */ 831 #define EFUSE_RD_BLOCK2_6 0xFFFFFFFFU 832 #define EFUSE_RD_BLOCK2_6_M (EFUSE_RD_BLOCK2_6_V << EFUSE_RD_BLOCK2_6_S) 833 #define EFUSE_RD_BLOCK2_6_V 0xFFFFFFFFU 834 #define EFUSE_RD_BLOCK2_6_S 0 835 836 /** EFUSE_BLK2_RDATA7_REG register */ 837 #define EFUSE_BLK2_RDATA7_REG (DR_REG_EFUSE_BASE + 0x74) 838 /** EFUSE_RD_BLOCK2_7 : R; bitpos: [31:0]; default: 0; 839 * Security boot key 840 */ 841 #define EFUSE_RD_BLOCK2_7 0xFFFFFFFFU 842 #define EFUSE_RD_BLOCK2_7_M (EFUSE_RD_BLOCK2_7_V << EFUSE_RD_BLOCK2_7_S) 843 #define EFUSE_RD_BLOCK2_7_V 0xFFFFFFFFU 844 #define EFUSE_RD_BLOCK2_7_S 0 845 846 /** EFUSE_BLK3_RDATA0_REG register */ 847 #define EFUSE_BLK3_RDATA0_REG (DR_REG_EFUSE_BASE + 0x78) 848 /** EFUSE_RD_CUSTOM_MAC_CRC : R; bitpos: [7:0]; default: 0; 849 * CRC8 for custom MAC address 850 */ 851 #define EFUSE_RD_CUSTOM_MAC_CRC 0x000000FFU 852 #define EFUSE_RD_CUSTOM_MAC_CRC_M (EFUSE_RD_CUSTOM_MAC_CRC_V << EFUSE_RD_CUSTOM_MAC_CRC_S) 853 #define EFUSE_RD_CUSTOM_MAC_CRC_V 0x000000FFU 854 #define EFUSE_RD_CUSTOM_MAC_CRC_S 0 855 /** EFUSE_RD_CUSTOM_MAC : R; bitpos: [31:8]; default: 0; 856 * Custom MAC address 857 */ 858 #define EFUSE_RD_CUSTOM_MAC 0x00FFFFFFU 859 #define EFUSE_RD_CUSTOM_MAC_M (EFUSE_RD_CUSTOM_MAC_V << EFUSE_RD_CUSTOM_MAC_S) 860 #define EFUSE_RD_CUSTOM_MAC_V 0x00FFFFFFU 861 #define EFUSE_RD_CUSTOM_MAC_S 8 862 863 /** EFUSE_BLK3_RDATA1_REG register */ 864 #define EFUSE_BLK3_RDATA1_REG (DR_REG_EFUSE_BASE + 0x7c) 865 /** EFUSE_RD_CUSTOM_MAC_1 : R; bitpos: [23:0]; default: 0; 866 * Custom MAC address 867 */ 868 #define EFUSE_RD_CUSTOM_MAC_1 0x00FFFFFFU 869 #define EFUSE_RD_CUSTOM_MAC_1_M (EFUSE_RD_CUSTOM_MAC_1_V << EFUSE_RD_CUSTOM_MAC_1_S) 870 #define EFUSE_RD_CUSTOM_MAC_1_V 0x00FFFFFFU 871 #define EFUSE_RD_CUSTOM_MAC_1_S 0 872 /** EFUSE_RESERVED_3_56 : R; bitpos: [31:24]; default: 0; 873 * reserved 874 */ 875 #define EFUSE_RESERVED_3_56 0x000000FFU 876 #define EFUSE_RESERVED_3_56_M (EFUSE_RESERVED_3_56_V << EFUSE_RESERVED_3_56_S) 877 #define EFUSE_RESERVED_3_56_V 0x000000FFU 878 #define EFUSE_RESERVED_3_56_S 24 879 880 /** EFUSE_BLK3_RDATA2_REG register */ 881 #define EFUSE_BLK3_RDATA2_REG (DR_REG_EFUSE_BASE + 0x80) 882 /** EFUSE_RD_BLK3_RESERVED_2 : R; bitpos: [31:0]; default: 0; 883 * read for BLOCK3 884 */ 885 #define EFUSE_RD_BLK3_RESERVED_2 0xFFFFFFFFU 886 #define EFUSE_RD_BLK3_RESERVED_2_M (EFUSE_RD_BLK3_RESERVED_2_V << EFUSE_RD_BLK3_RESERVED_2_S) 887 #define EFUSE_RD_BLK3_RESERVED_2_V 0xFFFFFFFFU 888 #define EFUSE_RD_BLK3_RESERVED_2_S 0 889 890 /** EFUSE_BLK3_RDATA3_REG register */ 891 #define EFUSE_BLK3_RDATA3_REG (DR_REG_EFUSE_BASE + 0x84) 892 /** EFUSE_RD_ADC1_TP_LOW : RW; bitpos: [6:0]; default: 0; 893 * ADC1 Two Point calibration low point. Only valid if EFUSE_RD_BLK3_PART_RESERVE 894 */ 895 #define EFUSE_RD_ADC1_TP_LOW 0x0000007FU 896 #define EFUSE_RD_ADC1_TP_LOW_M (EFUSE_RD_ADC1_TP_LOW_V << EFUSE_RD_ADC1_TP_LOW_S) 897 #define EFUSE_RD_ADC1_TP_LOW_V 0x0000007FU 898 #define EFUSE_RD_ADC1_TP_LOW_S 0 899 /** EFUSE_RD_ADC1_TP_HIGH : RW; bitpos: [15:7]; default: 0; 900 * ADC1 Two Point calibration high point. Only valid if EFUSE_RD_BLK3_PART_RESERVE 901 */ 902 #define EFUSE_RD_ADC1_TP_HIGH 0x000001FFU 903 #define EFUSE_RD_ADC1_TP_HIGH_M (EFUSE_RD_ADC1_TP_HIGH_V << EFUSE_RD_ADC1_TP_HIGH_S) 904 #define EFUSE_RD_ADC1_TP_HIGH_V 0x000001FFU 905 #define EFUSE_RD_ADC1_TP_HIGH_S 7 906 /** EFUSE_RD_ADC2_TP_LOW : RW; bitpos: [22:16]; default: 0; 907 * ADC2 Two Point calibration low point. Only valid if EFUSE_RD_BLK3_PART_RESERVE 908 */ 909 #define EFUSE_RD_ADC2_TP_LOW 0x0000007FU 910 #define EFUSE_RD_ADC2_TP_LOW_M (EFUSE_RD_ADC2_TP_LOW_V << EFUSE_RD_ADC2_TP_LOW_S) 911 #define EFUSE_RD_ADC2_TP_LOW_V 0x0000007FU 912 #define EFUSE_RD_ADC2_TP_LOW_S 16 913 /** EFUSE_RD_ADC2_TP_HIGH : RW; bitpos: [31:23]; default: 0; 914 * ADC2 Two Point calibration high point. Only valid if EFUSE_RD_BLK3_PART_RESERVE 915 */ 916 #define EFUSE_RD_ADC2_TP_HIGH 0x000001FFU 917 #define EFUSE_RD_ADC2_TP_HIGH_M (EFUSE_RD_ADC2_TP_HIGH_V << EFUSE_RD_ADC2_TP_HIGH_S) 918 #define EFUSE_RD_ADC2_TP_HIGH_V 0x000001FFU 919 #define EFUSE_RD_ADC2_TP_HIGH_S 23 920 921 /** EFUSE_BLK3_RDATA4_REG register */ 922 #define EFUSE_BLK3_RDATA4_REG (DR_REG_EFUSE_BASE + 0x88) 923 /** EFUSE_RD_SECURE_VERSION : R; bitpos: [31:0]; default: 0; 924 * Secure version for anti-rollback 925 */ 926 #define EFUSE_RD_SECURE_VERSION 0xFFFFFFFFU 927 #define EFUSE_RD_SECURE_VERSION_M (EFUSE_RD_SECURE_VERSION_V << EFUSE_RD_SECURE_VERSION_S) 928 #define EFUSE_RD_SECURE_VERSION_V 0xFFFFFFFFU 929 #define EFUSE_RD_SECURE_VERSION_S 0 930 931 /** EFUSE_BLK3_RDATA5_REG register */ 932 #define EFUSE_BLK3_RDATA5_REG (DR_REG_EFUSE_BASE + 0x8c) 933 /** EFUSE_RESERVED_3_160 : R; bitpos: [23:0]; default: 0; 934 * reserved 935 */ 936 #define EFUSE_RESERVED_3_160 0x00FFFFFFU 937 #define EFUSE_RESERVED_3_160_M (EFUSE_RESERVED_3_160_V << EFUSE_RESERVED_3_160_S) 938 #define EFUSE_RESERVED_3_160_V 0x00FFFFFFU 939 #define EFUSE_RESERVED_3_160_S 0 940 /** EFUSE_RD_MAC_VERSION : R; bitpos: [31:24]; default: 0; 941 * Custom MAC version 942 */ 943 #define EFUSE_RD_MAC_VERSION 0x000000FFU 944 #define EFUSE_RD_MAC_VERSION_M (EFUSE_RD_MAC_VERSION_V << EFUSE_RD_MAC_VERSION_S) 945 #define EFUSE_RD_MAC_VERSION_V 0x000000FFU 946 #define EFUSE_RD_MAC_VERSION_S 24 947 948 /** EFUSE_BLK3_RDATA6_REG register */ 949 #define EFUSE_BLK3_RDATA6_REG (DR_REG_EFUSE_BASE + 0x90) 950 /** EFUSE_RD_BLK3_RESERVED_6 : R; bitpos: [31:0]; default: 0; 951 * read for BLOCK3 952 */ 953 #define EFUSE_RD_BLK3_RESERVED_6 0xFFFFFFFFU 954 #define EFUSE_RD_BLK3_RESERVED_6_M (EFUSE_RD_BLK3_RESERVED_6_V << EFUSE_RD_BLK3_RESERVED_6_S) 955 #define EFUSE_RD_BLK3_RESERVED_6_V 0xFFFFFFFFU 956 #define EFUSE_RD_BLK3_RESERVED_6_S 0 957 958 /** EFUSE_BLK3_RDATA7_REG register */ 959 #define EFUSE_BLK3_RDATA7_REG (DR_REG_EFUSE_BASE + 0x94) 960 /** EFUSE_RD_BLK3_RESERVED_7 : R; bitpos: [31:0]; default: 0; 961 * read for BLOCK3 962 */ 963 #define EFUSE_RD_BLK3_RESERVED_7 0xFFFFFFFFU 964 #define EFUSE_RD_BLK3_RESERVED_7_M (EFUSE_RD_BLK3_RESERVED_7_V << EFUSE_RD_BLK3_RESERVED_7_S) 965 #define EFUSE_RD_BLK3_RESERVED_7_V 0xFFFFFFFFU 966 #define EFUSE_RD_BLK3_RESERVED_7_S 0 967 968 /** EFUSE_BLK1_WDATA0_REG register */ 969 #define EFUSE_BLK1_WDATA0_REG (DR_REG_EFUSE_BASE + 0x98) 970 /** EFUSE_BLK1_DIN0 : RW; bitpos: [31:0]; default: 0; 971 * program for BLOCK1 972 */ 973 #define EFUSE_BLK1_DIN0 0xFFFFFFFFU 974 #define EFUSE_BLK1_DIN0_M (EFUSE_BLK1_DIN0_V << EFUSE_BLK1_DIN0_S) 975 #define EFUSE_BLK1_DIN0_V 0xFFFFFFFFU 976 #define EFUSE_BLK1_DIN0_S 0 977 978 /** EFUSE_BLK1_WDATA1_REG register */ 979 #define EFUSE_BLK1_WDATA1_REG (DR_REG_EFUSE_BASE + 0x9c) 980 /** EFUSE_BLK1_DIN1 : RW; bitpos: [31:0]; default: 0; 981 * program for BLOCK1 982 */ 983 #define EFUSE_BLK1_DIN1 0xFFFFFFFFU 984 #define EFUSE_BLK1_DIN1_M (EFUSE_BLK1_DIN1_V << EFUSE_BLK1_DIN1_S) 985 #define EFUSE_BLK1_DIN1_V 0xFFFFFFFFU 986 #define EFUSE_BLK1_DIN1_S 0 987 988 /** EFUSE_BLK1_WDATA2_REG register */ 989 #define EFUSE_BLK1_WDATA2_REG (DR_REG_EFUSE_BASE + 0xa0) 990 /** EFUSE_BLK1_DIN2 : RW; bitpos: [31:0]; default: 0; 991 * program for BLOCK1 992 */ 993 #define EFUSE_BLK1_DIN2 0xFFFFFFFFU 994 #define EFUSE_BLK1_DIN2_M (EFUSE_BLK1_DIN2_V << EFUSE_BLK1_DIN2_S) 995 #define EFUSE_BLK1_DIN2_V 0xFFFFFFFFU 996 #define EFUSE_BLK1_DIN2_S 0 997 998 /** EFUSE_BLK1_WDATA3_REG register */ 999 #define EFUSE_BLK1_WDATA3_REG (DR_REG_EFUSE_BASE + 0xa4) 1000 /** EFUSE_BLK1_DIN3 : RW; bitpos: [31:0]; default: 0; 1001 * program for BLOCK1 1002 */ 1003 #define EFUSE_BLK1_DIN3 0xFFFFFFFFU 1004 #define EFUSE_BLK1_DIN3_M (EFUSE_BLK1_DIN3_V << EFUSE_BLK1_DIN3_S) 1005 #define EFUSE_BLK1_DIN3_V 0xFFFFFFFFU 1006 #define EFUSE_BLK1_DIN3_S 0 1007 1008 /** EFUSE_BLK1_WDATA4_REG register */ 1009 #define EFUSE_BLK1_WDATA4_REG (DR_REG_EFUSE_BASE + 0xa8) 1010 /** EFUSE_BLK1_DIN4 : RW; bitpos: [31:0]; default: 0; 1011 * program for BLOCK1 1012 */ 1013 #define EFUSE_BLK1_DIN4 0xFFFFFFFFU 1014 #define EFUSE_BLK1_DIN4_M (EFUSE_BLK1_DIN4_V << EFUSE_BLK1_DIN4_S) 1015 #define EFUSE_BLK1_DIN4_V 0xFFFFFFFFU 1016 #define EFUSE_BLK1_DIN4_S 0 1017 1018 /** EFUSE_BLK1_WDATA5_REG register */ 1019 #define EFUSE_BLK1_WDATA5_REG (DR_REG_EFUSE_BASE + 0xac) 1020 /** EFUSE_BLK1_DIN5 : RW; bitpos: [31:0]; default: 0; 1021 * program for BLOCK1 1022 */ 1023 #define EFUSE_BLK1_DIN5 0xFFFFFFFFU 1024 #define EFUSE_BLK1_DIN5_M (EFUSE_BLK1_DIN5_V << EFUSE_BLK1_DIN5_S) 1025 #define EFUSE_BLK1_DIN5_V 0xFFFFFFFFU 1026 #define EFUSE_BLK1_DIN5_S 0 1027 1028 /** EFUSE_BLK1_WDATA6_REG register */ 1029 #define EFUSE_BLK1_WDATA6_REG (DR_REG_EFUSE_BASE + 0xb0) 1030 /** EFUSE_BLK1_DIN6 : RW; bitpos: [31:0]; default: 0; 1031 * program for BLOCK1 1032 */ 1033 #define EFUSE_BLK1_DIN6 0xFFFFFFFFU 1034 #define EFUSE_BLK1_DIN6_M (EFUSE_BLK1_DIN6_V << EFUSE_BLK1_DIN6_S) 1035 #define EFUSE_BLK1_DIN6_V 0xFFFFFFFFU 1036 #define EFUSE_BLK1_DIN6_S 0 1037 1038 /** EFUSE_BLK1_WDATA7_REG register */ 1039 #define EFUSE_BLK1_WDATA7_REG (DR_REG_EFUSE_BASE + 0xb4) 1040 /** EFUSE_BLK1_DIN7 : RW; bitpos: [31:0]; default: 0; 1041 * program for BLOCK1 1042 */ 1043 #define EFUSE_BLK1_DIN7 0xFFFFFFFFU 1044 #define EFUSE_BLK1_DIN7_M (EFUSE_BLK1_DIN7_V << EFUSE_BLK1_DIN7_S) 1045 #define EFUSE_BLK1_DIN7_V 0xFFFFFFFFU 1046 #define EFUSE_BLK1_DIN7_S 0 1047 1048 /** EFUSE_BLK2_WDATA0_REG register */ 1049 #define EFUSE_BLK2_WDATA0_REG (DR_REG_EFUSE_BASE + 0xb8) 1050 /** EFUSE_BLK2_DIN0 : RW; bitpos: [31:0]; default: 0; 1051 * program for BLOCK2 1052 */ 1053 #define EFUSE_BLK2_DIN0 0xFFFFFFFFU 1054 #define EFUSE_BLK2_DIN0_M (EFUSE_BLK2_DIN0_V << EFUSE_BLK2_DIN0_S) 1055 #define EFUSE_BLK2_DIN0_V 0xFFFFFFFFU 1056 #define EFUSE_BLK2_DIN0_S 0 1057 1058 /** EFUSE_BLK2_WDATA1_REG register */ 1059 #define EFUSE_BLK2_WDATA1_REG (DR_REG_EFUSE_BASE + 0xbc) 1060 /** EFUSE_BLK2_DIN1 : RW; bitpos: [31:0]; default: 0; 1061 * program for BLOCK2 1062 */ 1063 #define EFUSE_BLK2_DIN1 0xFFFFFFFFU 1064 #define EFUSE_BLK2_DIN1_M (EFUSE_BLK2_DIN1_V << EFUSE_BLK2_DIN1_S) 1065 #define EFUSE_BLK2_DIN1_V 0xFFFFFFFFU 1066 #define EFUSE_BLK2_DIN1_S 0 1067 1068 /** EFUSE_BLK2_WDATA2_REG register */ 1069 #define EFUSE_BLK2_WDATA2_REG (DR_REG_EFUSE_BASE + 0xc0) 1070 /** EFUSE_BLK2_DIN2 : RW; bitpos: [31:0]; default: 0; 1071 * program for BLOCK2 1072 */ 1073 #define EFUSE_BLK2_DIN2 0xFFFFFFFFU 1074 #define EFUSE_BLK2_DIN2_M (EFUSE_BLK2_DIN2_V << EFUSE_BLK2_DIN2_S) 1075 #define EFUSE_BLK2_DIN2_V 0xFFFFFFFFU 1076 #define EFUSE_BLK2_DIN2_S 0 1077 1078 /** EFUSE_BLK2_WDATA3_REG register */ 1079 #define EFUSE_BLK2_WDATA3_REG (DR_REG_EFUSE_BASE + 0xc4) 1080 /** EFUSE_BLK2_DIN3 : RW; bitpos: [31:0]; default: 0; 1081 * program for BLOCK2 1082 */ 1083 #define EFUSE_BLK2_DIN3 0xFFFFFFFFU 1084 #define EFUSE_BLK2_DIN3_M (EFUSE_BLK2_DIN3_V << EFUSE_BLK2_DIN3_S) 1085 #define EFUSE_BLK2_DIN3_V 0xFFFFFFFFU 1086 #define EFUSE_BLK2_DIN3_S 0 1087 1088 /** EFUSE_BLK2_WDATA4_REG register */ 1089 #define EFUSE_BLK2_WDATA4_REG (DR_REG_EFUSE_BASE + 0xc8) 1090 /** EFUSE_BLK2_DIN4 : RW; bitpos: [31:0]; default: 0; 1091 * program for BLOCK2 1092 */ 1093 #define EFUSE_BLK2_DIN4 0xFFFFFFFFU 1094 #define EFUSE_BLK2_DIN4_M (EFUSE_BLK2_DIN4_V << EFUSE_BLK2_DIN4_S) 1095 #define EFUSE_BLK2_DIN4_V 0xFFFFFFFFU 1096 #define EFUSE_BLK2_DIN4_S 0 1097 1098 /** EFUSE_BLK2_WDATA5_REG register */ 1099 #define EFUSE_BLK2_WDATA5_REG (DR_REG_EFUSE_BASE + 0xcc) 1100 /** EFUSE_BLK2_DIN5 : RW; bitpos: [31:0]; default: 0; 1101 * program for BLOCK2 1102 */ 1103 #define EFUSE_BLK2_DIN5 0xFFFFFFFFU 1104 #define EFUSE_BLK2_DIN5_M (EFUSE_BLK2_DIN5_V << EFUSE_BLK2_DIN5_S) 1105 #define EFUSE_BLK2_DIN5_V 0xFFFFFFFFU 1106 #define EFUSE_BLK2_DIN5_S 0 1107 1108 /** EFUSE_BLK2_WDATA6_REG register */ 1109 #define EFUSE_BLK2_WDATA6_REG (DR_REG_EFUSE_BASE + 0xd0) 1110 /** EFUSE_BLK2_DIN6 : RW; bitpos: [31:0]; default: 0; 1111 * program for BLOCK2 1112 */ 1113 #define EFUSE_BLK2_DIN6 0xFFFFFFFFU 1114 #define EFUSE_BLK2_DIN6_M (EFUSE_BLK2_DIN6_V << EFUSE_BLK2_DIN6_S) 1115 #define EFUSE_BLK2_DIN6_V 0xFFFFFFFFU 1116 #define EFUSE_BLK2_DIN6_S 0 1117 1118 /** EFUSE_BLK2_WDATA7_REG register */ 1119 #define EFUSE_BLK2_WDATA7_REG (DR_REG_EFUSE_BASE + 0xd4) 1120 /** EFUSE_BLK2_DIN7 : RW; bitpos: [31:0]; default: 0; 1121 * program for BLOCK2 1122 */ 1123 #define EFUSE_BLK2_DIN7 0xFFFFFFFFU 1124 #define EFUSE_BLK2_DIN7_M (EFUSE_BLK2_DIN7_V << EFUSE_BLK2_DIN7_S) 1125 #define EFUSE_BLK2_DIN7_V 0xFFFFFFFFU 1126 #define EFUSE_BLK2_DIN7_S 0 1127 1128 /** EFUSE_BLK3_WDATA0_REG register */ 1129 #define EFUSE_BLK3_WDATA0_REG (DR_REG_EFUSE_BASE + 0xd8) 1130 /** EFUSE_BLK3_DIN0 : RW; bitpos: [31:0]; default: 0; 1131 * program for BLOCK3 1132 */ 1133 #define EFUSE_BLK3_DIN0 0xFFFFFFFFU 1134 #define EFUSE_BLK3_DIN0_M (EFUSE_BLK3_DIN0_V << EFUSE_BLK3_DIN0_S) 1135 #define EFUSE_BLK3_DIN0_V 0xFFFFFFFFU 1136 #define EFUSE_BLK3_DIN0_S 0 1137 1138 /** EFUSE_BLK3_WDATA1_REG register */ 1139 #define EFUSE_BLK3_WDATA1_REG (DR_REG_EFUSE_BASE + 0xdc) 1140 /** EFUSE_BLK3_DIN1 : RW; bitpos: [31:0]; default: 0; 1141 * program for BLOCK3 1142 */ 1143 #define EFUSE_BLK3_DIN1 0xFFFFFFFFU 1144 #define EFUSE_BLK3_DIN1_M (EFUSE_BLK3_DIN1_V << EFUSE_BLK3_DIN1_S) 1145 #define EFUSE_BLK3_DIN1_V 0xFFFFFFFFU 1146 #define EFUSE_BLK3_DIN1_S 0 1147 1148 /** EFUSE_BLK3_WDATA2_REG register */ 1149 #define EFUSE_BLK3_WDATA2_REG (DR_REG_EFUSE_BASE + 0xe0) 1150 /** EFUSE_BLK3_DIN2 : RW; bitpos: [31:0]; default: 0; 1151 * program for BLOCK3 1152 */ 1153 #define EFUSE_BLK3_DIN2 0xFFFFFFFFU 1154 #define EFUSE_BLK3_DIN2_M (EFUSE_BLK3_DIN2_V << EFUSE_BLK3_DIN2_S) 1155 #define EFUSE_BLK3_DIN2_V 0xFFFFFFFFU 1156 #define EFUSE_BLK3_DIN2_S 0 1157 1158 /** EFUSE_BLK3_WDATA3_REG register */ 1159 #define EFUSE_BLK3_WDATA3_REG (DR_REG_EFUSE_BASE + 0xe4) 1160 /** EFUSE_ADC1_TP_LOW : RW; bitpos: [6:0]; default: 0; 1161 * ADC1 Two Point calibration low point. Only valid if EFUSE_RD_BLK3_PART_RESERVE 1162 */ 1163 #define EFUSE_ADC1_TP_LOW 0x0000007FU 1164 #define EFUSE_ADC1_TP_LOW_M (EFUSE_ADC1_TP_LOW_V << EFUSE_ADC1_TP_LOW_S) 1165 #define EFUSE_ADC1_TP_LOW_V 0x0000007FU 1166 #define EFUSE_ADC1_TP_LOW_S 0 1167 /** EFUSE_ADC1_TP_HIGH : RW; bitpos: [15:7]; default: 0; 1168 * ADC1 Two Point calibration high point. Only valid if EFUSE_RD_BLK3_PART_RESERVE 1169 */ 1170 #define EFUSE_ADC1_TP_HIGH 0x000001FFU 1171 #define EFUSE_ADC1_TP_HIGH_M (EFUSE_ADC1_TP_HIGH_V << EFUSE_ADC1_TP_HIGH_S) 1172 #define EFUSE_ADC1_TP_HIGH_V 0x000001FFU 1173 #define EFUSE_ADC1_TP_HIGH_S 7 1174 /** EFUSE_ADC2_TP_LOW : RW; bitpos: [22:16]; default: 0; 1175 * ADC2 Two Point calibration low point. Only valid if EFUSE_RD_BLK3_PART_RESERVE 1176 */ 1177 #define EFUSE_ADC2_TP_LOW 0x0000007FU 1178 #define EFUSE_ADC2_TP_LOW_M (EFUSE_ADC2_TP_LOW_V << EFUSE_ADC2_TP_LOW_S) 1179 #define EFUSE_ADC2_TP_LOW_V 0x0000007FU 1180 #define EFUSE_ADC2_TP_LOW_S 16 1181 /** EFUSE_ADC2_TP_HIGH : RW; bitpos: [31:23]; default: 0; 1182 * ADC2 Two Point calibration high point. Only valid if EFUSE_RD_BLK3_PART_RESERVE 1183 */ 1184 #define EFUSE_ADC2_TP_HIGH 0x000001FFU 1185 #define EFUSE_ADC2_TP_HIGH_M (EFUSE_ADC2_TP_HIGH_V << EFUSE_ADC2_TP_HIGH_S) 1186 #define EFUSE_ADC2_TP_HIGH_V 0x000001FFU 1187 #define EFUSE_ADC2_TP_HIGH_S 23 1188 1189 /** EFUSE_BLK3_WDATA4_REG register */ 1190 #define EFUSE_BLK3_WDATA4_REG (DR_REG_EFUSE_BASE + 0xe8) 1191 /** EFUSE_SECURE_VERSION : R; bitpos: [31:0]; default: 0; 1192 * Secure version for anti-rollback 1193 */ 1194 #define EFUSE_SECURE_VERSION 0xFFFFFFFFU 1195 #define EFUSE_SECURE_VERSION_M (EFUSE_SECURE_VERSION_V << EFUSE_SECURE_VERSION_S) 1196 #define EFUSE_SECURE_VERSION_V 0xFFFFFFFFU 1197 #define EFUSE_SECURE_VERSION_S 0 1198 1199 /** EFUSE_BLK3_WDATA5_REG register */ 1200 #define EFUSE_BLK3_WDATA5_REG (DR_REG_EFUSE_BASE + 0xec) 1201 /** EFUSE_BLK3_DIN5 : RW; bitpos: [31:0]; default: 0; 1202 * program for BLOCK3 1203 */ 1204 #define EFUSE_BLK3_DIN5 0xFFFFFFFFU 1205 #define EFUSE_BLK3_DIN5_M (EFUSE_BLK3_DIN5_V << EFUSE_BLK3_DIN5_S) 1206 #define EFUSE_BLK3_DIN5_V 0xFFFFFFFFU 1207 #define EFUSE_BLK3_DIN5_S 0 1208 1209 /** EFUSE_BLK3_WDATA6_REG register */ 1210 #define EFUSE_BLK3_WDATA6_REG (DR_REG_EFUSE_BASE + 0xf0) 1211 /** EFUSE_BLK3_DIN6 : RW; bitpos: [31:0]; default: 0; 1212 * program for BLOCK3 1213 */ 1214 #define EFUSE_BLK3_DIN6 0xFFFFFFFFU 1215 #define EFUSE_BLK3_DIN6_M (EFUSE_BLK3_DIN6_V << EFUSE_BLK3_DIN6_S) 1216 #define EFUSE_BLK3_DIN6_V 0xFFFFFFFFU 1217 #define EFUSE_BLK3_DIN6_S 0 1218 1219 /** EFUSE_BLK3_WDATA7_REG register */ 1220 #define EFUSE_BLK3_WDATA7_REG (DR_REG_EFUSE_BASE + 0xf4) 1221 /** EFUSE_BLK3_DIN7 : RW; bitpos: [31:0]; default: 0; 1222 * program for BLOCK3 1223 */ 1224 #define EFUSE_BLK3_DIN7 0xFFFFFFFFU 1225 #define EFUSE_BLK3_DIN7_M (EFUSE_BLK3_DIN7_V << EFUSE_BLK3_DIN7_S) 1226 #define EFUSE_BLK3_DIN7_V 0xFFFFFFFFU 1227 #define EFUSE_BLK3_DIN7_S 0 1228 1229 /** EFUSE_CLK_REG register */ 1230 #define EFUSE_CLK_REG (DR_REG_EFUSE_BASE + 0xf8) 1231 /** EFUSE_CLK_SEL0 : RW; bitpos: [7:0]; default: 82; 1232 * efuse timing configure 1233 */ 1234 #define EFUSE_CLK_SEL0 0x000000FFU 1235 #define EFUSE_CLK_SEL0_M (EFUSE_CLK_SEL0_V << EFUSE_CLK_SEL0_S) 1236 #define EFUSE_CLK_SEL0_V 0x000000FFU 1237 #define EFUSE_CLK_SEL0_S 0 1238 /** EFUSE_CLK_SEL1 : RW; bitpos: [15:8]; default: 64; 1239 * efuse timing configure 1240 */ 1241 #define EFUSE_CLK_SEL1 0x000000FFU 1242 #define EFUSE_CLK_SEL1_M (EFUSE_CLK_SEL1_V << EFUSE_CLK_SEL1_S) 1243 #define EFUSE_CLK_SEL1_V 0x000000FFU 1244 #define EFUSE_CLK_SEL1_S 8 1245 /** EFUSE_CLK_EN : RW; bitpos: [16]; default: 0; */ 1246 #define EFUSE_CLK_EN (BIT(16)) 1247 #define EFUSE_CLK_EN_M (EFUSE_CLK_EN_V << EFUSE_CLK_EN_S) 1248 #define EFUSE_CLK_EN_V 0x00000001U 1249 #define EFUSE_CLK_EN_S 16 1250 1251 /** EFUSE_CONF_REG register */ 1252 #define EFUSE_CONF_REG (DR_REG_EFUSE_BASE + 0xfc) 1253 /** EFUSE_OP_CODE : RW; bitpos: [15:0]; default: 0; 1254 * efuse operation code 1255 */ 1256 #define EFUSE_OP_CODE 0x0000FFFFU 1257 #define EFUSE_OP_CODE_M (EFUSE_OP_CODE_V << EFUSE_OP_CODE_S) 1258 #define EFUSE_OP_CODE_V 0x0000FFFFU 1259 #define EFUSE_OP_CODE_S 0 1260 /** EFUSE_FORCE_NO_WR_RD_DIS : RW; bitpos: [16]; default: 1; */ 1261 #define EFUSE_FORCE_NO_WR_RD_DIS (BIT(16)) 1262 #define EFUSE_FORCE_NO_WR_RD_DIS_M (EFUSE_FORCE_NO_WR_RD_DIS_V << EFUSE_FORCE_NO_WR_RD_DIS_S) 1263 #define EFUSE_FORCE_NO_WR_RD_DIS_V 0x00000001U 1264 #define EFUSE_FORCE_NO_WR_RD_DIS_S 16 1265 1266 /** EFUSE_STATUS_REG register */ 1267 #define EFUSE_STATUS_REG (DR_REG_EFUSE_BASE + 0x100) 1268 /** EFUSE_DEBUG : R; bitpos: [31:0]; default: 0; */ 1269 #define EFUSE_DEBUG 0xFFFFFFFFU 1270 #define EFUSE_DEBUG_M (EFUSE_DEBUG_V << EFUSE_DEBUG_S) 1271 #define EFUSE_DEBUG_V 0xFFFFFFFFU 1272 #define EFUSE_DEBUG_S 0 1273 1274 /** EFUSE_CMD_REG register */ 1275 #define EFUSE_CMD_REG (DR_REG_EFUSE_BASE + 0x104) 1276 /** EFUSE_READ_CMD : RW; bitpos: [0]; default: 0; 1277 * command for read 1278 */ 1279 #define EFUSE_READ_CMD (BIT(0)) 1280 #define EFUSE_READ_CMD_M (EFUSE_READ_CMD_V << EFUSE_READ_CMD_S) 1281 #define EFUSE_READ_CMD_V 0x00000001U 1282 #define EFUSE_READ_CMD_S 0 1283 /** EFUSE_PGM_CMD : RW; bitpos: [1]; default: 0; 1284 * command for program 1285 */ 1286 #define EFUSE_PGM_CMD (BIT(1)) 1287 #define EFUSE_PGM_CMD_M (EFUSE_PGM_CMD_V << EFUSE_PGM_CMD_S) 1288 #define EFUSE_PGM_CMD_V 0x00000001U 1289 #define EFUSE_PGM_CMD_S 1 1290 1291 /** EFUSE_INT_RAW_REG register */ 1292 #define EFUSE_INT_RAW_REG (DR_REG_EFUSE_BASE + 0x108) 1293 /** EFUSE_READ_DONE_INT_RAW : R; bitpos: [0]; default: 0; 1294 * read done interrupt raw status 1295 */ 1296 #define EFUSE_READ_DONE_INT_RAW (BIT(0)) 1297 #define EFUSE_READ_DONE_INT_RAW_M (EFUSE_READ_DONE_INT_RAW_V << EFUSE_READ_DONE_INT_RAW_S) 1298 #define EFUSE_READ_DONE_INT_RAW_V 0x00000001U 1299 #define EFUSE_READ_DONE_INT_RAW_S 0 1300 /** EFUSE_PGM_DONE_INT_RAW : R; bitpos: [1]; default: 0; 1301 * program done interrupt raw status 1302 */ 1303 #define EFUSE_PGM_DONE_INT_RAW (BIT(1)) 1304 #define EFUSE_PGM_DONE_INT_RAW_M (EFUSE_PGM_DONE_INT_RAW_V << EFUSE_PGM_DONE_INT_RAW_S) 1305 #define EFUSE_PGM_DONE_INT_RAW_V 0x00000001U 1306 #define EFUSE_PGM_DONE_INT_RAW_S 1 1307 1308 /** EFUSE_INT_ST_REG register */ 1309 #define EFUSE_INT_ST_REG (DR_REG_EFUSE_BASE + 0x10c) 1310 /** EFUSE_READ_DONE_INT_ST : R; bitpos: [0]; default: 0; 1311 * read done interrupt status 1312 */ 1313 #define EFUSE_READ_DONE_INT_ST (BIT(0)) 1314 #define EFUSE_READ_DONE_INT_ST_M (EFUSE_READ_DONE_INT_ST_V << EFUSE_READ_DONE_INT_ST_S) 1315 #define EFUSE_READ_DONE_INT_ST_V 0x00000001U 1316 #define EFUSE_READ_DONE_INT_ST_S 0 1317 /** EFUSE_PGM_DONE_INT_ST : R; bitpos: [1]; default: 0; 1318 * program done interrupt status 1319 */ 1320 #define EFUSE_PGM_DONE_INT_ST (BIT(1)) 1321 #define EFUSE_PGM_DONE_INT_ST_M (EFUSE_PGM_DONE_INT_ST_V << EFUSE_PGM_DONE_INT_ST_S) 1322 #define EFUSE_PGM_DONE_INT_ST_V 0x00000001U 1323 #define EFUSE_PGM_DONE_INT_ST_S 1 1324 1325 /** EFUSE_INT_ENA_REG register */ 1326 #define EFUSE_INT_ENA_REG (DR_REG_EFUSE_BASE + 0x110) 1327 /** EFUSE_READ_DONE_INT_ENA : RW; bitpos: [0]; default: 0; 1328 * read done interrupt enable 1329 */ 1330 #define EFUSE_READ_DONE_INT_ENA (BIT(0)) 1331 #define EFUSE_READ_DONE_INT_ENA_M (EFUSE_READ_DONE_INT_ENA_V << EFUSE_READ_DONE_INT_ENA_S) 1332 #define EFUSE_READ_DONE_INT_ENA_V 0x00000001U 1333 #define EFUSE_READ_DONE_INT_ENA_S 0 1334 /** EFUSE_PGM_DONE_INT_ENA : RW; bitpos: [1]; default: 0; 1335 * program done interrupt enable 1336 */ 1337 #define EFUSE_PGM_DONE_INT_ENA (BIT(1)) 1338 #define EFUSE_PGM_DONE_INT_ENA_M (EFUSE_PGM_DONE_INT_ENA_V << EFUSE_PGM_DONE_INT_ENA_S) 1339 #define EFUSE_PGM_DONE_INT_ENA_V 0x00000001U 1340 #define EFUSE_PGM_DONE_INT_ENA_S 1 1341 1342 /** EFUSE_INT_CLR_REG register */ 1343 #define EFUSE_INT_CLR_REG (DR_REG_EFUSE_BASE + 0x114) 1344 /** EFUSE_READ_DONE_INT_CLR : W; bitpos: [0]; default: 0; 1345 * read done interrupt clear 1346 */ 1347 #define EFUSE_READ_DONE_INT_CLR (BIT(0)) 1348 #define EFUSE_READ_DONE_INT_CLR_M (EFUSE_READ_DONE_INT_CLR_V << EFUSE_READ_DONE_INT_CLR_S) 1349 #define EFUSE_READ_DONE_INT_CLR_V 0x00000001U 1350 #define EFUSE_READ_DONE_INT_CLR_S 0 1351 /** EFUSE_PGM_DONE_INT_CLR : W; bitpos: [1]; default: 0; 1352 * program done interrupt clear 1353 */ 1354 #define EFUSE_PGM_DONE_INT_CLR (BIT(1)) 1355 #define EFUSE_PGM_DONE_INT_CLR_M (EFUSE_PGM_DONE_INT_CLR_V << EFUSE_PGM_DONE_INT_CLR_S) 1356 #define EFUSE_PGM_DONE_INT_CLR_V 0x00000001U 1357 #define EFUSE_PGM_DONE_INT_CLR_S 1 1358 1359 /** EFUSE_DAC_CONF_REG register */ 1360 #define EFUSE_DAC_CONF_REG (DR_REG_EFUSE_BASE + 0x118) 1361 /** EFUSE_DAC_CLK_DIV : RW; bitpos: [7:0]; default: 40; 1362 * efuse timing configure 1363 */ 1364 #define EFUSE_DAC_CLK_DIV 0x000000FFU 1365 #define EFUSE_DAC_CLK_DIV_M (EFUSE_DAC_CLK_DIV_V << EFUSE_DAC_CLK_DIV_S) 1366 #define EFUSE_DAC_CLK_DIV_V 0x000000FFU 1367 #define EFUSE_DAC_CLK_DIV_S 0 1368 /** EFUSE_DAC_CLK_PAD_SEL : RW; bitpos: [8]; default: 0; */ 1369 #define EFUSE_DAC_CLK_PAD_SEL (BIT(8)) 1370 #define EFUSE_DAC_CLK_PAD_SEL_M (EFUSE_DAC_CLK_PAD_SEL_V << EFUSE_DAC_CLK_PAD_SEL_S) 1371 #define EFUSE_DAC_CLK_PAD_SEL_V 0x00000001U 1372 #define EFUSE_DAC_CLK_PAD_SEL_S 8 1373 1374 /** EFUSE_DEC_STATUS_REG register */ 1375 #define EFUSE_DEC_STATUS_REG (DR_REG_EFUSE_BASE + 0x11c) 1376 /** EFUSE_DEC_WARNINGS : R; bitpos: [11:0]; default: 0; 1377 * the decode result of 3/4 coding scheme has warning 1378 */ 1379 #define EFUSE_DEC_WARNINGS 0x00000FFFU 1380 #define EFUSE_DEC_WARNINGS_M (EFUSE_DEC_WARNINGS_V << EFUSE_DEC_WARNINGS_S) 1381 #define EFUSE_DEC_WARNINGS_V 0x00000FFFU 1382 #define EFUSE_DEC_WARNINGS_S 0 1383 1384 /** EFUSE_DATE_REG register */ 1385 #define EFUSE_DATE_REG (DR_REG_EFUSE_BASE + 0x1fc) 1386 /** EFUSE_DATE : RW; bitpos: [31:0]; default: 369370624; */ 1387 #define EFUSE_DATE 0xFFFFFFFFU 1388 #define EFUSE_DATE_M (EFUSE_DATE_V << EFUSE_DATE_S) 1389 #define EFUSE_DATE_V 0xFFFFFFFFU 1390 #define EFUSE_DATE_S 0 1391 1392 #ifdef __cplusplus 1393 } 1394 #endif 1395
