1 /*
2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
3 * Copyright 2016-2017 NXP
4 * All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9 #include "fsl_edma.h"
10
11 /*******************************************************************************
12 * Definitions
13 ******************************************************************************/
14
15 #define EDMA_TRANSFER_ENABLED_MASK 0x80U
16
17 /*******************************************************************************
18 * Prototypes
19 ******************************************************************************/
20
21 /*!
22 * @brief Get instance number for EDMA.
23 *
24 * @param base EDMA peripheral base address.
25 */
26 static uint32_t EDMA_GetInstance(DMA_Type *base);
27
28 /*******************************************************************************
29 * Variables
30 ******************************************************************************/
31
32 /*! @brief Array to map EDMA instance number to base pointer. */
33 static DMA_Type *const s_edmaBases[] = DMA_BASE_PTRS;
34
35 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
36 /*! @brief Array to map EDMA instance number to clock name. */
37 static const clock_ip_name_t s_edmaClockName[] = EDMA_CLOCKS;
38 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
39
40 /*! @brief Array to map EDMA instance number to IRQ number. */
41 static const IRQn_Type s_edmaIRQNumber[][FSL_FEATURE_EDMA_MODULE_CHANNEL] = DMA_CHN_IRQS;
42
43 /*! @brief Pointers to transfer handle for each EDMA channel. */
44 static edma_handle_t *s_EDMAHandle[FSL_FEATURE_EDMA_MODULE_CHANNEL * FSL_FEATURE_SOC_EDMA_COUNT];
45
46 /*******************************************************************************
47 * Code
48 ******************************************************************************/
49
EDMA_GetInstance(DMA_Type * base)50 static uint32_t EDMA_GetInstance(DMA_Type *base)
51 {
52 uint32_t instance;
53
54 /* Find the instance index from base address mappings. */
55 for (instance = 0; instance < ARRAY_SIZE(s_edmaBases); instance++)
56 {
57 if (s_edmaBases[instance] == base)
58 {
59 break;
60 }
61 }
62
63 assert(instance < ARRAY_SIZE(s_edmaBases));
64
65 return instance;
66 }
67
EDMA_InstallTCD(DMA_Type * base,uint32_t channel,edma_tcd_t * tcd)68 void EDMA_InstallTCD(DMA_Type *base, uint32_t channel, edma_tcd_t *tcd)
69 {
70 assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
71 assert(tcd != NULL);
72 assert(((uint32_t)tcd & 0x1FU) == 0);
73
74 /* Push tcd into hardware TCD register */
75 base->TCD[channel].SADDR = tcd->SADDR;
76 base->TCD[channel].SOFF = tcd->SOFF;
77 base->TCD[channel].ATTR = tcd->ATTR;
78 base->TCD[channel].NBYTES_MLNO = tcd->NBYTES;
79 base->TCD[channel].SLAST = tcd->SLAST;
80 base->TCD[channel].DADDR = tcd->DADDR;
81 base->TCD[channel].DOFF = tcd->DOFF;
82 base->TCD[channel].CITER_ELINKNO = tcd->CITER;
83 base->TCD[channel].DLAST_SGA = tcd->DLAST_SGA;
84 /* Clear DONE bit first, otherwise ESG cannot be set */
85 base->TCD[channel].CSR = 0;
86 base->TCD[channel].CSR = tcd->CSR;
87 base->TCD[channel].BITER_ELINKNO = tcd->BITER;
88 }
89
EDMA_Init(DMA_Type * base,const edma_config_t * config)90 void EDMA_Init(DMA_Type *base, const edma_config_t *config)
91 {
92 assert(config != NULL);
93
94 uint32_t tmpreg;
95
96 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
97 /* Ungate EDMA periphral clock */
98 CLOCK_EnableClock(s_edmaClockName[EDMA_GetInstance(base)]);
99 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
100 /* Configure EDMA peripheral according to the configuration structure. */
101 tmpreg = base->CR;
102 tmpreg &= ~(DMA_CR_ERCA_MASK | DMA_CR_HOE_MASK | DMA_CR_CLM_MASK | DMA_CR_EDBG_MASK);
103 tmpreg |= (DMA_CR_ERCA(config->enableRoundRobinArbitration) | DMA_CR_HOE(config->enableHaltOnError) |
104 DMA_CR_CLM(config->enableContinuousLinkMode) | DMA_CR_EDBG(config->enableDebugMode) | DMA_CR_EMLM(true));
105 base->CR = tmpreg;
106 }
107
EDMA_Deinit(DMA_Type * base)108 void EDMA_Deinit(DMA_Type *base)
109 {
110 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
111 /* Gate EDMA periphral clock */
112 CLOCK_DisableClock(s_edmaClockName[EDMA_GetInstance(base)]);
113 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
114 }
115
EDMA_GetDefaultConfig(edma_config_t * config)116 void EDMA_GetDefaultConfig(edma_config_t *config)
117 {
118 assert(config != NULL);
119
120 config->enableRoundRobinArbitration = false;
121 config->enableHaltOnError = true;
122 config->enableContinuousLinkMode = false;
123 config->enableDebugMode = false;
124 }
125
EDMA_ResetChannel(DMA_Type * base,uint32_t channel)126 void EDMA_ResetChannel(DMA_Type *base, uint32_t channel)
127 {
128 assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
129
130 EDMA_TcdReset((edma_tcd_t *)&base->TCD[channel]);
131 }
132
EDMA_SetTransferConfig(DMA_Type * base,uint32_t channel,const edma_transfer_config_t * config,edma_tcd_t * nextTcd)133 void EDMA_SetTransferConfig(DMA_Type *base, uint32_t channel, const edma_transfer_config_t *config, edma_tcd_t *nextTcd)
134 {
135 assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
136 assert(config != NULL);
137 assert(((uint32_t)nextTcd & 0x1FU) == 0);
138
139 EDMA_TcdSetTransferConfig((edma_tcd_t *)&base->TCD[channel], config, nextTcd);
140 }
141
EDMA_SetMinorOffsetConfig(DMA_Type * base,uint32_t channel,const edma_minor_offset_config_t * config)142 void EDMA_SetMinorOffsetConfig(DMA_Type *base, uint32_t channel, const edma_minor_offset_config_t *config)
143 {
144 assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
145 assert(config != NULL);
146
147 uint32_t tmpreg;
148
149 tmpreg = base->TCD[channel].NBYTES_MLOFFYES;
150 tmpreg &= ~(DMA_NBYTES_MLOFFYES_SMLOE_MASK | DMA_NBYTES_MLOFFYES_DMLOE_MASK | DMA_NBYTES_MLOFFYES_MLOFF_MASK);
151 tmpreg |=
152 (DMA_NBYTES_MLOFFYES_SMLOE(config->enableSrcMinorOffset) |
153 DMA_NBYTES_MLOFFYES_DMLOE(config->enableDestMinorOffset) | DMA_NBYTES_MLOFFYES_MLOFF(config->minorOffset));
154 base->TCD[channel].NBYTES_MLOFFYES = tmpreg;
155 }
156
EDMA_SetChannelLink(DMA_Type * base,uint32_t channel,edma_channel_link_type_t type,uint32_t linkedChannel)157 void EDMA_SetChannelLink(DMA_Type *base, uint32_t channel, edma_channel_link_type_t type, uint32_t linkedChannel)
158 {
159 assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
160 assert(linkedChannel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
161
162 EDMA_TcdSetChannelLink((edma_tcd_t *)&base->TCD[channel], type, linkedChannel);
163 }
164
EDMA_SetBandWidth(DMA_Type * base,uint32_t channel,edma_bandwidth_t bandWidth)165 void EDMA_SetBandWidth(DMA_Type *base, uint32_t channel, edma_bandwidth_t bandWidth)
166 {
167 assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
168
169 base->TCD[channel].CSR = (base->TCD[channel].CSR & (~DMA_CSR_BWC_MASK)) | DMA_CSR_BWC(bandWidth);
170 }
171
EDMA_SetModulo(DMA_Type * base,uint32_t channel,edma_modulo_t srcModulo,edma_modulo_t destModulo)172 void EDMA_SetModulo(DMA_Type *base, uint32_t channel, edma_modulo_t srcModulo, edma_modulo_t destModulo)
173 {
174 assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
175
176 uint32_t tmpreg;
177
178 tmpreg = base->TCD[channel].ATTR & (~(DMA_ATTR_SMOD_MASK | DMA_ATTR_DMOD_MASK));
179 base->TCD[channel].ATTR = tmpreg | DMA_ATTR_DMOD(destModulo) | DMA_ATTR_SMOD(srcModulo);
180 }
181
EDMA_EnableChannelInterrupts(DMA_Type * base,uint32_t channel,uint32_t mask)182 void EDMA_EnableChannelInterrupts(DMA_Type *base, uint32_t channel, uint32_t mask)
183 {
184 assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
185
186 /* Enable error interrupt */
187 if (mask & kEDMA_ErrorInterruptEnable)
188 {
189 base->EEI |= (0x1U << channel);
190 }
191
192 /* Enable Major interrupt */
193 if (mask & kEDMA_MajorInterruptEnable)
194 {
195 base->TCD[channel].CSR |= DMA_CSR_INTMAJOR_MASK;
196 }
197
198 /* Enable Half major interrupt */
199 if (mask & kEDMA_HalfInterruptEnable)
200 {
201 base->TCD[channel].CSR |= DMA_CSR_INTHALF_MASK;
202 }
203 }
204
EDMA_DisableChannelInterrupts(DMA_Type * base,uint32_t channel,uint32_t mask)205 void EDMA_DisableChannelInterrupts(DMA_Type *base, uint32_t channel, uint32_t mask)
206 {
207 assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
208
209 /* Disable error interrupt */
210 if (mask & kEDMA_ErrorInterruptEnable)
211 {
212 base->EEI &= ~(0x1U << channel);
213 }
214
215 /* Disable Major interrupt */
216 if (mask & kEDMA_MajorInterruptEnable)
217 {
218 base->TCD[channel].CSR &= ~DMA_CSR_INTMAJOR_MASK;
219 }
220
221 /* Disable Half major interrupt */
222 if (mask & kEDMA_HalfInterruptEnable)
223 {
224 base->TCD[channel].CSR &= ~DMA_CSR_INTHALF_MASK;
225 }
226 }
227
EDMA_TcdReset(edma_tcd_t * tcd)228 void EDMA_TcdReset(edma_tcd_t *tcd)
229 {
230 assert(tcd != NULL);
231 assert(((uint32_t)tcd & 0x1FU) == 0);
232
233 /* Reset channel TCD */
234 tcd->SADDR = 0U;
235 tcd->SOFF = 0U;
236 tcd->ATTR = 0U;
237 tcd->NBYTES = 0U;
238 tcd->SLAST = 0U;
239 tcd->DADDR = 0U;
240 tcd->DOFF = 0U;
241 tcd->CITER = 0U;
242 tcd->DLAST_SGA = 0U;
243 /* Enable auto disable request feature */
244 tcd->CSR = DMA_CSR_DREQ(true);
245 tcd->BITER = 0U;
246 }
247
EDMA_TcdSetTransferConfig(edma_tcd_t * tcd,const edma_transfer_config_t * config,edma_tcd_t * nextTcd)248 void EDMA_TcdSetTransferConfig(edma_tcd_t *tcd, const edma_transfer_config_t *config, edma_tcd_t *nextTcd)
249 {
250 assert(tcd != NULL);
251 assert(((uint32_t)tcd & 0x1FU) == 0);
252 assert(config != NULL);
253 assert(((uint32_t)nextTcd & 0x1FU) == 0);
254
255 /* source address */
256 tcd->SADDR = config->srcAddr;
257 /* destination address */
258 tcd->DADDR = config->destAddr;
259 /* Source data and destination data transfer size */
260 tcd->ATTR = DMA_ATTR_SSIZE(config->srcTransferSize) | DMA_ATTR_DSIZE(config->destTransferSize);
261 /* Source address signed offset */
262 tcd->SOFF = config->srcOffset;
263 /* Destination address signed offset */
264 tcd->DOFF = config->destOffset;
265 /* Minor byte transfer count */
266 tcd->NBYTES = config->minorLoopBytes;
267 /* Current major iteration count */
268 tcd->CITER = config->majorLoopCounts;
269 /* Starting major iteration count */
270 tcd->BITER = config->majorLoopCounts;
271 /* Enable scatter/gather processing */
272 if (nextTcd != NULL)
273 {
274 tcd->DLAST_SGA = (uint32_t)nextTcd;
275 /*
276 Before call EDMA_TcdSetTransferConfig or EDMA_SetTransferConfig,
277 user must call EDMA_TcdReset or EDMA_ResetChannel which will set
278 DREQ, so must use "|" or "&" rather than "=".
279
280 Clear the DREQ bit because scatter gather has been enabled, so the
281 previous transfer is not the last transfer, and channel request should
282 be enabled at the next transfer(the next TCD).
283 */
284 tcd->CSR = (tcd->CSR | DMA_CSR_ESG_MASK) & ~DMA_CSR_DREQ_MASK;
285 }
286 }
287
EDMA_TcdSetMinorOffsetConfig(edma_tcd_t * tcd,const edma_minor_offset_config_t * config)288 void EDMA_TcdSetMinorOffsetConfig(edma_tcd_t *tcd, const edma_minor_offset_config_t *config)
289 {
290 assert(tcd != NULL);
291 assert(((uint32_t)tcd & 0x1FU) == 0);
292
293 uint32_t tmpreg;
294
295 tmpreg = tcd->NBYTES &
296 ~(DMA_NBYTES_MLOFFYES_SMLOE_MASK | DMA_NBYTES_MLOFFYES_DMLOE_MASK | DMA_NBYTES_MLOFFYES_MLOFF_MASK);
297 tmpreg |=
298 (DMA_NBYTES_MLOFFYES_SMLOE(config->enableSrcMinorOffset) |
299 DMA_NBYTES_MLOFFYES_DMLOE(config->enableDestMinorOffset) | DMA_NBYTES_MLOFFYES_MLOFF(config->minorOffset));
300 tcd->NBYTES = tmpreg;
301 }
302
EDMA_TcdSetChannelLink(edma_tcd_t * tcd,edma_channel_link_type_t type,uint32_t linkedChannel)303 void EDMA_TcdSetChannelLink(edma_tcd_t *tcd, edma_channel_link_type_t type, uint32_t linkedChannel)
304 {
305 assert(tcd != NULL);
306 assert(((uint32_t)tcd & 0x1FU) == 0);
307 assert(linkedChannel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
308
309 if (type == kEDMA_MinorLink) /* Minor link config */
310 {
311 uint32_t tmpreg;
312
313 /* Enable minor link */
314 tcd->CITER |= DMA_CITER_ELINKYES_ELINK_MASK;
315 tcd->BITER |= DMA_BITER_ELINKYES_ELINK_MASK;
316 /* Set likned channel */
317 tmpreg = tcd->CITER & (~DMA_CITER_ELINKYES_LINKCH_MASK);
318 tmpreg |= DMA_CITER_ELINKYES_LINKCH(linkedChannel);
319 tcd->CITER = tmpreg;
320 tmpreg = tcd->BITER & (~DMA_BITER_ELINKYES_LINKCH_MASK);
321 tmpreg |= DMA_BITER_ELINKYES_LINKCH(linkedChannel);
322 tcd->BITER = tmpreg;
323 }
324 else if (type == kEDMA_MajorLink) /* Major link config */
325 {
326 uint32_t tmpreg;
327
328 /* Enable major link */
329 tcd->CSR |= DMA_CSR_MAJORELINK_MASK;
330 /* Set major linked channel */
331 tmpreg = tcd->CSR & (~DMA_CSR_MAJORLINKCH_MASK);
332 tcd->CSR = tmpreg | DMA_CSR_MAJORLINKCH(linkedChannel);
333 }
334 else /* Link none */
335 {
336 tcd->CITER &= ~DMA_CITER_ELINKYES_ELINK_MASK;
337 tcd->BITER &= ~DMA_BITER_ELINKYES_ELINK_MASK;
338 tcd->CSR &= ~DMA_CSR_MAJORELINK_MASK;
339 }
340 }
341
EDMA_TcdSetModulo(edma_tcd_t * tcd,edma_modulo_t srcModulo,edma_modulo_t destModulo)342 void EDMA_TcdSetModulo(edma_tcd_t *tcd, edma_modulo_t srcModulo, edma_modulo_t destModulo)
343 {
344 assert(tcd != NULL);
345 assert(((uint32_t)tcd & 0x1FU) == 0);
346
347 uint32_t tmpreg;
348
349 tmpreg = tcd->ATTR & (~(DMA_ATTR_SMOD_MASK | DMA_ATTR_DMOD_MASK));
350 tcd->ATTR = tmpreg | DMA_ATTR_DMOD(destModulo) | DMA_ATTR_SMOD(srcModulo);
351 }
352
EDMA_TcdEnableInterrupts(edma_tcd_t * tcd,uint32_t mask)353 void EDMA_TcdEnableInterrupts(edma_tcd_t *tcd, uint32_t mask)
354 {
355 assert(tcd != NULL);
356
357 /* Enable Major interrupt */
358 if (mask & kEDMA_MajorInterruptEnable)
359 {
360 tcd->CSR |= DMA_CSR_INTMAJOR_MASK;
361 }
362
363 /* Enable Half major interrupt */
364 if (mask & kEDMA_HalfInterruptEnable)
365 {
366 tcd->CSR |= DMA_CSR_INTHALF_MASK;
367 }
368 }
369
EDMA_TcdDisableInterrupts(edma_tcd_t * tcd,uint32_t mask)370 void EDMA_TcdDisableInterrupts(edma_tcd_t *tcd, uint32_t mask)
371 {
372 assert(tcd != NULL);
373
374 /* Disable Major interrupt */
375 if (mask & kEDMA_MajorInterruptEnable)
376 {
377 tcd->CSR &= ~DMA_CSR_INTMAJOR_MASK;
378 }
379
380 /* Disable Half major interrupt */
381 if (mask & kEDMA_HalfInterruptEnable)
382 {
383 tcd->CSR &= ~DMA_CSR_INTHALF_MASK;
384 }
385 }
386
EDMA_GetRemainingMajorLoopCount(DMA_Type * base,uint32_t channel)387 uint32_t EDMA_GetRemainingMajorLoopCount(DMA_Type *base, uint32_t channel)
388 {
389 assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
390
391 uint32_t remainingCount = 0;
392
393 if (DMA_CSR_DONE_MASK & base->TCD[channel].CSR)
394 {
395 remainingCount = 0;
396 }
397 else
398 {
399 /* Calculate the unfinished bytes */
400 if (base->TCD[channel].CITER_ELINKNO & DMA_CITER_ELINKNO_ELINK_MASK)
401 {
402 remainingCount =
403 (base->TCD[channel].CITER_ELINKYES & DMA_CITER_ELINKYES_CITER_MASK) >> DMA_CITER_ELINKYES_CITER_SHIFT;
404 }
405 else
406 {
407 remainingCount =
408 (base->TCD[channel].CITER_ELINKNO & DMA_CITER_ELINKNO_CITER_MASK) >> DMA_CITER_ELINKNO_CITER_SHIFT;
409 }
410 }
411
412 return remainingCount;
413 }
414
EDMA_GetChannelStatusFlags(DMA_Type * base,uint32_t channel)415 uint32_t EDMA_GetChannelStatusFlags(DMA_Type *base, uint32_t channel)
416 {
417 assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
418
419 uint32_t retval = 0;
420
421 /* Get DONE bit flag */
422 retval |= ((base->TCD[channel].CSR & DMA_CSR_DONE_MASK) >> DMA_CSR_DONE_SHIFT);
423 /* Get ERROR bit flag */
424 retval |= (((base->ERR >> channel) & 0x1U) << 1U);
425 /* Get INT bit flag */
426 retval |= (((base->INT >> channel) & 0x1U) << 2U);
427
428 return retval;
429 }
430
EDMA_ClearChannelStatusFlags(DMA_Type * base,uint32_t channel,uint32_t mask)431 void EDMA_ClearChannelStatusFlags(DMA_Type *base, uint32_t channel, uint32_t mask)
432 {
433 assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
434
435 /* Clear DONE bit flag */
436 if (mask & kEDMA_DoneFlag)
437 {
438 base->CDNE = channel;
439 }
440 /* Clear ERROR bit flag */
441 if (mask & kEDMA_ErrorFlag)
442 {
443 base->CERR = channel;
444 }
445 /* Clear INT bit flag */
446 if (mask & kEDMA_InterruptFlag)
447 {
448 base->CINT = channel;
449 }
450 }
451
Get_StartInstance(void)452 static uint8_t Get_StartInstance(void)
453 {
454 static uint8_t StartInstanceNum;
455
456 #if defined(DMA0)
457 StartInstanceNum = EDMA_GetInstance(DMA0);
458 #elif defined(DMA1)
459 StartInstanceNum = EDMA_GetInstance(DMA1);
460 #elif defined(DMA2)
461 StartInstanceNum = EDMA_GetInstance(DMA2);
462 #elif defined(DMA3)
463 StartInstanceNum = EDMA_GetInstance(DMA3);
464 #endif
465
466 return StartInstanceNum;
467 }
468
EDMA_CreateHandle(edma_handle_t * handle,DMA_Type * base,uint32_t channel)469 void EDMA_CreateHandle(edma_handle_t *handle, DMA_Type *base, uint32_t channel)
470 {
471 assert(handle != NULL);
472 assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
473
474 uint32_t edmaInstance;
475 uint32_t channelIndex;
476 uint8_t StartInstance;
477 edma_tcd_t *tcdRegs;
478
479 /* Zero the handle */
480 memset(handle, 0, sizeof(*handle));
481
482 handle->base = base;
483 handle->channel = channel;
484 /* Get the DMA instance number */
485 edmaInstance = EDMA_GetInstance(base);
486 StartInstance = Get_StartInstance();
487 channelIndex = ((edmaInstance - StartInstance) * FSL_FEATURE_EDMA_MODULE_CHANNEL) + channel;
488 s_EDMAHandle[channelIndex] = handle;
489
490 /* Enable NVIC interrupt */
491 EnableIRQ(s_edmaIRQNumber[edmaInstance][channel]);
492
493 /*
494 Reset TCD registers to zero. Unlike the EDMA_TcdReset(DREQ will be set),
495 CSR will be 0. Because in order to suit EDMA busy check mechanism in
496 EDMA_SubmitTransfer, CSR must be set 0.
497 */
498 tcdRegs = (edma_tcd_t *)&handle->base->TCD[handle->channel];
499 tcdRegs->SADDR = 0;
500 tcdRegs->SOFF = 0;
501 tcdRegs->ATTR = 0;
502 tcdRegs->NBYTES = 0;
503 tcdRegs->SLAST = 0;
504 tcdRegs->DADDR = 0;
505 tcdRegs->DOFF = 0;
506 tcdRegs->CITER = 0;
507 tcdRegs->DLAST_SGA = 0;
508 tcdRegs->CSR = 0;
509 tcdRegs->BITER = 0;
510 }
511
EDMA_InstallTCDMemory(edma_handle_t * handle,edma_tcd_t * tcdPool,uint32_t tcdSize)512 void EDMA_InstallTCDMemory(edma_handle_t *handle, edma_tcd_t *tcdPool, uint32_t tcdSize)
513 {
514 assert(handle != NULL);
515 assert(((uint32_t)tcdPool & 0x1FU) == 0);
516
517 /* Initialize tcd queue attibute. */
518 handle->header = 0;
519 handle->tail = 0;
520 handle->tcdUsed = 0;
521 handle->tcdSize = tcdSize;
522 handle->flags = 0;
523 handle->tcdPool = tcdPool;
524 }
525
EDMA_SetCallback(edma_handle_t * handle,edma_callback callback,void * userData)526 void EDMA_SetCallback(edma_handle_t *handle, edma_callback callback, void *userData)
527 {
528 assert(handle != NULL);
529
530 handle->callback = callback;
531 handle->userData = userData;
532 }
533
EDMA_PrepareTransfer(edma_transfer_config_t * config,void * srcAddr,uint32_t srcWidth,void * destAddr,uint32_t destWidth,uint32_t bytesEachRequest,uint32_t transferBytes,edma_transfer_type_t type)534 void EDMA_PrepareTransfer(edma_transfer_config_t *config,
535 void *srcAddr,
536 uint32_t srcWidth,
537 void *destAddr,
538 uint32_t destWidth,
539 uint32_t bytesEachRequest,
540 uint32_t transferBytes,
541 edma_transfer_type_t type)
542 {
543 assert(config != NULL);
544 assert(srcAddr != NULL);
545 assert(destAddr != NULL);
546 assert((srcWidth == 1U) || (srcWidth == 2U) || (srcWidth == 4U) || (srcWidth == 16U) || (srcWidth == 32U));
547 assert((destWidth == 1U) || (destWidth == 2U) || (destWidth == 4U) || (destWidth == 16U) || (destWidth == 32U));
548 assert(transferBytes % bytesEachRequest == 0);
549
550 config->destAddr = (uint32_t)destAddr;
551 config->srcAddr = (uint32_t)srcAddr;
552 config->minorLoopBytes = bytesEachRequest;
553 config->majorLoopCounts = transferBytes / bytesEachRequest;
554 switch (srcWidth)
555 {
556 case 1U:
557 config->srcTransferSize = kEDMA_TransferSize1Bytes;
558 break;
559 case 2U:
560 config->srcTransferSize = kEDMA_TransferSize2Bytes;
561 break;
562 case 4U:
563 config->srcTransferSize = kEDMA_TransferSize4Bytes;
564 break;
565 case 16U:
566 config->srcTransferSize = kEDMA_TransferSize16Bytes;
567 break;
568 case 32U:
569 config->srcTransferSize = kEDMA_TransferSize32Bytes;
570 break;
571 default:
572 break;
573 }
574 switch (destWidth)
575 {
576 case 1U:
577 config->destTransferSize = kEDMA_TransferSize1Bytes;
578 break;
579 case 2U:
580 config->destTransferSize = kEDMA_TransferSize2Bytes;
581 break;
582 case 4U:
583 config->destTransferSize = kEDMA_TransferSize4Bytes;
584 break;
585 case 16U:
586 config->destTransferSize = kEDMA_TransferSize16Bytes;
587 break;
588 case 32U:
589 config->destTransferSize = kEDMA_TransferSize32Bytes;
590 break;
591 default:
592 break;
593 }
594 switch (type)
595 {
596 case kEDMA_MemoryToMemory:
597 config->destOffset = destWidth;
598 config->srcOffset = srcWidth;
599 break;
600 case kEDMA_MemoryToPeripheral:
601 config->destOffset = 0U;
602 config->srcOffset = srcWidth;
603 break;
604 case kEDMA_PeripheralToMemory:
605 config->destOffset = destWidth;
606 config->srcOffset = 0U;
607 break;
608 default:
609 break;
610 }
611 }
612
EDMA_SubmitTransfer(edma_handle_t * handle,const edma_transfer_config_t * config)613 status_t EDMA_SubmitTransfer(edma_handle_t *handle, const edma_transfer_config_t *config)
614 {
615 assert(handle != NULL);
616 assert(config != NULL);
617
618 edma_tcd_t *tcdRegs = (edma_tcd_t *)&handle->base->TCD[handle->channel];
619
620 if (handle->tcdPool == NULL)
621 {
622 /*
623 Check if EDMA is busy: if the given channel started transfer, CSR will be not zero. Because
624 if it is the last transfer, DREQ will be set. If not, ESG will be set. So in order to suit
625 this check mechanism, EDMA_CreatHandle will clear CSR register.
626 */
627 if ((tcdRegs->CSR != 0) && ((tcdRegs->CSR & DMA_CSR_DONE_MASK) == 0))
628 {
629 return kStatus_EDMA_Busy;
630 }
631 else
632 {
633 EDMA_SetTransferConfig(handle->base, handle->channel, config, NULL);
634 /* Enable auto disable request feature */
635 handle->base->TCD[handle->channel].CSR |= DMA_CSR_DREQ_MASK;
636 /* Enable major interrupt */
637 handle->base->TCD[handle->channel].CSR |= DMA_CSR_INTMAJOR_MASK;
638
639 return kStatus_Success;
640 }
641 }
642 else /* Use the TCD queue. */
643 {
644 uint32_t primask;
645 uint32_t csr;
646 int8_t currentTcd;
647 int8_t previousTcd;
648 int8_t nextTcd;
649
650 /* Check if tcd pool is full. */
651 primask = DisableGlobalIRQ();
652 if (handle->tcdUsed >= handle->tcdSize)
653 {
654 EnableGlobalIRQ(primask);
655
656 return kStatus_EDMA_QueueFull;
657 }
658 currentTcd = handle->tail;
659 handle->tcdUsed++;
660 /* Calculate index of next TCD */
661 nextTcd = currentTcd + 1U;
662 if (nextTcd == handle->tcdSize)
663 {
664 nextTcd = 0U;
665 }
666 /* Advance queue tail index */
667 handle->tail = nextTcd;
668 EnableGlobalIRQ(primask);
669 /* Calculate index of previous TCD */
670 previousTcd = currentTcd ? currentTcd - 1U : handle->tcdSize - 1U;
671 /* Configure current TCD block. */
672 EDMA_TcdReset(&handle->tcdPool[currentTcd]);
673 EDMA_TcdSetTransferConfig(&handle->tcdPool[currentTcd], config, NULL);
674 /* Enable major interrupt */
675 handle->tcdPool[currentTcd].CSR |= DMA_CSR_INTMAJOR_MASK;
676 /* Link current TCD with next TCD for identification of current TCD */
677 handle->tcdPool[currentTcd].DLAST_SGA = (uint32_t)&handle->tcdPool[nextTcd];
678 /* Chain from previous descriptor unless tcd pool size is 1(this descriptor is its own predecessor). */
679 if (currentTcd != previousTcd)
680 {
681 /* Enable scatter/gather feature in the previous TCD block. */
682 csr = (handle->tcdPool[previousTcd].CSR | DMA_CSR_ESG_MASK) & ~DMA_CSR_DREQ_MASK;
683 handle->tcdPool[previousTcd].CSR = csr;
684 /*
685 Check if the TCD blcok in the registers is the previous one (points to current TCD block). It
686 is used to check if the previous TCD linked has been loaded in TCD register. If so, it need to
687 link the TCD register in case link the current TCD with the dead chain when TCD loading occurs
688 before link the previous TCD block.
689 */
690 if (tcdRegs->DLAST_SGA == (uint32_t)&handle->tcdPool[currentTcd])
691 {
692 /* Enable scatter/gather also in the TCD registers. */
693 csr = (tcdRegs->CSR | DMA_CSR_ESG_MASK) & ~DMA_CSR_DREQ_MASK;
694 /* Must write the CSR register one-time, because the transfer maybe finished anytime. */
695 tcdRegs->CSR = csr;
696 /*
697 It is very important to check the ESG bit!
698 Because this hardware design: if DONE bit is set, the ESG bit can not be set. So it can
699 be used to check if the dynamic TCD link operation is successful. If ESG bit is not set
700 and the DLAST_SGA is not the next TCD address(it means the dynamic TCD link succeed and
701 the current TCD block has been loaded into TCD registers), it means transfer finished
702 and TCD link operation fail, so must install TCD content into TCD registers and enable
703 transfer again. And if ESG is set, it means transfer has notfinished, so TCD dynamic
704 link succeed.
705 */
706 if (tcdRegs->CSR & DMA_CSR_ESG_MASK)
707 {
708 return kStatus_Success;
709 }
710 /*
711 Check whether the current TCD block is already loaded in the TCD registers. It is another
712 condition when ESG bit is not set: it means the dynamic TCD link succeed and the current
713 TCD block has been loaded into TCD registers.
714 */
715 if (tcdRegs->DLAST_SGA == (uint32_t)&handle->tcdPool[nextTcd])
716 {
717 return kStatus_Success;
718 }
719 /*
720 If go to this, means the previous transfer finished, and the DONE bit is set.
721 So shall configure TCD registers.
722 */
723 }
724 else if (tcdRegs->DLAST_SGA != 0)
725 {
726 /* The current TCD block has been linked successfully. */
727 return kStatus_Success;
728 }
729 else
730 {
731 /*
732 DLAST_SGA is 0 and it means the first submit transfer, so shall configure
733 TCD registers.
734 */
735 }
736 }
737 /* There is no live chain, TCD block need to be installed in TCD registers. */
738 EDMA_InstallTCD(handle->base, handle->channel, &handle->tcdPool[currentTcd]);
739 /* Enable channel request again. */
740 if (handle->flags & EDMA_TRANSFER_ENABLED_MASK)
741 {
742 handle->base->SERQ = DMA_SERQ_SERQ(handle->channel);
743 }
744
745 return kStatus_Success;
746 }
747 }
748
EDMA_StartTransfer(edma_handle_t * handle)749 void EDMA_StartTransfer(edma_handle_t *handle)
750 {
751 assert(handle != NULL);
752
753 if (handle->tcdPool == NULL)
754 {
755 handle->base->SERQ = DMA_SERQ_SERQ(handle->channel);
756 }
757 else /* Use the TCD queue. */
758 {
759 uint32_t primask;
760 edma_tcd_t *tcdRegs = (edma_tcd_t *)&handle->base->TCD[handle->channel];
761
762 handle->flags |= EDMA_TRANSFER_ENABLED_MASK;
763
764 /* Check if there was at least one descriptor submitted since reset (TCD in registers is valid) */
765 if (tcdRegs->DLAST_SGA != 0U)
766 {
767 primask = DisableGlobalIRQ();
768 /* Check if channel request is actually disable. */
769 if ((handle->base->ERQ & (1U << handle->channel)) == 0U)
770 {
771 /* Check if transfer is paused. */
772 if ((!(tcdRegs->CSR & DMA_CSR_DONE_MASK)) || (tcdRegs->CSR & DMA_CSR_ESG_MASK))
773 {
774 /*
775 Re-enable channel request must be as soon as possible, so must put it into
776 critical section to avoid task switching or interrupt service routine.
777 */
778 handle->base->SERQ = DMA_SERQ_SERQ(handle->channel);
779 }
780 }
781 EnableGlobalIRQ(primask);
782 }
783 }
784 }
785
EDMA_StopTransfer(edma_handle_t * handle)786 void EDMA_StopTransfer(edma_handle_t *handle)
787 {
788 assert(handle != NULL);
789
790 handle->flags &= (~EDMA_TRANSFER_ENABLED_MASK);
791 handle->base->CERQ = DMA_CERQ_CERQ(handle->channel);
792 }
793
EDMA_AbortTransfer(edma_handle_t * handle)794 void EDMA_AbortTransfer(edma_handle_t *handle)
795 {
796 handle->base->CERQ = DMA_CERQ_CERQ(handle->channel);
797 /*
798 Clear CSR to release channel. Because if the given channel started transfer,
799 CSR will be not zero. Because if it is the last transfer, DREQ will be set.
800 If not, ESG will be set.
801 */
802 handle->base->TCD[handle->channel].CSR = 0;
803 /* Cancel all next TCD transfer. */
804 handle->base->TCD[handle->channel].DLAST_SGA = 0;
805
806 /* Handle the tcd */
807 if (handle->tcdPool != NULL)
808 {
809 handle->header = 0;
810 handle->tail = 0;
811 handle->tcdUsed = 0;
812 }
813 }
814
EDMA_HandleIRQ(edma_handle_t * handle)815 void EDMA_HandleIRQ(edma_handle_t *handle)
816 {
817 assert(handle != NULL);
818
819 /* Clear EDMA interrupt flag */
820 handle->base->CINT = handle->channel;
821 if ((handle->tcdPool == NULL) && (handle->callback != NULL))
822 {
823 (handle->callback)(handle, handle->userData, true, 0);
824 }
825 else /* Use the TCD queue. Please refer to the API descriptions in the eDMA header file for detailed information. */
826 {
827 uint32_t sga = handle->base->TCD[handle->channel].DLAST_SGA;
828 uint32_t sga_index;
829 int32_t tcds_done;
830 uint8_t new_header;
831 bool transfer_done;
832
833 /* Check if transfer is already finished. */
834 transfer_done = ((handle->base->TCD[handle->channel].CSR & DMA_CSR_DONE_MASK) != 0);
835 /* Get the offset of the next transfer TCD blcoks to be loaded into the eDMA engine. */
836 sga -= (uint32_t)handle->tcdPool;
837 /* Get the index of the next transfer TCD blcoks to be loaded into the eDMA engine. */
838 sga_index = sga / sizeof(edma_tcd_t);
839 /* Adjust header positions. */
840 if (transfer_done)
841 {
842 /* New header shall point to the next TCD to be loaded (current one is already finished) */
843 new_header = sga_index;
844 }
845 else
846 {
847 /* New header shall point to this descriptor currently loaded (not finished yet) */
848 new_header = sga_index ? sga_index - 1U : handle->tcdSize - 1U;
849 }
850 /* Calculate the number of finished TCDs */
851 if (new_header == handle->header)
852 {
853 if (handle->tcdUsed == handle->tcdSize)
854 {
855 tcds_done = handle->tcdUsed;
856 }
857 else
858 {
859 /* No TCD in the memory are going to be loaded or internal error occurs. */
860 tcds_done = 0;
861 }
862 }
863 else
864 {
865 tcds_done = new_header - handle->header;
866 if (tcds_done < 0)
867 {
868 tcds_done += handle->tcdSize;
869 }
870 }
871 /* Advance header which points to the TCD to be loaded into the eDMA engine from memory. */
872 handle->header = new_header;
873 /* Release TCD blocks. tcdUsed is the TCD number which can be used/loaded in the memory pool. */
874 handle->tcdUsed -= tcds_done;
875 /* Invoke callback function. */
876 if (handle->callback)
877 {
878 (handle->callback)(handle, handle->userData, transfer_done, tcds_done);
879 }
880 }
881 }
882
883 /* 8 channels (Shared): kl28 */
884 #if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && FSL_FEATURE_EDMA_MODULE_CHANNEL == 8U
885
886 #if defined(DMA0)
DMA0_04_DriverIRQHandler(void)887 void DMA0_04_DriverIRQHandler(void)
888 {
889 if ((EDMA_GetChannelStatusFlags(DMA0, 0U) & kEDMA_InterruptFlag) != 0U)
890 {
891 EDMA_HandleIRQ(s_EDMAHandle[0]);
892 }
893 if ((EDMA_GetChannelStatusFlags(DMA0, 4U) & kEDMA_InterruptFlag) != 0U)
894 {
895 EDMA_HandleIRQ(s_EDMAHandle[4]);
896 }
897 }
898
DMA0_15_DriverIRQHandler(void)899 void DMA0_15_DriverIRQHandler(void)
900 {
901 if ((EDMA_GetChannelStatusFlags(DMA0, 1U) & kEDMA_InterruptFlag) != 0U)
902 {
903 EDMA_HandleIRQ(s_EDMAHandle[1]);
904 }
905 if ((EDMA_GetChannelStatusFlags(DMA0, 5U) & kEDMA_InterruptFlag) != 0U)
906 {
907 EDMA_HandleIRQ(s_EDMAHandle[5]);
908 }
909 }
910
DMA0_26_DriverIRQHandler(void)911 void DMA0_26_DriverIRQHandler(void)
912 {
913 if ((EDMA_GetChannelStatusFlags(DMA0, 2U) & kEDMA_InterruptFlag) != 0U)
914 {
915 EDMA_HandleIRQ(s_EDMAHandle[2]);
916 }
917 if ((EDMA_GetChannelStatusFlags(DMA0, 6U) & kEDMA_InterruptFlag) != 0U)
918 {
919 EDMA_HandleIRQ(s_EDMAHandle[6]);
920 }
921 }
922
DMA0_37_DriverIRQHandler(void)923 void DMA0_37_DriverIRQHandler(void)
924 {
925 if ((EDMA_GetChannelStatusFlags(DMA0, 3U) & kEDMA_InterruptFlag) != 0U)
926 {
927 EDMA_HandleIRQ(s_EDMAHandle[3]);
928 }
929 if ((EDMA_GetChannelStatusFlags(DMA0, 7U) & kEDMA_InterruptFlag) != 0U)
930 {
931 EDMA_HandleIRQ(s_EDMAHandle[7]);
932 }
933 }
934 #endif
935
936 #if defined(DMA1)
937
938 #if defined(DMA0)
DMA1_04_DriverIRQHandler(void)939 void DMA1_04_DriverIRQHandler(void)
940 {
941 if ((EDMA_GetChannelStatusFlags(DMA1, 0U) & kEDMA_InterruptFlag) != 0U)
942 {
943 EDMA_HandleIRQ(s_EDMAHandle[8]);
944 }
945 if ((EDMA_GetChannelStatusFlags(DMA1, 4U) & kEDMA_InterruptFlag) != 0U)
946 {
947 EDMA_HandleIRQ(s_EDMAHandle[12]);
948 }
949 }
950
DMA1_15_DriverIRQHandler(void)951 void DMA1_15_DriverIRQHandler(void)
952 {
953 if ((EDMA_GetChannelStatusFlags(DMA1, 1U) & kEDMA_InterruptFlag) != 0U)
954 {
955 EDMA_HandleIRQ(s_EDMAHandle[9]);
956 }
957 if ((EDMA_GetChannelStatusFlags(DMA1, 5U) & kEDMA_InterruptFlag) != 0U)
958 {
959 EDMA_HandleIRQ(s_EDMAHandle[13]);
960 }
961 }
962
DMA1_26_DriverIRQHandler(void)963 void DMA1_26_DriverIRQHandler(void)
964 {
965 if ((EDMA_GetChannelStatusFlags(DMA1, 2U) & kEDMA_InterruptFlag) != 0U)
966 {
967 EDMA_HandleIRQ(s_EDMAHandle[10]);
968 }
969 if ((EDMA_GetChannelStatusFlags(DMA1, 6U) & kEDMA_InterruptFlag) != 0U)
970 {
971 EDMA_HandleIRQ(s_EDMAHandle[14]);
972 }
973 }
974
DMA1_37_DriverIRQHandler(void)975 void DMA1_37_DriverIRQHandler(void)
976 {
977 if ((EDMA_GetChannelStatusFlags(DMA1, 3U) & kEDMA_InterruptFlag) != 0U)
978 {
979 EDMA_HandleIRQ(s_EDMAHandle[11]);
980 }
981 if ((EDMA_GetChannelStatusFlags(DMA1, 7U) & kEDMA_InterruptFlag) != 0U)
982 {
983 EDMA_HandleIRQ(s_EDMAHandle[15]);
984 }
985 }
986
987 #else
DMA1_04_DriverIRQHandler(void)988 void DMA1_04_DriverIRQHandler(void)
989 {
990 if ((EDMA_GetChannelStatusFlags(DMA1, 0U) & kEDMA_InterruptFlag) != 0U)
991 {
992 EDMA_HandleIRQ(s_EDMAHandle[0]);
993 }
994 if ((EDMA_GetChannelStatusFlags(DMA1, 4U) & kEDMA_InterruptFlag) != 0U)
995 {
996 EDMA_HandleIRQ(s_EDMAHandle[4]);
997 }
998 }
999
DMA1_15_DriverIRQHandler(void)1000 void DMA1_15_DriverIRQHandler(void)
1001 {
1002 if ((EDMA_GetChannelStatusFlags(DMA1, 1U) & kEDMA_InterruptFlag) != 0U)
1003 {
1004 EDMA_HandleIRQ(s_EDMAHandle[1]);
1005 }
1006 if ((EDMA_GetChannelStatusFlags(DMA1, 5U) & kEDMA_InterruptFlag) != 0U)
1007 {
1008 EDMA_HandleIRQ(s_EDMAHandle[5]);
1009 }
1010 }
1011
DMA1_26_DriverIRQHandler(void)1012 void DMA1_26_DriverIRQHandler(void)
1013 {
1014 if ((EDMA_GetChannelStatusFlags(DMA1, 2U) & kEDMA_InterruptFlag) != 0U)
1015 {
1016 EDMA_HandleIRQ(s_EDMAHandle[2]);
1017 }
1018 if ((EDMA_GetChannelStatusFlags(DMA1, 6U) & kEDMA_InterruptFlag) != 0U)
1019 {
1020 EDMA_HandleIRQ(s_EDMAHandle[6]);
1021 }
1022 }
1023
DMA1_37_DriverIRQHandler(void)1024 void DMA1_37_DriverIRQHandler(void)
1025 {
1026 if ((EDMA_GetChannelStatusFlags(DMA1, 3U) & kEDMA_InterruptFlag) != 0U)
1027 {
1028 EDMA_HandleIRQ(s_EDMAHandle[3]);
1029 }
1030 if ((EDMA_GetChannelStatusFlags(DMA1, 7U) & kEDMA_InterruptFlag) != 0U)
1031 {
1032 EDMA_HandleIRQ(s_EDMAHandle[7]);
1033 }
1034 }
1035 #endif
1036 #endif
1037 #endif /* 8 channels (Shared) */
1038
1039 /* 16 channels (Shared): K32H844P */
1040 #if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && FSL_FEATURE_EDMA_MODULE_CHANNEL == 16U
1041
DMA0_08_DriverIRQHandler(void)1042 void DMA0_08_DriverIRQHandler(void)
1043 {
1044 if ((EDMA_GetChannelStatusFlags(DMA0, 0U) & kEDMA_InterruptFlag) != 0U)
1045 {
1046 EDMA_HandleIRQ(s_EDMAHandle[0]);
1047 }
1048 if ((EDMA_GetChannelStatusFlags(DMA0, 8U) & kEDMA_InterruptFlag) != 0U)
1049 {
1050 EDMA_HandleIRQ(s_EDMAHandle[8]);
1051 }
1052 }
1053
DMA0_19_DriverIRQHandler(void)1054 void DMA0_19_DriverIRQHandler(void)
1055 {
1056 if ((EDMA_GetChannelStatusFlags(DMA0, 1U) & kEDMA_InterruptFlag) != 0U)
1057 {
1058 EDMA_HandleIRQ(s_EDMAHandle[1]);
1059 }
1060 if ((EDMA_GetChannelStatusFlags(DMA0, 9U) & kEDMA_InterruptFlag) != 0U)
1061 {
1062 EDMA_HandleIRQ(s_EDMAHandle[9]);
1063 }
1064 }
1065
DMA0_210_DriverIRQHandler(void)1066 void DMA0_210_DriverIRQHandler(void)
1067 {
1068 if ((EDMA_GetChannelStatusFlags(DMA0, 2U) & kEDMA_InterruptFlag) != 0U)
1069 {
1070 EDMA_HandleIRQ(s_EDMAHandle[2]);
1071 }
1072 if ((EDMA_GetChannelStatusFlags(DMA0, 10U) & kEDMA_InterruptFlag) != 0U)
1073 {
1074 EDMA_HandleIRQ(s_EDMAHandle[10]);
1075 }
1076 }
1077
DMA0_311_DriverIRQHandler(void)1078 void DMA0_311_DriverIRQHandler(void)
1079 {
1080 if ((EDMA_GetChannelStatusFlags(DMA0, 3U) & kEDMA_InterruptFlag) != 0U)
1081 {
1082 EDMA_HandleIRQ(s_EDMAHandle[3]);
1083 }
1084 if ((EDMA_GetChannelStatusFlags(DMA0, 11U) & kEDMA_InterruptFlag) != 0U)
1085 {
1086 EDMA_HandleIRQ(s_EDMAHandle[11]);
1087 }
1088 }
1089
DMA0_412_DriverIRQHandler(void)1090 void DMA0_412_DriverIRQHandler(void)
1091 {
1092 if ((EDMA_GetChannelStatusFlags(DMA0, 4U) & kEDMA_InterruptFlag) != 0U)
1093 {
1094 EDMA_HandleIRQ(s_EDMAHandle[4]);
1095 }
1096 if ((EDMA_GetChannelStatusFlags(DMA0, 12U) & kEDMA_InterruptFlag) != 0U)
1097 {
1098 EDMA_HandleIRQ(s_EDMAHandle[12]);
1099 }
1100 }
1101
DMA0_513_DriverIRQHandler(void)1102 void DMA0_513_DriverIRQHandler(void)
1103 {
1104 if ((EDMA_GetChannelStatusFlags(DMA0, 5U) & kEDMA_InterruptFlag) != 0U)
1105 {
1106 EDMA_HandleIRQ(s_EDMAHandle[5]);
1107 }
1108 if ((EDMA_GetChannelStatusFlags(DMA0, 13U) & kEDMA_InterruptFlag) != 0U)
1109 {
1110 EDMA_HandleIRQ(s_EDMAHandle[13]);
1111 }
1112 }
1113
DMA0_614_DriverIRQHandler(void)1114 void DMA0_614_DriverIRQHandler(void)
1115 {
1116 if ((EDMA_GetChannelStatusFlags(DMA0, 6U) & kEDMA_InterruptFlag) != 0U)
1117 {
1118 EDMA_HandleIRQ(s_EDMAHandle[6]);
1119 }
1120 if ((EDMA_GetChannelStatusFlags(DMA0, 14U) & kEDMA_InterruptFlag) != 0U)
1121 {
1122 EDMA_HandleIRQ(s_EDMAHandle[14]);
1123 }
1124 }
1125
DMA0_715_DriverIRQHandler(void)1126 void DMA0_715_DriverIRQHandler(void)
1127 {
1128 if ((EDMA_GetChannelStatusFlags(DMA0, 7U) & kEDMA_InterruptFlag) != 0U)
1129 {
1130 EDMA_HandleIRQ(s_EDMAHandle[7]);
1131 }
1132 if ((EDMA_GetChannelStatusFlags(DMA0, 15U) & kEDMA_InterruptFlag) != 0U)
1133 {
1134 EDMA_HandleIRQ(s_EDMAHandle[15]);
1135 }
1136 }
1137
1138 #if defined(DMA1)
DMA1_08_DriverIRQHandler(void)1139 void DMA1_08_DriverIRQHandler(void)
1140 {
1141 if ((EDMA_GetChannelStatusFlags(DMA1, 0U) & kEDMA_InterruptFlag) != 0U)
1142 {
1143 EDMA_HandleIRQ(s_EDMAHandle[16]);
1144 }
1145 if ((EDMA_GetChannelStatusFlags(DMA1, 8U) & kEDMA_InterruptFlag) != 0U)
1146 {
1147 EDMA_HandleIRQ(s_EDMAHandle[24]);
1148 }
1149 }
1150
DMA1_19_DriverIRQHandler(void)1151 void DMA1_19_DriverIRQHandler(void)
1152 {
1153 if ((EDMA_GetChannelStatusFlags(DMA1, 1U) & kEDMA_InterruptFlag) != 0U)
1154 {
1155 EDMA_HandleIRQ(s_EDMAHandle[17]);
1156 }
1157 if ((EDMA_GetChannelStatusFlags(DMA1, 9U) & kEDMA_InterruptFlag) != 0U)
1158 {
1159 EDMA_HandleIRQ(s_EDMAHandle[25]);
1160 }
1161 }
1162
DMA1_210_DriverIRQHandler(void)1163 void DMA1_210_DriverIRQHandler(void)
1164 {
1165 if ((EDMA_GetChannelStatusFlags(DMA1, 2U) & kEDMA_InterruptFlag) != 0U)
1166 {
1167 EDMA_HandleIRQ(s_EDMAHandle[18]);
1168 }
1169 if ((EDMA_GetChannelStatusFlags(DMA1, 10U) & kEDMA_InterruptFlag) != 0U)
1170 {
1171 EDMA_HandleIRQ(s_EDMAHandle[26]);
1172 }
1173 }
1174
DMA1_311_DriverIRQHandler(void)1175 void DMA1_311_DriverIRQHandler(void)
1176 {
1177 if ((EDMA_GetChannelStatusFlags(DMA1, 3U) & kEDMA_InterruptFlag) != 0U)
1178 {
1179 EDMA_HandleIRQ(s_EDMAHandle[19]);
1180 }
1181 if ((EDMA_GetChannelStatusFlags(DMA1, 11U) & kEDMA_InterruptFlag) != 0U)
1182 {
1183 EDMA_HandleIRQ(s_EDMAHandle[27]);
1184 }
1185 }
1186
DMA1_412_DriverIRQHandler(void)1187 void DMA1_412_DriverIRQHandler(void)
1188 {
1189 if ((EDMA_GetChannelStatusFlags(DMA1, 4U) & kEDMA_InterruptFlag) != 0U)
1190 {
1191 EDMA_HandleIRQ(s_EDMAHandle[20]);
1192 }
1193 if ((EDMA_GetChannelStatusFlags(DMA1, 12U) & kEDMA_InterruptFlag) != 0U)
1194 {
1195 EDMA_HandleIRQ(s_EDMAHandle[28]);
1196 }
1197 }
1198
DMA1_513_DriverIRQHandler(void)1199 void DMA1_513_DriverIRQHandler(void)
1200 {
1201 if ((EDMA_GetChannelStatusFlags(DMA1, 5U) & kEDMA_InterruptFlag) != 0U)
1202 {
1203 EDMA_HandleIRQ(s_EDMAHandle[21]);
1204 }
1205 if ((EDMA_GetChannelStatusFlags(DMA1, 13U) & kEDMA_InterruptFlag) != 0U)
1206 {
1207 EDMA_HandleIRQ(s_EDMAHandle[29]);
1208 }
1209 }
1210
DMA1_614_DriverIRQHandler(void)1211 void DMA1_614_DriverIRQHandler(void)
1212 {
1213 if ((EDMA_GetChannelStatusFlags(DMA1, 6U) & kEDMA_InterruptFlag) != 0U)
1214 {
1215 EDMA_HandleIRQ(s_EDMAHandle[22]);
1216 }
1217 if ((EDMA_GetChannelStatusFlags(DMA1, 14U) & kEDMA_InterruptFlag) != 0U)
1218 {
1219 EDMA_HandleIRQ(s_EDMAHandle[30]);
1220 }
1221 }
1222
DMA1_715_DriverIRQHandler(void)1223 void DMA1_715_DriverIRQHandler(void)
1224 {
1225 if ((EDMA_GetChannelStatusFlags(DMA1, 7U) & kEDMA_InterruptFlag) != 0U)
1226 {
1227 EDMA_HandleIRQ(s_EDMAHandle[23]);
1228 }
1229 if ((EDMA_GetChannelStatusFlags(DMA1, 15U) & kEDMA_InterruptFlag) != 0U)
1230 {
1231 EDMA_HandleIRQ(s_EDMAHandle[31]);
1232 }
1233 }
1234 #endif
1235 #endif /* 16 channels (Shared) */
1236
1237 /* 32 channels (Shared): k80 */
1238 #if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && FSL_FEATURE_EDMA_MODULE_CHANNEL == 32U
1239
DMA0_DMA16_DriverIRQHandler(void)1240 void DMA0_DMA16_DriverIRQHandler(void)
1241 {
1242 if ((EDMA_GetChannelStatusFlags(DMA0, 0U) & kEDMA_InterruptFlag) != 0U)
1243 {
1244 EDMA_HandleIRQ(s_EDMAHandle[0]);
1245 }
1246 if ((EDMA_GetChannelStatusFlags(DMA0, 16U) & kEDMA_InterruptFlag) != 0U)
1247 {
1248 EDMA_HandleIRQ(s_EDMAHandle[16]);
1249 }
1250 }
1251
DMA1_DMA17_DriverIRQHandler(void)1252 void DMA1_DMA17_DriverIRQHandler(void)
1253 {
1254 if ((EDMA_GetChannelStatusFlags(DMA0, 1U) & kEDMA_InterruptFlag) != 0U)
1255 {
1256 EDMA_HandleIRQ(s_EDMAHandle[1]);
1257 }
1258 if ((EDMA_GetChannelStatusFlags(DMA0, 17U) & kEDMA_InterruptFlag) != 0U)
1259 {
1260 EDMA_HandleIRQ(s_EDMAHandle[17]);
1261 }
1262 }
1263
DMA2_DMA18_DriverIRQHandler(void)1264 void DMA2_DMA18_DriverIRQHandler(void)
1265 {
1266 if ((EDMA_GetChannelStatusFlags(DMA0, 2U) & kEDMA_InterruptFlag) != 0U)
1267 {
1268 EDMA_HandleIRQ(s_EDMAHandle[2]);
1269 }
1270 if ((EDMA_GetChannelStatusFlags(DMA0, 18U) & kEDMA_InterruptFlag) != 0U)
1271 {
1272 EDMA_HandleIRQ(s_EDMAHandle[18]);
1273 }
1274 }
1275
DMA3_DMA19_DriverIRQHandler(void)1276 void DMA3_DMA19_DriverIRQHandler(void)
1277 {
1278 if ((EDMA_GetChannelStatusFlags(DMA0, 3U) & kEDMA_InterruptFlag) != 0U)
1279 {
1280 EDMA_HandleIRQ(s_EDMAHandle[3]);
1281 }
1282 if ((EDMA_GetChannelStatusFlags(DMA0, 19U) & kEDMA_InterruptFlag) != 0U)
1283 {
1284 EDMA_HandleIRQ(s_EDMAHandle[19]);
1285 }
1286 }
1287
DMA4_DMA20_DriverIRQHandler(void)1288 void DMA4_DMA20_DriverIRQHandler(void)
1289 {
1290 if ((EDMA_GetChannelStatusFlags(DMA0, 4U) & kEDMA_InterruptFlag) != 0U)
1291 {
1292 EDMA_HandleIRQ(s_EDMAHandle[4]);
1293 }
1294 if ((EDMA_GetChannelStatusFlags(DMA0, 20U) & kEDMA_InterruptFlag) != 0U)
1295 {
1296 EDMA_HandleIRQ(s_EDMAHandle[20]);
1297 }
1298 }
1299
DMA5_DMA21_DriverIRQHandler(void)1300 void DMA5_DMA21_DriverIRQHandler(void)
1301 {
1302 if ((EDMA_GetChannelStatusFlags(DMA0, 5U) & kEDMA_InterruptFlag) != 0U)
1303 {
1304 EDMA_HandleIRQ(s_EDMAHandle[5]);
1305 }
1306 if ((EDMA_GetChannelStatusFlags(DMA0, 21U) & kEDMA_InterruptFlag) != 0U)
1307 {
1308 EDMA_HandleIRQ(s_EDMAHandle[21]);
1309 }
1310 }
1311
DMA6_DMA22_DriverIRQHandler(void)1312 void DMA6_DMA22_DriverIRQHandler(void)
1313 {
1314 if ((EDMA_GetChannelStatusFlags(DMA0, 6U) & kEDMA_InterruptFlag) != 0U)
1315 {
1316 EDMA_HandleIRQ(s_EDMAHandle[6]);
1317 }
1318 if ((EDMA_GetChannelStatusFlags(DMA0, 22U) & kEDMA_InterruptFlag) != 0U)
1319 {
1320 EDMA_HandleIRQ(s_EDMAHandle[22]);
1321 }
1322 }
1323
DMA7_DMA23_DriverIRQHandler(void)1324 void DMA7_DMA23_DriverIRQHandler(void)
1325 {
1326 if ((EDMA_GetChannelStatusFlags(DMA0, 7U) & kEDMA_InterruptFlag) != 0U)
1327 {
1328 EDMA_HandleIRQ(s_EDMAHandle[7]);
1329 }
1330 if ((EDMA_GetChannelStatusFlags(DMA0, 23U) & kEDMA_InterruptFlag) != 0U)
1331 {
1332 EDMA_HandleIRQ(s_EDMAHandle[23]);
1333 }
1334 }
1335
DMA8_DMA24_DriverIRQHandler(void)1336 void DMA8_DMA24_DriverIRQHandler(void)
1337 {
1338 if ((EDMA_GetChannelStatusFlags(DMA0, 8U) & kEDMA_InterruptFlag) != 0U)
1339 {
1340 EDMA_HandleIRQ(s_EDMAHandle[8]);
1341 }
1342 if ((EDMA_GetChannelStatusFlags(DMA0, 24U) & kEDMA_InterruptFlag) != 0U)
1343 {
1344 EDMA_HandleIRQ(s_EDMAHandle[24]);
1345 }
1346 }
1347
DMA9_DMA25_DriverIRQHandler(void)1348 void DMA9_DMA25_DriverIRQHandler(void)
1349 {
1350 if ((EDMA_GetChannelStatusFlags(DMA0, 9U) & kEDMA_InterruptFlag) != 0U)
1351 {
1352 EDMA_HandleIRQ(s_EDMAHandle[9]);
1353 }
1354 if ((EDMA_GetChannelStatusFlags(DMA0, 25U) & kEDMA_InterruptFlag) != 0U)
1355 {
1356 EDMA_HandleIRQ(s_EDMAHandle[25]);
1357 }
1358 }
1359
DMA10_DMA26_DriverIRQHandler(void)1360 void DMA10_DMA26_DriverIRQHandler(void)
1361 {
1362 if ((EDMA_GetChannelStatusFlags(DMA0, 10U) & kEDMA_InterruptFlag) != 0U)
1363 {
1364 EDMA_HandleIRQ(s_EDMAHandle[10]);
1365 }
1366 if ((EDMA_GetChannelStatusFlags(DMA0, 26U) & kEDMA_InterruptFlag) != 0U)
1367 {
1368 EDMA_HandleIRQ(s_EDMAHandle[26]);
1369 }
1370 }
1371
DMA11_DMA27_DriverIRQHandler(void)1372 void DMA11_DMA27_DriverIRQHandler(void)
1373 {
1374 if ((EDMA_GetChannelStatusFlags(DMA0, 11U) & kEDMA_InterruptFlag) != 0U)
1375 {
1376 EDMA_HandleIRQ(s_EDMAHandle[11]);
1377 }
1378 if ((EDMA_GetChannelStatusFlags(DMA0, 27U) & kEDMA_InterruptFlag) != 0U)
1379 {
1380 EDMA_HandleIRQ(s_EDMAHandle[27]);
1381 }
1382 }
1383
DMA12_DMA28_DriverIRQHandler(void)1384 void DMA12_DMA28_DriverIRQHandler(void)
1385 {
1386 if ((EDMA_GetChannelStatusFlags(DMA0, 12U) & kEDMA_InterruptFlag) != 0U)
1387 {
1388 EDMA_HandleIRQ(s_EDMAHandle[12]);
1389 }
1390 if ((EDMA_GetChannelStatusFlags(DMA0, 28U) & kEDMA_InterruptFlag) != 0U)
1391 {
1392 EDMA_HandleIRQ(s_EDMAHandle[28]);
1393 }
1394 }
1395
DMA13_DMA29_DriverIRQHandler(void)1396 void DMA13_DMA29_DriverIRQHandler(void)
1397 {
1398 if ((EDMA_GetChannelStatusFlags(DMA0, 13U) & kEDMA_InterruptFlag) != 0U)
1399 {
1400 EDMA_HandleIRQ(s_EDMAHandle[13]);
1401 }
1402 if ((EDMA_GetChannelStatusFlags(DMA0, 29U) & kEDMA_InterruptFlag) != 0U)
1403 {
1404 EDMA_HandleIRQ(s_EDMAHandle[29]);
1405 }
1406 }
1407
DMA14_DMA30_DriverIRQHandler(void)1408 void DMA14_DMA30_DriverIRQHandler(void)
1409 {
1410 if ((EDMA_GetChannelStatusFlags(DMA0, 14U) & kEDMA_InterruptFlag) != 0U)
1411 {
1412 EDMA_HandleIRQ(s_EDMAHandle[14]);
1413 }
1414 if ((EDMA_GetChannelStatusFlags(DMA0, 30U) & kEDMA_InterruptFlag) != 0U)
1415 {
1416 EDMA_HandleIRQ(s_EDMAHandle[30]);
1417 }
1418 }
1419
DMA15_DMA31_DriverIRQHandler(void)1420 void DMA15_DMA31_DriverIRQHandler(void)
1421 {
1422 if ((EDMA_GetChannelStatusFlags(DMA0, 15U) & kEDMA_InterruptFlag) != 0U)
1423 {
1424 EDMA_HandleIRQ(s_EDMAHandle[15]);
1425 }
1426 if ((EDMA_GetChannelStatusFlags(DMA0, 31U) & kEDMA_InterruptFlag) != 0U)
1427 {
1428 EDMA_HandleIRQ(s_EDMAHandle[31]);
1429 }
1430 }
1431 #endif /* 32 channels (Shared) */
1432
1433 /* 32 channels (Shared): MCIMX7U5_M4 */
1434 #if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && FSL_FEATURE_EDMA_MODULE_CHANNEL == 32U
1435
DMA0_0_4_DriverIRQHandler(void)1436 void DMA0_0_4_DriverIRQHandler(void)
1437 {
1438 if ((EDMA_GetChannelStatusFlags(DMA0, 0U) & kEDMA_InterruptFlag) != 0U)
1439 {
1440 EDMA_HandleIRQ(s_EDMAHandle[0]);
1441 }
1442 if ((EDMA_GetChannelStatusFlags(DMA0, 4U) & kEDMA_InterruptFlag) != 0U)
1443 {
1444 EDMA_HandleIRQ(s_EDMAHandle[4]);
1445 }
1446 }
1447
DMA0_1_5_DriverIRQHandler(void)1448 void DMA0_1_5_DriverIRQHandler(void)
1449 {
1450 if ((EDMA_GetChannelStatusFlags(DMA0, 1U) & kEDMA_InterruptFlag) != 0U)
1451 {
1452 EDMA_HandleIRQ(s_EDMAHandle[1]);
1453 }
1454 if ((EDMA_GetChannelStatusFlags(DMA0, 5U) & kEDMA_InterruptFlag) != 0U)
1455 {
1456 EDMA_HandleIRQ(s_EDMAHandle[5]);
1457 }
1458 }
1459
DMA0_2_6_DriverIRQHandler(void)1460 void DMA0_2_6_DriverIRQHandler(void)
1461 {
1462 if ((EDMA_GetChannelStatusFlags(DMA0, 2U) & kEDMA_InterruptFlag) != 0U)
1463 {
1464 EDMA_HandleIRQ(s_EDMAHandle[2]);
1465 }
1466 if ((EDMA_GetChannelStatusFlags(DMA0, 6U) & kEDMA_InterruptFlag) != 0U)
1467 {
1468 EDMA_HandleIRQ(s_EDMAHandle[6]);
1469 }
1470 }
1471
DMA0_3_7_DriverIRQHandler(void)1472 void DMA0_3_7_DriverIRQHandler(void)
1473 {
1474 if ((EDMA_GetChannelStatusFlags(DMA0, 3U) & kEDMA_InterruptFlag) != 0U)
1475 {
1476 EDMA_HandleIRQ(s_EDMAHandle[3]);
1477 }
1478 if ((EDMA_GetChannelStatusFlags(DMA0, 7U) & kEDMA_InterruptFlag) != 0U)
1479 {
1480 EDMA_HandleIRQ(s_EDMAHandle[7]);
1481 }
1482 }
1483
DMA0_8_12_DriverIRQHandler(void)1484 void DMA0_8_12_DriverIRQHandler(void)
1485 {
1486 if ((EDMA_GetChannelStatusFlags(DMA0, 8U) & kEDMA_InterruptFlag) != 0U)
1487 {
1488 EDMA_HandleIRQ(s_EDMAHandle[8]);
1489 }
1490 if ((EDMA_GetChannelStatusFlags(DMA0, 12U) & kEDMA_InterruptFlag) != 0U)
1491 {
1492 EDMA_HandleIRQ(s_EDMAHandle[12]);
1493 }
1494 }
1495
DMA0_9_13_DriverIRQHandler(void)1496 void DMA0_9_13_DriverIRQHandler(void)
1497 {
1498 if ((EDMA_GetChannelStatusFlags(DMA0, 9U) & kEDMA_InterruptFlag) != 0U)
1499 {
1500 EDMA_HandleIRQ(s_EDMAHandle[9]);
1501 }
1502 if ((EDMA_GetChannelStatusFlags(DMA0, 13U) & kEDMA_InterruptFlag) != 0U)
1503 {
1504 EDMA_HandleIRQ(s_EDMAHandle[13]);
1505 }
1506 }
1507
DMA0_10_14_DriverIRQHandler(void)1508 void DMA0_10_14_DriverIRQHandler(void)
1509 {
1510 if ((EDMA_GetChannelStatusFlags(DMA0, 10U) & kEDMA_InterruptFlag) != 0U)
1511 {
1512 EDMA_HandleIRQ(s_EDMAHandle[10]);
1513 }
1514 if ((EDMA_GetChannelStatusFlags(DMA0, 14U) & kEDMA_InterruptFlag) != 0U)
1515 {
1516 EDMA_HandleIRQ(s_EDMAHandle[14]);
1517 }
1518 }
1519
DMA0_11_15_DriverIRQHandler(void)1520 void DMA0_11_15_DriverIRQHandler(void)
1521 {
1522 if ((EDMA_GetChannelStatusFlags(DMA0, 11U) & kEDMA_InterruptFlag) != 0U)
1523 {
1524 EDMA_HandleIRQ(s_EDMAHandle[11]);
1525 }
1526 if ((EDMA_GetChannelStatusFlags(DMA0, 15U) & kEDMA_InterruptFlag) != 0U)
1527 {
1528 EDMA_HandleIRQ(s_EDMAHandle[15]);
1529 }
1530 }
1531
DMA0_16_20_DriverIRQHandler(void)1532 void DMA0_16_20_DriverIRQHandler(void)
1533 {
1534 if ((EDMA_GetChannelStatusFlags(DMA0, 16U) & kEDMA_InterruptFlag) != 0U)
1535 {
1536 EDMA_HandleIRQ(s_EDMAHandle[16]);
1537 }
1538 if ((EDMA_GetChannelStatusFlags(DMA0, 20U) & kEDMA_InterruptFlag) != 0U)
1539 {
1540 EDMA_HandleIRQ(s_EDMAHandle[20]);
1541 }
1542 }
1543
DMA0_17_21_DriverIRQHandler(void)1544 void DMA0_17_21_DriverIRQHandler(void)
1545 {
1546 if ((EDMA_GetChannelStatusFlags(DMA0, 17U) & kEDMA_InterruptFlag) != 0U)
1547 {
1548 EDMA_HandleIRQ(s_EDMAHandle[17]);
1549 }
1550 if ((EDMA_GetChannelStatusFlags(DMA0, 21U) & kEDMA_InterruptFlag) != 0U)
1551 {
1552 EDMA_HandleIRQ(s_EDMAHandle[21]);
1553 }
1554 }
1555
DMA0_18_22_DriverIRQHandler(void)1556 void DMA0_18_22_DriverIRQHandler(void)
1557 {
1558 if ((EDMA_GetChannelStatusFlags(DMA0, 18U) & kEDMA_InterruptFlag) != 0U)
1559 {
1560 EDMA_HandleIRQ(s_EDMAHandle[18]);
1561 }
1562 if ((EDMA_GetChannelStatusFlags(DMA0, 22U) & kEDMA_InterruptFlag) != 0U)
1563 {
1564 EDMA_HandleIRQ(s_EDMAHandle[22]);
1565 }
1566 }
1567
DMA0_19_23_DriverIRQHandler(void)1568 void DMA0_19_23_DriverIRQHandler(void)
1569 {
1570 if ((EDMA_GetChannelStatusFlags(DMA0, 19U) & kEDMA_InterruptFlag) != 0U)
1571 {
1572 EDMA_HandleIRQ(s_EDMAHandle[19]);
1573 }
1574 if ((EDMA_GetChannelStatusFlags(DMA0, 23U) & kEDMA_InterruptFlag) != 0U)
1575 {
1576 EDMA_HandleIRQ(s_EDMAHandle[23]);
1577 }
1578 }
1579
DMA0_24_28_DriverIRQHandler(void)1580 void DMA0_24_28_DriverIRQHandler(void)
1581 {
1582 if ((EDMA_GetChannelStatusFlags(DMA0, 24U) & kEDMA_InterruptFlag) != 0U)
1583 {
1584 EDMA_HandleIRQ(s_EDMAHandle[24]);
1585 }
1586 if ((EDMA_GetChannelStatusFlags(DMA0, 28U) & kEDMA_InterruptFlag) != 0U)
1587 {
1588 EDMA_HandleIRQ(s_EDMAHandle[28]);
1589 }
1590 }
1591
DMA0_25_29_DriverIRQHandler(void)1592 void DMA0_25_29_DriverIRQHandler(void)
1593 {
1594 if ((EDMA_GetChannelStatusFlags(DMA0, 25U) & kEDMA_InterruptFlag) != 0U)
1595 {
1596 EDMA_HandleIRQ(s_EDMAHandle[25]);
1597 }
1598 if ((EDMA_GetChannelStatusFlags(DMA0, 29U) & kEDMA_InterruptFlag) != 0U)
1599 {
1600 EDMA_HandleIRQ(s_EDMAHandle[29]);
1601 }
1602 }
1603
DMA0_26_30_DriverIRQHandler(void)1604 void DMA0_26_30_DriverIRQHandler(void)
1605 {
1606 if ((EDMA_GetChannelStatusFlags(DMA0, 26U) & kEDMA_InterruptFlag) != 0U)
1607 {
1608 EDMA_HandleIRQ(s_EDMAHandle[26]);
1609 }
1610 if ((EDMA_GetChannelStatusFlags(DMA0, 30U) & kEDMA_InterruptFlag) != 0U)
1611 {
1612 EDMA_HandleIRQ(s_EDMAHandle[30]);
1613 }
1614 }
1615
DMA0_27_31_DriverIRQHandler(void)1616 void DMA0_27_31_DriverIRQHandler(void)
1617 {
1618 if ((EDMA_GetChannelStatusFlags(DMA0, 27U) & kEDMA_InterruptFlag) != 0U)
1619 {
1620 EDMA_HandleIRQ(s_EDMAHandle[27]);
1621 }
1622 if ((EDMA_GetChannelStatusFlags(DMA0, 31U) & kEDMA_InterruptFlag) != 0U)
1623 {
1624 EDMA_HandleIRQ(s_EDMAHandle[31]);
1625 }
1626 }
1627 #endif /* 32 channels (Shared): MCIMX7U5 */
1628
1629 /* 4 channels (No Shared): kv10 */
1630 #if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && FSL_FEATURE_EDMA_MODULE_CHANNEL > 0
1631
DMA0_DriverIRQHandler(void)1632 void DMA0_DriverIRQHandler(void)
1633 {
1634 EDMA_HandleIRQ(s_EDMAHandle[0]);
1635 }
1636
DMA1_DriverIRQHandler(void)1637 void DMA1_DriverIRQHandler(void)
1638 {
1639 EDMA_HandleIRQ(s_EDMAHandle[1]);
1640 }
1641
DMA2_DriverIRQHandler(void)1642 void DMA2_DriverIRQHandler(void)
1643 {
1644 EDMA_HandleIRQ(s_EDMAHandle[2]);
1645 }
1646
DMA3_DriverIRQHandler(void)1647 void DMA3_DriverIRQHandler(void)
1648 {
1649 EDMA_HandleIRQ(s_EDMAHandle[3]);
1650 }
1651
1652 /* 8 channels (No Shared) */
1653 #if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && FSL_FEATURE_EDMA_MODULE_CHANNEL > 4U
1654
DMA4_DriverIRQHandler(void)1655 void DMA4_DriverIRQHandler(void)
1656 {
1657 EDMA_HandleIRQ(s_EDMAHandle[4]);
1658 }
1659
DMA5_DriverIRQHandler(void)1660 void DMA5_DriverIRQHandler(void)
1661 {
1662 EDMA_HandleIRQ(s_EDMAHandle[5]);
1663 }
1664
DMA6_DriverIRQHandler(void)1665 void DMA6_DriverIRQHandler(void)
1666 {
1667 EDMA_HandleIRQ(s_EDMAHandle[6]);
1668 }
1669
DMA7_DriverIRQHandler(void)1670 void DMA7_DriverIRQHandler(void)
1671 {
1672 EDMA_HandleIRQ(s_EDMAHandle[7]);
1673 }
1674 #endif /* FSL_FEATURE_EDMA_MODULE_CHANNEL == 8 */
1675
1676 /* 16 channels (No Shared) */
1677 #if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && FSL_FEATURE_EDMA_MODULE_CHANNEL > 8U
1678
DMA8_DriverIRQHandler(void)1679 void DMA8_DriverIRQHandler(void)
1680 {
1681 EDMA_HandleIRQ(s_EDMAHandle[8]);
1682 }
1683
DMA9_DriverIRQHandler(void)1684 void DMA9_DriverIRQHandler(void)
1685 {
1686 EDMA_HandleIRQ(s_EDMAHandle[9]);
1687 }
1688
DMA10_DriverIRQHandler(void)1689 void DMA10_DriverIRQHandler(void)
1690 {
1691 EDMA_HandleIRQ(s_EDMAHandle[10]);
1692 }
1693
DMA11_DriverIRQHandler(void)1694 void DMA11_DriverIRQHandler(void)
1695 {
1696 EDMA_HandleIRQ(s_EDMAHandle[11]);
1697 }
1698
DMA12_DriverIRQHandler(void)1699 void DMA12_DriverIRQHandler(void)
1700 {
1701 EDMA_HandleIRQ(s_EDMAHandle[12]);
1702 }
1703
DMA13_DriverIRQHandler(void)1704 void DMA13_DriverIRQHandler(void)
1705 {
1706 EDMA_HandleIRQ(s_EDMAHandle[13]);
1707 }
1708
DMA14_DriverIRQHandler(void)1709 void DMA14_DriverIRQHandler(void)
1710 {
1711 EDMA_HandleIRQ(s_EDMAHandle[14]);
1712 }
1713
DMA15_DriverIRQHandler(void)1714 void DMA15_DriverIRQHandler(void)
1715 {
1716 EDMA_HandleIRQ(s_EDMAHandle[15]);
1717 }
1718 #endif /* FSL_FEATURE_EDMA_MODULE_CHANNEL == 16 */
1719
1720 /* 32 channels (No Shared) */
1721 #if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && FSL_FEATURE_EDMA_MODULE_CHANNEL > 16U
1722
DMA16_DriverIRQHandler(void)1723 void DMA16_DriverIRQHandler(void)
1724 {
1725 EDMA_HandleIRQ(s_EDMAHandle[16]);
1726 }
1727
DMA17_DriverIRQHandler(void)1728 void DMA17_DriverIRQHandler(void)
1729 {
1730 EDMA_HandleIRQ(s_EDMAHandle[17]);
1731 }
1732
DMA18_DriverIRQHandler(void)1733 void DMA18_DriverIRQHandler(void)
1734 {
1735 EDMA_HandleIRQ(s_EDMAHandle[18]);
1736 }
1737
DMA19_DriverIRQHandler(void)1738 void DMA19_DriverIRQHandler(void)
1739 {
1740 EDMA_HandleIRQ(s_EDMAHandle[19]);
1741 }
1742
DMA20_DriverIRQHandler(void)1743 void DMA20_DriverIRQHandler(void)
1744 {
1745 EDMA_HandleIRQ(s_EDMAHandle[20]);
1746 }
1747
DMA21_DriverIRQHandler(void)1748 void DMA21_DriverIRQHandler(void)
1749 {
1750 EDMA_HandleIRQ(s_EDMAHandle[21]);
1751 }
1752
DMA22_DriverIRQHandler(void)1753 void DMA22_DriverIRQHandler(void)
1754 {
1755 EDMA_HandleIRQ(s_EDMAHandle[22]);
1756 }
1757
DMA23_DriverIRQHandler(void)1758 void DMA23_DriverIRQHandler(void)
1759 {
1760 EDMA_HandleIRQ(s_EDMAHandle[23]);
1761 }
1762
DMA24_DriverIRQHandler(void)1763 void DMA24_DriverIRQHandler(void)
1764 {
1765 EDMA_HandleIRQ(s_EDMAHandle[24]);
1766 }
1767
DMA25_DriverIRQHandler(void)1768 void DMA25_DriverIRQHandler(void)
1769 {
1770 EDMA_HandleIRQ(s_EDMAHandle[25]);
1771 }
1772
DMA26_DriverIRQHandler(void)1773 void DMA26_DriverIRQHandler(void)
1774 {
1775 EDMA_HandleIRQ(s_EDMAHandle[26]);
1776 }
1777
DMA27_DriverIRQHandler(void)1778 void DMA27_DriverIRQHandler(void)
1779 {
1780 EDMA_HandleIRQ(s_EDMAHandle[27]);
1781 }
1782
DMA28_DriverIRQHandler(void)1783 void DMA28_DriverIRQHandler(void)
1784 {
1785 EDMA_HandleIRQ(s_EDMAHandle[28]);
1786 }
1787
DMA29_DriverIRQHandler(void)1788 void DMA29_DriverIRQHandler(void)
1789 {
1790 EDMA_HandleIRQ(s_EDMAHandle[29]);
1791 }
1792
DMA30_DriverIRQHandler(void)1793 void DMA30_DriverIRQHandler(void)
1794 {
1795 EDMA_HandleIRQ(s_EDMAHandle[30]);
1796 }
1797
DMA31_DriverIRQHandler(void)1798 void DMA31_DriverIRQHandler(void)
1799 {
1800 EDMA_HandleIRQ(s_EDMAHandle[31]);
1801 }
1802 #endif /* FSL_FEATURE_EDMA_MODULE_CHANNEL == 32 */
1803
1804 #endif /* 4/8/16/32 channels (No Shared) */
1805
1806 #if defined(DMA0)
DMA0_0_4_8_12_IRQHandler(void)1807 void DMA0_0_4_8_12_IRQHandler(void)
1808 {
1809 if ((EDMA_GetChannelStatusFlags(DMA0, 0U) & kEDMA_InterruptFlag) != 0U)
1810 {
1811 EDMA_HandleIRQ(s_EDMAHandle[0]);
1812 }
1813 if ((EDMA_GetChannelStatusFlags(DMA0, 4U) & kEDMA_InterruptFlag) != 0U)
1814 {
1815 EDMA_HandleIRQ(s_EDMAHandle[4]);
1816 }
1817 if ((EDMA_GetChannelStatusFlags(DMA0, 8U) & kEDMA_InterruptFlag) != 0U)
1818 {
1819 EDMA_HandleIRQ(s_EDMAHandle[8]);
1820 }
1821 if ((EDMA_GetChannelStatusFlags(DMA0, 12U) & kEDMA_InterruptFlag) != 0U)
1822 {
1823 EDMA_HandleIRQ(s_EDMAHandle[12]);
1824 }
1825 }
1826
DMA0_1_5_9_13_IRQHandler(void)1827 void DMA0_1_5_9_13_IRQHandler(void)
1828 {
1829 if ((EDMA_GetChannelStatusFlags(DMA0, 1U) & kEDMA_InterruptFlag) != 0U)
1830 {
1831 EDMA_HandleIRQ(s_EDMAHandle[1]);
1832 }
1833 if ((EDMA_GetChannelStatusFlags(DMA0, 5U) & kEDMA_InterruptFlag) != 0U)
1834 {
1835 EDMA_HandleIRQ(s_EDMAHandle[5]);
1836 }
1837 if ((EDMA_GetChannelStatusFlags(DMA0, 9U) & kEDMA_InterruptFlag) != 0U)
1838 {
1839 EDMA_HandleIRQ(s_EDMAHandle[9]);
1840 }
1841 if ((EDMA_GetChannelStatusFlags(DMA0, 13U) & kEDMA_InterruptFlag) != 0U)
1842 {
1843 EDMA_HandleIRQ(s_EDMAHandle[13]);
1844 }
1845 }
1846
DMA0_2_6_10_14_IRQHandler(void)1847 void DMA0_2_6_10_14_IRQHandler(void)
1848 {
1849 if ((EDMA_GetChannelStatusFlags(DMA0, 2U) & kEDMA_InterruptFlag) != 0U)
1850 {
1851 EDMA_HandleIRQ(s_EDMAHandle[2]);
1852 }
1853 if ((EDMA_GetChannelStatusFlags(DMA0, 6U) & kEDMA_InterruptFlag) != 0U)
1854 {
1855 EDMA_HandleIRQ(s_EDMAHandle[6]);
1856 }
1857 if ((EDMA_GetChannelStatusFlags(DMA0, 10U) & kEDMA_InterruptFlag) != 0U)
1858 {
1859 EDMA_HandleIRQ(s_EDMAHandle[10]);
1860 }
1861 if ((EDMA_GetChannelStatusFlags(DMA0, 14U) & kEDMA_InterruptFlag) != 0U)
1862 {
1863 EDMA_HandleIRQ(s_EDMAHandle[14]);
1864 }
1865 }
1866
DMA0_3_7_11_15_IRQHandler(void)1867 void DMA0_3_7_11_15_IRQHandler(void)
1868 {
1869 if ((EDMA_GetChannelStatusFlags(DMA0, 3U) & kEDMA_InterruptFlag) != 0U)
1870 {
1871 EDMA_HandleIRQ(s_EDMAHandle[3]);
1872 }
1873 if ((EDMA_GetChannelStatusFlags(DMA0, 7U) & kEDMA_InterruptFlag) != 0U)
1874 {
1875 EDMA_HandleIRQ(s_EDMAHandle[7]);
1876 }
1877 if ((EDMA_GetChannelStatusFlags(DMA0, 11U) & kEDMA_InterruptFlag) != 0U)
1878 {
1879 EDMA_HandleIRQ(s_EDMAHandle[11]);
1880 }
1881 if ((EDMA_GetChannelStatusFlags(DMA0, 15U) & kEDMA_InterruptFlag) != 0U)
1882 {
1883 EDMA_HandleIRQ(s_EDMAHandle[15]);
1884 }
1885 }
1886 #endif
1887
