1 /** 2 * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #pragma once 7 8 #include <stdint.h> 9 #include "soc/soc.h" 10 #ifdef __cplusplus 11 extern "C" { 12 #endif 13 14 /** ECDSA_CONF_REG register 15 * ECDSA configure register 16 */ 17 #define ECDSA_CONF_REG (DR_REG_ECDSA_BASE + 0x4) 18 /** ECDSA_WORK_MODE : R/W; bitpos: [0]; default: 0; 19 * The work mode bits of ECDSA Accelerator. 0: Signature Verify mode. 1: Signature 20 * Generate Mode. 21 */ 22 #define ECDSA_WORK_MODE (BIT(0)) 23 #define ECDSA_WORK_MODE_M (ECDSA_WORK_MODE_V << ECDSA_WORK_MODE_S) 24 #define ECDSA_WORK_MODE_V 0x00000001U 25 #define ECDSA_WORK_MODE_S 0 26 /** ECDSA_ECC_CURVE : R/W; bitpos: [1]; default: 0; 27 * The ecc curve select bit of ECDSA Accelerator. 0: P-192. 1: P-256. 28 */ 29 #define ECDSA_ECC_CURVE (BIT(1)) 30 #define ECDSA_ECC_CURVE_M (ECDSA_ECC_CURVE_V << ECDSA_ECC_CURVE_S) 31 #define ECDSA_ECC_CURVE_V 0x00000001U 32 #define ECDSA_ECC_CURVE_S 1 33 /** ECDSA_SOFTWARE_SET_K : R/W; bitpos: [2]; default: 0; 34 * The source of k select bit. 0: k is automatically generated by TRNG. 1: k is 35 * written by software. 36 */ 37 #define ECDSA_SOFTWARE_SET_K (BIT(2)) 38 #define ECDSA_SOFTWARE_SET_K_M (ECDSA_SOFTWARE_SET_K_V << ECDSA_SOFTWARE_SET_K_S) 39 #define ECDSA_SOFTWARE_SET_K_V 0x00000001U 40 #define ECDSA_SOFTWARE_SET_K_S 2 41 /** ECDSA_SOFTWARE_SET_Z : R/W; bitpos: [3]; default: 0; 42 * The source of z select bit. 0: z is generated from SHA result. 1: z is written by 43 * software. 44 */ 45 #define ECDSA_SOFTWARE_SET_Z (BIT(3)) 46 #define ECDSA_SOFTWARE_SET_Z_M (ECDSA_SOFTWARE_SET_Z_V << ECDSA_SOFTWARE_SET_Z_S) 47 #define ECDSA_SOFTWARE_SET_Z_V 0x00000001U 48 #define ECDSA_SOFTWARE_SET_Z_S 3 49 50 /** ECDSA_CLK_REG register 51 * ECDSA clock gate register 52 */ 53 #define ECDSA_CLK_REG (DR_REG_ECDSA_BASE + 0x8) 54 /** ECDSA_CLK_GATE_FORCE_ON : R/W; bitpos: [0]; default: 0; 55 * Write 1 to force on register clock gate. 56 */ 57 #define ECDSA_CLK_GATE_FORCE_ON (BIT(0)) 58 #define ECDSA_CLK_GATE_FORCE_ON_M (ECDSA_CLK_GATE_FORCE_ON_V << ECDSA_CLK_GATE_FORCE_ON_S) 59 #define ECDSA_CLK_GATE_FORCE_ON_V 0x00000001U 60 #define ECDSA_CLK_GATE_FORCE_ON_S 0 61 62 /** ECDSA_INT_RAW_REG register 63 * ECDSA interrupt raw register, valid in level. 64 */ 65 #define ECDSA_INT_RAW_REG (DR_REG_ECDSA_BASE + 0xc) 66 /** ECDSA_CALC_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0; 67 * The raw interrupt status bit for the ecdsa_calc_done_int interrupt 68 */ 69 #define ECDSA_CALC_DONE_INT_RAW (BIT(0)) 70 #define ECDSA_CALC_DONE_INT_RAW_M (ECDSA_CALC_DONE_INT_RAW_V << ECDSA_CALC_DONE_INT_RAW_S) 71 #define ECDSA_CALC_DONE_INT_RAW_V 0x00000001U 72 #define ECDSA_CALC_DONE_INT_RAW_S 0 73 /** ECDSA_SHA_RELEASE_INT_RAW : RO/WTC/SS; bitpos: [1]; default: 0; 74 * The raw interrupt status bit for the ecdsa_sha_release_int interrupt 75 */ 76 #define ECDSA_SHA_RELEASE_INT_RAW (BIT(1)) 77 #define ECDSA_SHA_RELEASE_INT_RAW_M (ECDSA_SHA_RELEASE_INT_RAW_V << ECDSA_SHA_RELEASE_INT_RAW_S) 78 #define ECDSA_SHA_RELEASE_INT_RAW_V 0x00000001U 79 #define ECDSA_SHA_RELEASE_INT_RAW_S 1 80 81 /** ECDSA_INT_ST_REG register 82 * ECDSA interrupt status register. 83 */ 84 #define ECDSA_INT_ST_REG (DR_REG_ECDSA_BASE + 0x10) 85 /** ECDSA_CALC_DONE_INT_ST : RO; bitpos: [0]; default: 0; 86 * The masked interrupt status bit for the ecdsa_calc_done_int interrupt 87 */ 88 #define ECDSA_CALC_DONE_INT_ST (BIT(0)) 89 #define ECDSA_CALC_DONE_INT_ST_M (ECDSA_CALC_DONE_INT_ST_V << ECDSA_CALC_DONE_INT_ST_S) 90 #define ECDSA_CALC_DONE_INT_ST_V 0x00000001U 91 #define ECDSA_CALC_DONE_INT_ST_S 0 92 /** ECDSA_SHA_RELEASE_INT_ST : RO; bitpos: [1]; default: 0; 93 * The masked interrupt status bit for the ecdsa_sha_release_int interrupt 94 */ 95 #define ECDSA_SHA_RELEASE_INT_ST (BIT(1)) 96 #define ECDSA_SHA_RELEASE_INT_ST_M (ECDSA_SHA_RELEASE_INT_ST_V << ECDSA_SHA_RELEASE_INT_ST_S) 97 #define ECDSA_SHA_RELEASE_INT_ST_V 0x00000001U 98 #define ECDSA_SHA_RELEASE_INT_ST_S 1 99 100 /** ECDSA_INT_ENA_REG register 101 * ECDSA interrupt enable register. 102 */ 103 #define ECDSA_INT_ENA_REG (DR_REG_ECDSA_BASE + 0x14) 104 /** ECDSA_CALC_DONE_INT_ENA : R/W; bitpos: [0]; default: 0; 105 * The interrupt enable bit for the ecdsa_calc_done_int interrupt 106 */ 107 #define ECDSA_CALC_DONE_INT_ENA (BIT(0)) 108 #define ECDSA_CALC_DONE_INT_ENA_M (ECDSA_CALC_DONE_INT_ENA_V << ECDSA_CALC_DONE_INT_ENA_S) 109 #define ECDSA_CALC_DONE_INT_ENA_V 0x00000001U 110 #define ECDSA_CALC_DONE_INT_ENA_S 0 111 /** ECDSA_SHA_RELEASE_INT_ENA : R/W; bitpos: [1]; default: 0; 112 * The interrupt enable bit for the ecdsa_sha_release_int interrupt 113 */ 114 #define ECDSA_SHA_RELEASE_INT_ENA (BIT(1)) 115 #define ECDSA_SHA_RELEASE_INT_ENA_M (ECDSA_SHA_RELEASE_INT_ENA_V << ECDSA_SHA_RELEASE_INT_ENA_S) 116 #define ECDSA_SHA_RELEASE_INT_ENA_V 0x00000001U 117 #define ECDSA_SHA_RELEASE_INT_ENA_S 1 118 119 /** ECDSA_INT_CLR_REG register 120 * ECDSA interrupt clear register. 121 */ 122 #define ECDSA_INT_CLR_REG (DR_REG_ECDSA_BASE + 0x18) 123 /** ECDSA_CALC_DONE_INT_CLR : WT; bitpos: [0]; default: 0; 124 * Set this bit to clear the ecdsa_calc_done_int interrupt 125 */ 126 #define ECDSA_CALC_DONE_INT_CLR (BIT(0)) 127 #define ECDSA_CALC_DONE_INT_CLR_M (ECDSA_CALC_DONE_INT_CLR_V << ECDSA_CALC_DONE_INT_CLR_S) 128 #define ECDSA_CALC_DONE_INT_CLR_V 0x00000001U 129 #define ECDSA_CALC_DONE_INT_CLR_S 0 130 /** ECDSA_SHA_RELEASE_INT_CLR : WT; bitpos: [1]; default: 0; 131 * Set this bit to clear the ecdsa_sha_release_int interrupt 132 */ 133 #define ECDSA_SHA_RELEASE_INT_CLR (BIT(1)) 134 #define ECDSA_SHA_RELEASE_INT_CLR_M (ECDSA_SHA_RELEASE_INT_CLR_V << ECDSA_SHA_RELEASE_INT_CLR_S) 135 #define ECDSA_SHA_RELEASE_INT_CLR_V 0x00000001U 136 #define ECDSA_SHA_RELEASE_INT_CLR_S 1 137 138 /** ECDSA_START_REG register 139 * ECDSA start register 140 */ 141 #define ECDSA_START_REG (DR_REG_ECDSA_BASE + 0x1c) 142 /** ECDSA_START : WT; bitpos: [0]; default: 0; 143 * Write 1 to start caculation of ECDSA Accelerator. This bit will be self-cleared 144 * after configuration. 145 */ 146 #define ECDSA_START (BIT(0)) 147 #define ECDSA_START_M (ECDSA_START_V << ECDSA_START_S) 148 #define ECDSA_START_V 0x00000001U 149 #define ECDSA_START_S 0 150 /** ECDSA_LOAD_DONE : WT; bitpos: [1]; default: 0; 151 * Write 1 to input load done signal of ECDSA Accelerator. This bit will be 152 * self-cleared after configuration. 153 */ 154 #define ECDSA_LOAD_DONE (BIT(1)) 155 #define ECDSA_LOAD_DONE_M (ECDSA_LOAD_DONE_V << ECDSA_LOAD_DONE_S) 156 #define ECDSA_LOAD_DONE_V 0x00000001U 157 #define ECDSA_LOAD_DONE_S 1 158 /** ECDSA_GET_DONE : WT; bitpos: [2]; default: 0; 159 * Write 1 to input get done signal of ECDSA Accelerator. This bit will be 160 * self-cleared after configuration. 161 */ 162 #define ECDSA_GET_DONE (BIT(2)) 163 #define ECDSA_GET_DONE_M (ECDSA_GET_DONE_V << ECDSA_GET_DONE_S) 164 #define ECDSA_GET_DONE_V 0x00000001U 165 #define ECDSA_GET_DONE_S 2 166 167 /** ECDSA_STATE_REG register 168 * ECDSA status register 169 */ 170 #define ECDSA_STATE_REG (DR_REG_ECDSA_BASE + 0x20) 171 /** ECDSA_BUSY : RO; bitpos: [1:0]; default: 0; 172 * The status bits of ECDSA Accelerator. ECDSA is at 0: IDLE, 1: LOAD, 2: GET, 3: BUSY 173 * state. 174 */ 175 #define ECDSA_BUSY 0x00000003U 176 #define ECDSA_BUSY_M (ECDSA_BUSY_V << ECDSA_BUSY_S) 177 #define ECDSA_BUSY_V 0x00000003U 178 #define ECDSA_BUSY_S 0 179 180 /** ECDSA_RESULT_REG register 181 * ECDSA result register 182 */ 183 #define ECDSA_RESULT_REG (DR_REG_ECDSA_BASE + 0x24) 184 /** ECDSA_OPERATION_RESULT : RO/SS; bitpos: [0]; default: 0; 185 * The operation result bit of ECDSA Accelerator, only valid when ECDSA calculation is 186 * done. 187 */ 188 #define ECDSA_OPERATION_RESULT (BIT(0)) 189 #define ECDSA_OPERATION_RESULT_M (ECDSA_OPERATION_RESULT_V << ECDSA_OPERATION_RESULT_S) 190 #define ECDSA_OPERATION_RESULT_V 0x00000001U 191 #define ECDSA_OPERATION_RESULT_S 0 192 193 /** ECDSA_DATE_REG register 194 * Version control register 195 */ 196 #define ECDSA_DATE_REG (DR_REG_ECDSA_BASE + 0xfc) 197 /** ECDSA_DATE : R/W; bitpos: [27:0]; default: 35684752; 198 * ECDSA version control register 199 */ 200 #define ECDSA_DATE 0x0FFFFFFFU 201 #define ECDSA_DATE_M (ECDSA_DATE_V << ECDSA_DATE_S) 202 #define ECDSA_DATE_V 0x0FFFFFFFU 203 #define ECDSA_DATE_S 0 204 205 /** ECDSA_SHA_MODE_REG register 206 * ECDSA control SHA register 207 */ 208 #define ECDSA_SHA_MODE_REG (DR_REG_ECDSA_BASE + 0x200) 209 /** ECDSA_SHA_MODE : R/W; bitpos: [2:0]; default: 0; 210 * The work mode bits of SHA Calculator in ECDSA Accelerator. 1: SHA-224. 2: SHA-256. 211 * Others: invalid. 212 */ 213 #define ECDSA_SHA_MODE 0x00000007U 214 #define ECDSA_SHA_MODE_M (ECDSA_SHA_MODE_V << ECDSA_SHA_MODE_S) 215 #define ECDSA_SHA_MODE_V 0x00000007U 216 #define ECDSA_SHA_MODE_S 0 217 218 /** ECDSA_SHA_START_REG register 219 * ECDSA control SHA register 220 */ 221 #define ECDSA_SHA_START_REG (DR_REG_ECDSA_BASE + 0x210) 222 /** ECDSA_SHA_START : WT; bitpos: [0]; default: 0; 223 * Write 1 to start the first caculation of SHA Calculator in ECDSA Accelerator. This 224 * bit will be self-cleared after configuration. 225 */ 226 #define ECDSA_SHA_START (BIT(0)) 227 #define ECDSA_SHA_START_M (ECDSA_SHA_START_V << ECDSA_SHA_START_S) 228 #define ECDSA_SHA_START_V 0x00000001U 229 #define ECDSA_SHA_START_S 0 230 231 /** ECDSA_SHA_CONTINUE_REG register 232 * ECDSA control SHA register 233 */ 234 #define ECDSA_SHA_CONTINUE_REG (DR_REG_ECDSA_BASE + 0x214) 235 /** ECDSA_SHA_CONTINUE : WT; bitpos: [0]; default: 0; 236 * Write 1 to start the latter caculation of SHA Calculator in ECDSA Accelerator. This 237 * bit will be self-cleared after configuration. 238 */ 239 #define ECDSA_SHA_CONTINUE (BIT(0)) 240 #define ECDSA_SHA_CONTINUE_M (ECDSA_SHA_CONTINUE_V << ECDSA_SHA_CONTINUE_S) 241 #define ECDSA_SHA_CONTINUE_V 0x00000001U 242 #define ECDSA_SHA_CONTINUE_S 0 243 244 /** ECDSA_SHA_BUSY_REG register 245 * ECDSA status register 246 */ 247 #define ECDSA_SHA_BUSY_REG (DR_REG_ECDSA_BASE + 0x218) 248 /** ECDSA_SHA_BUSY : RO; bitpos: [0]; default: 0; 249 * The busy status bit of SHA Calculator in ECDSA Accelerator. 1:SHA is in 250 * calculation. 0: SHA is idle. 251 */ 252 #define ECDSA_SHA_BUSY (BIT(0)) 253 #define ECDSA_SHA_BUSY_M (ECDSA_SHA_BUSY_V << ECDSA_SHA_BUSY_S) 254 #define ECDSA_SHA_BUSY_V 0x00000001U 255 #define ECDSA_SHA_BUSY_S 0 256 257 /** ECDSA_MESSAGE_MEM register 258 * The memory that stores message. 259 */ 260 #define ECDSA_MESSAGE_MEM (DR_REG_ECDSA_BASE + 0x280) 261 #define ECDSA_MESSAGE_MEM_SIZE_BYTES 32 262 263 /** ECDSA_R_MEM register 264 * The memory that stores r. 265 */ 266 #define ECDSA_R_MEM (DR_REG_ECDSA_BASE + 0xa00) 267 #define ECDSA_R_MEM_SIZE_BYTES 32 268 269 /** ECDSA_S_MEM register 270 * The memory that stores s. 271 */ 272 #define ECDSA_S_MEM (DR_REG_ECDSA_BASE + 0xa20) 273 #define ECDSA_S_MEM_SIZE_BYTES 32 274 275 /** ECDSA_Z_MEM register 276 * The memory that stores software written z. 277 */ 278 #define ECDSA_Z_MEM (DR_REG_ECDSA_BASE + 0xa40) 279 #define ECDSA_Z_MEM_SIZE_BYTES 32 280 281 /** ECDSA_QAX_MEM register 282 * The memory that stores x coordinates of QA or software written k. 283 */ 284 #define ECDSA_QAX_MEM (DR_REG_ECDSA_BASE + 0xa60) 285 #define ECDSA_QAX_MEM_SIZE_BYTES 32 286 287 /** ECDSA_QAY_MEM register 288 * The memory that stores y coordinates of QA. 289 */ 290 #define ECDSA_QAY_MEM (DR_REG_ECDSA_BASE + 0xa80) 291 #define ECDSA_QAY_MEM_SIZE_BYTES 32 292 293 #ifdef __cplusplus 294 } 295 #endif 296
