1 /**************************************************************************//** 2 * @file eadc_reg.h 3 * @version V1.00 4 * @brief EADC register definition header file 5 * 6 * SPDX-License-Identifier: Apache-2.0 7 * @copyright (C) 2023 Nuvoton Technology Corp. All rights reserved. 8 *****************************************************************************/ 9 #ifndef __EADC_REG_H__ 10 #define __EADC_REG_H__ 11 12 #if defined ( __CC_ARM ) 13 #pragma anon_unions 14 #endif 15 16 /** 17 @addtogroup REGISTER Control Register 18 @{ 19 */ 20 21 /** 22 @addtogroup EADC Enhanced Analog to Digital Converter (EADC) 23 Memory Mapped Structure for EADC Controller 24 @{ */ 25 26 typedef struct 27 { 28 29 30 /** 31 * @var EADC_T::DAT[19] 32 * Offset: 0x00/0x04/0x08/0x0C/0x10/0x14/0x18/0x1C/0x20/0x24/0x28/0x2C/0x30/0x34/0x38/0x3C/0x40/0x44/0x48 EADC Data Register 0~18 for Sample Module 0~18 33 * --------------------------------------------------------------------------------------------------- 34 * |Bits |Field |Descriptions 35 * | :----: | :----: | :---- | 36 * |[15:0] |RESULT |EADC Conversion Result 37 * | | |This field contains 12 bits conversion result. 38 * | | |The 12-bit EADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12]. 39 * | | |Note: When operating in oversampling mode, RESULT[15:0] can represent oversampling results. 40 * |[16] |OV |Overrun Flag 41 * | | |If converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register, OV is set to 1. 42 * | | |0 = Data in RESULT[11:0] is recent conversion result. 43 * | | |1 = Data in RESULT[11:0] is overwrite. 44 * | | |Note: It is cleared by hardware after EADC_DAT register is read. 45 * |[17] |VALID |Valid Flag 46 * | | |This bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read. 47 * | | |0 = Data in RESULT[11:0] bits is not valid. 48 * | | |1 = Data in RESULT[11:0] bits is valid. 49 * @var EADC_T::CURDAT 50 * Offset: 0x4C EADC PDMA Current Transfer Data Register 51 * --------------------------------------------------------------------------------------------------- 52 * |Bits |Field |Descriptions 53 * | :----: | :----: | :---- | 54 * |[30:0] |CURDAT |EADC PDMA Current Transfer Data (Read Only) 55 * | | |This register is a shadow register of EADC_DATn (n=0~30) for PDMA support. 56 * @var EADC_T::CTL 57 * Offset: 0x50 EADC Control Register 58 * --------------------------------------------------------------------------------------------------- 59 * |Bits |Field |Descriptions 60 * | :----: | :----: | :---- | 61 * |[0] |ADCEN |EADC Converter Enable Bit 62 * | | |0 = EADC Disabled. 63 * | | |1 = EADC Enabled. 64 * | | |Note: Before starting EADC conversion function, this bit should be set to 1 65 * | | |Clear it to 0 to disable EADC converter analog circuit power consumption. 66 * |[1] |ADCRST |EADC Converter Control Circuits Reset 67 * | | |0 = No effect. 68 * | | |1 = Cause EADC control circuits reset to initial state, but not change the EADC registers value. 69 * | | |Note: EADCRST bit remains 1 during EADC reset, when EADC reset end, the EADCRST bit is automatically cleared to 0. 70 * |[2] |ADCIEN0 |Specific Sample Module EADC ADINT0 Interrupt Enable Bit 71 * | | |The EADC converter generates a conversion end ADIF0 (EADC_STATUS2[0]) upon the end of specific sample module EADC conversion 72 * | | |If ADCIEN0 bit is set then conversion end interrupt request ADINT0 is generated. 73 * | | |0 = Specific sample module EADC ADINT0 interrupt function Disabled. 74 * | | |1 = Specific sample module EADC ADINT0 interrupt function Enabled. 75 * |[3] |ADCIEN1 |Specific Sample Module EADC ADINT1 Interrupt Enable Bit 76 * | | |The EADC converter generates a conversion end ADIF1 (EADC_STATUS2[1]) upon the end of specific sample module EADC conversion 77 * | | |If EADCIEN1 bit is set then conversion end interrupt request ADINT1 is generated. 78 * | | |0 = Specific sample module EADC ADINT1 interrupt function Disabled. 79 * | | |1 = Specific sample module EADC ADINT1 interrupt function Enabled. 80 * |[4] |ADCIEN2 |Specific Sample Module EADC ADINT2 Interrupt Enable Bit 81 * | | |The EADC converter generates a conversion end ADIF2 (EADC_STATUS2[2]) upon the end of specific sample module EADC conversion 82 * | | |If EADCIEN2 bit is set then conversion end interrupt request ADINT2 is generated. 83 * | | |0 = Specific sample module EADC ADINT2 interrupt function Disabled. 84 * | | |1 = Specific sample module EADC ADINT2 interrupt function Enabled. 85 * |[5] |ADCIEN3 |Specific Sample Module EADC ADINT3 Interrupt Enable Bit 86 * | | |The EADC converter generates a conversion end ADIF3 (EADC_STATUS2[3]) upon the end of specific sample module EADC conversion 87 * | | |If EADCIEN3 bit is set then conversion end interrupt request ADINT3 is generated. 88 * | | |0 = Specific sample module EADC ADINT3 interrupt function Disabled. 89 * | | |1 = Specific sample module EADC ADINT3 interrupt function Enabled. 90 * |[8] |DIFFEN |Differential Analog Input Mode Enable Bit 91 * | | |0 = Single-end analog input mode. 92 * | | |1 = Differential analog input mode. 93 * | | |Note: In the differential mode, the input channel pair must be configured to EADC_CHx, EADC_CHx+1 , x=0,2,4,6,8,10,12,14. 94 * |[9] |DMOF |ADC Differential Input Mode Output Format 95 * | | |0 = ADC conversion result will be filled in RESULT (EADC_DATn[15:0], where n= 0 ~18) with unsigned format. 96 * | | |1 = ADC conversion result will be filled in RESULT (EADC_DATn[15:0], where n= 0 ~18) with 2'complement format. 97 * |[19:16] |INTDELAY0 |ADC Start Of Conversion ADINT0 Delay Cycle Selection 98 * | | |Start of conversion interrupt ADINT0 will delay INTDELAY0 PCLK cycles to generate interrupt 99 * | | |The function support delay 1 PCLK to 15 PCLK cycles, user can select one of the options according to the relationship of PCLK and ADC _CLK which user selected. 100 * | | |4'h0 = No delay cycle. 101 * | | |4'h1 = Start of conversion interrupt ADINT0 delay 1 PCLK cycle. 102 * | | |4'h2 = Start of conversion interrupt ADINT0 delay 2 PCLK cycles. 103 * | | |4'h3 = Start of conversion interrupt ADINT0 delay 3 PCLK cycles. 104 * | | |4'h4 = Start of conversion interrupt ADINT0 delay 4 PCLK cycles. 105 * | | |4'h5 = Start of conversion interrupt ADINT0 delay 5 PCLK cycles. 106 * | | |4'h6 = Start of conversion interrupt ADINT0 delay 6 PCLK cycles. 107 * | | |4'h7 = Start of conversion interrupt ADINT0 delay 7 PCLK cycles. 108 * | | |4'h8 = Start of conversion interrupt ADINT0 delay 8 PCLK cycles. 109 * | | |4'h9 = Start of conversion interrupt ADINT0 delay 9 PCLK cycles. 110 * | | |4'ha = Start of conversion interrupt ADINT0 delay 10 PCLK cycles. 111 * | | |4'hb = Start of conversion interrupt ADINT0 delay 11 PCLK cycles. 112 * | | |4'hc = Start of conversion interrupt ADINT0 delay 12 PCLK cycles. 113 * | | |4'hd = Start of conversion interrupt ADINT0 delay 13 PCLK cycles. 114 * | | |4'he = Start of conversion interrupt ADINT0 delay 14 PCLK cycles. 115 * | | |4'hf = Start of conversion interrupt ADINT0 delay 15 PCLK cycles. 116 * | | |Note: This function is workable only when any one of INTPOS (EADC_SCTLx[5]), x=0~15 is set. 117 * | | |Note: It is noted that the delayed interrupt ADINT0 must occurs before the next ADINT0 generated when use the same sample module to control EADC conversion. 118 * |[23:20] |INTDELAY1 |ADC Start Of Conversion ADINT1 Delay Cycle Selection 119 * | | |Start of conversion interrupt ADINT1 will delay INTDELAY1 PCLK cycles to generate interrupt 120 * | | |The function support delay 1 PCLK to 15 PCLK cycles, user can select one of the options according to the relationship of PCLK and ADC _CLK which user selected. 121 * | | |4'h0 = No delay cycle. 122 * | | |4'h1 = Start of conversion interrupt ADINT1 delay 1 PCLK cycle. 123 * | | |4'h2 = Start of conversion interrupt ADINT1 delay 2 PCLK cycles. 124 * | | |4'h3 = Start of conversion interrupt ADINT1 delay 3 PCLK cycles. 125 * | | |4'h4 = Start of conversion interrupt ADINT1 delay 4 PCLK cycles. 126 * | | |4'h5 = Start of conversion interrupt ADINT1 delay 5 PCLK cycles. 127 * | | |4'h6 = Start of conversion interrupt ADINT1 delay 6 PCLK cycles. 128 * | | |4'h7 = Start of conversion interrupt ADINT1 delay 7 PCLK cycles. 129 * | | |4'h8 = Start of conversion interrupt ADINT1 delay 8 PCLK cycles. 130 * | | |4'h9 = Start of conversion interrupt ADINT1 delay 9 PCLK cycles. 131 * | | |4'ha = Start of conversion interrupt ADINT1 delay 10 PCLK cycles. 132 * | | |4'hb = Start of conversion interrupt ADINT1 delay 11 PCLK cycles. 133 * | | |4'hc = Start of conversion interrupt ADINT1 delay 12 PCLK cycles. 134 * | | |4'hd = Start of conversion interrupt ADINT1 delay 13 PCLK cycles. 135 * | | |4'he = Start of conversion interrupt ADINT1 delay 14 PCLK cycles. 136 * | | |4'hf = Start of conversion interrupt ADINT1 delay 15 PCLK cycles. 137 * | | |Note: This function is workable only when any one of INTPOS (EADC_SCTLx[5]), x=0~15 is set. 138 * | | |Note: It is noted that the delayed interrupt ADINT1 must occurs before the next ADINT1 generated when use the same sample module to control EADC conversion. 139 * |[27:24] |INTDELAY2 |ADC Start Of Conversion ADINT2 Delay Cycle Selection 140 * | | |Start of conversion interrupt ADINT2 will delay INTDELAY2 PCLK cycles to generate interrupt 141 * | | |The function support delay 1 PCLK to 15 PCLK cycles, user can select one of the options according to the relationship of PCLK and ADC _CLK which user which user selected. 142 * | | |4'h0 = No delay cycle. 143 * | | |4'h1 = Start of conversion interrupt ADINT2 delay 1 PCLK cycle. 144 * | | |4'h2 = Start of conversion interrupt ADINT2 delay 2 PCLK cycles. 145 * | | |4'h3 = Start of conversion interrupt ADINT2 delay 3 PCLK cycles. 146 * | | |4'h4 = Start of conversion interrupt ADINT2 delay 4 PCLK cycles. 147 * | | |4'h5 = Start of conversion interrupt ADINT2 delay 5 PCLK cycles. 148 * | | |4'h6 = Start of conversion interrupt ADINT2 delay 6 PCLK cycles. 149 * | | |4'h7 = Start of conversion interrupt ADINT2 delay 7 PCLK cycles. 150 * | | |4'h8 = Start of conversion interrupt ADINT2 delay 8 PCLK cycles. 151 * | | |4'h9 = Start of conversion interrupt ADINT2 delay 9 PCLK cycles. 152 * | | |4'ha = Start of conversion interrupt ADINT2 delay 10 PCLK cycles. 153 * | | |4'hb = Start of conversion interrupt ADINT2 delay 11 PCLK cycles. 154 * | | |4'hc = Start of conversion interrupt ADINT2 delay 12 PCLK cycles. 155 * | | |4'hd = Start of conversion interrupt ADINT2 delay 13 PCLK cycles. 156 * | | |4'he = Start of conversion interrupt ADINT2 delay 14 PCLK cycles. 157 * | | |4'hf = Start of conversion interrupt ADINT2 delay 15 PCLK cycles. 158 * | | |Note: This function is workable only when any one of INTPOS (EADC_SCTLx[5]), x=0~15 is set. 159 * | | |Note: It is noted that the delayed interrupt ADINT2 must occurs before the next ADINT2 generated when use the same sample module to control EADC conversion. 160 * |[31:28] |INTDELAY3 |ADC Start Of Conversion ADINT3 Delay Cycle Selection 161 * | | |Start of conversion interrupt ADINT3 will delay INTDELAY3 PCLK cycles to generate interrupt 162 * | | |The function support delay 1 PCLK to 15 PCLK cycles, user can select one of the options according to the relationship of PCLK and ADC _CLK which user selected. 163 * | | |4'h0 = No delay cycle. 164 * | | |4'h1 = Start of conversion interrupt ADINT3 delay 1 PCLK cycle. 165 * | | |4'h2 = Start of conversion interrupt ADINT3 delay 2 PCLK cycles. 166 * | | |4'h3 = Start of conversion interrupt ADINT3 delay 3 PCLK cycles. 167 * | | |4'h4 = Start of conversion interrupt ADINT3 delay 4 PCLK cycles. 168 * | | |4'h5 = Start of conversion interrupt ADINT3 delay 5 PCLK cycles. 169 * | | |4'h6 = Start of conversion interrupt ADINT3 delay 6 PCLK cycles. 170 * | | |4'h7 = Start of conversion interrupt ADINT3 delay 7 PCLK cycles. 171 * | | |4'h8 = Start of conversion interrupt ADINT3 delay 8 PCLK cycles. 172 * | | |4'h9 = Start of conversion interrupt ADINT3 delay 9 PCLK cycles. 173 * | | |4'ha = Start of conversion interrupt ADINT3 delay 10 PCLK cycles. 174 * | | |4'hb = Start of conversion interrupt ADINT3 delay 11 PCLK cycles. 175 * | | |4'hc = Start of conversion interrupt ADINT3 delay 12 PCLK cycles. 176 * | | |4'hd = Start of conversion interrupt ADINT3 delay 13 PCLK cycles. 177 * | | |4'he = Start of conversion interrupt ADINT3 delay 14 PCLK cycles. 178 * | | |4'hf = Start of conversion interrupt ADINT3 delay 15 PCLK cycles. 179 * | | |Note: This function is workable only when any one of INTPOS (EADC_SCTLx[5]), x=0~15 is set. 180 * | | |Note: It is noted that the delayed interrupt ADINT3 must occurs before the next ADINT3 generated when use the same sample module to control EADC conversion. 181 * @var EADC_T::SWTRG 182 * Offset: 0x54 EADC Sample Module Software Start Register 183 * --------------------------------------------------------------------------------------------------- 184 * |Bits |Field |Descriptions 185 * | :----: | :----: | :---- | 186 * |[30:0] |SWTRG |EADC Sample Module 0~30 Software Force to Start EADC Conversion 187 * | | |0 = No effect. 188 * | | |1 = Cause an EADC conversion when the priority is given to sample module. 189 * | | |Note: After writing this register to start EADC conversion, the EADC_PENDSTS register will show which sample module will conversion 190 * | | |If user want to disable the conversion of the sample module, user can write EADC_PENDSTS register to clear it. 191 * @var EADC_T::PENDSTS 192 * Offset: 0x58 EADC Start of Conversion Pending Flag Register 193 * --------------------------------------------------------------------------------------------------- 194 * |Bits |Field |Descriptions 195 * | :----: | :----: | :---- | 196 * |[30:0] |STPF |EADC Sample Module 0~30 Start of Conversion Pending Flag 197 * | | |Read Operation: 198 * | | |0 = There is no pending conversion for sample module. 199 * | | |1 = Sample module EADC start of conversion is pending. 200 * | | |Write Operation: 201 * | | |1 = Clear pending flag & cancel the conversion for sample module. 202 * | | |Note: This bit remains 1 during pending state, when the respective EADC conversion is end, the STPFn (n=0~30) bit is automatically cleared to 0 203 * @var EADC_T::OVSTS 204 * Offset: 0x5C EADC Sample Module Start of Conversion Overrun Flag Register 205 * --------------------------------------------------------------------------------------------------- 206 * |Bits |Field |Descriptions 207 * | :----: | :----: | :---- | 208 * |[30:0] |SPOVF |EADC SAMPLE0~30 Overrun Flag 209 * | | |0 = No sample module event overrun. 210 * | | |1 = Indicates a new sample module event is generated while an old one event is pending. 211 * | | |Note: This bit is cleared by writing 1 to it. 212 * @var EADC_T::CTL1 213 * Offset: 0x60 EADC Control1 Register 214 * --------------------------------------------------------------------------------------------------- 215 * |Bits |Field |Descriptions 216 * | :----: | :----: | :---- | 217 * |[0] |PRECHEN |Precharge Enable 218 * | | |0 = Channel precharge Disabled. 219 * | | |1 = Channel precharge Enabled. 220 * | | |Note: Analog input voltage is 1/2 VREF when PRECHEN and DISCHEN are all enable. 221 * |[1] |DISCHEN |Discharge Enable 222 * | | |0 = Channel discharge Disabled. 223 * | | |1 = Channel discharge Enabled. 224 * | | |Note: Analog input voltage is 1/2 VREF when PRECHEN and DISCHEN are all enable. 225 * |[5:4] |RESSEL |Resolution Select Bits 226 * | | |00 = ADC resolution 12 bits. 227 * | | |01 = ADC resolution 10 bits. 228 * | | |10 = ADC resolution 8 bits. 229 * | | |11 = Reserved. 230 * |[8] |FDETCHEN |Floating Detect Channel Enable Bit 231 * | | |0 = Floating Detect Channel Disabled. 232 * | | |1 = Floating Detect Channel Enabled. 233 * |[20] |CMP0TRG |ADC Comparator 0 Trigger EPWM Brake Enable Bit 234 * | | |0 = Comparator 0 trigger EPWM brake is disabled. 235 * | | |1 = Comparator 0 trigger EPWM brake is enabled. 236 * |[21] |CMP1TRG |ADC Comparator 1 Trigger EPWM Brake Enable Bit 237 * | | |0 = Comparator 1 trigger EPWM brake is disabled. 238 * | | |1 = Comparator 1 trigger EPWM brake is enabled. 239 * |[22] |CMP2TRG |ADC Comparator 2 Trigger EPWM Brake Enable Bit 240 * | | |0 = Comparator 2 trigger EPWM brake is disabled. 241 * | | |1 = Comparator 2 trigger EPWM brake is enabled. 242 * |[23] |CMP3TRG |ADC Comparator 3 Trigger EPWM Brake Enable Bit 243 * | | |0 = Comparator 3 trigger EPWM brake is disabled. 244 * | | |1 = Comparator 3 trigger EPWM brake is enabled. 245 * @var EADC_T::SCTL[19] 246 * Offset: 0x80/0x84/0x88/0x8C/0x90/0x94/0x98/0x9C/0xA0/0xA4/0xA8/0xAC/0xB0/0xB4/0xB8/0xBC/0xC0/0xC4/0xC8 EADC Sample Module 0~18 Control Register 247 * --------------------------------------------------------------------------------------------------- 248 * |Bits |Field |Descriptions 249 * | :----: | :----: | :---- | 250 * |[4:0] |CHSEL |EADC Sample Module Channel Selection 251 * | | |00H = EADC_CH0. 252 * | | |01H = EADC_CH1. 253 * | | |02H = EADC_CH2. 254 * | | |03H = EADC_CH3. 255 * | | |04H = EADC_CH4. 256 * | | |05H = EADC_CH5. 257 * | | |06H = EADC_CH6. 258 * | | |07H = EADC_CH7. 259 * | | |08H = EADC_CH8. 260 * | | |09H = EADC_CH9. 261 * | | |0AH = EADC_CH10. 262 * | | |0BH = EADC_CH11. 263 * | | |0CH = EADC_CH12. 264 * | | |0DH = EADC_CH13. 265 * | | |0EH = EADC_CH14. 266 * | | |0FH = EADC_CH15. 267 * | | |10H = EADC_CH16. 268 * | | |11H = EADC_CH17. 269 * | | |12H = EADC_CH18. 270 * | | |13H = EADC_CH19. 271 * | | |14H = EADC_CH20. 272 * | | |15H = EADC_CH21. 273 * | | |16H = EADC_CH22. 274 * | | |17H = EADC_CH23. 275 * | | |18H = EADC_CH24. 276 * | | |19H = EADC_CH25. 277 * | | |1AH = EADC_CH26. 278 * | | |Others = Reserved. 279 * |[5] |INTPOS |Interrupt Flag Position Select 280 * | | |0 = Set ADIFn (EADC_STATUS2[n], n=0~3) at EADC end of conversion. 281 * | | |1 = Set ADIFn (EADC_STATUS2[n], n=0~3) at EADC start of conversion. 282 * |[7:6] |TRGDLYDIV |EADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection 283 * | | |Trigger delay clock frequency: 284 * | | |00 = EADC_CLK/1. 285 * | | |01 = EADC_CLK/2. 286 * | | |10 = EADC_CLK/4. 287 * | | |11 = EADC_CLK/16. 288 * |[15:8] |TRGDLYCNT |EADC Sample Module Start of Conversion Trigger Delay Time 289 * | | |Trigger delay time = TRGDLYCNT x EADC_CLK period x n (n=1,2,4,16 from TRGDLYDIV setting). 290 * |[21:16] |TRGSEL |EADC Sample Module Start of Conversion Trigger Source Selection 291 * | | |0H = Disable trigger. 292 * | | |1H = External trigger from EADC0_ST pin input. 293 * | | |2H = EADC ADINT0 interrupt EOC pulse trigger. 294 * | | |3H = EADC ADINT1 interrupt EOC pulse trigger. 295 * | | |4H = Timer0 overflow pulse trigger. 296 * | | |5H = Timer1 overflow pulse trigger. 297 * | | |6H = Timer2 overflow pulse trigger. 298 * | | |7H = Timer3 overflow pulse trigger. 299 * | | |8H = EPWM0TG0. 300 * | | |9H = EPWM0TG1. 301 * | | |AH = EPWM0TG2. 302 * | | |BH = EPWM0TG3. 303 * | | |CH = EPWM0TG4. 304 * | | |DH = EPWM0TG5. 305 * | | |EH = EPWM1TG0. 306 * | | |FH = EPWM1TG1. 307 * | | |10H = EPWM1TG2. 308 * | | |11H = EPWM1TG3. 309 * | | |12H = EPWM1TG4. 310 * | | |13H = EPWM1TG5. 311 * | | |14H = PWM0TG0. 312 * | | |15H = PWM0TG1. 313 * | | |16H = PWM0TG2. 314 * | | |17H = PWM0TG3. 315 * | | |18H = PWM0TG4. 316 * | | |19H = PWM0TG5. 317 * | | |1AH = PWM1TG0. 318 * | | |1BH = PWM1TG1. 319 * | | |1CH = PWM1TG2. 320 * | | |1DH = PWM1TG3. 321 * | | |1EH = PWM1TG4. 322 * | | |1FH = PWM1TG5. 323 * | | |20H = ACMP0_INT. 324 * | | |21H = ACMP1_INT. 325 * | | |22H = ACMP2_INT. 326 * | | |other = Reserved. 327 * |[22] |EXTREN |EADC External Trigger Rising Edge Enable Bit 328 * | | |0 = Rising edge Disabled when EADC selects EADC0_ST as trigger source. 329 * | | |1 = Rising edge Enabled when EADC selects EADC0_ST as trigger source. 330 * |[23] |EXTFEN |EADC External Trigger Falling Edge Enable Bit 331 * | | |0 = Falling edge Disabled when EADC selects EADC0_ST as trigger source. 332 * | | |1 = Falling edge Enabled when EADC selects EADC0_ST as trigger source. 333 * |[31:24] |EXTSMPT |EADC Sampling Time Extend 334 * | | |When EADC converting at high conversion rate, the sampling time of analog input voltage may not be enough if input channel loading is heavy, and software can extend EADC sampling time after trigger source is coming to get enough sampling time. 335 * | | |Extended Sampling Time = (EXTSMPT x EADC_CLK period x n)+2 [n=1,2,4,16 from EXTSTDIV setting]. 336 * @var EADC_T::INTSRC[4] 337 * Offset: 0xD0/0XD4/0xD8/0xDC EADC Interrupt 0~3 Source Enable Control Register. 338 * --------------------------------------------------------------------------------------------------- 339 * |Bits |Field |Descriptions 340 * | :----: | :----: | :---- | 341 * |[0] |SPLIE0 |Sample Module 0 Interrupt Enable Bit 342 * | | |0 = Sample Module 0 interrupt Disabled. 343 * | | |1 = Sample Module 0 interrupt Enabled. 344 * |[1] |SPLIE1 |Sample Module 1 Interrupt Enable Bit 345 * | | |0 = Sample Module 1 interrupt Disabled. 346 * | | |1 = Sample Module 1 interrupt Enabled. 347 * |[2] |SPLIE2 |Sample Module 2 Interrupt Enable Bit 348 * | | |0 = Sample Module 2 interrupt Disabled. 349 * | | |1 = Sample Module 2 interrupt Enabled. 350 * |[3] |SPLIE3 |Sample Module 3 Interrupt Enable Bit 351 * | | |0 = Sample Module 3 interrupt Disabled. 352 * | | |1 = Sample Module 3 interrupt Enabled. 353 * |[4] |SPLIE4 |Sample Module 4 Interrupt Enable Bit 354 * | | |0 = Sample Module 4 interrupt Disabled. 355 * | | |1 = Sample Module 4 interrupt Enabled. 356 * |[5] |SPLIE5 |Sample Module 5 Interrupt Enable Bit 357 * | | |0 = Sample Module 5 interrupt Disabled. 358 * | | |1 = Sample Module 5 interrupt Enabled. 359 * |[6] |SPLIE6 |Sample Module 6 Interrupt Enable Bit 360 * | | |0 = Sample Module 6 interrupt Disabled. 361 * | | |1 = Sample Module 6 interrupt Enabled. 362 * |[7] |SPLIE7 |Sample Module 7 Interrupt Enable Bit 363 * | | |0 = Sample Module 7 interrupt Disabled. 364 * | | |1 = Sample Module 7 interrupt Enabled. 365 * |[8] |SPLIE8 |Sample Module 8 Interrupt Enable Bit 366 * | | |0 = Sample Module 8 interrupt Disabled. 367 * | | |1 = Sample Module 8 interrupt Enabled. 368 * |[9] |SPLIE9 |Sample Module 9 Interrupt Enable Bit 369 * | | |0 = Sample Module 9 interrupt Disabled. 370 * | | |1 = Sample Module 9 interrupt Enabled. 371 * |[10] |SPLIE10 |Sample Module 10 Interrupt Enable Bit 372 * | | |0 = Sample Module 10 interrupt Disabled. 373 * | | |1 = Sample Module 10 interrupt Enabled. 374 * |[11] |SPLIE11 |Sample Module 11 Interrupt Enable Bit 375 * | | |0 = Sample Module 11 interrupt Disabled. 376 * | | |1 = Sample Module 11 interrupt Enabled. 377 * |[12] |SPLIE12 |Sample Module 12 Interrupt Enable Bit 378 * | | |0 = Sample Module 12 interrupt Disabled. 379 * | | |1 = Sample Module 12 interrupt Enabled. 380 * |[13] |SPLIE13 |Sample Module 13 Interrupt Enable Bit 381 * | | |0 = Sample Module 13 interrupt Disabled. 382 * | | |1 = Sample Module 13 interrupt Enabled. 383 * |[14] |SPLIE14 |Sample Module 14 Interrupt Enable Bit 384 * | | |0 = Sample Module 14 interrupt Disabled. 385 * | | |1 = Sample Module 14 interrupt Enabled. 386 * |[15] |SPLIE15 |Sample Module 15 Interrupt Enable Bit 387 * | | |0 = Sample Module 15 interrupt Disabled. 388 * | | |1 = Sample Module 15 interrupt Enabled. 389 * |[16] |SPLIE16 |Sample Module 16 Interrupt Enable Bit 390 * | | |0 = Sample Module 16 interrupt Disabled. 391 * | | |1 = Sample Module 16 interrupt Enabled. 392 * |[17] |SPLIE17 |Sample Module 17 Interrupt Enable Bit 393 * | | |0 = Sample Module 17 interrupt Disabled. 394 * | | |1 = Sample Module 17 interrupt Enabled. 395 * |[18] |SPLIE18 |Sample Module 18 Interrupt Enable Bit 396 * | | |0 = Sample Module 18 interrupt Disabled. 397 * | | |1 = Sample Module 18 interrupt Enabled. 398 * |[19] |SPLIE19 |Sample Module 19 Interrupt Enable Bit 399 * | | |0 = Sample Module 19 interrupt Disabled. 400 * | | |1 = Sample Module 19 interrupt Enabled. 401 * |[20] |SPLIE20 |Sample Module 20 Interrupt Enable Bit 402 * | | |0 = Sample Module 20 interrupt Disabled. 403 * | | |1 = Sample Module 20 interrupt Enabled. 404 * |[21] |SPLIE21 |Sample Module 21 Interrupt Enable Bit 405 * | | |0 = Sample Module 21 interrupt Disabled. 406 * | | |1 = Sample Module 21 interrupt Enabled. 407 * |[22] |SPLIE22 |Sample Module 22 Interrupt Enable Bit 408 * | | |0 = Sample Module 22 interrupt Disabled. 409 * | | |1 = Sample Module 22 interrupt Enabled. 410 * |[23] |SPLIE23 |Sample Module 23 Interrupt Enable Bit 411 * | | |0 = Sample Module 23 interrupt Disabled. 412 * | | |1 = Sample Module 23 interrupt Enabled. 413 * |[24] |SPLIE24 |Sample Module 24 Interrupt Enable Bit 414 * | | |0 = Sample Module 24 interrupt Disabled. 415 * | | |1 = Sample Module 24 interrupt Enabled. 416 * |[25] |SPLIE25 |Sample Module 25 Interrupt Enable Bit 417 * | | |0 = Sample Module 25 interrupt Disabled. 418 * | | |1 = Sample Module 25 interrupt Enabled. 419 * |[26] |SPLIE26 |Sample Module 26 Interrupt Enable Bit 420 * | | |0 = Sample Module 26 interrupt Disabled. 421 * | | |1 = Sample Module 26 interrupt Enabled. 422 * |[27] |SPLIE27 |Sample Module 27 Interrupt Enable Bit 423 * | | |0 = Sample Module 27 interrupt Disabled. 424 * | | |1 = Sample Module 27 interrupt Enabled. 425 * |[28] |SPLIE28 |Sample Module 28 Interrupt Enable Bit 426 * | | |0 = Sample Module 28 interrupt Disabled. 427 * | | |1 = Sample Module 28 interrupt Enabled. 428 * |[29] |SPLIE29 |Sample Module 29 Interrupt Enable Bit 429 * | | |0 = Sample Module 29 interrupt Disabled. 430 * | | |1 = Sample Module 29 interrupt Enabled. 431 * |[30] |SPLIE30 |Sample Module 30 Interrupt Enable Bit 432 * | | |0 = Sample Module 30 interrupt Disabled. 433 * | | |1 = Sample Module 30 interrupt Enabled. 434 * @var EADC_T::CMP[4] 435 * Offset: 0xE0/0xE4/0xE8/0xEC EADC Result Compare Register 0~3 436 * --------------------------------------------------------------------------------------------------- 437 * |Bits |Field |Descriptions 438 * | :----: | :----: | :---- | 439 * |[0] |ADCMPEN |EADC Result Compare Enable Bit 440 * | | |0 = Compare Disabled. 441 * | | |1 = Compare Enabled. 442 * | | |Set this bit to 1 to enable compare CMPDAT (EADC_CMPn[27:16], n=0~3) with specified sample module conversion result when converted data is loaded into EADC_DAT register. 443 * |[1] |ADCMPIE |EADC Result Compare Interrupt Enable Bit 444 * | | |0 = Compare function interrupt Disabled. 445 * | | |1 = Compare function interrupt Enabled. 446 * | | |If the compare function is enabled and the compare condition matches the setting of CMPCOND (EADC_CMPn[2], n=0~3) and CMPMCNT (EADC_CMPn[11:8], n=0~3), ADCMPFn (EADC_STATUS2[7:4], n=0~3) will be asserted, in the meanwhile, if ADCMPIE is set to 1, a compare interrupt request is generated. 447 * |[2] |CMPCOND |Compare Condition 448 * | | |0= Set the compare condition as that when a 12-bit EADC conversion result is less than the 12-bit CMPDAT (EADC_CMPn [27:16]), the internal match counter will increase one. 449 * | | |1= Set the compare condition as that when a 12-bit EADC conversion result is greater or equal to the 12-bit CMPDAT (EADC_CMPn [27:16]), the internal match counter will increase one. 450 * | | |Note: When the internal counter reaches the value to (CMPMCNT (EADC_CMPn[11:8], n=0~3) +1), the ADCMPF bit will be set. 451 * |[7:3] |CMPSPL |Compare Sample Module Selection 452 * | | |00000 = Sample Module 0 conversion result EADC_DAT0 is selected to be compared. 453 * | | |00001 = Sample Module 1 conversion result EADC_DAT1 is selected to be compared. 454 * | | |00010 = Sample Module 2 conversion result EADC_DAT2 is selected to be compared. 455 * | | |00011 = Sample Module 3 conversion result EADC_DAT3 is selected to be compared. 456 * | | |00100 = Sample Module 4 conversion result EADC_DAT4 is selected to be compared. 457 * | | |00101 = Sample Module 5 conversion result EADC_DAT5 is selected to be compared. 458 * | | |00110 = Sample Module 6 conversion result EADC_DAT6 is selected to be compared. 459 * | | |00111 = Sample Module 7 conversion result EADC_DAT7 is selected to be compared. 460 * | | |01000 = Sample Module 8 conversion result EADC_DAT8 is selected to be compared. 461 * | | |01001 = Sample Module 9 conversion result EADC_DAT9 is selected to be compared. 462 * | | |01010 = Sample Module 10 conversion result EADC_DAT10 is selected to be compared. 463 * | | |01011 = Sample Module 11 conversion result EADC_DAT11 is selected to be compared. 464 * | | |01100 = Sample Module 12 conversion result EADC_DAT12 is selected to be compared. 465 * | | |01101 = Sample Module 13 conversion result EADC_DAT13 is selected to be compared. 466 * | | |01110 = Sample Module 14 conversion result EADC_DAT14 is selected to be compared. 467 * | | |01111 = Sample Module 15 conversion result EADC_DAT15 is selected to be compared. 468 * | | |10000 = Sample Module 16 conversion result EADC_DAT16 is selected to be compared. 469 * | | |10001 = Sample Module 17 conversion result EADC_DAT17 is selected to be compared. 470 * | | |10010 = Sample Module 18 conversion result EADC_DAT18 is selected to be compared. 471 * | | |10011 = Sample Module 19 conversion result EADC_DAT19 is selected to be compared. 472 * | | |10100 = Sample Module 20 conversion result EADC_DAT20 is selected to be compared. 473 * | | |10101 = Sample Module 21 conversion result EADC_DAT21 is selected to be compared. 474 * | | |10110 = Sample Module 22 conversion result EADC_DAT22 is selected to be compared. 475 * | | |10111 = Sample Module 23 conversion result EADC_DAT23 is selected to be compared. 476 * | | |11000 = Sample Module 24 conversion result EADC_DAT24 is selected to be compared. 477 * | | |11001 = Sample Module 25 conversion result EADC_DAT25 is selected to be compared. 478 * | | |11010 = Sample Module 26 conversion result EADC_DAT26 is selected to be compared. 479 * | | |11011 = Sample Module 27 conversion result EADC_DAT27 is selected to be compared. 480 * | | |11100 = Sample Module 28 conversion result EADC_DAT28 is selected to be compared. 481 * | | |11101 = Sample Module 29 conversion result EADC_DAT29 is selected to be compared. 482 * | | |11110 = Sample Module 30 conversion result EADC_DAT30 is selected to be compared. 483 * | | |Others = reserved. 484 * |[11:8] |CMPMCNT |Compare Match Count 485 * | | |When the specified EADC sample module analog conversion result matches the compare condition defined by CMPCOND (EADC_CMPn[2], n=0~3), the internal match counter will increase 1 486 * | | |If the compare result does not meet the compare condition, the internal compare match counter will reset to 0 487 * | | |When the internal counter reaches the value to (CMPMCNT +1), the ADCMPFn (EADC_STATUS2[7:4], n=0~3) will be set. 488 * |[15] |CMPWEN |Compare Window Mode Enable Bit 489 * | | |0 = EADCMPF0 (EADC_STATUS2[4]) will be set when EADC_CMP0 compared condition matched 490 * | | |EADCMPF2 (EADC_STATUS2[6]) will be set when EADC_CMP2 compared condition matched 491 * | | |1 = EADCMPF0 (EADC_STATUS2[4]) will be set when both EADC_CMP0 and EADC_CMP1 compared condition matched 492 * | | |EADCMPF2 (EADC_STATUS2[6]) will be set when both EADC_CMP2 and EADC_CMP3 compared condition matched. 493 * | | |Note: This bit is only present in EADC_CMP0 and EADC_CMP2 register. 494 * | | |Note: When in compare window mode, the CMPCNT setting only follow EADC_CMP0, EADC_CMP2 registers 495 * |[27:16] |CMPDAT |Comparison Data 496 * | | |The 12 bits data is used to compare with conversion result of specified sample module 497 * | | |User can use it to monitor the external analog input pin voltage transition without imposing a load on software. 498 * @var EADC_T::STATUS0 499 * Offset: 0xF0 EADC Status Register 0 500 * --------------------------------------------------------------------------------------------------- 501 * |Bits |Field |Descriptions 502 * | :----: | :----: | :---- | 503 * |[15:0] |VALID |EADC_DAT0~15 Data Valid Flag 504 * | | |It is a mirror of VALID bit in sample module EADC result data register EADC_DATn. (n=0~15). 505 * |[31:16] |OV |EADC_DAT0~15 Overrun Flag 506 * | | |It is a mirror to OV bit in sample module EADC result data register EADC_DATn. (n=0~15). 507 * @var EADC_T::STATUS1 508 * Offset: 0xF4 EADC Status Register 1 509 * --------------------------------------------------------------------------------------------------- 510 * |Bits |Field |Descriptions 511 * | :----: | :----: | :---- | 512 * |[14:0] |VALID |EADC_DAT16~30 Data Valid Flag 513 * | | |It is a mirror of VALID bit in sample module EADC result data register EADC_DATn. (n=16~30). 514 * |[30:16] |OV |EADC_DAT16~30 Overrun Flag 515 * | | |It is a mirror to OV bit in sample module EADC result data register EADC_DATn. (n=16~30). 516 * @var EADC_T::STATUS2 517 * Offset: 0xF8 EADC Status Register 2 518 * --------------------------------------------------------------------------------------------------- 519 * |Bits |Field |Descriptions 520 * | :----: | :----: | :---- | 521 * |[0] |ADIF0 |EADC ADINT0 Interrupt Flag 522 * | | |0 = No ADINT0 interrupt pulse received. 523 * | | |1 = ADINT0 interrupt pulse has been received. 524 * | | |Note 1: This bit is cleared by writing 1 to it. 525 * | | |Note 2: This bit indicates whether an EADC conversion of specific sample module has been completed 526 * |[1] |ADIF1 |EADC ADINT1 Interrupt Flag 527 * | | |0 = No ADINT1 interrupt pulse received. 528 * | | |1 = ADINT1 interrupt pulse has been received. 529 * | | |Note 1: This bit is cleared by writing 1 to it. 530 * | | |Note 2: This bit indicates whether an EADC conversion of specific sample module has been completed 531 * |[2] |ADIF2 |EADC ADINT2 Interrupt Flag 532 * | | |0 = No ADINT2 interrupt pulse received. 533 * | | |1 = ADINT2 interrupt pulse has been received. 534 * | | |Note 1: This bit is cleared by writing 1 to it. 535 * | | |Note 2: This bit indicates whether an EADC conversion of specific sample module has been completed 536 * |[3] |ADIF3 |EADC ADINT3 Interrupt Flag 537 * | | |0 = No ADINT3 interrupt pulse received. 538 * | | |1 = ADINT3 interrupt pulse has been received. 539 * | | |Note 1: This bit is cleared by writing 1 to it. 540 * | | |Note 2: This bit indicates whether an EADC conversion of specific sample module has been completed 541 * |[4] |ADCMPF0 |EADC Compare 0 Flag 542 * | | |When the specific sample module EADC conversion result meets setting condition in EADC_CMP0 then this bit is set to 1. 543 * | | |0 = Conversion result in EADC_DAT does not meet EADC_CMP0 register setting. 544 * | | |1 = Conversion result in EADC_DAT meets EADC_CMP0 register setting. 545 * | | |Note: This bit is cleared by writing 1 to it. 546 * |[5] |ADCMPF1 |EADC Compare 1 Flag 547 * | | |When the specific sample module EADC conversion result meets setting condition in EADC_CMP1 then this bit is set to 1. 548 * | | |0 = Conversion result in EADC_DAT does not meet EADC_CMP1 register setting. 549 * | | |1 = Conversion result in EADC_DAT meets EADC_CMP1 register setting. 550 * | | |Note: This bit is cleared by writing 1 to it. 551 * |[6] |ADCMPF2 |EADC Compare 2 Flag 552 * | | |When the specific sample module EADC conversion result meets setting condition in EADC_CMP2 then this bit is set to 1. 553 * | | |0 = Conversion result in EADC_DAT does not meet EADC_CMP2 register setting. 554 * | | |1 = Conversion result in EADC_DAT meets EADC_CMP2 register setting. 555 * | | |Note: This bit is cleared by writing 1 to it. 556 * |[7] |ADCMPF3 |EADC Compare 3 Flag 557 * | | |When the specific sample module EADC conversion result meets setting condition in EADC_CMP3 then this bit is set to 1. 558 * | | |0 = Conversion result in EADC_DAT does not meet EADC_CMP3 register setting. 559 * | | |1 = Conversion result in EADC_DAT meets EADC_CMP3 register setting. 560 * | | |Note: This bit is cleared by writing 1 to it. 561 * |[8] |ADOVIF0 |EADC ADINT0 Interrupt Flag Overrun 562 * | | |0 = ADINT0 interrupt flag is not overwritten to 1. 563 * | | |1 = ADINT0 interrupt flag is overwritten to 1. 564 * | | |Note: This bit is cleared by writing 1 to it. 565 * |[9] |ADOVIF1 |EADC ADINT1 Interrupt Flag Overrun 566 * | | |0 = ADINT1 interrupt flag is not overwritten to 1. 567 * | | |1 = ADINT1 interrupt flag is overwritten to 1. 568 * | | |Note: This bit is cleared by writing 1 to it. 569 * |[10] |ADOVIF2 |EADC ADINT2 Interrupt Flag Overrun 570 * | | |0 = ADINT2 interrupt flag is not overwritten to 1. 571 * | | |1 = ADINT2 interrupt flag is s overwritten to 1. 572 * | | |Note: This bit is cleared by writing 1 to it. 573 * |[11] |ADOVIF3 |EADC ADINT3 Interrupt Flag Overrun 574 * | | |0 = ADINT3 interrupt flag is not overwritten to 1. 575 * | | |1 = ADINT3 interrupt flag is overwritten to 1. 576 * | | |Note: This bit is cleared by writing 1 to it. 577 * |[12] |ADCMPO0 |EADC Compare 0 Output Status (Read Only) 578 * | | |The 12 bits compare0 data CMPDAT0 (EADC_CMP0[27:16]) is used to compare with conversion result of specified sample module 579 * | | |User can use it to monitor the external analog input pin voltage status. 580 * | | |0 = Conversion result in EADC_DAT less than CMPDAT0 setting. 581 * | | |1 = Conversion result in EADC_DAT great than or equal CMPDAT0 setting. 582 * |[13] |ADCMPO1 |EADC Compare 1 Output Status (Read Only) 583 * | | |The 12 bits compare1 data CMPDAT1 (EADC_CMP1[27:16]) is used to compare with conversion result of specified sample module 584 * | | |User can use it to monitor the external analog input pin voltage status. 585 * | | |0 = Conversion result in EADC_DAT less than CMPDAT1 setting. 586 * | | |1 = Conversion result in EADC_DAT great than or equal to CMPDAT1 setting. 587 * |[14] |ADCMPO2 |EADC Compare 2 Output Status (Read Only) 588 * | | |The 12 bits compare2 data CMPDAT2 (EADC_CMP2[27:16]) is used to compare with conversion result of specified sample module 589 * | | |User can use it to monitor the external analog input pin voltage status. 590 * | | |0 = Conversion result in EADC_DAT less than CMPDAT2 setting. 591 * | | |1 = Conversion result in EADC_DAT great than or equal to CMPDAT2 setting. 592 * |[15] |ADCMPO3 |EADC Compare 3 Output Status (Read Only) 593 * | | |The 12 bits compare3 data CMPDAT3 (EADC_CMP3[27:16]) is used to compare with conversion result of specified sample module 594 * | | |User can use it to monitor the external analog input pin voltage status. 595 * | | |0 = Conversion result in EADC_DAT less than CMPDAT3 setting. 596 * | | |1 = Conversion result in EADC_DAT great than or equal to CMPDAT3 setting. 597 * |[20:16] |CHANNEL |Current Conversion Channel (Read Only) 598 * | | |This filed reflects EADC current conversion channel when BUSY=1. 599 * | | |00H = EADC_CH0. 600 * | | |01H = EADC_CH1. 601 * | | |02H = EADC_CH2. 602 * | | |03H = EADC_CH3. 603 * | | |04H = EADC_CH4. 604 * | | |05H = EADC_CH5. 605 * | | |06H = EADC_CH6. 606 * | | |07H = EADC_CH7. 607 * | | |08H = EADC_CH8. 608 * | | |09H = EADC_CH9. 609 * | | |0AH = EADC_CH10. 610 * | | |0BH = EADC_CH11. 611 * | | |0CH = EADC_CH12. 612 * | | |0DH = EADC_CH13. 613 * | | |0EH = EADC_CH14. 614 * | | |0FH = EADC_CH15. 615 * | | |10H = EADC_CH16. 616 * | | |11H = EADC_CH17. 617 * | | |12H = EADC_CH18. 618 * | | |13H = EADC_CH19. 619 * | | |14H = EADC_CH20. 620 * | | |15H = EADC_CH21. 621 * | | |16H = EADC_CH22. 622 * | | |17H = EADC_CH23. 623 * | | |18H = EADC_CH24. 624 * | | |19H = EADC_CH25. 625 * | | |1AH = EADC_CH26. 626 * | | |1BH = AVDD/4. 627 * | | |1CH = VBG. 628 * | | |1DH = VTEMP . 629 * | | |1EH = VBAT/4. 630 * |[23] |BUSY |Busy/Idle (Read Only) 631 * | | |0 = EADC is in idle state. 632 * | | |1 = EADC is busy at conversion. 633 * | | |Note: This flag will be high after 4*EADC_CLK cycles, when the trigger source is coming. 634 * |[24] |ADOVIF |All EADC Interrupt Flag Overrun Bits Check (Read Only) 635 * | | |n=0~3. 636 * | | |0 = None of ADINT interrupt flag ADOVIFn, n=0~3 is overwritten to 1. 637 * | | |1 = Any one of ADINT interrupt flag ADOVIFn, n=0~3 is overwritten to 1. 638 * | | |Note: This bit will keep 1 when any ADOVIFn Flag is equal to 1. 639 * |[25] |STOVF |for All EADC Sample Module Start of Conversion Overrun Flags Check (Read Only) 640 * | | |n=0~30. 641 * | | |0 = None of sample module event overrun flag SPOVFn (EADC_OVSTS[n]) is set to 1. 642 * | | |1 = Any one of sample module event overrun flag SPOVFn (EADC_OVSTS[n]) is set to 1. 643 * | | |Note: This bit will keep 1 when any SPOVFn Flag is equal to 1. 644 * |[26] |AVALID |for All Sample Module EADC Result Data Register EADC_DAT Data Valid Flag Check (Read Only) 645 * | | |n=0~30. 646 * | | |0 = None of sample module data register valid flag VALIDn (EADC_DATn[17]) is set to 1. 647 * | | |1 = Any one of sample module data register valid flag VALIDn (EADC_DATn[17]) is set to 1. 648 * | | |Note: This bit will keep 1 when any VALIDn Flag is equal to 1. 649 * |[27] |AOV |for All Sample Module EADC Result Data Register Overrun Flags Check (Read Only) 650 * | | |n=0~30. 651 * | | |0 = None of sample module data register overrun flag OVn (EADC_DATn[16]) is set to 1. 652 * | | |1 = Any one of sample module data register overrun flag OVn (EADC_DATn[16]) is set to 1. 653 * | | |Note: This bit will keep 1 when any OVn Flag is equal to 1. 654 * @var EADC_T::STATUS3 655 * Offset: 0xFC EADC Status Register 3 656 * --------------------------------------------------------------------------------------------------- 657 * |Bits |Field |Descriptions 658 * | :----: | :----: | :---- | 659 * |[4:0] |CURSPL |EADC Current Sample Module (Read Only) 660 * | | |This register shows the current EADC is controlled by which sample module control logic modules. 661 * | | |If the EADC is Idle, the bit filed will set to 0x1F. 662 * @var EADC_T::DDAT[4] 663 * Offset: 0x100/0x104/0x108/0x10C EADC Double Data Register 0~3 for Sample Module 0~3 664 * --------------------------------------------------------------------------------------------------- 665 * |Bits |Field |Descriptions 666 * | :----: | :----: | :---- | 667 * |[15:0] |RESULT |EADC Conversion Results 668 * | | |This field contains 12 bits conversion results. 669 * | | |The 12-bit EADC conversion result with unsigned format will be filled in RESULT [11:0] and zero will be filled in RESULT [15:12]. 670 * |[16] |OV |Overrun Flag 671 * | | |0 = Double Data in RESULT (EADC_DDATn[15:0], n=0~3) is recent conversion result. 672 * | | |1 = Double Data in RESULT (EADC_DDATn[15:0], n=0~3) is overwrite. 673 * | | |If converted data in RESULT[15:0] has not been read before new conversion result is loaded to this register, OV is set to 1 674 * | | |It is cleared by hardware after EADC_DDAT register is read. 675 * |[17] |VALID |Valid Flag 676 * | | |0 = Double data in RESULT (EADC_DDATn[15:0]) is not valid. 677 * | | |1 = Double data in RESULT (EADC_DDATn[15:0]) is valid. 678 * | | |This bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DDATn register is read 679 * | | |(n=0~3). 680 * @var EADC_T::CALCTL 681 * Offset: 0x114 EADC Calibration Control Register 682 * --------------------------------------------------------------------------------------------------- 683 * |Bits |Field |Descriptions 684 * | :----: | :----: | :---- | 685 * |[0] |CAL |Calibration Enable Bit 686 * | | |0 = Calibration Disabled. 687 * | | |1 = Calibration Enabled. 688 * | | |Note: This bit is hardware auto cleared when calibration is done 689 * |[1] |CALIE |Calibration Interrupt Enable Bit 690 * | | |0 = Calibration interrupt Disabled. 691 * | | |1 = Calibration interrupt Enabled. 692 * @var EADC_T::CALSR 693 * Offset: 0x118 EADC Calibration Status Register 694 * --------------------------------------------------------------------------------------------------- 695 * |Bits |Field |Descriptions 696 * | :----: | :----: | :---- | 697 * |[16] |CALIF |Calibration Finish Interrupt Flag 698 * | | |If calibration is finished, this flag will be set to 1. It is cleared by writing 1 to it. 699 * @var EADC_T::PDMACTL 700 * Offset: 0x130 EADC PDMA Control Register 701 * --------------------------------------------------------------------------------------------------- 702 * |Bits |Field |Descriptions 703 * | :----: | :----: | :---- | 704 * |[30:0] |PDMATEN |PDMA Transfer Enable Bit 705 * | | |When EADC conversion is completed, the converted data is loaded into EADC_DATn (n: 0 ~ 30) register, user can enable this bit to generate a PDMA data transfer request. 706 * | | |0 = PDMA data transfer Disabled. 707 * | | |1 = PDMA data transfer Enabled. 708 * | | |Note:When setting this bit field to 1, user must set ADCIENn (EADC_CTL[5:2], n=0~3) = 0 to disable interrupt. 709 * @var EADC_T::MCTL1[19] 710 * Offset: 0x140/0x144/0x148/0x14C/0x150/0x154/0x158/0x15C/0x160/0x164/0x168/0x16C/0x170/0x174/0x178/0x17C/0x180/0x184/0x188 EADC Sample Module 0~18 Control Register 1 711 * --------------------------------------------------------------------------------------------------- 712 * |Bits |Field |Descriptions 713 * | :----: | :----: | :---- | 714 * |[0] |ALIGN |Alignment Selection 715 * | | |0 = The conversion result will be right aligned in data register. 716 * | | |1 = The conversion result will be left aligned in data register. 717 * |[1] |AVG |Average Mode Selection 718 * | | |0 = Conversion results will be stored in data register without averaging. 719 * | | |1 = Conversion results in data register will be averaged. 720 * | | |Note: This bit needs to work with ACU (EADC_MnCTL1[7:4], n=0~26). 721 * |[7:4] |ACU |Number of Accumulated Conversion Results Selection 722 * | | |0000 = 1 conversion result will be accumulated. 723 * | | |0001 = 2 conversion result will be accumulated. 724 * | | |0010 = 4 conversion result will be accumulated. 725 * | | |0011 = 8 conversion result will be accumulated. 726 * | | |0100 = 16 conversion result will be accumulated. 727 * | | |0101 = 32 conversion result will be accumulated. 728 * | | |0110 = 64 conversion result will be accumulated. 729 * | | |0111 = 128 conversion result will be accumulated. 730 * | | |1000 = 256 conversion result will be accumulated. 731 * | | |Others = Reserved. 732 * |[17:16] |EXTSTDIV |EADC Extended Sampling Time Clock Divider Selection 733 * | | |Clock frequency for extending sampling time: 734 * | | |00 = EADC_CLK/1. 735 * | | |01 = EADC_CLK/2. 736 * | | |10 = EADC_CLK/4. 737 * | | |11 = EADC_CLK/16. 738 * |[20] |DBMEN |Double Buffer Mode Enable Bit 739 * | | |0 = Sample has one sample result register (default). 740 * | | |1 = Sample has two sample result registers. 741 * @var EADC_T::DAT19[12] 742 * Offset: 0x200/0x204/0x208/0x20C/0x210/0x214/0x218/0x21C/0x220/0x224/0x228/0x22C EADC Data Register 19~30 for Sample Module 19~30 743 * --------------------------------------------------------------------------------------------------- 744 * |Bits |Field |Descriptions 745 * | :----: | :----: | :---- | 746 * |[15:0] |RESULT |EADC Conversion Result 747 * | | |This field contains 12 bits conversion result 748 * | | |The 12-bit EADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12]. 749 * | | |Note: When operating in oversampling mode, RESULT[15:0] can represent oversampling results. 750 * |[16] |OV |Overrun Flag 751 * | | |If converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register, OV is set to 1. 752 * | | |0 = Data in RESULT[11:0] is recent conversion result. 753 * | | |1 = Data in RESULT[11:0] is overwrite. 754 * | | |Note: It is cleared by hardware after EADC_DAT register is read. 755 * |[17] |VALID |Valid Flag 756 * | | |This bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read. 757 * | | |0 = Data in RESULT[11:0] bits is not valid. 758 * | | |1 = Data in RESULT[11:0] bits is valid. 759 * @var EADC_T::SCTL19[12] 760 * Offset: 0x230/0x234/0x238/0x23C/0x240/0x244/0x248/0x24C/0x250/0x254/0x258/0x25C EADC Sample Module 19~30 Control Register 761 * --------------------------------------------------------------------------------------------------- 762 * |Bits |Field |Descriptions 763 * | :----: | :----: | :---- | 764 * |[4:0] |CHSEL |EADC Sample Module Channel Selection 765 * | | |00H = EADC_CH0. 766 * | | |01H = EADC_CH1. 767 * | | |02H = EADC_CH2. 768 * | | |03H = EADC_CH3. 769 * | | |04H = EADC_CH4. 770 * | | |05H = EADC_CH5. 771 * | | |06H = EADC_CH6. 772 * | | |07H = EADC_CH7. 773 * | | |08H = EADC_CH8. 774 * | | |09H = EADC_CH9. 775 * | | |0AH = EADC_CH10. 776 * | | |0BH = EADC_CH11. 777 * | | |0CH = EADC_CH12. 778 * | | |0DH = EADC_CH13. 779 * | | |0EH = EADC_CH14. 780 * | | |0FH = EADC_CH15. 781 * | | |10H = EADC_CH16. 782 * | | |11H = EADC_CH17. 783 * | | |12H = EADC_CH18. 784 * | | |13H = EADC_CH19. 785 * | | |14H = EADC_CH20. 786 * | | |15H = EADC_CH21. 787 * | | |16H = EADC_CH22. 788 * | | |17H = EADC_CH23. 789 * | | |18H = EADC_CH24. 790 * | | |19H = EADC_CH25. 791 * | | |1AH = EADC_CH26. 792 * | | |Others = Reserved. 793 * |[5] |INTPOS |Interrupt Flag Position Select 794 * | | |0 = Set ADIFn (EADC_STATUS2[n], n=0~3) at EADC end of conversion. 795 * | | |1 = Set ADIFn (EADC_STATUS2[n], n=0~3) at EADC start of conversion. 796 * |[7:6] |TRGDLYDIV |EADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection 797 * | | |Trigger delay clock frequency: 798 * | | |00 = EADC_CLK/1. 799 * | | |01 = EADC_CLK/2. 800 * | | |10 = EADC_CLK/4. 801 * | | |11 = EADC_CLK/16. 802 * |[15:8] |TRGDLYCNT |EADC Sample Module Start of Conversion Trigger Delay Time 803 * | | |Trigger delay time = TRGDLYCNT x EADC_CLK period x n (n=1,2,4,16 from TRGDLYDIV setting). 804 * |[21:16] |TRGSEL |EADC Sample Module Start of Conversion Trigger Source Selection 805 * | | |0H = Disable trigger. 806 * | | |1H = External trigger from EADC0_ST pin input. 807 * | | |2H = EADC ADINT0 interrupt EOC pulse trigger. 808 * | | |3H = EADC ADINT1 interrupt EOC pulse trigger. 809 * | | |4H = Timer0 overflow pulse trigger. 810 * | | |5H = Timer1 overflow pulse trigger. 811 * | | |6H = Timer2 overflow pulse trigger. 812 * | | |7H = Timer3 overflow pulse trigger. 813 * | | |8H = EPWM0TG0. 814 * | | |9H = EPWM0TG1. 815 * | | |AH = EPWM0TG2. 816 * | | |BH = EPWM0TG3. 817 * | | |CH = EPWM0TG4. 818 * | | |DH = EPWM0TG5. 819 * | | |EH = EPWM1TG0. 820 * | | |FH = EPWM1TG1. 821 * | | |10H = EPWM1TG2. 822 * | | |11H = EPWM1TG3. 823 * | | |12H = EPWM1TG4. 824 * | | |13H = EPWM1TG5. 825 * | | |14H = PWM0TG0. 826 * | | |15H = PWM0TG1. 827 * | | |16H = PWM0TG2. 828 * | | |17H = PWM0TG3. 829 * | | |18H = PWM0TG4. 830 * | | |19H = PWM0TG5. 831 * | | |1AH = PWM1TG0. 832 * | | |1BH = PWM1TG1. 833 * | | |1CH = PWM1TG2. 834 * | | |1DH = PWM1TG3. 835 * | | |1EH = PWM1TG4. 836 * | | |1FH = PWM1TG5. 837 * | | |20H = ACMP0_INT. 838 * | | |21H = ACMP1_INT. 839 * | | |22H = ACMP2_INT. 840 * | | |other = Reserved. 841 * |[22] |EXTREN |EADC External Trigger Rising Edge Enable Bit 842 * | | |0 = Rising edge Disabled when EADC selects EADC0_ST as trigger source. 843 * | | |1 = Rising edge Enabled when EADC selects EADC0_ST as trigger source. 844 * |[23] |EXTFEN |EADC External Trigger Falling Edge Enable Bit 845 * | | |0 = Falling edge Disabled when EADC selects EADC0_ST as trigger source. 846 * | | |1 = Falling edge Enabled when EADC selects EADC0_ST as trigger source. 847 * |[31:24] |EXTSMPT |EADC Sampling Time Extend 848 * | | |When EADC converting at high conversion rate, the sampling time of analog input voltage may not be enough if input channel loading is heavy, and software can extend EADC sampling time after trigger source is coming to get enough sampling time. 849 * | | |Extended Sampling Time = (EXTSMPT x EADC_CLK period x n)+2 [n=1,2,4,16 from EXTSTDIV setting]. 850 * @var EADC_T::M19CTL1[12] 851 * Offset: 0x260/0x264/0x268/0x26C/0x270/0x274/0x278/0x27C/0x280/0x284/0x288/0x28C EADC Sample Module 19~30 Control Register 1 852 * --------------------------------------------------------------------------------------------------- 853 * |Bits |Field |Descriptions 854 * | :----: | :----: | :---- | 855 * |[0] |ALIGN |Alignment Selection 856 * | | |0 = The conversion result will be right aligned in data register. 857 * | | |1 = The conversion result will be left aligned in data register. 858 * |[1] |AVG |Average Mode Selection 859 * | | |0 = Conversion results will be stored in data register without averaging. 860 * | | |1 = Conversion results in data register will be averaged. 861 * | | |Note: This bit needs to work with ACU (EADC_MnCTL1[7:4], n=0~26). 862 * |[7:4] |ACU |Number of Accumulated Conversion Results Selection 863 * | | |0000 = 1 conversion result will be accumulated. 864 * | | |0001 = 2 conversion result will be accumulated. 865 * | | |0010 = 4 conversion result will be accumulated. 866 * | | |0011 = 8 conversion result will be accumulated. 867 * | | |0100 = 16 conversion result will be accumulated. 868 * | | |0101 = 32 conversion result will be accumulated. 869 * | | |0110 = 64 conversion result will be accumulated. 870 * | | |0111 = 128 conversion result will be accumulated. 871 * | | |1000 = 256 conversion result will be accumulated. 872 * | | |Others = Reserved. 873 * |[17:16] |EXTSTDIV |EADC Extended Sampling Time Clock Divider Selection 874 * | | |Clock frequency for extending sampling time: 875 * | | |00 = EADC_CLK/1. 876 * | | |01 = EADC_CLK/2. 877 * | | |10 = EADC_CLK/4. 878 * | | |11 = EADC_CLK/16. 879 */ 880 __I uint32_t DAT[19]; /*!< [0x0000-0x0048] EADC Data Register 0~18 for Sample Module 0~18 */ 881 __I uint32_t CURDAT; /*!< [0x004c] EADC PDMA Current Transfer Data Register */ 882 __IO uint32_t CTL; /*!< [0x0050] EADC Control Register */ 883 __O uint32_t SWTRG; /*!< [0x0054] EADC Sample Module Software Start Register */ 884 __IO uint32_t PENDSTS; /*!< [0x0058] EADC Start of Conversion Pending Flag Register */ 885 __IO uint32_t OVSTS; /*!< [0x005c] EADC Sample Module Start of Conversion Overrun Flag Register */ 886 __IO uint32_t CTL1; /*!< [0x0060] EADC Control1 Register */ 887 __I uint32_t RESERVE0[7]; 888 __IO uint32_t SCTL[19]; /*!< [0x0080-0x00c8] EADC Sample Module 0~18 Control Register */ 889 __I uint32_t RESERVE1[1]; 890 __IO uint32_t INTSRC[4]; /*!< [0x00d0-0x00dc] EADC Interrupt 0~3 Source Enable Control Register. */ 891 __IO uint32_t CMP[4]; /*!< [0x00e0-0x00ec] EADC Result Compare Register 0~3 */ 892 __I uint32_t STATUS0; /*!< [0x00f0] EADC Status Register 0 */ 893 __I uint32_t STATUS1; /*!< [0x00f4] EADC Status Register 1 */ 894 __IO uint32_t STATUS2; /*!< [0x00f8] EADC Status Register 2 */ 895 __I uint32_t STATUS3; /*!< [0x00fc] EADC Status Register 3 */ 896 __I uint32_t DDAT[4]; /*!< [0x0100-0x010c] EADC Double Data Register 0~3 for Sample Module 0~3 */ 897 __I uint32_t RESERVE2[1]; 898 __IO uint32_t CALCTL; /*!< [0x0114] EADC Calibration Control Register */ 899 __IO uint32_t CALSR; /*!< [0x0118] EADC Calibration Status Register */ 900 __I uint32_t RESERVE3[5]; 901 __IO uint32_t PDMACTL; /*!< [0x0130] EADC PDMA Control Register */ 902 __I uint32_t RESERVE4[3]; 903 __IO uint32_t MCTL1[19]; /*!< [0x0140-0x0188] EADC Sample Module 0~18 Control Register 1 */ 904 __I uint32_t RESERVE5[29]; 905 __I uint32_t DAT19[12]; /*!< [0x0200-0x022c] EADC Data Register 19~30 for Sample Module 19~30 */ 906 __IO uint32_t SCTL19[12]; /*!< [0x0230-0x025c] EADC Sample Module 19~30 Control Register */ 907 __IO uint32_t M19CTL1[12]; /*!< [0x0260-0x028c] EADC Sample Module 19~30 Control Register 1 */ 908 909 } EADC_T; 910 911 /** 912 @addtogroup EADC_CONST EADC Bit Field Definition 913 Constant Definitions for EADC Controller 914 @{ */ 915 916 917 #define EADC_DAT_RESULT_Pos (0) /*!< EADC_T::DAT: RESULT Position */ 918 #define EADC_DAT_RESULT_Msk (0xffffUL << EADC_DAT_RESULT_Pos) /*!< EADC_T::DAT: RESULT Mask */ 919 920 #define EADC_DAT_OV_Pos (16) /*!< EADC_T::DAT: OV Position */ 921 #define EADC_DAT_OV_Msk (0x1UL << EADC_DAT_OV_Pos) /*!< EADC_T::DAT: OV Mask */ 922 923 #define EADC_DAT_VALID_Pos (17) /*!< EADC_T::DAT: VALID Position */ 924 #define EADC_DAT_VALID_Msk (0x1UL << EADC_DAT_VALID_Pos) /*!< EADC_T::DAT: VALID Mask */ 925 926 #define EADC_DAT0_RESULT_Pos (0) /*!< EADC_T::DAT0: RESULT Position */ 927 #define EADC_DAT0_RESULT_Msk (0xfffful << EADC_DAT0_RESULT_Pos) /*!< EADC_T::DAT0: RESULT Mask */ 928 929 #define EADC_DAT0_OV_Pos (16) /*!< EADC_T::DAT0: OV Position */ 930 #define EADC_DAT0_OV_Msk (0x1ul << EADC_DAT0_OV_Pos) /*!< EADC_T::DAT0: OV Mask */ 931 932 #define EADC_DAT0_VALID_Pos (17) /*!< EADC_T::DAT0: VALID Position */ 933 #define EADC_DAT0_VALID_Msk (0x1ul << EADC_DAT0_VALID_Pos) /*!< EADC_T::DAT0: VALID Mask */ 934 935 #define EADC_DAT1_RESULT_Pos (0) /*!< EADC_T::DAT1: RESULT Position */ 936 #define EADC_DAT1_RESULT_Msk (0xfffful << EADC_DAT1_RESULT_Pos) /*!< EADC_T::DAT1: RESULT Mask */ 937 938 #define EADC_DAT1_OV_Pos (16) /*!< EADC_T::DAT1: OV Position */ 939 #define EADC_DAT1_OV_Msk (0x1ul << EADC_DAT1_OV_Pos) /*!< EADC_T::DAT1: OV Mask */ 940 941 #define EADC_DAT1_VALID_Pos (17) /*!< EADC_T::DAT1: VALID Position */ 942 #define EADC_DAT1_VALID_Msk (0x1ul << EADC_DAT1_VALID_Pos) /*!< EADC_T::DAT1: VALID Mask */ 943 944 #define EADC_DAT2_RESULT_Pos (0) /*!< EADC_T::DAT2: RESULT Position */ 945 #define EADC_DAT2_RESULT_Msk (0xfffful << EADC_DAT2_RESULT_Pos) /*!< EADC_T::DAT2: RESULT Mask */ 946 947 #define EADC_DAT2_OV_Pos (16) /*!< EADC_T::DAT2: OV Position */ 948 #define EADC_DAT2_OV_Msk (0x1ul << EADC_DAT2_OV_Pos) /*!< EADC_T::DAT2: OV Mask */ 949 950 #define EADC_DAT2_VALID_Pos (17) /*!< EADC_T::DAT2: VALID Position */ 951 #define EADC_DAT2_VALID_Msk (0x1ul << EADC_DAT2_VALID_Pos) /*!< EADC_T::DAT2: VALID Mask */ 952 953 #define EADC_DAT3_RESULT_Pos (0) /*!< EADC_T::DAT3: RESULT Position */ 954 #define EADC_DAT3_RESULT_Msk (0xfffful << EADC_DAT3_RESULT_Pos) /*!< EADC_T::DAT3: RESULT Mask */ 955 956 #define EADC_DAT3_OV_Pos (16) /*!< EADC_T::DAT3: OV Position */ 957 #define EADC_DAT3_OV_Msk (0x1ul << EADC_DAT3_OV_Pos) /*!< EADC_T::DAT3: OV Mask */ 958 959 #define EADC_DAT3_VALID_Pos (17) /*!< EADC_T::DAT3: VALID Position */ 960 #define EADC_DAT3_VALID_Msk (0x1ul << EADC_DAT3_VALID_Pos) /*!< EADC_T::DAT3: VALID Mask */ 961 962 #define EADC_DAT4_RESULT_Pos (0) /*!< EADC_T::DAT4: RESULT Position */ 963 #define EADC_DAT4_RESULT_Msk (0xfffful << EADC_DAT4_RESULT_Pos) /*!< EADC_T::DAT4: RESULT Mask */ 964 965 #define EADC_DAT4_OV_Pos (16) /*!< EADC_T::DAT4: OV Position */ 966 #define EADC_DAT4_OV_Msk (0x1ul << EADC_DAT4_OV_Pos) /*!< EADC_T::DAT4: OV Mask */ 967 968 #define EADC_DAT4_VALID_Pos (17) /*!< EADC_T::DAT4: VALID Position */ 969 #define EADC_DAT4_VALID_Msk (0x1ul << EADC_DAT4_VALID_Pos) /*!< EADC_T::DAT4: VALID Mask */ 970 971 #define EADC_DAT5_RESULT_Pos (0) /*!< EADC_T::DAT5: RESULT Position */ 972 #define EADC_DAT5_RESULT_Msk (0xfffful << EADC_DAT5_RESULT_Pos) /*!< EADC_T::DAT5: RESULT Mask */ 973 974 #define EADC_DAT5_OV_Pos (16) /*!< EADC_T::DAT5: OV Position */ 975 #define EADC_DAT5_OV_Msk (0x1ul << EADC_DAT5_OV_Pos) /*!< EADC_T::DAT5: OV Mask */ 976 977 #define EADC_DAT5_VALID_Pos (17) /*!< EADC_T::DAT5: VALID Position */ 978 #define EADC_DAT5_VALID_Msk (0x1ul << EADC_DAT5_VALID_Pos) /*!< EADC_T::DAT5: VALID Mask */ 979 980 #define EADC_DAT6_RESULT_Pos (0) /*!< EADC_T::DAT6: RESULT Position */ 981 #define EADC_DAT6_RESULT_Msk (0xfffful << EADC_DAT6_RESULT_Pos) /*!< EADC_T::DAT6: RESULT Mask */ 982 983 #define EADC_DAT6_OV_Pos (16) /*!< EADC_T::DAT6: OV Position */ 984 #define EADC_DAT6_OV_Msk (0x1ul << EADC_DAT6_OV_Pos) /*!< EADC_T::DAT6: OV Mask */ 985 986 #define EADC_DAT6_VALID_Pos (17) /*!< EADC_T::DAT6: VALID Position */ 987 #define EADC_DAT6_VALID_Msk (0x1ul << EADC_DAT6_VALID_Pos) /*!< EADC_T::DAT6: VALID Mask */ 988 989 #define EADC_DAT7_RESULT_Pos (0) /*!< EADC_T::DAT7: RESULT Position */ 990 #define EADC_DAT7_RESULT_Msk (0xfffful << EADC_DAT7_RESULT_Pos) /*!< EADC_T::DAT7: RESULT Mask */ 991 992 #define EADC_DAT7_OV_Pos (16) /*!< EADC_T::DAT7: OV Position */ 993 #define EADC_DAT7_OV_Msk (0x1ul << EADC_DAT7_OV_Pos) /*!< EADC_T::DAT7: OV Mask */ 994 995 #define EADC_DAT7_VALID_Pos (17) /*!< EADC_T::DAT7: VALID Position */ 996 #define EADC_DAT7_VALID_Msk (0x1ul << EADC_DAT7_VALID_Pos) /*!< EADC_T::DAT7: VALID Mask */ 997 998 #define EADC_DAT8_RESULT_Pos (0) /*!< EADC_T::DAT8: RESULT Position */ 999 #define EADC_DAT8_RESULT_Msk (0xfffful << EADC_DAT8_RESULT_Pos) /*!< EADC_T::DAT8: RESULT Mask */ 1000 1001 #define EADC_DAT8_OV_Pos (16) /*!< EADC_T::DAT8: OV Position */ 1002 #define EADC_DAT8_OV_Msk (0x1ul << EADC_DAT8_OV_Pos) /*!< EADC_T::DAT8: OV Mask */ 1003 1004 #define EADC_DAT8_VALID_Pos (17) /*!< EADC_T::DAT8: VALID Position */ 1005 #define EADC_DAT8_VALID_Msk (0x1ul << EADC_DAT8_VALID_Pos) /*!< EADC_T::DAT8: VALID Mask */ 1006 1007 #define EADC_DAT9_RESULT_Pos (0) /*!< EADC_T::DAT9: RESULT Position */ 1008 #define EADC_DAT9_RESULT_Msk (0xfffful << EADC_DAT9_RESULT_Pos) /*!< EADC_T::DAT9: RESULT Mask */ 1009 1010 #define EADC_DAT9_OV_Pos (16) /*!< EADC_T::DAT9: OV Position */ 1011 #define EADC_DAT9_OV_Msk (0x1ul << EADC_DAT9_OV_Pos) /*!< EADC_T::DAT9: OV Mask */ 1012 1013 #define EADC_DAT9_VALID_Pos (17) /*!< EADC_T::DAT9: VALID Position */ 1014 #define EADC_DAT9_VALID_Msk (0x1ul << EADC_DAT9_VALID_Pos) /*!< EADC_T::DAT9: VALID Mask */ 1015 1016 #define EADC_DAT10_RESULT_Pos (0) /*!< EADC_T::DAT10: RESULT Position */ 1017 #define EADC_DAT10_RESULT_Msk (0xfffful << EADC_DAT10_RESULT_Pos) /*!< EADC_T::DAT10: RESULT Mask */ 1018 1019 #define EADC_DAT10_OV_Pos (16) /*!< EADC_T::DAT10: OV Position */ 1020 #define EADC_DAT10_OV_Msk (0x1ul << EADC_DAT10_OV_Pos) /*!< EADC_T::DAT10: OV Mask */ 1021 1022 #define EADC_DAT10_VALID_Pos (17) /*!< EADC_T::DAT10: VALID Position */ 1023 #define EADC_DAT10_VALID_Msk (0x1ul << EADC_DAT10_VALID_Pos) /*!< EADC_T::DAT10: VALID Mask */ 1024 1025 #define EADC_DAT11_RESULT_Pos (0) /*!< EADC_T::DAT11: RESULT Position */ 1026 #define EADC_DAT11_RESULT_Msk (0xfffful << EADC_DAT11_RESULT_Pos) /*!< EADC_T::DAT11: RESULT Mask */ 1027 1028 #define EADC_DAT11_OV_Pos (16) /*!< EADC_T::DAT11: OV Position */ 1029 #define EADC_DAT11_OV_Msk (0x1ul << EADC_DAT11_OV_Pos) /*!< EADC_T::DAT11: OV Mask */ 1030 1031 #define EADC_DAT11_VALID_Pos (17) /*!< EADC_T::DAT11: VALID Position */ 1032 #define EADC_DAT11_VALID_Msk (0x1ul << EADC_DAT11_VALID_Pos) /*!< EADC_T::DAT11: VALID Mask */ 1033 1034 #define EADC_DAT12_RESULT_Pos (0) /*!< EADC_T::DAT12: RESULT Position */ 1035 #define EADC_DAT12_RESULT_Msk (0xfffful << EADC_DAT12_RESULT_Pos) /*!< EADC_T::DAT12: RESULT Mask */ 1036 1037 #define EADC_DAT12_OV_Pos (16) /*!< EADC_T::DAT12: OV Position */ 1038 #define EADC_DAT12_OV_Msk (0x1ul << EADC_DAT12_OV_Pos) /*!< EADC_T::DAT12: OV Mask */ 1039 1040 #define EADC_DAT12_VALID_Pos (17) /*!< EADC_T::DAT12: VALID Position */ 1041 #define EADC_DAT12_VALID_Msk (0x1ul << EADC_DAT12_VALID_Pos) /*!< EADC_T::DAT12: VALID Mask */ 1042 1043 #define EADC_DAT13_RESULT_Pos (0) /*!< EADC_T::DAT13: RESULT Position */ 1044 #define EADC_DAT13_RESULT_Msk (0xfffful << EADC_DAT13_RESULT_Pos) /*!< EADC_T::DAT13: RESULT Mask */ 1045 1046 #define EADC_DAT13_OV_Pos (16) /*!< EADC_T::DAT13: OV Position */ 1047 #define EADC_DAT13_OV_Msk (0x1ul << EADC_DAT13_OV_Pos) /*!< EADC_T::DAT13: OV Mask */ 1048 1049 #define EADC_DAT13_VALID_Pos (17) /*!< EADC_T::DAT13: VALID Position */ 1050 #define EADC_DAT13_VALID_Msk (0x1ul << EADC_DAT13_VALID_Pos) /*!< EADC_T::DAT13: VALID Mask */ 1051 1052 #define EADC_DAT14_RESULT_Pos (0) /*!< EADC_T::DAT14: RESULT Position */ 1053 #define EADC_DAT14_RESULT_Msk (0xfffful << EADC_DAT14_RESULT_Pos) /*!< EADC_T::DAT14: RESULT Mask */ 1054 1055 #define EADC_DAT14_OV_Pos (16) /*!< EADC_T::DAT14: OV Position */ 1056 #define EADC_DAT14_OV_Msk (0x1ul << EADC_DAT14_OV_Pos) /*!< EADC_T::DAT14: OV Mask */ 1057 1058 #define EADC_DAT14_VALID_Pos (17) /*!< EADC_T::DAT14: VALID Position */ 1059 #define EADC_DAT14_VALID_Msk (0x1ul << EADC_DAT14_VALID_Pos) /*!< EADC_T::DAT14: VALID Mask */ 1060 1061 #define EADC_DAT15_RESULT_Pos (0) /*!< EADC_T::DAT15: RESULT Position */ 1062 #define EADC_DAT15_RESULT_Msk (0xfffful << EADC_DAT15_RESULT_Pos) /*!< EADC_T::DAT15: RESULT Mask */ 1063 1064 #define EADC_DAT15_OV_Pos (16) /*!< EADC_T::DAT15: OV Position */ 1065 #define EADC_DAT15_OV_Msk (0x1ul << EADC_DAT15_OV_Pos) /*!< EADC_T::DAT15: OV Mask */ 1066 1067 #define EADC_DAT15_VALID_Pos (17) /*!< EADC_T::DAT15: VALID Position */ 1068 #define EADC_DAT15_VALID_Msk (0x1ul << EADC_DAT15_VALID_Pos) /*!< EADC_T::DAT15: VALID Mask */ 1069 1070 #define EADC_DAT16_RESULT_Pos (0) /*!< EADC_T::DAT16: RESULT Position */ 1071 #define EADC_DAT16_RESULT_Msk (0xfffful << EADC_DAT16_RESULT_Pos) /*!< EADC_T::DAT16: RESULT Mask */ 1072 1073 #define EADC_DAT16_OV_Pos (16) /*!< EADC_T::DAT16: OV Position */ 1074 #define EADC_DAT16_OV_Msk (0x1ul << EADC_DAT16_OV_Pos) /*!< EADC_T::DAT16: OV Mask */ 1075 1076 #define EADC_DAT16_VALID_Pos (17) /*!< EADC_T::DAT16: VALID Position */ 1077 #define EADC_DAT16_VALID_Msk (0x1ul << EADC_DAT16_VALID_Pos) /*!< EADC_T::DAT16: VALID Mask */ 1078 1079 #define EADC_DAT17_RESULT_Pos (0) /*!< EADC_T::DAT17: RESULT Position */ 1080 #define EADC_DAT17_RESULT_Msk (0xfffful << EADC_DAT17_RESULT_Pos) /*!< EADC_T::DAT17: RESULT Mask */ 1081 1082 #define EADC_DAT17_OV_Pos (16) /*!< EADC_T::DAT17: OV Position */ 1083 #define EADC_DAT17_OV_Msk (0x1ul << EADC_DAT17_OV_Pos) /*!< EADC_T::DAT17: OV Mask */ 1084 1085 #define EADC_DAT17_VALID_Pos (17) /*!< EADC_T::DAT17: VALID Position */ 1086 #define EADC_DAT17_VALID_Msk (0x1ul << EADC_DAT17_VALID_Pos) /*!< EADC_T::DAT17: VALID Mask */ 1087 1088 #define EADC_DAT18_RESULT_Pos (0) /*!< EADC_T::DAT18: RESULT Position */ 1089 #define EADC_DAT18_RESULT_Msk (0xfffful << EADC_DAT18_RESULT_Pos) /*!< EADC_T::DAT18: RESULT Mask */ 1090 1091 #define EADC_DAT18_OV_Pos (16) /*!< EADC_T::DAT18: OV Position */ 1092 #define EADC_DAT18_OV_Msk (0x1ul << EADC_DAT18_OV_Pos) /*!< EADC_T::DAT18: OV Mask */ 1093 1094 #define EADC_DAT18_VALID_Pos (17) /*!< EADC_T::DAT18: VALID Position */ 1095 #define EADC_DAT18_VALID_Msk (0x1ul << EADC_DAT18_VALID_Pos) /*!< EADC_T::DAT18: VALID Mask */ 1096 1097 #define EADC_CURDAT_CURDAT_Pos (0) /*!< EADC_T::CURDAT: CURDAT Position */ 1098 #define EADC_CURDAT_CURDAT_Msk (0x7ffffffful << EADC_CURDAT_CURDAT_Pos) /*!< EADC_T::CURDAT: CURDAT Mask */ 1099 1100 #define EADC_CTL_ADCEN_Pos (0) /*!< EADC_T::CTL: ADCEN Position */ 1101 #define EADC_CTL_ADCEN_Msk (0x1ul << EADC_CTL_ADCEN_Pos) /*!< EADC_T::CTL: ADCEN Mask */ 1102 1103 #define EADC_CTL_ADCRST_Pos (1) /*!< EADC_T::CTL: ADCRST Position */ 1104 #define EADC_CTL_ADCRST_Msk (0x1ul << EADC_CTL_ADCRST_Pos) /*!< EADC_T::CTL: ADCRST Mask */ 1105 1106 #define EADC_CTL_ADCIEN0_Pos (2) /*!< EADC_T::CTL: ADCIEN0 Position */ 1107 #define EADC_CTL_ADCIEN0_Msk (0x1ul << EADC_CTL_ADCIEN0_Pos) /*!< EADC_T::CTL: ADCIEN0 Mask */ 1108 1109 #define EADC_CTL_ADCIEN1_Pos (3) /*!< EADC_T::CTL: ADCIEN1 Position */ 1110 #define EADC_CTL_ADCIEN1_Msk (0x1ul << EADC_CTL_ADCIEN1_Pos) /*!< EADC_T::CTL: ADCIEN1 Mask */ 1111 1112 #define EADC_CTL_ADCIEN2_Pos (4) /*!< EADC_T::CTL: ADCIEN2 Position */ 1113 #define EADC_CTL_ADCIEN2_Msk (0x1ul << EADC_CTL_ADCIEN2_Pos) /*!< EADC_T::CTL: ADCIEN2 Mask */ 1114 1115 #define EADC_CTL_ADCIEN3_Pos (5) /*!< EADC_T::CTL: ADCIEN3 Position */ 1116 #define EADC_CTL_ADCIEN3_Msk (0x1ul << EADC_CTL_ADCIEN3_Pos) /*!< EADC_T::CTL: ADCIEN3 Mask */ 1117 1118 #define EADC_CTL_DIFFEN_Pos (8) /*!< EADC_T::CTL: DIFFEN Position */ 1119 #define EADC_CTL_DIFFEN_Msk (0x1ul << EADC_CTL_DIFFEN_Pos) /*!< EADC_T::CTL: DIFFEN Mask */ 1120 1121 #define EADC_CTL_DMOF_Pos (9) /*!< EADC_T::CTL: DMOF Position */ 1122 #define EADC_CTL_DMOF_Msk (0x1ul << EADC_CTL_DMOF_Pos) /*!< EADC_T::CTL: DMOF Mask */ 1123 1124 #define EADC_CTL_INTDELAY0_Pos (16) /*!< EADC_T::CTL: INTDELAY0 Position */ 1125 #define EADC_CTL_INTDELAY0_Msk (0xful << EADC_CTL_INTDELAY0_Pos) /*!< EADC_T::CTL: INTDELAY0 Mask */ 1126 1127 #define EADC_CTL_INTDELAY1_Pos (20) /*!< EADC_T::CTL: INTDELAY1 Position */ 1128 #define EADC_CTL_INTDELAY1_Msk (0xful << EADC_CTL_INTDELAY1_Pos) /*!< EADC_T::CTL: INTDELAY1 Mask */ 1129 1130 #define EADC_CTL_INTDELAY2_Pos (24) /*!< EADC_T::CTL: INTDELAY2 Position */ 1131 #define EADC_CTL_INTDELAY2_Msk (0xful << EADC_CTL_INTDELAY2_Pos) /*!< EADC_T::CTL: INTDELAY2 Mask */ 1132 1133 #define EADC_CTL_INTDELAY3_Pos (28) /*!< EADC_T::CTL: INTDELAY3 Position */ 1134 #define EADC_CTL_INTDELAY3_Msk (0xful << EADC_CTL_INTDELAY3_Pos) /*!< EADC_T::CTL: INTDELAY3 Mask */ 1135 1136 #define EADC_SWTRG_SWTRG_Pos (0) /*!< EADC_T::SWTRG: SWTRG Position */ 1137 #define EADC_SWTRG_SWTRG_Msk (0x7ffffffful << EADC_SWTRG_SWTRG_Pos) /*!< EADC_T::SWTRG: SWTRG Mask */ 1138 1139 #define EADC_PENDSTS_STPF_Pos (0) /*!< EADC_T::PENDSTS: STPF Position */ 1140 #define EADC_PENDSTS_STPF_Msk (0x7ffffffful << EADC_PENDSTS_STPF_Pos) /*!< EADC_T::PENDSTS: STPF Mask */ 1141 1142 #define EADC_OVSTS_SPOVF_Pos (0) /*!< EADC_T::OVSTS: SPOVF Position */ 1143 #define EADC_OVSTS_SPOVF_Msk (0x7ffffffful << EADC_OVSTS_SPOVF_Pos) /*!< EADC_T::OVSTS: SPOVF Mask */ 1144 1145 #define EADC_CTL1_PRECHEN_Pos (0) /*!< EADC_T::CTL1: PRECHEN Position */ 1146 #define EADC_CTL1_PRECHEN_Msk (0x1ul << EADC_CTL1_PRECHEN_Pos) /*!< EADC_T::CTL1: PRECHEN Mask */ 1147 1148 #define EADC_CTL1_DISCHEN_Pos (1) /*!< EADC_T::CTL1: DISCHEN Position */ 1149 #define EADC_CTL1_DISCHEN_Msk (0x1ul << EADC_CTL1_DISCHEN_Pos) /*!< EADC_T::CTL1: DISCHEN Mask */ 1150 1151 #define EADC_CTL1_RESSEL_Pos (4) /*!< EADC_T::CTL1: RESSEL Position */ 1152 #define EADC_CTL1_RESSEL_Msk (0x3ul << EADC_CTL1_RESSEL_Pos) /*!< EADC_T::CTL1: RESSEL Mask */ 1153 1154 #define EADC_CTL1_FDETCHEN_Pos (8) /*!< EADC_T::CTL1: FDETCHEN Position */ 1155 #define EADC_CTL1_FDETCHEN_Msk (0x1ul << EADC_CTL1_FDETCHEN_Pos) /*!< EADC_T::CTL1: FDETCHEN Mask */ 1156 1157 #define EADC_CTL1_CMP0TRG_Pos (20) /*!< EADC_T::CTL1: CMP0TRG Position */ 1158 #define EADC_CTL1_CMP0TRG_Msk (0x1ul << EADC_CTL1_CMP0TRG_Pos) /*!< EADC_T::CTL1: CMP0TRG Mask */ 1159 1160 #define EADC_CTL1_CMP1TRG_Pos (21) /*!< EADC_T::CTL1: CMP1TRG Position */ 1161 #define EADC_CTL1_CMP1TRG_Msk (0x1ul << EADC_CTL1_CMP1TRG_Pos) /*!< EADC_T::CTL1: CMP1TRG Mask */ 1162 1163 #define EADC_CTL1_CMP2TRG_Pos (22) /*!< EADC_T::CTL1: CMP2TRG Position */ 1164 #define EADC_CTL1_CMP2TRG_Msk (0x1ul << EADC_CTL1_CMP2TRG_Pos) /*!< EADC_T::CTL1: CMP2TRG Mask */ 1165 1166 #define EADC_CTL1_CMP3TRG_Pos (23) /*!< EADC_T::CTL1: CMP3TRG Position */ 1167 #define EADC_CTL1_CMP3TRG_Msk (0x1ul << EADC_CTL1_CMP3TRG_Pos) /*!< EADC_T::CTL1: CMP3TRG Mask */ 1168 1169 #define EADC_SCTL_CHSEL_Pos (0) /*!< EADC_T::SCTL: CHSEL Position */ 1170 #define EADC_SCTL_CHSEL_Msk (0x1ful << EADC_SCTL_CHSEL_Pos) /*!< EADC_T::SCTL: CHSEL Mask */ 1171 1172 #define EADC_SCTL_INTPOS_Pos (5) /*!< EADC_T::SCTL: INTPOS Position */ 1173 #define EADC_SCTL_INTPOS_Msk (0x1ul << EADC_SCTL_INTPOS_Pos) /*!< EADC_T::SCTL: INTPOS Mask */ 1174 1175 #define EADC_SCTL_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL: TRGDLYDIV Position */ 1176 #define EADC_SCTL_TRGDLYDIV_Msk (0x3ul << EADC_SCTL_TRGDLYDIV_Pos) /*!< EADC_T::SCTL: TRGDLYDIV Mask */ 1177 1178 #define EADC_SCTL_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL: TRGDLYCNT Position */ 1179 #define EADC_SCTL_TRGDLYCNT_Msk (0xfful << EADC_SCTL_TRGDLYCNT_Pos) /*!< EADC_T::SCTL: TRGDLYCNT Mask */ 1180 1181 #define EADC_SCTL_TRGSEL_Pos (16) /*!< EADC_T::SCTL: TRGSEL Position */ 1182 #define EADC_SCTL_TRGSEL_Msk (0x3ful << EADC_SCTL_TRGSEL_Pos) /*!< EADC_T::SCTL: TRGSEL Mask */ 1183 1184 #define EADC_SCTL_EXTREN_Pos (22) /*!< EADC_T::SCTL: EXTREN Position */ 1185 #define EADC_SCTL_EXTREN_Msk (0x1ul << EADC_SCTL_EXTREN_Pos) /*!< EADC_T::SCTL: EXTREN Mask */ 1186 1187 #define EADC_SCTL_EXTFEN_Pos (23) /*!< EADC_T::SCTL: EXTFEN Position */ 1188 #define EADC_SCTL_EXTFEN_Msk (0x1ul << EADC_SCTL_EXTFEN_Pos) /*!< EADC_T::SCTL: EXTFEN Mask */ 1189 1190 #define EADC_SCTL_EXTSMPT_Pos (24) /*!< EADC_T::SCTL: EXTSMPT Position */ 1191 #define EADC_SCTL_EXTSMPT_Msk (0xfful << EADC_SCTL_EXTSMPT_Pos) /*!< EADC_T::SCTL: EXTSMPT Mask */ 1192 1193 #define EADC_SCTL0_CHSEL_Pos (0) /*!< EADC_T::SCTL0: CHSEL Position */ 1194 #define EADC_SCTL0_CHSEL_Msk (0x1ful << EADC_SCTL0_CHSEL_Pos) /*!< EADC_T::SCTL0: CHSEL Mask */ 1195 1196 #define EADC_SCTL0_INTPOS_Pos (5) /*!< EADC_T::SCTL0: INTPOS Position */ 1197 #define EADC_SCTL0_INTPOS_Msk (0x1ul << EADC_SCTL0_INTPOS_Pos) /*!< EADC_T::SCTL0: INTPOS Mask */ 1198 1199 #define EADC_SCTL0_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL0: TRGDLYDIV Position */ 1200 #define EADC_SCTL0_TRGDLYDIV_Msk (0x3ul << EADC_SCTL0_TRGDLYDIV_Pos) /*!< EADC_T::SCTL0: TRGDLYDIV Mask */ 1201 1202 #define EADC_SCTL0_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL0: TRGDLYCNT Position */ 1203 #define EADC_SCTL0_TRGDLYCNT_Msk (0xfful << EADC_SCTL0_TRGDLYCNT_Pos) /*!< EADC_T::SCTL0: TRGDLYCNT Mask */ 1204 1205 #define EADC_SCTL0_TRGSEL_Pos (16) /*!< EADC_T::SCTL0: TRGSEL Position */ 1206 #define EADC_SCTL0_TRGSEL_Msk (0x3ful << EADC_SCTL0_TRGSEL_Pos) /*!< EADC_T::SCTL0: TRGSEL Mask */ 1207 1208 #define EADC_SCTL0_EXTREN_Pos (22) /*!< EADC_T::SCTL0: EXTREN Position */ 1209 #define EADC_SCTL0_EXTREN_Msk (0x1ul << EADC_SCTL0_EXTREN_Pos) /*!< EADC_T::SCTL0: EXTREN Mask */ 1210 1211 #define EADC_SCTL0_EXTFEN_Pos (23) /*!< EADC_T::SCTL0: EXTFEN Position */ 1212 #define EADC_SCTL0_EXTFEN_Msk (0x1ul << EADC_SCTL0_EXTFEN_Pos) /*!< EADC_T::SCTL0: EXTFEN Mask */ 1213 1214 #define EADC_SCTL0_EXTSMPT_Pos (24) /*!< EADC_T::SCTL0: EXTSMPT Position */ 1215 #define EADC_SCTL0_EXTSMPT_Msk (0xfful << EADC_SCTL0_EXTSMPT_Pos) /*!< EADC_T::SCTL0: EXTSMPT Mask */ 1216 1217 #define EADC_SCTL1_CHSEL_Pos (0) /*!< EADC_T::SCTL1: CHSEL Position */ 1218 #define EADC_SCTL1_CHSEL_Msk (0x1ful << EADC_SCTL1_CHSEL_Pos) /*!< EADC_T::SCTL1: CHSEL Mask */ 1219 1220 #define EADC_SCTL1_INTPOS_Pos (5) /*!< EADC_T::SCTL1: INTPOS Position */ 1221 #define EADC_SCTL1_INTPOS_Msk (0x1ul << EADC_SCTL1_INTPOS_Pos) /*!< EADC_T::SCTL1: INTPOS Mask */ 1222 1223 #define EADC_SCTL1_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL1: TRGDLYDIV Position */ 1224 #define EADC_SCTL1_TRGDLYDIV_Msk (0x3ul << EADC_SCTL1_TRGDLYDIV_Pos) /*!< EADC_T::SCTL1: TRGDLYDIV Mask */ 1225 1226 #define EADC_SCTL1_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL1: TRGDLYCNT Position */ 1227 #define EADC_SCTL1_TRGDLYCNT_Msk (0xfful << EADC_SCTL1_TRGDLYCNT_Pos) /*!< EADC_T::SCTL1: TRGDLYCNT Mask */ 1228 1229 #define EADC_SCTL1_TRGSEL_Pos (16) /*!< EADC_T::SCTL1: TRGSEL Position */ 1230 #define EADC_SCTL1_TRGSEL_Msk (0x3ful << EADC_SCTL1_TRGSEL_Pos) /*!< EADC_T::SCTL1: TRGSEL Mask */ 1231 1232 #define EADC_SCTL1_EXTREN_Pos (22) /*!< EADC_T::SCTL1: EXTREN Position */ 1233 #define EADC_SCTL1_EXTREN_Msk (0x1ul << EADC_SCTL1_EXTREN_Pos) /*!< EADC_T::SCTL1: EXTREN Mask */ 1234 1235 #define EADC_SCTL1_EXTFEN_Pos (23) /*!< EADC_T::SCTL1: EXTFEN Position */ 1236 #define EADC_SCTL1_EXTFEN_Msk (0x1ul << EADC_SCTL1_EXTFEN_Pos) /*!< EADC_T::SCTL1: EXTFEN Mask */ 1237 1238 #define EADC_SCTL1_EXTSMPT_Pos (24) /*!< EADC_T::SCTL1: EXTSMPT Position */ 1239 #define EADC_SCTL1_EXTSMPT_Msk (0xfful << EADC_SCTL1_EXTSMPT_Pos) /*!< EADC_T::SCTL1: EXTSMPT Mask */ 1240 1241 #define EADC_SCTL2_CHSEL_Pos (0) /*!< EADC_T::SCTL2: CHSEL Position */ 1242 #define EADC_SCTL2_CHSEL_Msk (0x1ful << EADC_SCTL2_CHSEL_Pos) /*!< EADC_T::SCTL2: CHSEL Mask */ 1243 1244 #define EADC_SCTL2_INTPOS_Pos (5) /*!< EADC_T::SCTL2: INTPOS Position */ 1245 #define EADC_SCTL2_INTPOS_Msk (0x1ul << EADC_SCTL2_INTPOS_Pos) /*!< EADC_T::SCTL2: INTPOS Mask */ 1246 1247 #define EADC_SCTL2_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL2: TRGDLYDIV Position */ 1248 #define EADC_SCTL2_TRGDLYDIV_Msk (0x3ul << EADC_SCTL2_TRGDLYDIV_Pos) /*!< EADC_T::SCTL2: TRGDLYDIV Mask */ 1249 1250 #define EADC_SCTL2_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL2: TRGDLYCNT Position */ 1251 #define EADC_SCTL2_TRGDLYCNT_Msk (0xfful << EADC_SCTL2_TRGDLYCNT_Pos) /*!< EADC_T::SCTL2: TRGDLYCNT Mask */ 1252 1253 #define EADC_SCTL2_TRGSEL_Pos (16) /*!< EADC_T::SCTL2: TRGSEL Position */ 1254 #define EADC_SCTL2_TRGSEL_Msk (0x3ful << EADC_SCTL2_TRGSEL_Pos) /*!< EADC_T::SCTL2: TRGSEL Mask */ 1255 1256 #define EADC_SCTL2_EXTREN_Pos (22) /*!< EADC_T::SCTL2: EXTREN Position */ 1257 #define EADC_SCTL2_EXTREN_Msk (0x1ul << EADC_SCTL2_EXTREN_Pos) /*!< EADC_T::SCTL2: EXTREN Mask */ 1258 1259 #define EADC_SCTL2_EXTFEN_Pos (23) /*!< EADC_T::SCTL2: EXTFEN Position */ 1260 #define EADC_SCTL2_EXTFEN_Msk (0x1ul << EADC_SCTL2_EXTFEN_Pos) /*!< EADC_T::SCTL2: EXTFEN Mask */ 1261 1262 #define EADC_SCTL2_EXTSMPT_Pos (24) /*!< EADC_T::SCTL2: EXTSMPT Position */ 1263 #define EADC_SCTL2_EXTSMPT_Msk (0xfful << EADC_SCTL2_EXTSMPT_Pos) /*!< EADC_T::SCTL2: EXTSMPT Mask */ 1264 1265 #define EADC_SCTL3_CHSEL_Pos (0) /*!< EADC_T::SCTL3: CHSEL Position */ 1266 #define EADC_SCTL3_CHSEL_Msk (0x1ful << EADC_SCTL3_CHSEL_Pos) /*!< EADC_T::SCTL3: CHSEL Mask */ 1267 1268 #define EADC_SCTL3_INTPOS_Pos (5) /*!< EADC_T::SCTL3: INTPOS Position */ 1269 #define EADC_SCTL3_INTPOS_Msk (0x1ul << EADC_SCTL3_INTPOS_Pos) /*!< EADC_T::SCTL3: INTPOS Mask */ 1270 1271 #define EADC_SCTL3_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL3: TRGDLYDIV Position */ 1272 #define EADC_SCTL3_TRGDLYDIV_Msk (0x3ul << EADC_SCTL3_TRGDLYDIV_Pos) /*!< EADC_T::SCTL3: TRGDLYDIV Mask */ 1273 1274 #define EADC_SCTL3_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL3: TRGDLYCNT Position */ 1275 #define EADC_SCTL3_TRGDLYCNT_Msk (0xfful << EADC_SCTL3_TRGDLYCNT_Pos) /*!< EADC_T::SCTL3: TRGDLYCNT Mask */ 1276 1277 #define EADC_SCTL3_TRGSEL_Pos (16) /*!< EADC_T::SCTL3: TRGSEL Position */ 1278 #define EADC_SCTL3_TRGSEL_Msk (0x3ful << EADC_SCTL3_TRGSEL_Pos) /*!< EADC_T::SCTL3: TRGSEL Mask */ 1279 1280 #define EADC_SCTL3_EXTREN_Pos (22) /*!< EADC_T::SCTL3: EXTREN Position */ 1281 #define EADC_SCTL3_EXTREN_Msk (0x1ul << EADC_SCTL3_EXTREN_Pos) /*!< EADC_T::SCTL3: EXTREN Mask */ 1282 1283 #define EADC_SCTL3_EXTFEN_Pos (23) /*!< EADC_T::SCTL3: EXTFEN Position */ 1284 #define EADC_SCTL3_EXTFEN_Msk (0x1ul << EADC_SCTL3_EXTFEN_Pos) /*!< EADC_T::SCTL3: EXTFEN Mask */ 1285 1286 #define EADC_SCTL3_EXTSMPT_Pos (24) /*!< EADC_T::SCTL3: EXTSMPT Position */ 1287 #define EADC_SCTL3_EXTSMPT_Msk (0xfful << EADC_SCTL3_EXTSMPT_Pos) /*!< EADC_T::SCTL3: EXTSMPT Mask */ 1288 1289 #define EADC_SCTL4_CHSEL_Pos (0) /*!< EADC_T::SCTL4: CHSEL Position */ 1290 #define EADC_SCTL4_CHSEL_Msk (0x1ful << EADC_SCTL4_CHSEL_Pos) /*!< EADC_T::SCTL4: CHSEL Mask */ 1291 1292 #define EADC_SCTL4_INTPOS_Pos (5) /*!< EADC_T::SCTL4: INTPOS Position */ 1293 #define EADC_SCTL4_INTPOS_Msk (0x1ul << EADC_SCTL4_INTPOS_Pos) /*!< EADC_T::SCTL4: INTPOS Mask */ 1294 1295 #define EADC_SCTL4_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL4: TRGDLYDIV Position */ 1296 #define EADC_SCTL4_TRGDLYDIV_Msk (0x3ul << EADC_SCTL4_TRGDLYDIV_Pos) /*!< EADC_T::SCTL4: TRGDLYDIV Mask */ 1297 1298 #define EADC_SCTL4_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL4: TRGDLYCNT Position */ 1299 #define EADC_SCTL4_TRGDLYCNT_Msk (0xfful << EADC_SCTL4_TRGDLYCNT_Pos) /*!< EADC_T::SCTL4: TRGDLYCNT Mask */ 1300 1301 #define EADC_SCTL4_TRGSEL_Pos (16) /*!< EADC_T::SCTL4: TRGSEL Position */ 1302 #define EADC_SCTL4_TRGSEL_Msk (0x3ful << EADC_SCTL4_TRGSEL_Pos) /*!< EADC_T::SCTL4: TRGSEL Mask */ 1303 1304 #define EADC_SCTL4_EXTREN_Pos (22) /*!< EADC_T::SCTL4: EXTREN Position */ 1305 #define EADC_SCTL4_EXTREN_Msk (0x1ul << EADC_SCTL4_EXTREN_Pos) /*!< EADC_T::SCTL4: EXTREN Mask */ 1306 1307 #define EADC_SCTL4_EXTFEN_Pos (23) /*!< EADC_T::SCTL4: EXTFEN Position */ 1308 #define EADC_SCTL4_EXTFEN_Msk (0x1ul << EADC_SCTL4_EXTFEN_Pos) /*!< EADC_T::SCTL4: EXTFEN Mask */ 1309 1310 #define EADC_SCTL4_EXTSMPT_Pos (24) /*!< EADC_T::SCTL4: EXTSMPT Position */ 1311 #define EADC_SCTL4_EXTSMPT_Msk (0xfful << EADC_SCTL4_EXTSMPT_Pos) /*!< EADC_T::SCTL4: EXTSMPT Mask */ 1312 1313 #define EADC_SCTL5_CHSEL_Pos (0) /*!< EADC_T::SCTL5: CHSEL Position */ 1314 #define EADC_SCTL5_CHSEL_Msk (0x1ful << EADC_SCTL5_CHSEL_Pos) /*!< EADC_T::SCTL5: CHSEL Mask */ 1315 1316 #define EADC_SCTL5_INTPOS_Pos (5) /*!< EADC_T::SCTL5: INTPOS Position */ 1317 #define EADC_SCTL5_INTPOS_Msk (0x1ul << EADC_SCTL5_INTPOS_Pos) /*!< EADC_T::SCTL5: INTPOS Mask */ 1318 1319 #define EADC_SCTL5_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL5: TRGDLYDIV Position */ 1320 #define EADC_SCTL5_TRGDLYDIV_Msk (0x3ul << EADC_SCTL5_TRGDLYDIV_Pos) /*!< EADC_T::SCTL5: TRGDLYDIV Mask */ 1321 1322 #define EADC_SCTL5_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL5: TRGDLYCNT Position */ 1323 #define EADC_SCTL5_TRGDLYCNT_Msk (0xfful << EADC_SCTL5_TRGDLYCNT_Pos) /*!< EADC_T::SCTL5: TRGDLYCNT Mask */ 1324 1325 #define EADC_SCTL5_TRGSEL_Pos (16) /*!< EADC_T::SCTL5: TRGSEL Position */ 1326 #define EADC_SCTL5_TRGSEL_Msk (0x3ful << EADC_SCTL5_TRGSEL_Pos) /*!< EADC_T::SCTL5: TRGSEL Mask */ 1327 1328 #define EADC_SCTL5_EXTREN_Pos (22) /*!< EADC_T::SCTL5: EXTREN Position */ 1329 #define EADC_SCTL5_EXTREN_Msk (0x1ul << EADC_SCTL5_EXTREN_Pos) /*!< EADC_T::SCTL5: EXTREN Mask */ 1330 1331 #define EADC_SCTL5_EXTFEN_Pos (23) /*!< EADC_T::SCTL5: EXTFEN Position */ 1332 #define EADC_SCTL5_EXTFEN_Msk (0x1ul << EADC_SCTL5_EXTFEN_Pos) /*!< EADC_T::SCTL5: EXTFEN Mask */ 1333 1334 #define EADC_SCTL5_EXTSMPT_Pos (24) /*!< EADC_T::SCTL5: EXTSMPT Position */ 1335 #define EADC_SCTL5_EXTSMPT_Msk (0xfful << EADC_SCTL5_EXTSMPT_Pos) /*!< EADC_T::SCTL5: EXTSMPT Mask */ 1336 1337 #define EADC_SCTL6_CHSEL_Pos (0) /*!< EADC_T::SCTL6: CHSEL Position */ 1338 #define EADC_SCTL6_CHSEL_Msk (0x1ful << EADC_SCTL6_CHSEL_Pos) /*!< EADC_T::SCTL6: CHSEL Mask */ 1339 1340 #define EADC_SCTL6_INTPOS_Pos (5) /*!< EADC_T::SCTL6: INTPOS Position */ 1341 #define EADC_SCTL6_INTPOS_Msk (0x1ul << EADC_SCTL6_INTPOS_Pos) /*!< EADC_T::SCTL6: INTPOS Mask */ 1342 1343 #define EADC_SCTL6_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL6: TRGDLYDIV Position */ 1344 #define EADC_SCTL6_TRGDLYDIV_Msk (0x3ul << EADC_SCTL6_TRGDLYDIV_Pos) /*!< EADC_T::SCTL6: TRGDLYDIV Mask */ 1345 1346 #define EADC_SCTL6_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL6: TRGDLYCNT Position */ 1347 #define EADC_SCTL6_TRGDLYCNT_Msk (0xfful << EADC_SCTL6_TRGDLYCNT_Pos) /*!< EADC_T::SCTL6: TRGDLYCNT Mask */ 1348 1349 #define EADC_SCTL6_TRGSEL_Pos (16) /*!< EADC_T::SCTL6: TRGSEL Position */ 1350 #define EADC_SCTL6_TRGSEL_Msk (0x3ful << EADC_SCTL6_TRGSEL_Pos) /*!< EADC_T::SCTL6: TRGSEL Mask */ 1351 1352 #define EADC_SCTL6_EXTREN_Pos (22) /*!< EADC_T::SCTL6: EXTREN Position */ 1353 #define EADC_SCTL6_EXTREN_Msk (0x1ul << EADC_SCTL6_EXTREN_Pos) /*!< EADC_T::SCTL6: EXTREN Mask */ 1354 1355 #define EADC_SCTL6_EXTFEN_Pos (23) /*!< EADC_T::SCTL6: EXTFEN Position */ 1356 #define EADC_SCTL6_EXTFEN_Msk (0x1ul << EADC_SCTL6_EXTFEN_Pos) /*!< EADC_T::SCTL6: EXTFEN Mask */ 1357 1358 #define EADC_SCTL6_EXTSMPT_Pos (24) /*!< EADC_T::SCTL6: EXTSMPT Position */ 1359 #define EADC_SCTL6_EXTSMPT_Msk (0xfful << EADC_SCTL6_EXTSMPT_Pos) /*!< EADC_T::SCTL6: EXTSMPT Mask */ 1360 1361 #define EADC_SCTL7_CHSEL_Pos (0) /*!< EADC_T::SCTL7: CHSEL Position */ 1362 #define EADC_SCTL7_CHSEL_Msk (0x1ful << EADC_SCTL7_CHSEL_Pos) /*!< EADC_T::SCTL7: CHSEL Mask */ 1363 1364 #define EADC_SCTL7_INTPOS_Pos (5) /*!< EADC_T::SCTL7: INTPOS Position */ 1365 #define EADC_SCTL7_INTPOS_Msk (0x1ul << EADC_SCTL7_INTPOS_Pos) /*!< EADC_T::SCTL7: INTPOS Mask */ 1366 1367 #define EADC_SCTL7_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL7: TRGDLYDIV Position */ 1368 #define EADC_SCTL7_TRGDLYDIV_Msk (0x3ul << EADC_SCTL7_TRGDLYDIV_Pos) /*!< EADC_T::SCTL7: TRGDLYDIV Mask */ 1369 1370 #define EADC_SCTL7_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL7: TRGDLYCNT Position */ 1371 #define EADC_SCTL7_TRGDLYCNT_Msk (0xfful << EADC_SCTL7_TRGDLYCNT_Pos) /*!< EADC_T::SCTL7: TRGDLYCNT Mask */ 1372 1373 #define EADC_SCTL7_TRGSEL_Pos (16) /*!< EADC_T::SCTL7: TRGSEL Position */ 1374 #define EADC_SCTL7_TRGSEL_Msk (0x3ful << EADC_SCTL7_TRGSEL_Pos) /*!< EADC_T::SCTL7: TRGSEL Mask */ 1375 1376 #define EADC_SCTL7_EXTREN_Pos (22) /*!< EADC_T::SCTL7: EXTREN Position */ 1377 #define EADC_SCTL7_EXTREN_Msk (0x1ul << EADC_SCTL7_EXTREN_Pos) /*!< EADC_T::SCTL7: EXTREN Mask */ 1378 1379 #define EADC_SCTL7_EXTFEN_Pos (23) /*!< EADC_T::SCTL7: EXTFEN Position */ 1380 #define EADC_SCTL7_EXTFEN_Msk (0x1ul << EADC_SCTL7_EXTFEN_Pos) /*!< EADC_T::SCTL7: EXTFEN Mask */ 1381 1382 #define EADC_SCTL7_EXTSMPT_Pos (24) /*!< EADC_T::SCTL7: EXTSMPT Position */ 1383 #define EADC_SCTL7_EXTSMPT_Msk (0xfful << EADC_SCTL7_EXTSMPT_Pos) /*!< EADC_T::SCTL7: EXTSMPT Mask */ 1384 1385 #define EADC_SCTL8_CHSEL_Pos (0) /*!< EADC_T::SCTL8: CHSEL Position */ 1386 #define EADC_SCTL8_CHSEL_Msk (0x1ful << EADC_SCTL8_CHSEL_Pos) /*!< EADC_T::SCTL8: CHSEL Mask */ 1387 1388 #define EADC_SCTL8_INTPOS_Pos (5) /*!< EADC_T::SCTL8: INTPOS Position */ 1389 #define EADC_SCTL8_INTPOS_Msk (0x1ul << EADC_SCTL8_INTPOS_Pos) /*!< EADC_T::SCTL8: INTPOS Mask */ 1390 1391 #define EADC_SCTL8_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL8: TRGDLYDIV Position */ 1392 #define EADC_SCTL8_TRGDLYDIV_Msk (0x3ul << EADC_SCTL8_TRGDLYDIV_Pos) /*!< EADC_T::SCTL8: TRGDLYDIV Mask */ 1393 1394 #define EADC_SCTL8_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL8: TRGDLYCNT Position */ 1395 #define EADC_SCTL8_TRGDLYCNT_Msk (0xfful << EADC_SCTL8_TRGDLYCNT_Pos) /*!< EADC_T::SCTL8: TRGDLYCNT Mask */ 1396 1397 #define EADC_SCTL8_TRGSEL_Pos (16) /*!< EADC_T::SCTL8: TRGSEL Position */ 1398 #define EADC_SCTL8_TRGSEL_Msk (0x3ful << EADC_SCTL8_TRGSEL_Pos) /*!< EADC_T::SCTL8: TRGSEL Mask */ 1399 1400 #define EADC_SCTL8_EXTREN_Pos (22) /*!< EADC_T::SCTL8: EXTREN Position */ 1401 #define EADC_SCTL8_EXTREN_Msk (0x1ul << EADC_SCTL8_EXTREN_Pos) /*!< EADC_T::SCTL8: EXTREN Mask */ 1402 1403 #define EADC_SCTL8_EXTFEN_Pos (23) /*!< EADC_T::SCTL8: EXTFEN Position */ 1404 #define EADC_SCTL8_EXTFEN_Msk (0x1ul << EADC_SCTL8_EXTFEN_Pos) /*!< EADC_T::SCTL8: EXTFEN Mask */ 1405 1406 #define EADC_SCTL8_EXTSMPT_Pos (24) /*!< EADC_T::SCTL8: EXTSMPT Position */ 1407 #define EADC_SCTL8_EXTSMPT_Msk (0xfful << EADC_SCTL8_EXTSMPT_Pos) /*!< EADC_T::SCTL8: EXTSMPT Mask */ 1408 1409 #define EADC_SCTL9_CHSEL_Pos (0) /*!< EADC_T::SCTL9: CHSEL Position */ 1410 #define EADC_SCTL9_CHSEL_Msk (0x1ful << EADC_SCTL9_CHSEL_Pos) /*!< EADC_T::SCTL9: CHSEL Mask */ 1411 1412 #define EADC_SCTL9_INTPOS_Pos (5) /*!< EADC_T::SCTL9: INTPOS Position */ 1413 #define EADC_SCTL9_INTPOS_Msk (0x1ul << EADC_SCTL9_INTPOS_Pos) /*!< EADC_T::SCTL9: INTPOS Mask */ 1414 1415 #define EADC_SCTL9_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL9: TRGDLYDIV Position */ 1416 #define EADC_SCTL9_TRGDLYDIV_Msk (0x3ul << EADC_SCTL9_TRGDLYDIV_Pos) /*!< EADC_T::SCTL9: TRGDLYDIV Mask */ 1417 1418 #define EADC_SCTL9_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL9: TRGDLYCNT Position */ 1419 #define EADC_SCTL9_TRGDLYCNT_Msk (0xfful << EADC_SCTL9_TRGDLYCNT_Pos) /*!< EADC_T::SCTL9: TRGDLYCNT Mask */ 1420 1421 #define EADC_SCTL9_TRGSEL_Pos (16) /*!< EADC_T::SCTL9: TRGSEL Position */ 1422 #define EADC_SCTL9_TRGSEL_Msk (0x3ful << EADC_SCTL9_TRGSEL_Pos) /*!< EADC_T::SCTL9: TRGSEL Mask */ 1423 1424 #define EADC_SCTL9_EXTREN_Pos (22) /*!< EADC_T::SCTL9: EXTREN Position */ 1425 #define EADC_SCTL9_EXTREN_Msk (0x1ul << EADC_SCTL9_EXTREN_Pos) /*!< EADC_T::SCTL9: EXTREN Mask */ 1426 1427 #define EADC_SCTL9_EXTFEN_Pos (23) /*!< EADC_T::SCTL9: EXTFEN Position */ 1428 #define EADC_SCTL9_EXTFEN_Msk (0x1ul << EADC_SCTL9_EXTFEN_Pos) /*!< EADC_T::SCTL9: EXTFEN Mask */ 1429 1430 #define EADC_SCTL9_EXTSMPT_Pos (24) /*!< EADC_T::SCTL9: EXTSMPT Position */ 1431 #define EADC_SCTL9_EXTSMPT_Msk (0xfful << EADC_SCTL9_EXTSMPT_Pos) /*!< EADC_T::SCTL9: EXTSMPT Mask */ 1432 1433 #define EADC_SCTL10_CHSEL_Pos (0) /*!< EADC_T::SCTL10: CHSEL Position */ 1434 #define EADC_SCTL10_CHSEL_Msk (0x1ful << EADC_SCTL10_CHSEL_Pos) /*!< EADC_T::SCTL10: CHSEL Mask */ 1435 1436 #define EADC_SCTL10_INTPOS_Pos (5) /*!< EADC_T::SCTL10: INTPOS Position */ 1437 #define EADC_SCTL10_INTPOS_Msk (0x1ul << EADC_SCTL10_INTPOS_Pos) /*!< EADC_T::SCTL10: INTPOS Mask */ 1438 1439 #define EADC_SCTL10_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL10: TRGDLYDIV Position */ 1440 #define EADC_SCTL10_TRGDLYDIV_Msk (0x3ul << EADC_SCTL10_TRGDLYDIV_Pos) /*!< EADC_T::SCTL10: TRGDLYDIV Mask */ 1441 1442 #define EADC_SCTL10_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL10: TRGDLYCNT Position */ 1443 #define EADC_SCTL10_TRGDLYCNT_Msk (0xfful << EADC_SCTL10_TRGDLYCNT_Pos) /*!< EADC_T::SCTL10: TRGDLYCNT Mask */ 1444 1445 #define EADC_SCTL10_TRGSEL_Pos (16) /*!< EADC_T::SCTL10: TRGSEL Position */ 1446 #define EADC_SCTL10_TRGSEL_Msk (0x3ful << EADC_SCTL10_TRGSEL_Pos) /*!< EADC_T::SCTL10: TRGSEL Mask */ 1447 1448 #define EADC_SCTL10_EXTREN_Pos (22) /*!< EADC_T::SCTL10: EXTREN Position */ 1449 #define EADC_SCTL10_EXTREN_Msk (0x1ul << EADC_SCTL10_EXTREN_Pos) /*!< EADC_T::SCTL10: EXTREN Mask */ 1450 1451 #define EADC_SCTL10_EXTFEN_Pos (23) /*!< EADC_T::SCTL10: EXTFEN Position */ 1452 #define EADC_SCTL10_EXTFEN_Msk (0x1ul << EADC_SCTL10_EXTFEN_Pos) /*!< EADC_T::SCTL10: EXTFEN Mask */ 1453 1454 #define EADC_SCTL10_EXTSMPT_Pos (24) /*!< EADC_T::SCTL10: EXTSMPT Position */ 1455 #define EADC_SCTL10_EXTSMPT_Msk (0xfful << EADC_SCTL10_EXTSMPT_Pos) /*!< EADC_T::SCTL10: EXTSMPT Mask */ 1456 1457 #define EADC_SCTL11_CHSEL_Pos (0) /*!< EADC_T::SCTL11: CHSEL Position */ 1458 #define EADC_SCTL11_CHSEL_Msk (0x1ful << EADC_SCTL11_CHSEL_Pos) /*!< EADC_T::SCTL11: CHSEL Mask */ 1459 1460 #define EADC_SCTL11_INTPOS_Pos (5) /*!< EADC_T::SCTL11: INTPOS Position */ 1461 #define EADC_SCTL11_INTPOS_Msk (0x1ul << EADC_SCTL11_INTPOS_Pos) /*!< EADC_T::SCTL11: INTPOS Mask */ 1462 1463 #define EADC_SCTL11_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL11: TRGDLYDIV Position */ 1464 #define EADC_SCTL11_TRGDLYDIV_Msk (0x3ul << EADC_SCTL11_TRGDLYDIV_Pos) /*!< EADC_T::SCTL11: TRGDLYDIV Mask */ 1465 1466 #define EADC_SCTL11_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL11: TRGDLYCNT Position */ 1467 #define EADC_SCTL11_TRGDLYCNT_Msk (0xfful << EADC_SCTL11_TRGDLYCNT_Pos) /*!< EADC_T::SCTL11: TRGDLYCNT Mask */ 1468 1469 #define EADC_SCTL11_TRGSEL_Pos (16) /*!< EADC_T::SCTL11: TRGSEL Position */ 1470 #define EADC_SCTL11_TRGSEL_Msk (0x3ful << EADC_SCTL11_TRGSEL_Pos) /*!< EADC_T::SCTL11: TRGSEL Mask */ 1471 1472 #define EADC_SCTL11_EXTREN_Pos (22) /*!< EADC_T::SCTL11: EXTREN Position */ 1473 #define EADC_SCTL11_EXTREN_Msk (0x1ul << EADC_SCTL11_EXTREN_Pos) /*!< EADC_T::SCTL11: EXTREN Mask */ 1474 1475 #define EADC_SCTL11_EXTFEN_Pos (23) /*!< EADC_T::SCTL11: EXTFEN Position */ 1476 #define EADC_SCTL11_EXTFEN_Msk (0x1ul << EADC_SCTL11_EXTFEN_Pos) /*!< EADC_T::SCTL11: EXTFEN Mask */ 1477 1478 #define EADC_SCTL11_EXTSMPT_Pos (24) /*!< EADC_T::SCTL11: EXTSMPT Position */ 1479 #define EADC_SCTL11_EXTSMPT_Msk (0xfful << EADC_SCTL11_EXTSMPT_Pos) /*!< EADC_T::SCTL11: EXTSMPT Mask */ 1480 1481 #define EADC_SCTL12_CHSEL_Pos (0) /*!< EADC_T::SCTL12: CHSEL Position */ 1482 #define EADC_SCTL12_CHSEL_Msk (0x1ful << EADC_SCTL12_CHSEL_Pos) /*!< EADC_T::SCTL12: CHSEL Mask */ 1483 1484 #define EADC_SCTL12_INTPOS_Pos (5) /*!< EADC_T::SCTL12: INTPOS Position */ 1485 #define EADC_SCTL12_INTPOS_Msk (0x1ul << EADC_SCTL12_INTPOS_Pos) /*!< EADC_T::SCTL12: INTPOS Mask */ 1486 1487 #define EADC_SCTL12_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL12: TRGDLYDIV Position */ 1488 #define EADC_SCTL12_TRGDLYDIV_Msk (0x3ul << EADC_SCTL12_TRGDLYDIV_Pos) /*!< EADC_T::SCTL12: TRGDLYDIV Mask */ 1489 1490 #define EADC_SCTL12_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL12: TRGDLYCNT Position */ 1491 #define EADC_SCTL12_TRGDLYCNT_Msk (0xfful << EADC_SCTL12_TRGDLYCNT_Pos) /*!< EADC_T::SCTL12: TRGDLYCNT Mask */ 1492 1493 #define EADC_SCTL12_TRGSEL_Pos (16) /*!< EADC_T::SCTL12: TRGSEL Position */ 1494 #define EADC_SCTL12_TRGSEL_Msk (0x3ful << EADC_SCTL12_TRGSEL_Pos) /*!< EADC_T::SCTL12: TRGSEL Mask */ 1495 1496 #define EADC_SCTL12_EXTREN_Pos (22) /*!< EADC_T::SCTL12: EXTREN Position */ 1497 #define EADC_SCTL12_EXTREN_Msk (0x1ul << EADC_SCTL12_EXTREN_Pos) /*!< EADC_T::SCTL12: EXTREN Mask */ 1498 1499 #define EADC_SCTL12_EXTFEN_Pos (23) /*!< EADC_T::SCTL12: EXTFEN Position */ 1500 #define EADC_SCTL12_EXTFEN_Msk (0x1ul << EADC_SCTL12_EXTFEN_Pos) /*!< EADC_T::SCTL12: EXTFEN Mask */ 1501 1502 #define EADC_SCTL12_EXTSMPT_Pos (24) /*!< EADC_T::SCTL12: EXTSMPT Position */ 1503 #define EADC_SCTL12_EXTSMPT_Msk (0xfful << EADC_SCTL12_EXTSMPT_Pos) /*!< EADC_T::SCTL12: EXTSMPT Mask */ 1504 1505 #define EADC_SCTL13_CHSEL_Pos (0) /*!< EADC_T::SCTL13: CHSEL Position */ 1506 #define EADC_SCTL13_CHSEL_Msk (0x1ful << EADC_SCTL13_CHSEL_Pos) /*!< EADC_T::SCTL13: CHSEL Mask */ 1507 1508 #define EADC_SCTL13_INTPOS_Pos (5) /*!< EADC_T::SCTL13: INTPOS Position */ 1509 #define EADC_SCTL13_INTPOS_Msk (0x1ul << EADC_SCTL13_INTPOS_Pos) /*!< EADC_T::SCTL13: INTPOS Mask */ 1510 1511 #define EADC_SCTL13_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL13: TRGDLYDIV Position */ 1512 #define EADC_SCTL13_TRGDLYDIV_Msk (0x3ul << EADC_SCTL13_TRGDLYDIV_Pos) /*!< EADC_T::SCTL13: TRGDLYDIV Mask */ 1513 1514 #define EADC_SCTL13_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL13: TRGDLYCNT Position */ 1515 #define EADC_SCTL13_TRGDLYCNT_Msk (0xfful << EADC_SCTL13_TRGDLYCNT_Pos) /*!< EADC_T::SCTL13: TRGDLYCNT Mask */ 1516 1517 #define EADC_SCTL13_TRGSEL_Pos (16) /*!< EADC_T::SCTL13: TRGSEL Position */ 1518 #define EADC_SCTL13_TRGSEL_Msk (0x3ful << EADC_SCTL13_TRGSEL_Pos) /*!< EADC_T::SCTL13: TRGSEL Mask */ 1519 1520 #define EADC_SCTL13_EXTREN_Pos (22) /*!< EADC_T::SCTL13: EXTREN Position */ 1521 #define EADC_SCTL13_EXTREN_Msk (0x1ul << EADC_SCTL13_EXTREN_Pos) /*!< EADC_T::SCTL13: EXTREN Mask */ 1522 1523 #define EADC_SCTL13_EXTFEN_Pos (23) /*!< EADC_T::SCTL13: EXTFEN Position */ 1524 #define EADC_SCTL13_EXTFEN_Msk (0x1ul << EADC_SCTL13_EXTFEN_Pos) /*!< EADC_T::SCTL13: EXTFEN Mask */ 1525 1526 #define EADC_SCTL13_EXTSMPT_Pos (24) /*!< EADC_T::SCTL13: EXTSMPT Position */ 1527 #define EADC_SCTL13_EXTSMPT_Msk (0xfful << EADC_SCTL13_EXTSMPT_Pos) /*!< EADC_T::SCTL13: EXTSMPT Mask */ 1528 1529 #define EADC_SCTL14_CHSEL_Pos (0) /*!< EADC_T::SCTL14: CHSEL Position */ 1530 #define EADC_SCTL14_CHSEL_Msk (0x1ful << EADC_SCTL14_CHSEL_Pos) /*!< EADC_T::SCTL14: CHSEL Mask */ 1531 1532 #define EADC_SCTL14_INTPOS_Pos (5) /*!< EADC_T::SCTL14: INTPOS Position */ 1533 #define EADC_SCTL14_INTPOS_Msk (0x1ul << EADC_SCTL14_INTPOS_Pos) /*!< EADC_T::SCTL14: INTPOS Mask */ 1534 1535 #define EADC_SCTL14_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL14: TRGDLYDIV Position */ 1536 #define EADC_SCTL14_TRGDLYDIV_Msk (0x3ul << EADC_SCTL14_TRGDLYDIV_Pos) /*!< EADC_T::SCTL14: TRGDLYDIV Mask */ 1537 1538 #define EADC_SCTL14_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL14: TRGDLYCNT Position */ 1539 #define EADC_SCTL14_TRGDLYCNT_Msk (0xfful << EADC_SCTL14_TRGDLYCNT_Pos) /*!< EADC_T::SCTL14: TRGDLYCNT Mask */ 1540 1541 #define EADC_SCTL14_TRGSEL_Pos (16) /*!< EADC_T::SCTL14: TRGSEL Position */ 1542 #define EADC_SCTL14_TRGSEL_Msk (0x3ful << EADC_SCTL14_TRGSEL_Pos) /*!< EADC_T::SCTL14: TRGSEL Mask */ 1543 1544 #define EADC_SCTL14_EXTREN_Pos (22) /*!< EADC_T::SCTL14: EXTREN Position */ 1545 #define EADC_SCTL14_EXTREN_Msk (0x1ul << EADC_SCTL14_EXTREN_Pos) /*!< EADC_T::SCTL14: EXTREN Mask */ 1546 1547 #define EADC_SCTL14_EXTFEN_Pos (23) /*!< EADC_T::SCTL14: EXTFEN Position */ 1548 #define EADC_SCTL14_EXTFEN_Msk (0x1ul << EADC_SCTL14_EXTFEN_Pos) /*!< EADC_T::SCTL14: EXTFEN Mask */ 1549 1550 #define EADC_SCTL14_EXTSMPT_Pos (24) /*!< EADC_T::SCTL14: EXTSMPT Position */ 1551 #define EADC_SCTL14_EXTSMPT_Msk (0xfful << EADC_SCTL14_EXTSMPT_Pos) /*!< EADC_T::SCTL14: EXTSMPT Mask */ 1552 1553 #define EADC_SCTL15_CHSEL_Pos (0) /*!< EADC_T::SCTL15: CHSEL Position */ 1554 #define EADC_SCTL15_CHSEL_Msk (0x1ful << EADC_SCTL15_CHSEL_Pos) /*!< EADC_T::SCTL15: CHSEL Mask */ 1555 1556 #define EADC_SCTL15_INTPOS_Pos (5) /*!< EADC_T::SCTL15: INTPOS Position */ 1557 #define EADC_SCTL15_INTPOS_Msk (0x1ul << EADC_SCTL15_INTPOS_Pos) /*!< EADC_T::SCTL15: INTPOS Mask */ 1558 1559 #define EADC_SCTL15_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL15: TRGDLYDIV Position */ 1560 #define EADC_SCTL15_TRGDLYDIV_Msk (0x3ul << EADC_SCTL15_TRGDLYDIV_Pos) /*!< EADC_T::SCTL15: TRGDLYDIV Mask */ 1561 1562 #define EADC_SCTL15_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL15: TRGDLYCNT Position */ 1563 #define EADC_SCTL15_TRGDLYCNT_Msk (0xfful << EADC_SCTL15_TRGDLYCNT_Pos) /*!< EADC_T::SCTL15: TRGDLYCNT Mask */ 1564 1565 #define EADC_SCTL15_TRGSEL_Pos (16) /*!< EADC_T::SCTL15: TRGSEL Position */ 1566 #define EADC_SCTL15_TRGSEL_Msk (0x3ful << EADC_SCTL15_TRGSEL_Pos) /*!< EADC_T::SCTL15: TRGSEL Mask */ 1567 1568 #define EADC_SCTL15_EXTREN_Pos (22) /*!< EADC_T::SCTL15: EXTREN Position */ 1569 #define EADC_SCTL15_EXTREN_Msk (0x1ul << EADC_SCTL15_EXTREN_Pos) /*!< EADC_T::SCTL15: EXTREN Mask */ 1570 1571 #define EADC_SCTL15_EXTFEN_Pos (23) /*!< EADC_T::SCTL15: EXTFEN Position */ 1572 #define EADC_SCTL15_EXTFEN_Msk (0x1ul << EADC_SCTL15_EXTFEN_Pos) /*!< EADC_T::SCTL15: EXTFEN Mask */ 1573 1574 #define EADC_SCTL15_EXTSMPT_Pos (24) /*!< EADC_T::SCTL15: EXTSMPT Position */ 1575 #define EADC_SCTL15_EXTSMPT_Msk (0xfful << EADC_SCTL15_EXTSMPT_Pos) /*!< EADC_T::SCTL15: EXTSMPT Mask */ 1576 1577 #define EADC_SCTL16_CHSEL_Pos (0) /*!< EADC_T::SCTL16: CHSEL Position */ 1578 #define EADC_SCTL16_CHSEL_Msk (0x1ful << EADC_SCTL16_CHSEL_Pos) /*!< EADC_T::SCTL16: CHSEL Mask */ 1579 1580 #define EADC_SCTL16_INTPOS_Pos (5) /*!< EADC_T::SCTL16: INTPOS Position */ 1581 #define EADC_SCTL16_INTPOS_Msk (0x1ul << EADC_SCTL16_INTPOS_Pos) /*!< EADC_T::SCTL16: INTPOS Mask */ 1582 1583 #define EADC_SCTL16_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL16: TRGDLYDIV Position */ 1584 #define EADC_SCTL16_TRGDLYDIV_Msk (0x3ul << EADC_SCTL16_TRGDLYDIV_Pos) /*!< EADC_T::SCTL16: TRGDLYDIV Mask */ 1585 1586 #define EADC_SCTL16_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL16: TRGDLYCNT Position */ 1587 #define EADC_SCTL16_TRGDLYCNT_Msk (0xfful << EADC_SCTL16_TRGDLYCNT_Pos) /*!< EADC_T::SCTL16: TRGDLYCNT Mask */ 1588 1589 #define EADC_SCTL16_TRGSEL_Pos (16) /*!< EADC_T::SCTL16: TRGSEL Position */ 1590 #define EADC_SCTL16_TRGSEL_Msk (0x3ful << EADC_SCTL16_TRGSEL_Pos) /*!< EADC_T::SCTL16: TRGSEL Mask */ 1591 1592 #define EADC_SCTL16_EXTREN_Pos (22) /*!< EADC_T::SCTL16: EXTREN Position */ 1593 #define EADC_SCTL16_EXTREN_Msk (0x1ul << EADC_SCTL16_EXTREN_Pos) /*!< EADC_T::SCTL16: EXTREN Mask */ 1594 1595 #define EADC_SCTL16_EXTFEN_Pos (23) /*!< EADC_T::SCTL16: EXTFEN Position */ 1596 #define EADC_SCTL16_EXTFEN_Msk (0x1ul << EADC_SCTL16_EXTFEN_Pos) /*!< EADC_T::SCTL16: EXTFEN Mask */ 1597 1598 #define EADC_SCTL16_EXTSMPT_Pos (24) /*!< EADC_T::SCTL16: EXTSMPT Position */ 1599 #define EADC_SCTL16_EXTSMPT_Msk (0xfful << EADC_SCTL16_EXTSMPT_Pos) /*!< EADC_T::SCTL16: EXTSMPT Mask */ 1600 1601 #define EADC_SCTL17_CHSEL_Pos (0) /*!< EADC_T::SCTL17: CHSEL Position */ 1602 #define EADC_SCTL17_CHSEL_Msk (0x1ful << EADC_SCTL17_CHSEL_Pos) /*!< EADC_T::SCTL17: CHSEL Mask */ 1603 1604 #define EADC_SCTL17_INTPOS_Pos (5) /*!< EADC_T::SCTL17: INTPOS Position */ 1605 #define EADC_SCTL17_INTPOS_Msk (0x1ul << EADC_SCTL17_INTPOS_Pos) /*!< EADC_T::SCTL17: INTPOS Mask */ 1606 1607 #define EADC_SCTL17_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL17: TRGDLYDIV Position */ 1608 #define EADC_SCTL17_TRGDLYDIV_Msk (0x3ul << EADC_SCTL17_TRGDLYDIV_Pos) /*!< EADC_T::SCTL17: TRGDLYDIV Mask */ 1609 1610 #define EADC_SCTL17_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL17: TRGDLYCNT Position */ 1611 #define EADC_SCTL17_TRGDLYCNT_Msk (0xfful << EADC_SCTL17_TRGDLYCNT_Pos) /*!< EADC_T::SCTL17: TRGDLYCNT Mask */ 1612 1613 #define EADC_SCTL17_TRGSEL_Pos (16) /*!< EADC_T::SCTL17: TRGSEL Position */ 1614 #define EADC_SCTL17_TRGSEL_Msk (0x3ful << EADC_SCTL17_TRGSEL_Pos) /*!< EADC_T::SCTL17: TRGSEL Mask */ 1615 1616 #define EADC_SCTL17_EXTREN_Pos (22) /*!< EADC_T::SCTL17: EXTREN Position */ 1617 #define EADC_SCTL17_EXTREN_Msk (0x1ul << EADC_SCTL17_EXTREN_Pos) /*!< EADC_T::SCTL17: EXTREN Mask */ 1618 1619 #define EADC_SCTL17_EXTFEN_Pos (23) /*!< EADC_T::SCTL17: EXTFEN Position */ 1620 #define EADC_SCTL17_EXTFEN_Msk (0x1ul << EADC_SCTL17_EXTFEN_Pos) /*!< EADC_T::SCTL17: EXTFEN Mask */ 1621 1622 #define EADC_SCTL17_EXTSMPT_Pos (24) /*!< EADC_T::SCTL17: EXTSMPT Position */ 1623 #define EADC_SCTL17_EXTSMPT_Msk (0xfful << EADC_SCTL17_EXTSMPT_Pos) /*!< EADC_T::SCTL17: EXTSMPT Mask */ 1624 1625 #define EADC_SCTL18_CHSEL_Pos (0) /*!< EADC_T::SCTL18: CHSEL Position */ 1626 #define EADC_SCTL18_CHSEL_Msk (0x1ful << EADC_SCTL18_CHSEL_Pos) /*!< EADC_T::SCTL18: CHSEL Mask */ 1627 1628 #define EADC_SCTL18_INTPOS_Pos (5) /*!< EADC_T::SCTL18: INTPOS Position */ 1629 #define EADC_SCTL18_INTPOS_Msk (0x1ul << EADC_SCTL18_INTPOS_Pos) /*!< EADC_T::SCTL18: INTPOS Mask */ 1630 1631 #define EADC_SCTL18_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL18: TRGDLYDIV Position */ 1632 #define EADC_SCTL18_TRGDLYDIV_Msk (0x3ul << EADC_SCTL18_TRGDLYDIV_Pos) /*!< EADC_T::SCTL18: TRGDLYDIV Mask */ 1633 1634 #define EADC_SCTL18_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL18: TRGDLYCNT Position */ 1635 #define EADC_SCTL18_TRGDLYCNT_Msk (0xfful << EADC_SCTL18_TRGDLYCNT_Pos) /*!< EADC_T::SCTL18: TRGDLYCNT Mask */ 1636 1637 #define EADC_SCTL18_TRGSEL_Pos (16) /*!< EADC_T::SCTL18: TRGSEL Position */ 1638 #define EADC_SCTL18_TRGSEL_Msk (0x3ful << EADC_SCTL18_TRGSEL_Pos) /*!< EADC_T::SCTL18: TRGSEL Mask */ 1639 1640 #define EADC_SCTL18_EXTREN_Pos (22) /*!< EADC_T::SCTL18: EXTREN Position */ 1641 #define EADC_SCTL18_EXTREN_Msk (0x1ul << EADC_SCTL18_EXTREN_Pos) /*!< EADC_T::SCTL18: EXTREN Mask */ 1642 1643 #define EADC_SCTL18_EXTFEN_Pos (23) /*!< EADC_T::SCTL18: EXTFEN Position */ 1644 #define EADC_SCTL18_EXTFEN_Msk (0x1ul << EADC_SCTL18_EXTFEN_Pos) /*!< EADC_T::SCTL18: EXTFEN Mask */ 1645 1646 #define EADC_SCTL18_EXTSMPT_Pos (24) /*!< EADC_T::SCTL18: EXTSMPT Position */ 1647 #define EADC_SCTL18_EXTSMPT_Msk (0xfful << EADC_SCTL18_EXTSMPT_Pos) /*!< EADC_T::SCTL18: EXTSMPT Mask */ 1648 1649 #define EADC_INTSRC0_SPLIE0_Pos (0) /*!< EADC_T::INTSRC0: SPLIE0 Position */ 1650 #define EADC_INTSRC0_SPLIE0_Msk (0x1ul << EADC_INTSRC0_SPLIE0_Pos) /*!< EADC_T::INTSRC0: SPLIE0 Mask */ 1651 1652 #define EADC_INTSRC0_SPLIE1_Pos (1) /*!< EADC_T::INTSRC0: SPLIE1 Position */ 1653 #define EADC_INTSRC0_SPLIE1_Msk (0x1ul << EADC_INTSRC0_SPLIE1_Pos) /*!< EADC_T::INTSRC0: SPLIE1 Mask */ 1654 1655 #define EADC_INTSRC0_SPLIE2_Pos (2) /*!< EADC_T::INTSRC0: SPLIE2 Position */ 1656 #define EADC_INTSRC0_SPLIE2_Msk (0x1ul << EADC_INTSRC0_SPLIE2_Pos) /*!< EADC_T::INTSRC0: SPLIE2 Mask */ 1657 1658 #define EADC_INTSRC0_SPLIE3_Pos (3) /*!< EADC_T::INTSRC0: SPLIE3 Position */ 1659 #define EADC_INTSRC0_SPLIE3_Msk (0x1ul << EADC_INTSRC0_SPLIE3_Pos) /*!< EADC_T::INTSRC0: SPLIE3 Mask */ 1660 1661 #define EADC_INTSRC0_SPLIE4_Pos (4) /*!< EADC_T::INTSRC0: SPLIE4 Position */ 1662 #define EADC_INTSRC0_SPLIE4_Msk (0x1ul << EADC_INTSRC0_SPLIE4_Pos) /*!< EADC_T::INTSRC0: SPLIE4 Mask */ 1663 1664 #define EADC_INTSRC0_SPLIE5_Pos (5) /*!< EADC_T::INTSRC0: SPLIE5 Position */ 1665 #define EADC_INTSRC0_SPLIE5_Msk (0x1ul << EADC_INTSRC0_SPLIE5_Pos) /*!< EADC_T::INTSRC0: SPLIE5 Mask */ 1666 1667 #define EADC_INTSRC0_SPLIE6_Pos (6) /*!< EADC_T::INTSRC0: SPLIE6 Position */ 1668 #define EADC_INTSRC0_SPLIE6_Msk (0x1ul << EADC_INTSRC0_SPLIE6_Pos) /*!< EADC_T::INTSRC0: SPLIE6 Mask */ 1669 1670 #define EADC_INTSRC0_SPLIE7_Pos (7) /*!< EADC_T::INTSRC0: SPLIE7 Position */ 1671 #define EADC_INTSRC0_SPLIE7_Msk (0x1ul << EADC_INTSRC0_SPLIE7_Pos) /*!< EADC_T::INTSRC0: SPLIE7 Mask */ 1672 1673 #define EADC_INTSRC0_SPLIE8_Pos (8) /*!< EADC_T::INTSRC0: SPLIE8 Position */ 1674 #define EADC_INTSRC0_SPLIE8_Msk (0x1ul << EADC_INTSRC0_SPLIE8_Pos) /*!< EADC_T::INTSRC0: SPLIE8 Mask */ 1675 1676 #define EADC_INTSRC0_SPLIE9_Pos (9) /*!< EADC_T::INTSRC0: SPLIE9 Position */ 1677 #define EADC_INTSRC0_SPLIE9_Msk (0x1ul << EADC_INTSRC0_SPLIE9_Pos) /*!< EADC_T::INTSRC0: SPLIE9 Mask */ 1678 1679 #define EADC_INTSRC0_SPLIE10_Pos (10) /*!< EADC_T::INTSRC0: SPLIE10 Position */ 1680 #define EADC_INTSRC0_SPLIE10_Msk (0x1ul << EADC_INTSRC0_SPLIE10_Pos) /*!< EADC_T::INTSRC0: SPLIE10 Mask */ 1681 1682 #define EADC_INTSRC0_SPLIE11_Pos (11) /*!< EADC_T::INTSRC0: SPLIE11 Position */ 1683 #define EADC_INTSRC0_SPLIE11_Msk (0x1ul << EADC_INTSRC0_SPLIE11_Pos) /*!< EADC_T::INTSRC0: SPLIE11 Mask */ 1684 1685 #define EADC_INTSRC0_SPLIE12_Pos (12) /*!< EADC_T::INTSRC0: SPLIE12 Position */ 1686 #define EADC_INTSRC0_SPLIE12_Msk (0x1ul << EADC_INTSRC0_SPLIE12_Pos) /*!< EADC_T::INTSRC0: SPLIE12 Mask */ 1687 1688 #define EADC_INTSRC0_SPLIE13_Pos (13) /*!< EADC_T::INTSRC0: SPLIE13 Position */ 1689 #define EADC_INTSRC0_SPLIE13_Msk (0x1ul << EADC_INTSRC0_SPLIE13_Pos) /*!< EADC_T::INTSRC0: SPLIE13 Mask */ 1690 1691 #define EADC_INTSRC0_SPLIE14_Pos (14) /*!< EADC_T::INTSRC0: SPLIE14 Position */ 1692 #define EADC_INTSRC0_SPLIE14_Msk (0x1ul << EADC_INTSRC0_SPLIE14_Pos) /*!< EADC_T::INTSRC0: SPLIE14 Mask */ 1693 1694 #define EADC_INTSRC0_SPLIE15_Pos (15) /*!< EADC_T::INTSRC0: SPLIE15 Position */ 1695 #define EADC_INTSRC0_SPLIE15_Msk (0x1ul << EADC_INTSRC0_SPLIE15_Pos) /*!< EADC_T::INTSRC0: SPLIE15 Mask */ 1696 1697 #define EADC_INTSRC0_SPLIE16_Pos (16) /*!< EADC_T::INTSRC0: SPLIE16 Position */ 1698 #define EADC_INTSRC0_SPLIE16_Msk (0x1ul << EADC_INTSRC0_SPLIE16_Pos) /*!< EADC_T::INTSRC0: SPLIE16 Mask */ 1699 1700 #define EADC_INTSRC0_SPLIE17_Pos (17) /*!< EADC_T::INTSRC0: SPLIE17 Position */ 1701 #define EADC_INTSRC0_SPLIE17_Msk (0x1ul << EADC_INTSRC0_SPLIE17_Pos) /*!< EADC_T::INTSRC0: SPLIE17 Mask */ 1702 1703 #define EADC_INTSRC0_SPLIE18_Pos (18) /*!< EADC_T::INTSRC0: SPLIE18 Position */ 1704 #define EADC_INTSRC0_SPLIE18_Msk (0x1ul << EADC_INTSRC0_SPLIE18_Pos) /*!< EADC_T::INTSRC0: SPLIE18 Mask */ 1705 1706 #define EADC_INTSRC0_SPLIE19_Pos (19) /*!< EADC_T::INTSRC0: SPLIE19 Position */ 1707 #define EADC_INTSRC0_SPLIE19_Msk (0x1ul << EADC_INTSRC0_SPLIE19_Pos) /*!< EADC_T::INTSRC0: SPLIE19 Mask */ 1708 1709 #define EADC_INTSRC0_SPLIE20_Pos (20) /*!< EADC_T::INTSRC0: SPLIE20 Position */ 1710 #define EADC_INTSRC0_SPLIE20_Msk (0x1ul << EADC_INTSRC0_SPLIE20_Pos) /*!< EADC_T::INTSRC0: SPLIE20 Mask */ 1711 1712 #define EADC_INTSRC0_SPLIE21_Pos (21) /*!< EADC_T::INTSRC0: SPLIE21 Position */ 1713 #define EADC_INTSRC0_SPLIE21_Msk (0x1ul << EADC_INTSRC0_SPLIE21_Pos) /*!< EADC_T::INTSRC0: SPLIE21 Mask */ 1714 1715 #define EADC_INTSRC0_SPLIE22_Pos (22) /*!< EADC_T::INTSRC0: SPLIE22 Position */ 1716 #define EADC_INTSRC0_SPLIE22_Msk (0x1ul << EADC_INTSRC0_SPLIE22_Pos) /*!< EADC_T::INTSRC0: SPLIE22 Mask */ 1717 1718 #define EADC_INTSRC0_SPLIE23_Pos (23) /*!< EADC_T::INTSRC0: SPLIE23 Position */ 1719 #define EADC_INTSRC0_SPLIE23_Msk (0x1ul << EADC_INTSRC0_SPLIE23_Pos) /*!< EADC_T::INTSRC0: SPLIE23 Mask */ 1720 1721 #define EADC_INTSRC0_SPLIE24_Pos (24) /*!< EADC_T::INTSRC0: SPLIE24 Position */ 1722 #define EADC_INTSRC0_SPLIE24_Msk (0x1ul << EADC_INTSRC0_SPLIE24_Pos) /*!< EADC_T::INTSRC0: SPLIE24 Mask */ 1723 1724 #define EADC_INTSRC0_SPLIE25_Pos (25) /*!< EADC_T::INTSRC0: SPLIE25 Position */ 1725 #define EADC_INTSRC0_SPLIE25_Msk (0x1ul << EADC_INTSRC0_SPLIE25_Pos) /*!< EADC_T::INTSRC0: SPLIE25 Mask */ 1726 1727 #define EADC_INTSRC0_SPLIE26_Pos (26) /*!< EADC_T::INTSRC0: SPLIE26 Position */ 1728 #define EADC_INTSRC0_SPLIE26_Msk (0x1ul << EADC_INTSRC0_SPLIE26_Pos) /*!< EADC_T::INTSRC0: SPLIE26 Mask */ 1729 1730 #define EADC_INTSRC0_SPLIE27_Pos (27) /*!< EADC_T::INTSRC0: SPLIE27 Position */ 1731 #define EADC_INTSRC0_SPLIE27_Msk (0x1ul << EADC_INTSRC0_SPLIE27_Pos) /*!< EADC_T::INTSRC0: SPLIE27 Mask */ 1732 1733 #define EADC_INTSRC0_SPLIE28_Pos (28) /*!< EADC_T::INTSRC0: SPLIE28 Position */ 1734 #define EADC_INTSRC0_SPLIE28_Msk (0x1ul << EADC_INTSRC0_SPLIE28_Pos) /*!< EADC_T::INTSRC0: SPLIE28 Mask */ 1735 1736 #define EADC_INTSRC0_SPLIE29_Pos (29) /*!< EADC_T::INTSRC0: SPLIE29 Position */ 1737 #define EADC_INTSRC0_SPLIE29_Msk (0x1ul << EADC_INTSRC0_SPLIE29_Pos) /*!< EADC_T::INTSRC0: SPLIE29 Mask */ 1738 1739 #define EADC_INTSRC0_SPLIE30_Pos (30) /*!< EADC_T::INTSRC0: SPLIE30 Position */ 1740 #define EADC_INTSRC0_SPLIE30_Msk (0x1ul << EADC_INTSRC0_SPLIE30_Pos) /*!< EADC_T::INTSRC0: SPLIE30 Mask */ 1741 1742 #define EADC_INTSRC1_SPLIE0_Pos (0) /*!< EADC_T::INTSRC1: SPLIE0 Position */ 1743 #define EADC_INTSRC1_SPLIE0_Msk (0x1ul << EADC_INTSRC1_SPLIE0_Pos) /*!< EADC_T::INTSRC1: SPLIE0 Mask */ 1744 1745 #define EADC_INTSRC1_SPLIE1_Pos (1) /*!< EADC_T::INTSRC1: SPLIE1 Position */ 1746 #define EADC_INTSRC1_SPLIE1_Msk (0x1ul << EADC_INTSRC1_SPLIE1_Pos) /*!< EADC_T::INTSRC1: SPLIE1 Mask */ 1747 1748 #define EADC_INTSRC1_SPLIE2_Pos (2) /*!< EADC_T::INTSRC1: SPLIE2 Position */ 1749 #define EADC_INTSRC1_SPLIE2_Msk (0x1ul << EADC_INTSRC1_SPLIE2_Pos) /*!< EADC_T::INTSRC1: SPLIE2 Mask */ 1750 1751 #define EADC_INTSRC1_SPLIE3_Pos (3) /*!< EADC_T::INTSRC1: SPLIE3 Position */ 1752 #define EADC_INTSRC1_SPLIE3_Msk (0x1ul << EADC_INTSRC1_SPLIE3_Pos) /*!< EADC_T::INTSRC1: SPLIE3 Mask */ 1753 1754 #define EADC_INTSRC1_SPLIE4_Pos (4) /*!< EADC_T::INTSRC1: SPLIE4 Position */ 1755 #define EADC_INTSRC1_SPLIE4_Msk (0x1ul << EADC_INTSRC1_SPLIE4_Pos) /*!< EADC_T::INTSRC1: SPLIE4 Mask */ 1756 1757 #define EADC_INTSRC1_SPLIE5_Pos (5) /*!< EADC_T::INTSRC1: SPLIE5 Position */ 1758 #define EADC_INTSRC1_SPLIE5_Msk (0x1ul << EADC_INTSRC1_SPLIE5_Pos) /*!< EADC_T::INTSRC1: SPLIE5 Mask */ 1759 1760 #define EADC_INTSRC1_SPLIE6_Pos (6) /*!< EADC_T::INTSRC1: SPLIE6 Position */ 1761 #define EADC_INTSRC1_SPLIE6_Msk (0x1ul << EADC_INTSRC1_SPLIE6_Pos) /*!< EADC_T::INTSRC1: SPLIE6 Mask */ 1762 1763 #define EADC_INTSRC1_SPLIE7_Pos (7) /*!< EADC_T::INTSRC1: SPLIE7 Position */ 1764 #define EADC_INTSRC1_SPLIE7_Msk (0x1ul << EADC_INTSRC1_SPLIE7_Pos) /*!< EADC_T::INTSRC1: SPLIE7 Mask */ 1765 1766 #define EADC_INTSRC1_SPLIE8_Pos (8) /*!< EADC_T::INTSRC1: SPLIE8 Position */ 1767 #define EADC_INTSRC1_SPLIE8_Msk (0x1ul << EADC_INTSRC1_SPLIE8_Pos) /*!< EADC_T::INTSRC1: SPLIE8 Mask */ 1768 1769 #define EADC_INTSRC1_SPLIE9_Pos (9) /*!< EADC_T::INTSRC1: SPLIE9 Position */ 1770 #define EADC_INTSRC1_SPLIE9_Msk (0x1ul << EADC_INTSRC1_SPLIE9_Pos) /*!< EADC_T::INTSRC1: SPLIE9 Mask */ 1771 1772 #define EADC_INTSRC1_SPLIE10_Pos (10) /*!< EADC_T::INTSRC1: SPLIE10 Position */ 1773 #define EADC_INTSRC1_SPLIE10_Msk (0x1ul << EADC_INTSRC1_SPLIE10_Pos) /*!< EADC_T::INTSRC1: SPLIE10 Mask */ 1774 1775 #define EADC_INTSRC1_SPLIE11_Pos (11) /*!< EADC_T::INTSRC1: SPLIE11 Position */ 1776 #define EADC_INTSRC1_SPLIE11_Msk (0x1ul << EADC_INTSRC1_SPLIE11_Pos) /*!< EADC_T::INTSRC1: SPLIE11 Mask */ 1777 1778 #define EADC_INTSRC1_SPLIE12_Pos (12) /*!< EADC_T::INTSRC1: SPLIE12 Position */ 1779 #define EADC_INTSRC1_SPLIE12_Msk (0x1ul << EADC_INTSRC1_SPLIE12_Pos) /*!< EADC_T::INTSRC1: SPLIE12 Mask */ 1780 1781 #define EADC_INTSRC1_SPLIE13_Pos (13) /*!< EADC_T::INTSRC1: SPLIE13 Position */ 1782 #define EADC_INTSRC1_SPLIE13_Msk (0x1ul << EADC_INTSRC1_SPLIE13_Pos) /*!< EADC_T::INTSRC1: SPLIE13 Mask */ 1783 1784 #define EADC_INTSRC1_SPLIE14_Pos (14) /*!< EADC_T::INTSRC1: SPLIE14 Position */ 1785 #define EADC_INTSRC1_SPLIE14_Msk (0x1ul << EADC_INTSRC1_SPLIE14_Pos) /*!< EADC_T::INTSRC1: SPLIE14 Mask */ 1786 1787 #define EADC_INTSRC1_SPLIE15_Pos (15) /*!< EADC_T::INTSRC1: SPLIE15 Position */ 1788 #define EADC_INTSRC1_SPLIE15_Msk (0x1ul << EADC_INTSRC1_SPLIE15_Pos) /*!< EADC_T::INTSRC1: SPLIE15 Mask */ 1789 1790 #define EADC_INTSRC1_SPLIE16_Pos (16) /*!< EADC_T::INTSRC1: SPLIE16 Position */ 1791 #define EADC_INTSRC1_SPLIE16_Msk (0x1ul << EADC_INTSRC1_SPLIE16_Pos) /*!< EADC_T::INTSRC1: SPLIE16 Mask */ 1792 1793 #define EADC_INTSRC1_SPLIE17_Pos (17) /*!< EADC_T::INTSRC1: SPLIE17 Position */ 1794 #define EADC_INTSRC1_SPLIE17_Msk (0x1ul << EADC_INTSRC1_SPLIE17_Pos) /*!< EADC_T::INTSRC1: SPLIE17 Mask */ 1795 1796 #define EADC_INTSRC1_SPLIE18_Pos (18) /*!< EADC_T::INTSRC1: SPLIE18 Position */ 1797 #define EADC_INTSRC1_SPLIE18_Msk (0x1ul << EADC_INTSRC1_SPLIE18_Pos) /*!< EADC_T::INTSRC1: SPLIE18 Mask */ 1798 1799 #define EADC_INTSRC1_SPLIE19_Pos (19) /*!< EADC_T::INTSRC1: SPLIE19 Position */ 1800 #define EADC_INTSRC1_SPLIE19_Msk (0x1ul << EADC_INTSRC1_SPLIE19_Pos) /*!< EADC_T::INTSRC1: SPLIE19 Mask */ 1801 1802 #define EADC_INTSRC1_SPLIE20_Pos (20) /*!< EADC_T::INTSRC1: SPLIE20 Position */ 1803 #define EADC_INTSRC1_SPLIE20_Msk (0x1ul << EADC_INTSRC1_SPLIE20_Pos) /*!< EADC_T::INTSRC1: SPLIE20 Mask */ 1804 1805 #define EADC_INTSRC1_SPLIE21_Pos (21) /*!< EADC_T::INTSRC1: SPLIE21 Position */ 1806 #define EADC_INTSRC1_SPLIE21_Msk (0x1ul << EADC_INTSRC1_SPLIE21_Pos) /*!< EADC_T::INTSRC1: SPLIE21 Mask */ 1807 1808 #define EADC_INTSRC1_SPLIE22_Pos (22) /*!< EADC_T::INTSRC1: SPLIE22 Position */ 1809 #define EADC_INTSRC1_SPLIE22_Msk (0x1ul << EADC_INTSRC1_SPLIE22_Pos) /*!< EADC_T::INTSRC1: SPLIE22 Mask */ 1810 1811 #define EADC_INTSRC1_SPLIE23_Pos (23) /*!< EADC_T::INTSRC1: SPLIE23 Position */ 1812 #define EADC_INTSRC1_SPLIE23_Msk (0x1ul << EADC_INTSRC1_SPLIE23_Pos) /*!< EADC_T::INTSRC1: SPLIE23 Mask */ 1813 1814 #define EADC_INTSRC1_SPLIE24_Pos (24) /*!< EADC_T::INTSRC1: SPLIE24 Position */ 1815 #define EADC_INTSRC1_SPLIE24_Msk (0x1ul << EADC_INTSRC1_SPLIE24_Pos) /*!< EADC_T::INTSRC1: SPLIE24 Mask */ 1816 1817 #define EADC_INTSRC1_SPLIE25_Pos (25) /*!< EADC_T::INTSRC1: SPLIE25 Position */ 1818 #define EADC_INTSRC1_SPLIE25_Msk (0x1ul << EADC_INTSRC1_SPLIE25_Pos) /*!< EADC_T::INTSRC1: SPLIE25 Mask */ 1819 1820 #define EADC_INTSRC1_SPLIE26_Pos (26) /*!< EADC_T::INTSRC1: SPLIE26 Position */ 1821 #define EADC_INTSRC1_SPLIE26_Msk (0x1ul << EADC_INTSRC1_SPLIE26_Pos) /*!< EADC_T::INTSRC1: SPLIE26 Mask */ 1822 1823 #define EADC_INTSRC1_SPLIE27_Pos (27) /*!< EADC_T::INTSRC1: SPLIE27 Position */ 1824 #define EADC_INTSRC1_SPLIE27_Msk (0x1ul << EADC_INTSRC1_SPLIE27_Pos) /*!< EADC_T::INTSRC1: SPLIE27 Mask */ 1825 1826 #define EADC_INTSRC1_SPLIE28_Pos (28) /*!< EADC_T::INTSRC1: SPLIE28 Position */ 1827 #define EADC_INTSRC1_SPLIE28_Msk (0x1ul << EADC_INTSRC1_SPLIE28_Pos) /*!< EADC_T::INTSRC1: SPLIE28 Mask */ 1828 1829 #define EADC_INTSRC1_SPLIE29_Pos (29) /*!< EADC_T::INTSRC1: SPLIE29 Position */ 1830 #define EADC_INTSRC1_SPLIE29_Msk (0x1ul << EADC_INTSRC1_SPLIE29_Pos) /*!< EADC_T::INTSRC1: SPLIE29 Mask */ 1831 1832 #define EADC_INTSRC1_SPLIE30_Pos (30) /*!< EADC_T::INTSRC1: SPLIE30 Position */ 1833 #define EADC_INTSRC1_SPLIE30_Msk (0x1ul << EADC_INTSRC1_SPLIE30_Pos) /*!< EADC_T::INTSRC1: SPLIE30 Mask */ 1834 1835 #define EADC_INTSRC2_SPLIE0_Pos (0) /*!< EADC_T::INTSRC2: SPLIE0 Position */ 1836 #define EADC_INTSRC2_SPLIE0_Msk (0x1ul << EADC_INTSRC2_SPLIE0_Pos) /*!< EADC_T::INTSRC2: SPLIE0 Mask */ 1837 1838 #define EADC_INTSRC2_SPLIE1_Pos (1) /*!< EADC_T::INTSRC2: SPLIE1 Position */ 1839 #define EADC_INTSRC2_SPLIE1_Msk (0x1ul << EADC_INTSRC2_SPLIE1_Pos) /*!< EADC_T::INTSRC2: SPLIE1 Mask */ 1840 1841 #define EADC_INTSRC2_SPLIE2_Pos (2) /*!< EADC_T::INTSRC2: SPLIE2 Position */ 1842 #define EADC_INTSRC2_SPLIE2_Msk (0x1ul << EADC_INTSRC2_SPLIE2_Pos) /*!< EADC_T::INTSRC2: SPLIE2 Mask */ 1843 1844 #define EADC_INTSRC2_SPLIE3_Pos (3) /*!< EADC_T::INTSRC2: SPLIE3 Position */ 1845 #define EADC_INTSRC2_SPLIE3_Msk (0x1ul << EADC_INTSRC2_SPLIE3_Pos) /*!< EADC_T::INTSRC2: SPLIE3 Mask */ 1846 1847 #define EADC_INTSRC2_SPLIE4_Pos (4) /*!< EADC_T::INTSRC2: SPLIE4 Position */ 1848 #define EADC_INTSRC2_SPLIE4_Msk (0x1ul << EADC_INTSRC2_SPLIE4_Pos) /*!< EADC_T::INTSRC2: SPLIE4 Mask */ 1849 1850 #define EADC_INTSRC2_SPLIE5_Pos (5) /*!< EADC_T::INTSRC2: SPLIE5 Position */ 1851 #define EADC_INTSRC2_SPLIE5_Msk (0x1ul << EADC_INTSRC2_SPLIE5_Pos) /*!< EADC_T::INTSRC2: SPLIE5 Mask */ 1852 1853 #define EADC_INTSRC2_SPLIE6_Pos (6) /*!< EADC_T::INTSRC2: SPLIE6 Position */ 1854 #define EADC_INTSRC2_SPLIE6_Msk (0x1ul << EADC_INTSRC2_SPLIE6_Pos) /*!< EADC_T::INTSRC2: SPLIE6 Mask */ 1855 1856 #define EADC_INTSRC2_SPLIE7_Pos (7) /*!< EADC_T::INTSRC2: SPLIE7 Position */ 1857 #define EADC_INTSRC2_SPLIE7_Msk (0x1ul << EADC_INTSRC2_SPLIE7_Pos) /*!< EADC_T::INTSRC2: SPLIE7 Mask */ 1858 1859 #define EADC_INTSRC2_SPLIE8_Pos (8) /*!< EADC_T::INTSRC2: SPLIE8 Position */ 1860 #define EADC_INTSRC2_SPLIE8_Msk (0x1ul << EADC_INTSRC2_SPLIE8_Pos) /*!< EADC_T::INTSRC2: SPLIE8 Mask */ 1861 1862 #define EADC_INTSRC2_SPLIE9_Pos (9) /*!< EADC_T::INTSRC2: SPLIE9 Position */ 1863 #define EADC_INTSRC2_SPLIE9_Msk (0x1ul << EADC_INTSRC2_SPLIE9_Pos) /*!< EADC_T::INTSRC2: SPLIE9 Mask */ 1864 1865 #define EADC_INTSRC2_SPLIE10_Pos (10) /*!< EADC_T::INTSRC2: SPLIE10 Position */ 1866 #define EADC_INTSRC2_SPLIE10_Msk (0x1ul << EADC_INTSRC2_SPLIE10_Pos) /*!< EADC_T::INTSRC2: SPLIE10 Mask */ 1867 1868 #define EADC_INTSRC2_SPLIE11_Pos (11) /*!< EADC_T::INTSRC2: SPLIE11 Position */ 1869 #define EADC_INTSRC2_SPLIE11_Msk (0x1ul << EADC_INTSRC2_SPLIE11_Pos) /*!< EADC_T::INTSRC2: SPLIE11 Mask */ 1870 1871 #define EADC_INTSRC2_SPLIE12_Pos (12) /*!< EADC_T::INTSRC2: SPLIE12 Position */ 1872 #define EADC_INTSRC2_SPLIE12_Msk (0x1ul << EADC_INTSRC2_SPLIE12_Pos) /*!< EADC_T::INTSRC2: SPLIE12 Mask */ 1873 1874 #define EADC_INTSRC2_SPLIE13_Pos (13) /*!< EADC_T::INTSRC2: SPLIE13 Position */ 1875 #define EADC_INTSRC2_SPLIE13_Msk (0x1ul << EADC_INTSRC2_SPLIE13_Pos) /*!< EADC_T::INTSRC2: SPLIE13 Mask */ 1876 1877 #define EADC_INTSRC2_SPLIE14_Pos (14) /*!< EADC_T::INTSRC2: SPLIE14 Position */ 1878 #define EADC_INTSRC2_SPLIE14_Msk (0x1ul << EADC_INTSRC2_SPLIE14_Pos) /*!< EADC_T::INTSRC2: SPLIE14 Mask */ 1879 1880 #define EADC_INTSRC2_SPLIE15_Pos (15) /*!< EADC_T::INTSRC2: SPLIE15 Position */ 1881 #define EADC_INTSRC2_SPLIE15_Msk (0x1ul << EADC_INTSRC2_SPLIE15_Pos) /*!< EADC_T::INTSRC2: SPLIE15 Mask */ 1882 1883 #define EADC_INTSRC2_SPLIE16_Pos (16) /*!< EADC_T::INTSRC2: SPLIE16 Position */ 1884 #define EADC_INTSRC2_SPLIE16_Msk (0x1ul << EADC_INTSRC2_SPLIE16_Pos) /*!< EADC_T::INTSRC2: SPLIE16 Mask */ 1885 1886 #define EADC_INTSRC2_SPLIE17_Pos (17) /*!< EADC_T::INTSRC2: SPLIE17 Position */ 1887 #define EADC_INTSRC2_SPLIE17_Msk (0x1ul << EADC_INTSRC2_SPLIE17_Pos) /*!< EADC_T::INTSRC2: SPLIE17 Mask */ 1888 1889 #define EADC_INTSRC2_SPLIE18_Pos (18) /*!< EADC_T::INTSRC2: SPLIE18 Position */ 1890 #define EADC_INTSRC2_SPLIE18_Msk (0x1ul << EADC_INTSRC2_SPLIE18_Pos) /*!< EADC_T::INTSRC2: SPLIE18 Mask */ 1891 1892 #define EADC_INTSRC2_SPLIE19_Pos (19) /*!< EADC_T::INTSRC2: SPLIE19 Position */ 1893 #define EADC_INTSRC2_SPLIE19_Msk (0x1ul << EADC_INTSRC2_SPLIE19_Pos) /*!< EADC_T::INTSRC2: SPLIE19 Mask */ 1894 1895 #define EADC_INTSRC2_SPLIE20_Pos (20) /*!< EADC_T::INTSRC2: SPLIE20 Position */ 1896 #define EADC_INTSRC2_SPLIE20_Msk (0x1ul << EADC_INTSRC2_SPLIE20_Pos) /*!< EADC_T::INTSRC2: SPLIE20 Mask */ 1897 1898 #define EADC_INTSRC2_SPLIE21_Pos (21) /*!< EADC_T::INTSRC2: SPLIE21 Position */ 1899 #define EADC_INTSRC2_SPLIE21_Msk (0x1ul << EADC_INTSRC2_SPLIE21_Pos) /*!< EADC_T::INTSRC2: SPLIE21 Mask */ 1900 1901 #define EADC_INTSRC2_SPLIE22_Pos (22) /*!< EADC_T::INTSRC2: SPLIE22 Position */ 1902 #define EADC_INTSRC2_SPLIE22_Msk (0x1ul << EADC_INTSRC2_SPLIE22_Pos) /*!< EADC_T::INTSRC2: SPLIE22 Mask */ 1903 1904 #define EADC_INTSRC2_SPLIE23_Pos (23) /*!< EADC_T::INTSRC2: SPLIE23 Position */ 1905 #define EADC_INTSRC2_SPLIE23_Msk (0x1ul << EADC_INTSRC2_SPLIE23_Pos) /*!< EADC_T::INTSRC2: SPLIE23 Mask */ 1906 1907 #define EADC_INTSRC2_SPLIE24_Pos (24) /*!< EADC_T::INTSRC2: SPLIE24 Position */ 1908 #define EADC_INTSRC2_SPLIE24_Msk (0x1ul << EADC_INTSRC2_SPLIE24_Pos) /*!< EADC_T::INTSRC2: SPLIE24 Mask */ 1909 1910 #define EADC_INTSRC2_SPLIE25_Pos (25) /*!< EADC_T::INTSRC2: SPLIE25 Position */ 1911 #define EADC_INTSRC2_SPLIE25_Msk (0x1ul << EADC_INTSRC2_SPLIE25_Pos) /*!< EADC_T::INTSRC2: SPLIE25 Mask */ 1912 1913 #define EADC_INTSRC2_SPLIE26_Pos (26) /*!< EADC_T::INTSRC2: SPLIE26 Position */ 1914 #define EADC_INTSRC2_SPLIE26_Msk (0x1ul << EADC_INTSRC2_SPLIE26_Pos) /*!< EADC_T::INTSRC2: SPLIE26 Mask */ 1915 1916 #define EADC_INTSRC2_SPLIE27_Pos (27) /*!< EADC_T::INTSRC2: SPLIE27 Position */ 1917 #define EADC_INTSRC2_SPLIE27_Msk (0x1ul << EADC_INTSRC2_SPLIE27_Pos) /*!< EADC_T::INTSRC2: SPLIE27 Mask */ 1918 1919 #define EADC_INTSRC2_SPLIE28_Pos (28) /*!< EADC_T::INTSRC2: SPLIE28 Position */ 1920 #define EADC_INTSRC2_SPLIE28_Msk (0x1ul << EADC_INTSRC2_SPLIE28_Pos) /*!< EADC_T::INTSRC2: SPLIE28 Mask */ 1921 1922 #define EADC_INTSRC2_SPLIE29_Pos (29) /*!< EADC_T::INTSRC2: SPLIE29 Position */ 1923 #define EADC_INTSRC2_SPLIE29_Msk (0x1ul << EADC_INTSRC2_SPLIE29_Pos) /*!< EADC_T::INTSRC2: SPLIE29 Mask */ 1924 1925 #define EADC_INTSRC2_SPLIE30_Pos (30) /*!< EADC_T::INTSRC2: SPLIE30 Position */ 1926 #define EADC_INTSRC2_SPLIE30_Msk (0x1ul << EADC_INTSRC2_SPLIE30_Pos) /*!< EADC_T::INTSRC2: SPLIE30 Mask */ 1927 1928 #define EADC_INTSRC3_SPLIE0_Pos (0) /*!< EADC_T::INTSRC3: SPLIE0 Position */ 1929 #define EADC_INTSRC3_SPLIE0_Msk (0x1ul << EADC_INTSRC3_SPLIE0_Pos) /*!< EADC_T::INTSRC3: SPLIE0 Mask */ 1930 1931 #define EADC_INTSRC3_SPLIE1_Pos (1) /*!< EADC_T::INTSRC3: SPLIE1 Position */ 1932 #define EADC_INTSRC3_SPLIE1_Msk (0x1ul << EADC_INTSRC3_SPLIE1_Pos) /*!< EADC_T::INTSRC3: SPLIE1 Mask */ 1933 1934 #define EADC_INTSRC3_SPLIE2_Pos (2) /*!< EADC_T::INTSRC3: SPLIE2 Position */ 1935 #define EADC_INTSRC3_SPLIE2_Msk (0x1ul << EADC_INTSRC3_SPLIE2_Pos) /*!< EADC_T::INTSRC3: SPLIE2 Mask */ 1936 1937 #define EADC_INTSRC3_SPLIE3_Pos (3) /*!< EADC_T::INTSRC3: SPLIE3 Position */ 1938 #define EADC_INTSRC3_SPLIE3_Msk (0x1ul << EADC_INTSRC3_SPLIE3_Pos) /*!< EADC_T::INTSRC3: SPLIE3 Mask */ 1939 1940 #define EADC_INTSRC3_SPLIE4_Pos (4) /*!< EADC_T::INTSRC3: SPLIE4 Position */ 1941 #define EADC_INTSRC3_SPLIE4_Msk (0x1ul << EADC_INTSRC3_SPLIE4_Pos) /*!< EADC_T::INTSRC3: SPLIE4 Mask */ 1942 1943 #define EADC_INTSRC3_SPLIE5_Pos (5) /*!< EADC_T::INTSRC3: SPLIE5 Position */ 1944 #define EADC_INTSRC3_SPLIE5_Msk (0x1ul << EADC_INTSRC3_SPLIE5_Pos) /*!< EADC_T::INTSRC3: SPLIE5 Mask */ 1945 1946 #define EADC_INTSRC3_SPLIE6_Pos (6) /*!< EADC_T::INTSRC3: SPLIE6 Position */ 1947 #define EADC_INTSRC3_SPLIE6_Msk (0x1ul << EADC_INTSRC3_SPLIE6_Pos) /*!< EADC_T::INTSRC3: SPLIE6 Mask */ 1948 1949 #define EADC_INTSRC3_SPLIE7_Pos (7) /*!< EADC_T::INTSRC3: SPLIE7 Position */ 1950 #define EADC_INTSRC3_SPLIE7_Msk (0x1ul << EADC_INTSRC3_SPLIE7_Pos) /*!< EADC_T::INTSRC3: SPLIE7 Mask */ 1951 1952 #define EADC_INTSRC3_SPLIE8_Pos (8) /*!< EADC_T::INTSRC3: SPLIE8 Position */ 1953 #define EADC_INTSRC3_SPLIE8_Msk (0x1ul << EADC_INTSRC3_SPLIE8_Pos) /*!< EADC_T::INTSRC3: SPLIE8 Mask */ 1954 1955 #define EADC_INTSRC3_SPLIE9_Pos (9) /*!< EADC_T::INTSRC3: SPLIE9 Position */ 1956 #define EADC_INTSRC3_SPLIE9_Msk (0x1ul << EADC_INTSRC3_SPLIE9_Pos) /*!< EADC_T::INTSRC3: SPLIE9 Mask */ 1957 1958 #define EADC_INTSRC3_SPLIE10_Pos (10) /*!< EADC_T::INTSRC3: SPLIE10 Position */ 1959 #define EADC_INTSRC3_SPLIE10_Msk (0x1ul << EADC_INTSRC3_SPLIE10_Pos) /*!< EADC_T::INTSRC3: SPLIE10 Mask */ 1960 1961 #define EADC_INTSRC3_SPLIE11_Pos (11) /*!< EADC_T::INTSRC3: SPLIE11 Position */ 1962 #define EADC_INTSRC3_SPLIE11_Msk (0x1ul << EADC_INTSRC3_SPLIE11_Pos) /*!< EADC_T::INTSRC3: SPLIE11 Mask */ 1963 1964 #define EADC_INTSRC3_SPLIE12_Pos (12) /*!< EADC_T::INTSRC3: SPLIE12 Position */ 1965 #define EADC_INTSRC3_SPLIE12_Msk (0x1ul << EADC_INTSRC3_SPLIE12_Pos) /*!< EADC_T::INTSRC3: SPLIE12 Mask */ 1966 1967 #define EADC_INTSRC3_SPLIE13_Pos (13) /*!< EADC_T::INTSRC3: SPLIE13 Position */ 1968 #define EADC_INTSRC3_SPLIE13_Msk (0x1ul << EADC_INTSRC3_SPLIE13_Pos) /*!< EADC_T::INTSRC3: SPLIE13 Mask */ 1969 1970 #define EADC_INTSRC3_SPLIE14_Pos (14) /*!< EADC_T::INTSRC3: SPLIE14 Position */ 1971 #define EADC_INTSRC3_SPLIE14_Msk (0x1ul << EADC_INTSRC3_SPLIE14_Pos) /*!< EADC_T::INTSRC3: SPLIE14 Mask */ 1972 1973 #define EADC_INTSRC3_SPLIE15_Pos (15) /*!< EADC_T::INTSRC3: SPLIE15 Position */ 1974 #define EADC_INTSRC3_SPLIE15_Msk (0x1ul << EADC_INTSRC3_SPLIE15_Pos) /*!< EADC_T::INTSRC3: SPLIE15 Mask */ 1975 1976 #define EADC_INTSRC3_SPLIE16_Pos (16) /*!< EADC_T::INTSRC3: SPLIE16 Position */ 1977 #define EADC_INTSRC3_SPLIE16_Msk (0x1ul << EADC_INTSRC3_SPLIE16_Pos) /*!< EADC_T::INTSRC3: SPLIE16 Mask */ 1978 1979 #define EADC_INTSRC3_SPLIE17_Pos (17) /*!< EADC_T::INTSRC3: SPLIE17 Position */ 1980 #define EADC_INTSRC3_SPLIE17_Msk (0x1ul << EADC_INTSRC3_SPLIE17_Pos) /*!< EADC_T::INTSRC3: SPLIE17 Mask */ 1981 1982 #define EADC_INTSRC3_SPLIE18_Pos (18) /*!< EADC_T::INTSRC3: SPLIE18 Position */ 1983 #define EADC_INTSRC3_SPLIE18_Msk (0x1ul << EADC_INTSRC3_SPLIE18_Pos) /*!< EADC_T::INTSRC3: SPLIE18 Mask */ 1984 1985 #define EADC_INTSRC3_SPLIE19_Pos (19) /*!< EADC_T::INTSRC3: SPLIE19 Position */ 1986 #define EADC_INTSRC3_SPLIE19_Msk (0x1ul << EADC_INTSRC3_SPLIE19_Pos) /*!< EADC_T::INTSRC3: SPLIE19 Mask */ 1987 1988 #define EADC_INTSRC3_SPLIE20_Pos (20) /*!< EADC_T::INTSRC3: SPLIE20 Position */ 1989 #define EADC_INTSRC3_SPLIE20_Msk (0x1ul << EADC_INTSRC3_SPLIE20_Pos) /*!< EADC_T::INTSRC3: SPLIE20 Mask */ 1990 1991 #define EADC_INTSRC3_SPLIE21_Pos (21) /*!< EADC_T::INTSRC3: SPLIE21 Position */ 1992 #define EADC_INTSRC3_SPLIE21_Msk (0x1ul << EADC_INTSRC3_SPLIE21_Pos) /*!< EADC_T::INTSRC3: SPLIE21 Mask */ 1993 1994 #define EADC_INTSRC3_SPLIE22_Pos (22) /*!< EADC_T::INTSRC3: SPLIE22 Position */ 1995 #define EADC_INTSRC3_SPLIE22_Msk (0x1ul << EADC_INTSRC3_SPLIE22_Pos) /*!< EADC_T::INTSRC3: SPLIE22 Mask */ 1996 1997 #define EADC_INTSRC3_SPLIE23_Pos (23) /*!< EADC_T::INTSRC3: SPLIE23 Position */ 1998 #define EADC_INTSRC3_SPLIE23_Msk (0x1ul << EADC_INTSRC3_SPLIE23_Pos) /*!< EADC_T::INTSRC3: SPLIE23 Mask */ 1999 2000 #define EADC_INTSRC3_SPLIE24_Pos (24) /*!< EADC_T::INTSRC3: SPLIE24 Position */ 2001 #define EADC_INTSRC3_SPLIE24_Msk (0x1ul << EADC_INTSRC3_SPLIE24_Pos) /*!< EADC_T::INTSRC3: SPLIE24 Mask */ 2002 2003 #define EADC_INTSRC3_SPLIE25_Pos (25) /*!< EADC_T::INTSRC3: SPLIE25 Position */ 2004 #define EADC_INTSRC3_SPLIE25_Msk (0x1ul << EADC_INTSRC3_SPLIE25_Pos) /*!< EADC_T::INTSRC3: SPLIE25 Mask */ 2005 2006 #define EADC_INTSRC3_SPLIE26_Pos (26) /*!< EADC_T::INTSRC3: SPLIE26 Position */ 2007 #define EADC_INTSRC3_SPLIE26_Msk (0x1ul << EADC_INTSRC3_SPLIE26_Pos) /*!< EADC_T::INTSRC3: SPLIE26 Mask */ 2008 2009 #define EADC_INTSRC3_SPLIE27_Pos (27) /*!< EADC_T::INTSRC3: SPLIE27 Position */ 2010 #define EADC_INTSRC3_SPLIE27_Msk (0x1ul << EADC_INTSRC3_SPLIE27_Pos) /*!< EADC_T::INTSRC3: SPLIE27 Mask */ 2011 2012 #define EADC_INTSRC3_SPLIE28_Pos (28) /*!< EADC_T::INTSRC3: SPLIE28 Position */ 2013 #define EADC_INTSRC3_SPLIE28_Msk (0x1ul << EADC_INTSRC3_SPLIE28_Pos) /*!< EADC_T::INTSRC3: SPLIE28 Mask */ 2014 2015 #define EADC_INTSRC3_SPLIE29_Pos (29) /*!< EADC_T::INTSRC3: SPLIE29 Position */ 2016 #define EADC_INTSRC3_SPLIE29_Msk (0x1ul << EADC_INTSRC3_SPLIE29_Pos) /*!< EADC_T::INTSRC3: SPLIE29 Mask */ 2017 2018 #define EADC_INTSRC3_SPLIE30_Pos (30) /*!< EADC_T::INTSRC3: SPLIE30 Position */ 2019 #define EADC_INTSRC3_SPLIE30_Msk (0x1ul << EADC_INTSRC3_SPLIE30_Pos) /*!< EADC_T::INTSRC3: SPLIE30 Mask */ 2020 2021 #define EADC_CMP_ADCMPEN_Pos (0) /*!< EADC_T::CMP0: ADCMPEN Position */ 2022 #define EADC_CMP_ADCMPEN_Msk (0x1ul << EADC_CMP_ADCMPEN_Pos) /*!< EADC_T::CMP0: ADCMPEN Mask */ 2023 2024 #define EADC_CMP_ADCMPIE_Pos (1) /*!< EADC_T::CMP0: ADCMPIE Position */ 2025 #define EADC_CMP_ADCMPIE_Msk (0x1ul << EADC_CMP_ADCMPIE_Pos) /*!< EADC_T::CMP0: ADCMPIE Mask */ 2026 2027 #define EADC_CMP_CMPCOND_Pos (2) /*!< EADC_T::CMP0: CMPCOND Position */ 2028 #define EADC_CMP_CMPCOND_Msk (0x1ul << EADC_CMP_CMPCOND_Pos) /*!< EADC_T::CMP0: CMPCOND Mask */ 2029 2030 #define EADC_CMP_CMPSPL_Pos (3) /*!< EADC_T::CMP0: CMPSPL Position */ 2031 #define EADC_CMP_CMPSPL_Msk (0x1ful << EADC_CMP_CMPSPL_Pos) /*!< EADC_T::CMP0: CMPSPL Mask */ 2032 2033 #define EADC_CMP_CMPMCNT_Pos (8) /*!< EADC_T::CMP0: CMPMCNT Position */ 2034 #define EADC_CMP_CMPMCNT_Msk (0xful << EADC_CMP_CMPMCNT_Pos) /*!< EADC_T::CMP0: CMPMCNT Mask */ 2035 2036 #define EADC_CMP_CMPWEN_Pos (15) /*!< EADC_T::CMP0: CMPWEN Position */ 2037 #define EADC_CMP_CMPWEN_Msk (0x1ul << EADC_CMP_CMPWEN_Pos) /*!< EADC_T::CMP0: CMPWEN Mask */ 2038 2039 #define EADC_CMP_CMPDAT_Pos (16) /*!< EADC_T::CMP0: CMPDAT Position */ 2040 #define EADC_CMP_CMPDAT_Msk (0xffful << EADC_CMP_CMPDAT_Pos) /*!< EADC_T::CMP0: CMPDAT Mask */ 2041 2042 #define EADC_CMP0_ADCMPEN_Pos (0) /*!< EADC_T::CMP0: ADCMPEN Position */ 2043 #define EADC_CMP0_ADCMPEN_Msk (0x1ul << EADC_CMP0_ADCMPEN_Pos) /*!< EADC_T::CMP0: ADCMPEN Mask */ 2044 2045 #define EADC_CMP0_ADCMPIE_Pos (1) /*!< EADC_T::CMP0: ADCMPIE Position */ 2046 #define EADC_CMP0_ADCMPIE_Msk (0x1ul << EADC_CMP0_ADCMPIE_Pos) /*!< EADC_T::CMP0: ADCMPIE Mask */ 2047 2048 #define EADC_CMP0_CMPCOND_Pos (2) /*!< EADC_T::CMP0: CMPCOND Position */ 2049 #define EADC_CMP0_CMPCOND_Msk (0x1ul << EADC_CMP0_CMPCOND_Pos) /*!< EADC_T::CMP0: CMPCOND Mask */ 2050 2051 #define EADC_CMP0_CMPSPL_Pos (3) /*!< EADC_T::CMP0: CMPSPL Position */ 2052 #define EADC_CMP0_CMPSPL_Msk (0x1ful << EADC_CMP0_CMPSPL_Pos) /*!< EADC_T::CMP0: CMPSPL Mask */ 2053 2054 #define EADC_CMP0_CMPMCNT_Pos (8) /*!< EADC_T::CMP0: CMPMCNT Position */ 2055 #define EADC_CMP0_CMPMCNT_Msk (0xful << EADC_CMP0_CMPMCNT_Pos) /*!< EADC_T::CMP0: CMPMCNT Mask */ 2056 2057 #define EADC_CMP0_CMPWEN_Pos (15) /*!< EADC_T::CMP0: CMPWEN Position */ 2058 #define EADC_CMP0_CMPWEN_Msk (0x1ul << EADC_CMP0_CMPWEN_Pos) /*!< EADC_T::CMP0: CMPWEN Mask */ 2059 2060 #define EADC_CMP0_CMPDAT_Pos (16) /*!< EADC_T::CMP0: CMPDAT Position */ 2061 #define EADC_CMP0_CMPDAT_Msk (0xffful << EADC_CMP0_CMPDAT_Pos) /*!< EADC_T::CMP0: CMPDAT Mask */ 2062 2063 #define EADC_CMP1_ADCMPEN_Pos (0) /*!< EADC_T::CMP1: ADCMPEN Position */ 2064 #define EADC_CMP1_ADCMPEN_Msk (0x1ul << EADC_CMP1_ADCMPEN_Pos) /*!< EADC_T::CMP1: ADCMPEN Mask */ 2065 2066 #define EADC_CMP1_ADCMPIE_Pos (1) /*!< EADC_T::CMP1: ADCMPIE Position */ 2067 #define EADC_CMP1_ADCMPIE_Msk (0x1ul << EADC_CMP1_ADCMPIE_Pos) /*!< EADC_T::CMP1: ADCMPIE Mask */ 2068 2069 #define EADC_CMP1_CMPCOND_Pos (2) /*!< EADC_T::CMP1: CMPCOND Position */ 2070 #define EADC_CMP1_CMPCOND_Msk (0x1ul << EADC_CMP1_CMPCOND_Pos) /*!< EADC_T::CMP1: CMPCOND Mask */ 2071 2072 #define EADC_CMP1_CMPSPL_Pos (3) /*!< EADC_T::CMP1: CMPSPL Position */ 2073 #define EADC_CMP1_CMPSPL_Msk (0x1ful << EADC_CMP1_CMPSPL_Pos) /*!< EADC_T::CMP1: CMPSPL Mask */ 2074 2075 #define EADC_CMP1_CMPMCNT_Pos (8) /*!< EADC_T::CMP1: CMPMCNT Position */ 2076 #define EADC_CMP1_CMPMCNT_Msk (0xful << EADC_CMP1_CMPMCNT_Pos) /*!< EADC_T::CMP1: CMPMCNT Mask */ 2077 2078 #define EADC_CMP1_CMPWEN_Pos (15) /*!< EADC_T::CMP1: CMPWEN Position */ 2079 #define EADC_CMP1_CMPWEN_Msk (0x1ul << EADC_CMP1_CMPWEN_Pos) /*!< EADC_T::CMP1: CMPWEN Mask */ 2080 2081 #define EADC_CMP1_CMPDAT_Pos (16) /*!< EADC_T::CMP1: CMPDAT Position */ 2082 #define EADC_CMP1_CMPDAT_Msk (0xffful << EADC_CMP1_CMPDAT_Pos) /*!< EADC_T::CMP1: CMPDAT Mask */ 2083 2084 #define EADC_CMP2_ADCMPEN_Pos (0) /*!< EADC_T::CMP2: ADCMPEN Position */ 2085 #define EADC_CMP2_ADCMPEN_Msk (0x1ul << EADC_CMP2_ADCMPEN_Pos) /*!< EADC_T::CMP2: ADCMPEN Mask */ 2086 2087 #define EADC_CMP2_ADCMPIE_Pos (1) /*!< EADC_T::CMP2: ADCMPIE Position */ 2088 #define EADC_CMP2_ADCMPIE_Msk (0x1ul << EADC_CMP2_ADCMPIE_Pos) /*!< EADC_T::CMP2: ADCMPIE Mask */ 2089 2090 #define EADC_CMP2_CMPCOND_Pos (2) /*!< EADC_T::CMP2: CMPCOND Position */ 2091 #define EADC_CMP2_CMPCOND_Msk (0x1ul << EADC_CMP2_CMPCOND_Pos) /*!< EADC_T::CMP2: CMPCOND Mask */ 2092 2093 #define EADC_CMP2_CMPSPL_Pos (3) /*!< EADC_T::CMP2: CMPSPL Position */ 2094 #define EADC_CMP2_CMPSPL_Msk (0x1ful << EADC_CMP2_CMPSPL_Pos) /*!< EADC_T::CMP2: CMPSPL Mask */ 2095 2096 #define EADC_CMP2_CMPMCNT_Pos (8) /*!< EADC_T::CMP2: CMPMCNT Position */ 2097 #define EADC_CMP2_CMPMCNT_Msk (0xful << EADC_CMP2_CMPMCNT_Pos) /*!< EADC_T::CMP2: CMPMCNT Mask */ 2098 2099 #define EADC_CMP2_CMPWEN_Pos (15) /*!< EADC_T::CMP2: CMPWEN Position */ 2100 #define EADC_CMP2_CMPWEN_Msk (0x1ul << EADC_CMP2_CMPWEN_Pos) /*!< EADC_T::CMP2: CMPWEN Mask */ 2101 2102 #define EADC_CMP2_CMPDAT_Pos (16) /*!< EADC_T::CMP2: CMPDAT Position */ 2103 #define EADC_CMP2_CMPDAT_Msk (0xffful << EADC_CMP2_CMPDAT_Pos) /*!< EADC_T::CMP2: CMPDAT Mask */ 2104 2105 #define EADC_CMP3_ADCMPEN_Pos (0) /*!< EADC_T::CMP3: ADCMPEN Position */ 2106 #define EADC_CMP3_ADCMPEN_Msk (0x1ul << EADC_CMP3_ADCMPEN_Pos) /*!< EADC_T::CMP3: ADCMPEN Mask */ 2107 2108 #define EADC_CMP3_ADCMPIE_Pos (1) /*!< EADC_T::CMP3: ADCMPIE Position */ 2109 #define EADC_CMP3_ADCMPIE_Msk (0x1ul << EADC_CMP3_ADCMPIE_Pos) /*!< EADC_T::CMP3: ADCMPIE Mask */ 2110 2111 #define EADC_CMP3_CMPCOND_Pos (2) /*!< EADC_T::CMP3: CMPCOND Position */ 2112 #define EADC_CMP3_CMPCOND_Msk (0x1ul << EADC_CMP3_CMPCOND_Pos) /*!< EADC_T::CMP3: CMPCOND Mask */ 2113 2114 #define EADC_CMP3_CMPSPL_Pos (3) /*!< EADC_T::CMP3: CMPSPL Position */ 2115 #define EADC_CMP3_CMPSPL_Msk (0x1ful << EADC_CMP3_CMPSPL_Pos) /*!< EADC_T::CMP3: CMPSPL Mask */ 2116 2117 #define EADC_CMP3_CMPMCNT_Pos (8) /*!< EADC_T::CMP3: CMPMCNT Position */ 2118 #define EADC_CMP3_CMPMCNT_Msk (0xful << EADC_CMP3_CMPMCNT_Pos) /*!< EADC_T::CMP3: CMPMCNT Mask */ 2119 2120 #define EADC_CMP3_CMPWEN_Pos (15) /*!< EADC_T::CMP3: CMPWEN Position */ 2121 #define EADC_CMP3_CMPWEN_Msk (0x1ul << EADC_CMP3_CMPWEN_Pos) /*!< EADC_T::CMP3: CMPWEN Mask */ 2122 2123 #define EADC_CMP3_CMPDAT_Pos (16) /*!< EADC_T::CMP3: CMPDAT Position */ 2124 #define EADC_CMP3_CMPDAT_Msk (0xffful << EADC_CMP3_CMPDAT_Pos) /*!< EADC_T::CMP3: CMPDAT Mask */ 2125 2126 #define EADC_STATUS0_VALID_Pos (0) /*!< EADC_T::STATUS0: VALID Position */ 2127 #define EADC_STATUS0_VALID_Msk (0xfffful << EADC_STATUS0_VALID_Pos) /*!< EADC_T::STATUS0: VALID Mask */ 2128 2129 #define EADC_STATUS0_OV_Pos (16) /*!< EADC_T::STATUS0: OV Position */ 2130 #define EADC_STATUS0_OV_Msk (0xfffful << EADC_STATUS0_OV_Pos) /*!< EADC_T::STATUS0: OV Mask */ 2131 2132 #define EADC_STATUS1_VALID_Pos (0) /*!< EADC_T::STATUS1: VALID Position */ 2133 #define EADC_STATUS1_VALID_Msk (0x7ffful << EADC_STATUS1_VALID_Pos) /*!< EADC_T::STATUS1: VALID Mask */ 2134 2135 #define EADC_STATUS1_OV_Pos (16) /*!< EADC_T::STATUS1: OV Position */ 2136 #define EADC_STATUS1_OV_Msk (0x7ffful << EADC_STATUS1_OV_Pos) /*!< EADC_T::STATUS1: OV Mask */ 2137 2138 #define EADC_STATUS2_ADIF0_Pos (0) /*!< EADC_T::STATUS2: ADIF0 Position */ 2139 #define EADC_STATUS2_ADIF0_Msk (0x1ul << EADC_STATUS2_ADIF0_Pos) /*!< EADC_T::STATUS2: ADIF0 Mask */ 2140 2141 #define EADC_STATUS2_ADIF1_Pos (1) /*!< EADC_T::STATUS2: ADIF1 Position */ 2142 #define EADC_STATUS2_ADIF1_Msk (0x1ul << EADC_STATUS2_ADIF1_Pos) /*!< EADC_T::STATUS2: ADIF1 Mask */ 2143 2144 #define EADC_STATUS2_ADIF2_Pos (2) /*!< EADC_T::STATUS2: ADIF2 Position */ 2145 #define EADC_STATUS2_ADIF2_Msk (0x1ul << EADC_STATUS2_ADIF2_Pos) /*!< EADC_T::STATUS2: ADIF2 Mask */ 2146 2147 #define EADC_STATUS2_ADIF3_Pos (3) /*!< EADC_T::STATUS2: ADIF3 Position */ 2148 #define EADC_STATUS2_ADIF3_Msk (0x1ul << EADC_STATUS2_ADIF3_Pos) /*!< EADC_T::STATUS2: ADIF3 Mask */ 2149 2150 #define EADC_STATUS2_ADCMPF0_Pos (4) /*!< EADC_T::STATUS2: ADCMPF0 Position */ 2151 #define EADC_STATUS2_ADCMPF0_Msk (0x1ul << EADC_STATUS2_ADCMPF0_Pos) /*!< EADC_T::STATUS2: ADCMPF0 Mask */ 2152 2153 #define EADC_STATUS2_ADCMPF1_Pos (5) /*!< EADC_T::STATUS2: ADCMPF1 Position */ 2154 #define EADC_STATUS2_ADCMPF1_Msk (0x1ul << EADC_STATUS2_ADCMPF1_Pos) /*!< EADC_T::STATUS2: ADCMPF1 Mask */ 2155 2156 #define EADC_STATUS2_ADCMPF2_Pos (6) /*!< EADC_T::STATUS2: ADCMPF2 Position */ 2157 #define EADC_STATUS2_ADCMPF2_Msk (0x1ul << EADC_STATUS2_ADCMPF2_Pos) /*!< EADC_T::STATUS2: ADCMPF2 Mask */ 2158 2159 #define EADC_STATUS2_ADCMPF3_Pos (7) /*!< EADC_T::STATUS2: ADCMPF3 Position */ 2160 #define EADC_STATUS2_ADCMPF3_Msk (0x1ul << EADC_STATUS2_ADCMPF3_Pos) /*!< EADC_T::STATUS2: ADCMPF3 Mask */ 2161 2162 #define EADC_STATUS2_ADOVIF0_Pos (8) /*!< EADC_T::STATUS2: ADOVIF0 Position */ 2163 #define EADC_STATUS2_ADOVIF0_Msk (0x1ul << EADC_STATUS2_ADOVIF0_Pos) /*!< EADC_T::STATUS2: ADOVIF0 Mask */ 2164 2165 #define EADC_STATUS2_ADOVIF1_Pos (9) /*!< EADC_T::STATUS2: ADOVIF1 Position */ 2166 #define EADC_STATUS2_ADOVIF1_Msk (0x1ul << EADC_STATUS2_ADOVIF1_Pos) /*!< EADC_T::STATUS2: ADOVIF1 Mask */ 2167 2168 #define EADC_STATUS2_ADOVIF2_Pos (10) /*!< EADC_T::STATUS2: ADOVIF2 Position */ 2169 #define EADC_STATUS2_ADOVIF2_Msk (0x1ul << EADC_STATUS2_ADOVIF2_Pos) /*!< EADC_T::STATUS2: ADOVIF2 Mask */ 2170 2171 #define EADC_STATUS2_ADOVIF3_Pos (11) /*!< EADC_T::STATUS2: ADOVIF3 Position */ 2172 #define EADC_STATUS2_ADOVIF3_Msk (0x1ul << EADC_STATUS2_ADOVIF3_Pos) /*!< EADC_T::STATUS2: ADOVIF3 Mask */ 2173 2174 #define EADC_STATUS2_ADCMPO0_Pos (12) /*!< EADC_T::STATUS2: ADCMPO0 Position */ 2175 #define EADC_STATUS2_ADCMPO0_Msk (0x1ul << EADC_STATUS2_ADCMPO0_Pos) /*!< EADC_T::STATUS2: ADCMPO0 Mask */ 2176 2177 #define EADC_STATUS2_ADCMPO1_Pos (13) /*!< EADC_T::STATUS2: ADCMPO1 Position */ 2178 #define EADC_STATUS2_ADCMPO1_Msk (0x1ul << EADC_STATUS2_ADCMPO1_Pos) /*!< EADC_T::STATUS2: ADCMPO1 Mask */ 2179 2180 #define EADC_STATUS2_ADCMPO2_Pos (14) /*!< EADC_T::STATUS2: ADCMPO2 Position */ 2181 #define EADC_STATUS2_ADCMPO2_Msk (0x1ul << EADC_STATUS2_ADCMPO2_Pos) /*!< EADC_T::STATUS2: ADCMPO2 Mask */ 2182 2183 #define EADC_STATUS2_ADCMPO3_Pos (15) /*!< EADC_T::STATUS2: ADCMPO3 Position */ 2184 #define EADC_STATUS2_ADCMPO3_Msk (0x1ul << EADC_STATUS2_ADCMPO3_Pos) /*!< EADC_T::STATUS2: ADCMPO3 Mask */ 2185 2186 #define EADC_STATUS2_CHANNEL_Pos (16) /*!< EADC_T::STATUS2: CHANNEL Position */ 2187 #define EADC_STATUS2_CHANNEL_Msk (0x1ful << EADC_STATUS2_CHANNEL_Pos) /*!< EADC_T::STATUS2: CHANNEL Mask */ 2188 2189 #define EADC_STATUS2_BUSY_Pos (23) /*!< EADC_T::STATUS2: BUSY Position */ 2190 #define EADC_STATUS2_BUSY_Msk (0x1ul << EADC_STATUS2_BUSY_Pos) /*!< EADC_T::STATUS2: BUSY Mask */ 2191 2192 #define EADC_STATUS2_ADOVIF_Pos (24) /*!< EADC_T::STATUS2: ADOVIF Position */ 2193 #define EADC_STATUS2_ADOVIF_Msk (0x1ul << EADC_STATUS2_ADOVIF_Pos) /*!< EADC_T::STATUS2: ADOVIF Mask */ 2194 2195 #define EADC_STATUS2_STOVF_Pos (25) /*!< EADC_T::STATUS2: STOVF Position */ 2196 #define EADC_STATUS2_STOVF_Msk (0x1ul << EADC_STATUS2_STOVF_Pos) /*!< EADC_T::STATUS2: STOVF Mask */ 2197 2198 #define EADC_STATUS2_AVALID_Pos (26) /*!< EADC_T::STATUS2: AVALID Position */ 2199 #define EADC_STATUS2_AVALID_Msk (0x1ul << EADC_STATUS2_AVALID_Pos) /*!< EADC_T::STATUS2: AVALID Mask */ 2200 2201 #define EADC_STATUS2_AOV_Pos (27) /*!< EADC_T::STATUS2: AOV Position */ 2202 #define EADC_STATUS2_AOV_Msk (0x1ul << EADC_STATUS2_AOV_Pos) /*!< EADC_T::STATUS2: AOV Mask */ 2203 2204 #define EADC_STATUS3_CURSPL_Pos (0) /*!< EADC_T::STATUS3: CURSPL Position */ 2205 #define EADC_STATUS3_CURSPL_Msk (0x1ful << EADC_STATUS3_CURSPL_Pos) /*!< EADC_T::STATUS3: CURSPL Mask */ 2206 2207 #define EADC_DDAT0_RESULT_Pos (0) /*!< EADC_T::DDAT0: RESULT Position */ 2208 #define EADC_DDAT0_RESULT_Msk (0xfffful << EADC_DDAT0_RESULT_Pos) /*!< EADC_T::DDAT0: RESULT Mask */ 2209 2210 #define EADC_DDAT0_OV_Pos (16) /*!< EADC_T::DDAT0: OV Position */ 2211 #define EADC_DDAT0_OV_Msk (0x1ul << EADC_DDAT0_OV_Pos) /*!< EADC_T::DDAT0: OV Mask */ 2212 2213 #define EADC_DDAT0_VALID_Pos (17) /*!< EADC_T::DDAT0: VALID Position */ 2214 #define EADC_DDAT0_VALID_Msk (0x1ul << EADC_DDAT0_VALID_Pos) /*!< EADC_T::DDAT0: VALID Mask */ 2215 2216 #define EADC_DDAT1_RESULT_Pos (0) /*!< EADC_T::DDAT1: RESULT Position */ 2217 #define EADC_DDAT1_RESULT_Msk (0xfffful << EADC_DDAT1_RESULT_Pos) /*!< EADC_T::DDAT1: RESULT Mask */ 2218 2219 #define EADC_DDAT1_OV_Pos (16) /*!< EADC_T::DDAT1: OV Position */ 2220 #define EADC_DDAT1_OV_Msk (0x1ul << EADC_DDAT1_OV_Pos) /*!< EADC_T::DDAT1: OV Mask */ 2221 2222 #define EADC_DDAT1_VALID_Pos (17) /*!< EADC_T::DDAT1: VALID Position */ 2223 #define EADC_DDAT1_VALID_Msk (0x1ul << EADC_DDAT1_VALID_Pos) /*!< EADC_T::DDAT1: VALID Mask */ 2224 2225 #define EADC_DDAT2_RESULT_Pos (0) /*!< EADC_T::DDAT2: RESULT Position */ 2226 #define EADC_DDAT2_RESULT_Msk (0xfffful << EADC_DDAT2_RESULT_Pos) /*!< EADC_T::DDAT2: RESULT Mask */ 2227 2228 #define EADC_DDAT2_OV_Pos (16) /*!< EADC_T::DDAT2: OV Position */ 2229 #define EADC_DDAT2_OV_Msk (0x1ul << EADC_DDAT2_OV_Pos) /*!< EADC_T::DDAT2: OV Mask */ 2230 2231 #define EADC_DDAT2_VALID_Pos (17) /*!< EADC_T::DDAT2: VALID Position */ 2232 #define EADC_DDAT2_VALID_Msk (0x1ul << EADC_DDAT2_VALID_Pos) /*!< EADC_T::DDAT2: VALID Mask */ 2233 2234 #define EADC_DDAT3_RESULT_Pos (0) /*!< EADC_T::DDAT3: RESULT Position */ 2235 #define EADC_DDAT3_RESULT_Msk (0xfffful << EADC_DDAT3_RESULT_Pos) /*!< EADC_T::DDAT3: RESULT Mask */ 2236 2237 #define EADC_DDAT3_OV_Pos (16) /*!< EADC_T::DDAT3: OV Position */ 2238 #define EADC_DDAT3_OV_Msk (0x1ul << EADC_DDAT3_OV_Pos) /*!< EADC_T::DDAT3: OV Mask */ 2239 2240 #define EADC_DDAT3_VALID_Pos (17) /*!< EADC_T::DDAT3: VALID Position */ 2241 #define EADC_DDAT3_VALID_Msk (0x1ul << EADC_DDAT3_VALID_Pos) /*!< EADC_T::DDAT3: VALID Mask */ 2242 2243 #define EADC_CALCTL_CAL_Pos (0) /*!< EADC_T::CALCTL: CAL Position */ 2244 #define EADC_CALCTL_CAL_Msk (0x1ul << EADC_CALCTL_CAL_Pos) /*!< EADC_T::CALCTL: CAL Mask */ 2245 2246 #define EADC_CALCTL_CALIE_Pos (1) /*!< EADC_T::CALCTL: CALIE Position */ 2247 #define EADC_CALCTL_CALIE_Msk (0x1ul << EADC_CALCTL_CALIE_Pos) /*!< EADC_T::CALCTL: CALIE Mask */ 2248 2249 #define EADC_CALSR_CALIF_Pos (16) /*!< EADC_T::CALSR: CALIF Position */ 2250 #define EADC_CALSR_CALIF_Msk (0x1ul << EADC_CALSR_CALIF_Pos) /*!< EADC_T::CALSR: CALIF Mask */ 2251 2252 #define EADC_PDMACTL_PDMATEN_Pos (0) /*!< EADC_T::PDMACTL: PDMATEN Position */ 2253 #define EADC_PDMACTL_PDMATEN_Msk (0x7ffffffful << EADC_PDMACTL_PDMATEN_Pos) /*!< EADC_T::PDMACTL: PDMATEN Mask */ 2254 2255 #define EADC_MCTL1_ALIGN_Pos (0) /*!< EADC_T::M0CTL1: ALIGN Position */ 2256 #define EADC_MCTL1_ALIGN_Msk (0x1ul << EADC_MCTL1_ALIGN_Pos) /*!< EADC_T::M0CTL1: ALIGN Mask */ 2257 2258 #define EADC_MCTL1_AVG_Pos (1) /*!< EADC_T::M0CTL1: AVG Position */ 2259 #define EADC_MCTL1_AVG_Msk (0x1ul << EADC_MCTL1_AVG_Pos) /*!< EADC_T::M0CTL1: AVG Mask */ 2260 2261 #define EADC_MCTL1_ACU_Pos (4) /*!< EADC_T::M0CTL1: ACU Position */ 2262 #define EADC_MCTL1_ACU_Msk (0xful << EADC_MCTL1_ACU_Pos) /*!< EADC_T::M0CTL1: ACU Mask */ 2263 2264 #define EADC_MCTL1_EXTSTDIV_Pos (16) /*!< EADC_T::M0CTL1: EXTSTDIV Position */ 2265 #define EADC_MCTL1_EXTSTDIV_Msk (0x3ul << EADC_MCTL1_EXTSTDIV_Pos) /*!< EADC_T::M0CTL1: EXTSTDIV Mask */ 2266 2267 #define EADC_MCTL1_DBMEN_Pos (20) /*!< EADC_T::M0CTL1: DBMEN Position */ 2268 #define EADC_MCTL1_DBMEN_Msk (0x1ul << EADC_MCTL1_DBMEN_Pos) /*!< EADC_T::M0CTL1: DBMEN Mask */ 2269 2270 #define EADC_M0CTL1_ALIGN_Pos (0) /*!< EADC_T::M0CTL1: ALIGN Position */ 2271 #define EADC_M0CTL1_ALIGN_Msk (0x1ul << EADC_M0CTL1_ALIGN_Pos) /*!< EADC_T::M0CTL1: ALIGN Mask */ 2272 2273 #define EADC_M0CTL1_AVG_Pos (1) /*!< EADC_T::M0CTL1: AVG Position */ 2274 #define EADC_M0CTL1_AVG_Msk (0x1ul << EADC_M0CTL1_AVG_Pos) /*!< EADC_T::M0CTL1: AVG Mask */ 2275 2276 #define EADC_M0CTL1_ACU_Pos (4) /*!< EADC_T::M0CTL1: ACU Position */ 2277 #define EADC_M0CTL1_ACU_Msk (0xful << EADC_M0CTL1_ACU_Pos) /*!< EADC_T::M0CTL1: ACU Mask */ 2278 2279 #define EADC_M0CTL1_EXTSTDIV_Pos (16) /*!< EADC_T::M0CTL1: EXTSTDIV Position */ 2280 #define EADC_M0CTL1_EXTSTDIV_Msk (0x3ul << EADC_M0CTL1_EXTSTDIV_Pos) /*!< EADC_T::M0CTL1: EXTSTDIV Mask */ 2281 2282 #define EADC_M0CTL1_DBMEN_Pos (20) /*!< EADC_T::M0CTL1: DBMEN Position */ 2283 #define EADC_M0CTL1_DBMEN_Msk (0x1ul << EADC_M0CTL1_DBMEN_Pos) /*!< EADC_T::M0CTL1: DBMEN Mask */ 2284 2285 #define EADC_M1CTL1_ALIGN_Pos (0) /*!< EADC_T::M1CTL1: ALIGN Position */ 2286 #define EADC_M1CTL1_ALIGN_Msk (0x1ul << EADC_M1CTL1_ALIGN_Pos) /*!< EADC_T::M1CTL1: ALIGN Mask */ 2287 2288 #define EADC_M1CTL1_AVG_Pos (1) /*!< EADC_T::M1CTL1: AVG Position */ 2289 #define EADC_M1CTL1_AVG_Msk (0x1ul << EADC_M1CTL1_AVG_Pos) /*!< EADC_T::M1CTL1: AVG Mask */ 2290 2291 #define EADC_M1CTL1_ACU_Pos (4) /*!< EADC_T::M1CTL1: ACU Position */ 2292 #define EADC_M1CTL1_ACU_Msk (0xful << EADC_M1CTL1_ACU_Pos) /*!< EADC_T::M1CTL1: ACU Mask */ 2293 2294 #define EADC_M1CTL1_EXTSTDIV_Pos (16) /*!< EADC_T::M1CTL1: EXTSTDIV Position */ 2295 #define EADC_M1CTL1_EXTSTDIV_Msk (0x3ul << EADC_M1CTL1_EXTSTDIV_Pos) /*!< EADC_T::M1CTL1: EXTSTDIV Mask */ 2296 2297 #define EADC_M1CTL1_DBMEN_Pos (20) /*!< EADC_T::M1CTL1: DBMEN Position */ 2298 #define EADC_M1CTL1_DBMEN_Msk (0x1ul << EADC_M1CTL1_DBMEN_Pos) /*!< EADC_T::M1CTL1: DBMEN Mask */ 2299 2300 #define EADC_M2CTL1_ALIGN_Pos (0) /*!< EADC_T::M2CTL1: ALIGN Position */ 2301 #define EADC_M2CTL1_ALIGN_Msk (0x1ul << EADC_M2CTL1_ALIGN_Pos) /*!< EADC_T::M2CTL1: ALIGN Mask */ 2302 2303 #define EADC_M2CTL1_AVG_Pos (1) /*!< EADC_T::M2CTL1: AVG Position */ 2304 #define EADC_M2CTL1_AVG_Msk (0x1ul << EADC_M2CTL1_AVG_Pos) /*!< EADC_T::M2CTL1: AVG Mask */ 2305 2306 #define EADC_M2CTL1_ACU_Pos (4) /*!< EADC_T::M2CTL1: ACU Position */ 2307 #define EADC_M2CTL1_ACU_Msk (0xful << EADC_M2CTL1_ACU_Pos) /*!< EADC_T::M2CTL1: ACU Mask */ 2308 2309 #define EADC_M2CTL1_EXTSTDIV_Pos (16) /*!< EADC_T::M2CTL1: EXTSTDIV Position */ 2310 #define EADC_M2CTL1_EXTSTDIV_Msk (0x3ul << EADC_M2CTL1_EXTSTDIV_Pos) /*!< EADC_T::M2CTL1: EXTSTDIV Mask */ 2311 2312 #define EADC_M2CTL1_DBMEN_Pos (20) /*!< EADC_T::M2CTL1: DBMEN Position */ 2313 #define EADC_M2CTL1_DBMEN_Msk (0x1ul << EADC_M2CTL1_DBMEN_Pos) /*!< EADC_T::M2CTL1: DBMEN Mask */ 2314 2315 #define EADC_M3CTL1_ALIGN_Pos (0) /*!< EADC_T::M3CTL1: ALIGN Position */ 2316 #define EADC_M3CTL1_ALIGN_Msk (0x1ul << EADC_M3CTL1_ALIGN_Pos) /*!< EADC_T::M3CTL1: ALIGN Mask */ 2317 2318 #define EADC_M3CTL1_AVG_Pos (1) /*!< EADC_T::M3CTL1: AVG Position */ 2319 #define EADC_M3CTL1_AVG_Msk (0x1ul << EADC_M3CTL1_AVG_Pos) /*!< EADC_T::M3CTL1: AVG Mask */ 2320 2321 #define EADC_M3CTL1_ACU_Pos (4) /*!< EADC_T::M3CTL1: ACU Position */ 2322 #define EADC_M3CTL1_ACU_Msk (0xful << EADC_M3CTL1_ACU_Pos) /*!< EADC_T::M3CTL1: ACU Mask */ 2323 2324 #define EADC_M3CTL1_EXTSTDIV_Pos (16) /*!< EADC_T::M3CTL1: EXTSTDIV Position */ 2325 #define EADC_M3CTL1_EXTSTDIV_Msk (0x3ul << EADC_M3CTL1_EXTSTDIV_Pos) /*!< EADC_T::M3CTL1: EXTSTDIV Mask */ 2326 2327 #define EADC_M3CTL1_DBMEN_Pos (20) /*!< EADC_T::M3CTL1: DBMEN Position */ 2328 #define EADC_M3CTL1_DBMEN_Msk (0x1ul << EADC_M3CTL1_DBMEN_Pos) /*!< EADC_T::M3CTL1: DBMEN Mask */ 2329 2330 #define EADC_M4CTL1_ALIGN_Pos (0) /*!< EADC_T::M4CTL1: ALIGN Position */ 2331 #define EADC_M4CTL1_ALIGN_Msk (0x1ul << EADC_M4CTL1_ALIGN_Pos) /*!< EADC_T::M4CTL1: ALIGN Mask */ 2332 2333 #define EADC_M4CTL1_AVG_Pos (1) /*!< EADC_T::M4CTL1: AVG Position */ 2334 #define EADC_M4CTL1_AVG_Msk (0x1ul << EADC_M4CTL1_AVG_Pos) /*!< EADC_T::M4CTL1: AVG Mask */ 2335 2336 #define EADC_M4CTL1_ACU_Pos (4) /*!< EADC_T::M4CTL1: ACU Position */ 2337 #define EADC_M4CTL1_ACU_Msk (0xful << EADC_M4CTL1_ACU_Pos) /*!< EADC_T::M4CTL1: ACU Mask */ 2338 2339 #define EADC_M4CTL1_EXTSTDIV_Pos (16) /*!< EADC_T::M4CTL1: EXTSTDIV Position */ 2340 #define EADC_M4CTL1_EXTSTDIV_Msk (0x3ul << EADC_M4CTL1_EXTSTDIV_Pos) /*!< EADC_T::M4CTL1: EXTSTDIV Mask */ 2341 2342 #define EADC_M5CTL1_ALIGN_Pos (0) /*!< EADC_T::M5CTL1: ALIGN Position */ 2343 #define EADC_M5CTL1_ALIGN_Msk (0x1ul << EADC_M5CTL1_ALIGN_Pos) /*!< EADC_T::M5CTL1: ALIGN Mask */ 2344 2345 #define EADC_M5CTL1_AVG_Pos (1) /*!< EADC_T::M5CTL1: AVG Position */ 2346 #define EADC_M5CTL1_AVG_Msk (0x1ul << EADC_M5CTL1_AVG_Pos) /*!< EADC_T::M5CTL1: AVG Mask */ 2347 2348 #define EADC_M5CTL1_ACU_Pos (4) /*!< EADC_T::M5CTL1: ACU Position */ 2349 #define EADC_M5CTL1_ACU_Msk (0xful << EADC_M5CTL1_ACU_Pos) /*!< EADC_T::M5CTL1: ACU Mask */ 2350 2351 #define EADC_M5CTL1_EXTSTDIV_Pos (16) /*!< EADC_T::M5CTL1: EXTSTDIV Position */ 2352 #define EADC_M5CTL1_EXTSTDIV_Msk (0x3ul << EADC_M5CTL1_EXTSTDIV_Pos) /*!< EADC_T::M5CTL1: EXTSTDIV Mask */ 2353 2354 #define EADC_M6CTL1_ALIGN_Pos (0) /*!< EADC_T::M6CTL1: ALIGN Position */ 2355 #define EADC_M6CTL1_ALIGN_Msk (0x1ul << EADC_M6CTL1_ALIGN_Pos) /*!< EADC_T::M6CTL1: ALIGN Mask */ 2356 2357 #define EADC_M6CTL1_AVG_Pos (1) /*!< EADC_T::M6CTL1: AVG Position */ 2358 #define EADC_M6CTL1_AVG_Msk (0x1ul << EADC_M6CTL1_AVG_Pos) /*!< EADC_T::M6CTL1: AVG Mask */ 2359 2360 #define EADC_M6CTL1_ACU_Pos (4) /*!< EADC_T::M6CTL1: ACU Position */ 2361 #define EADC_M6CTL1_ACU_Msk (0xful << EADC_M6CTL1_ACU_Pos) /*!< EADC_T::M6CTL1: ACU Mask */ 2362 2363 #define EADC_M6CTL1_EXTSTDIV_Pos (16) /*!< EADC_T::M6CTL1: EXTSTDIV Position */ 2364 #define EADC_M6CTL1_EXTSTDIV_Msk (0x3ul << EADC_M6CTL1_EXTSTDIV_Pos) /*!< EADC_T::M6CTL1: EXTSTDIV Mask */ 2365 2366 #define EADC_M7CTL1_ALIGN_Pos (0) /*!< EADC_T::M7CTL1: ALIGN Position */ 2367 #define EADC_M7CTL1_ALIGN_Msk (0x1ul << EADC_M7CTL1_ALIGN_Pos) /*!< EADC_T::M7CTL1: ALIGN Mask */ 2368 2369 #define EADC_M7CTL1_AVG_Pos (1) /*!< EADC_T::M7CTL1: AVG Position */ 2370 #define EADC_M7CTL1_AVG_Msk (0x1ul << EADC_M7CTL1_AVG_Pos) /*!< EADC_T::M7CTL1: AVG Mask */ 2371 2372 #define EADC_M7CTL1_ACU_Pos (4) /*!< EADC_T::M7CTL1: ACU Position */ 2373 #define EADC_M7CTL1_ACU_Msk (0xful << EADC_M7CTL1_ACU_Pos) /*!< EADC_T::M7CTL1: ACU Mask */ 2374 2375 #define EADC_M7CTL1_EXTSTDIV_Pos (16) /*!< EADC_T::M7CTL1: EXTSTDIV Position */ 2376 #define EADC_M7CTL1_EXTSTDIV_Msk (0x3ul << EADC_M7CTL1_EXTSTDIV_Pos) /*!< EADC_T::M7CTL1: EXTSTDIV Mask */ 2377 2378 #define EADC_M8CTL1_ALIGN_Pos (0) /*!< EADC_T::M8CTL1: ALIGN Position */ 2379 #define EADC_M8CTL1_ALIGN_Msk (0x1ul << EADC_M8CTL1_ALIGN_Pos) /*!< EADC_T::M8CTL1: ALIGN Mask */ 2380 2381 #define EADC_M8CTL1_AVG_Pos (1) /*!< EADC_T::M8CTL1: AVG Position */ 2382 #define EADC_M8CTL1_AVG_Msk (0x1ul << EADC_M8CTL1_AVG_Pos) /*!< EADC_T::M8CTL1: AVG Mask */ 2383 2384 #define EADC_M8CTL1_ACU_Pos (4) /*!< EADC_T::M8CTL1: ACU Position */ 2385 #define EADC_M8CTL1_ACU_Msk (0xful << EADC_M8CTL1_ACU_Pos) /*!< EADC_T::M8CTL1: ACU Mask */ 2386 2387 #define EADC_M8CTL1_EXTSTDIV_Pos (16) /*!< EADC_T::M8CTL1: EXTSTDIV Position */ 2388 #define EADC_M8CTL1_EXTSTDIV_Msk (0x3ul << EADC_M8CTL1_EXTSTDIV_Pos) /*!< EADC_T::M8CTL1: EXTSTDIV Mask */ 2389 2390 #define EADC_M9CTL1_ALIGN_Pos (0) /*!< EADC_T::M9CTL1: ALIGN Position */ 2391 #define EADC_M9CTL1_ALIGN_Msk (0x1ul << EADC_M9CTL1_ALIGN_Pos) /*!< EADC_T::M9CTL1: ALIGN Mask */ 2392 2393 #define EADC_M9CTL1_AVG_Pos (1) /*!< EADC_T::M9CTL1: AVG Position */ 2394 #define EADC_M9CTL1_AVG_Msk (0x1ul << EADC_M9CTL1_AVG_Pos) /*!< EADC_T::M9CTL1: AVG Mask */ 2395 2396 #define EADC_M9CTL1_ACU_Pos (4) /*!< EADC_T::M9CTL1: ACU Position */ 2397 #define EADC_M9CTL1_ACU_Msk (0xful << EADC_M9CTL1_ACU_Pos) /*!< EADC_T::M9CTL1: ACU Mask */ 2398 2399 #define EADC_M9CTL1_EXTSTDIV_Pos (16) /*!< EADC_T::M9CTL1: EXTSTDIV Position */ 2400 #define EADC_M9CTL1_EXTSTDIV_Msk (0x3ul << EADC_M9CTL1_EXTSTDIV_Pos) /*!< EADC_T::M9CTL1: EXTSTDIV Mask */ 2401 2402 #define EADC_M10CTL1_ALIGN_Pos (0) /*!< EADC_T::M10CTL1: ALIGN Position */ 2403 #define EADC_M10CTL1_ALIGN_Msk (0x1ul << EADC_M10CTL1_ALIGN_Pos) /*!< EADC_T::M10CTL1: ALIGN Mask */ 2404 2405 #define EADC_M10CTL1_AVG_Pos (1) /*!< EADC_T::M10CTL1: AVG Position */ 2406 #define EADC_M10CTL1_AVG_Msk (0x1ul << EADC_M10CTL1_AVG_Pos) /*!< EADC_T::M10CTL1: AVG Mask */ 2407 2408 #define EADC_M10CTL1_ACU_Pos (4) /*!< EADC_T::M10CTL1: ACU Position */ 2409 #define EADC_M10CTL1_ACU_Msk (0xful << EADC_M10CTL1_ACU_Pos) /*!< EADC_T::M10CTL1: ACU Mask */ 2410 2411 #define EADC_M10CTL1_EXTSTDIV_Pos (16) /*!< EADC_T::M10CTL1: EXTSTDIV Position */ 2412 #define EADC_M10CTL1_EXTSTDIV_Msk (0x3ul << EADC_M10CTL1_EXTSTDIV_Pos) /*!< EADC_T::M10CTL1: EXTSTDIV Mask */ 2413 2414 #define EADC_M11CTL1_ALIGN_Pos (0) /*!< EADC_T::M11CTL1: ALIGN Position */ 2415 #define EADC_M11CTL1_ALIGN_Msk (0x1ul << EADC_M11CTL1_ALIGN_Pos) /*!< EADC_T::M11CTL1: ALIGN Mask */ 2416 2417 #define EADC_M11CTL1_AVG_Pos (1) /*!< EADC_T::M11CTL1: AVG Position */ 2418 #define EADC_M11CTL1_AVG_Msk (0x1ul << EADC_M11CTL1_AVG_Pos) /*!< EADC_T::M11CTL1: AVG Mask */ 2419 2420 #define EADC_M11CTL1_ACU_Pos (4) /*!< EADC_T::M11CTL1: ACU Position */ 2421 #define EADC_M11CTL1_ACU_Msk (0xful << EADC_M11CTL1_ACU_Pos) /*!< EADC_T::M11CTL1: ACU Mask */ 2422 2423 #define EADC_M11CTL1_EXTSTDIV_Pos (16) /*!< EADC_T::M11CTL1: EXTSTDIV Position */ 2424 #define EADC_M11CTL1_EXTSTDIV_Msk (0x3ul << EADC_M11CTL1_EXTSTDIV_Pos) /*!< EADC_T::M11CTL1: EXTSTDIV Mask */ 2425 2426 #define EADC_M12CTL1_ALIGN_Pos (0) /*!< EADC_T::M12CTL1: ALIGN Position */ 2427 #define EADC_M12CTL1_ALIGN_Msk (0x1ul << EADC_M12CTL1_ALIGN_Pos) /*!< EADC_T::M12CTL1: ALIGN Mask */ 2428 2429 #define EADC_M12CTL1_AVG_Pos (1) /*!< EADC_T::M12CTL1: AVG Position */ 2430 #define EADC_M12CTL1_AVG_Msk (0x1ul << EADC_M12CTL1_AVG_Pos) /*!< EADC_T::M12CTL1: AVG Mask */ 2431 2432 #define EADC_M12CTL1_ACU_Pos (4) /*!< EADC_T::M12CTL1: ACU Position */ 2433 #define EADC_M12CTL1_ACU_Msk (0xful << EADC_M12CTL1_ACU_Pos) /*!< EADC_T::M12CTL1: ACU Mask */ 2434 2435 #define EADC_M12CTL1_EXTSTDIV_Pos (16) /*!< EADC_T::M12CTL1: EXTSTDIV Position */ 2436 #define EADC_M12CTL1_EXTSTDIV_Msk (0x3ul << EADC_M12CTL1_EXTSTDIV_Pos) /*!< EADC_T::M12CTL1: EXTSTDIV Mask */ 2437 2438 #define EADC_M13CTL1_ALIGN_Pos (0) /*!< EADC_T::M13CTL1: ALIGN Position */ 2439 #define EADC_M13CTL1_ALIGN_Msk (0x1ul << EADC_M13CTL1_ALIGN_Pos) /*!< EADC_T::M13CTL1: ALIGN Mask */ 2440 2441 #define EADC_M13CTL1_AVG_Pos (1) /*!< EADC_T::M13CTL1: AVG Position */ 2442 #define EADC_M13CTL1_AVG_Msk (0x1ul << EADC_M13CTL1_AVG_Pos) /*!< EADC_T::M13CTL1: AVG Mask */ 2443 2444 #define EADC_M13CTL1_ACU_Pos (4) /*!< EADC_T::M13CTL1: ACU Position */ 2445 #define EADC_M13CTL1_ACU_Msk (0xful << EADC_M13CTL1_ACU_Pos) /*!< EADC_T::M13CTL1: ACU Mask */ 2446 2447 #define EADC_M13CTL1_EXTSTDIV_Pos (16) /*!< EADC_T::M13CTL1: EXTSTDIV Position */ 2448 #define EADC_M13CTL1_EXTSTDIV_Msk (0x3ul << EADC_M13CTL1_EXTSTDIV_Pos) /*!< EADC_T::M13CTL1: EXTSTDIV Mask */ 2449 2450 #define EADC_M14CTL1_ALIGN_Pos (0) /*!< EADC_T::M14CTL1: ALIGN Position */ 2451 #define EADC_M14CTL1_ALIGN_Msk (0x1ul << EADC_M14CTL1_ALIGN_Pos) /*!< EADC_T::M14CTL1: ALIGN Mask */ 2452 2453 #define EADC_M14CTL1_AVG_Pos (1) /*!< EADC_T::M14CTL1: AVG Position */ 2454 #define EADC_M14CTL1_AVG_Msk (0x1ul << EADC_M14CTL1_AVG_Pos) /*!< EADC_T::M14CTL1: AVG Mask */ 2455 2456 #define EADC_M14CTL1_ACU_Pos (4) /*!< EADC_T::M14CTL1: ACU Position */ 2457 #define EADC_M14CTL1_ACU_Msk (0xful << EADC_M14CTL1_ACU_Pos) /*!< EADC_T::M14CTL1: ACU Mask */ 2458 2459 #define EADC_M14CTL1_EXTSTDIV_Pos (16) /*!< EADC_T::M14CTL1: EXTSTDIV Position */ 2460 #define EADC_M14CTL1_EXTSTDIV_Msk (0x3ul << EADC_M14CTL1_EXTSTDIV_Pos) /*!< EADC_T::M14CTL1: EXTSTDIV Mask */ 2461 2462 #define EADC_M15CTL1_ALIGN_Pos (0) /*!< EADC_T::M15CTL1: ALIGN Position */ 2463 #define EADC_M15CTL1_ALIGN_Msk (0x1ul << EADC_M15CTL1_ALIGN_Pos) /*!< EADC_T::M15CTL1: ALIGN Mask */ 2464 2465 #define EADC_M15CTL1_AVG_Pos (1) /*!< EADC_T::M15CTL1: AVG Position */ 2466 #define EADC_M15CTL1_AVG_Msk (0x1ul << EADC_M15CTL1_AVG_Pos) /*!< EADC_T::M15CTL1: AVG Mask */ 2467 2468 #define EADC_M15CTL1_ACU_Pos (4) /*!< EADC_T::M15CTL1: ACU Position */ 2469 #define EADC_M15CTL1_ACU_Msk (0xful << EADC_M15CTL1_ACU_Pos) /*!< EADC_T::M15CTL1: ACU Mask */ 2470 2471 #define EADC_M15CTL1_EXTSTDIV_Pos (16) /*!< EADC_T::M15CTL1: EXTSTDIV Position */ 2472 #define EADC_M15CTL1_EXTSTDIV_Msk (0x3ul << EADC_M15CTL1_EXTSTDIV_Pos) /*!< EADC_T::M15CTL1: EXTSTDIV Mask */ 2473 2474 #define EADC_M16CTL1_ALIGN_Pos (0) /*!< EADC_T::M16CTL1: ALIGN Position */ 2475 #define EADC_M16CTL1_ALIGN_Msk (0x1ul << EADC_M16CTL1_ALIGN_Pos) /*!< EADC_T::M16CTL1: ALIGN Mask */ 2476 2477 #define EADC_M16CTL1_AVG_Pos (1) /*!< EADC_T::M16CTL1: AVG Position */ 2478 #define EADC_M16CTL1_AVG_Msk (0x1ul << EADC_M16CTL1_AVG_Pos) /*!< EADC_T::M16CTL1: AVG Mask */ 2479 2480 #define EADC_M16CTL1_ACU_Pos (4) /*!< EADC_T::M16CTL1: ACU Position */ 2481 #define EADC_M16CTL1_ACU_Msk (0xful << EADC_M16CTL1_ACU_Pos) /*!< EADC_T::M16CTL1: ACU Mask */ 2482 2483 #define EADC_M16CTL1_EXTSTDIV_Pos (16) /*!< EADC_T::M16CTL1: EXTSTDIV Position */ 2484 #define EADC_M16CTL1_EXTSTDIV_Msk (0x3ul << EADC_M16CTL1_EXTSTDIV_Pos) /*!< EADC_T::M16CTL1: EXTSTDIV Mask */ 2485 2486 #define EADC_M17CTL1_ALIGN_Pos (0) /*!< EADC_T::M17CTL1: ALIGN Position */ 2487 #define EADC_M17CTL1_ALIGN_Msk (0x1ul << EADC_M17CTL1_ALIGN_Pos) /*!< EADC_T::M17CTL1: ALIGN Mask */ 2488 2489 #define EADC_M17CTL1_AVG_Pos (1) /*!< EADC_T::M17CTL1: AVG Position */ 2490 #define EADC_M17CTL1_AVG_Msk (0x1ul << EADC_M17CTL1_AVG_Pos) /*!< EADC_T::M17CTL1: AVG Mask */ 2491 2492 #define EADC_M17CTL1_ACU_Pos (4) /*!< EADC_T::M17CTL1: ACU Position */ 2493 #define EADC_M17CTL1_ACU_Msk (0xful << EADC_M17CTL1_ACU_Pos) /*!< EADC_T::M17CTL1: ACU Mask */ 2494 2495 #define EADC_M17CTL1_EXTSTDIV_Pos (16) /*!< EADC_T::M17CTL1: EXTSTDIV Position */ 2496 #define EADC_M17CTL1_EXTSTDIV_Msk (0x3ul << EADC_M17CTL1_EXTSTDIV_Pos) /*!< EADC_T::M17CTL1: EXTSTDIV Mask */ 2497 2498 #define EADC_M18CTL1_ALIGN_Pos (0) /*!< EADC_T::M18CTL1: ALIGN Position */ 2499 #define EADC_M18CTL1_ALIGN_Msk (0x1ul << EADC_M18CTL1_ALIGN_Pos) /*!< EADC_T::M18CTL1: ALIGN Mask */ 2500 2501 #define EADC_M18CTL1_AVG_Pos (1) /*!< EADC_T::M18CTL1: AVG Position */ 2502 #define EADC_M18CTL1_AVG_Msk (0x1ul << EADC_M18CTL1_AVG_Pos) /*!< EADC_T::M18CTL1: AVG Mask */ 2503 2504 #define EADC_M18CTL1_ACU_Pos (4) /*!< EADC_T::M18CTL1: ACU Position */ 2505 #define EADC_M18CTL1_ACU_Msk (0xful << EADC_M18CTL1_ACU_Pos) /*!< EADC_T::M18CTL1: ACU Mask */ 2506 2507 #define EADC_M18CTL1_EXTSTDIV_Pos (16) /*!< EADC_T::M18CTL1: EXTSTDIV Position */ 2508 #define EADC_M18CTL1_EXTSTDIV_Msk (0x3ul << EADC_M18CTL1_EXTSTDIV_Pos) /*!< EADC_T::M18CTL1: EXTSTDIV Mask */ 2509 2510 #define EADC_DAT19_RESULT_Pos (0) /*!< EADC_T::DAT19: RESULT Position */ 2511 #define EADC_DAT19_RESULT_Msk (0xfffful << EADC_DAT19_RESULT_Pos) /*!< EADC_T::DAT19: RESULT Mask */ 2512 2513 #define EADC_DAT19_OV_Pos (16) /*!< EADC_T::DAT19: OV Position */ 2514 #define EADC_DAT19_OV_Msk (0x1ul << EADC_DAT19_OV_Pos) /*!< EADC_T::DAT19: OV Mask */ 2515 2516 #define EADC_DAT19_VALID_Pos (17) /*!< EADC_T::DAT19: VALID Position */ 2517 #define EADC_DAT19_VALID_Msk (0x1ul << EADC_DAT19_VALID_Pos) /*!< EADC_T::DAT19: VALID Mask */ 2518 2519 #define EADC_DAT20_RESULT_Pos (0) /*!< EADC_T::DAT20: RESULT Position */ 2520 #define EADC_DAT20_RESULT_Msk (0xfffful << EADC_DAT20_RESULT_Pos) /*!< EADC_T::DAT20: RESULT Mask */ 2521 2522 #define EADC_DAT20_OV_Pos (16) /*!< EADC_T::DAT20: OV Position */ 2523 #define EADC_DAT20_OV_Msk (0x1ul << EADC_DAT20_OV_Pos) /*!< EADC_T::DAT20: OV Mask */ 2524 2525 #define EADC_DAT20_VALID_Pos (17) /*!< EADC_T::DAT20: VALID Position */ 2526 #define EADC_DAT20_VALID_Msk (0x1ul << EADC_DAT20_VALID_Pos) /*!< EADC_T::DAT20: VALID Mask */ 2527 2528 #define EADC_DAT21_RESULT_Pos (0) /*!< EADC_T::DAT21: RESULT Position */ 2529 #define EADC_DAT21_RESULT_Msk (0xfffful << EADC_DAT21_RESULT_Pos) /*!< EADC_T::DAT21: RESULT Mask */ 2530 2531 #define EADC_DAT21_OV_Pos (16) /*!< EADC_T::DAT21: OV Position */ 2532 #define EADC_DAT21_OV_Msk (0x1ul << EADC_DAT21_OV_Pos) /*!< EADC_T::DAT21: OV Mask */ 2533 2534 #define EADC_DAT21_VALID_Pos (17) /*!< EADC_T::DAT21: VALID Position */ 2535 #define EADC_DAT21_VALID_Msk (0x1ul << EADC_DAT21_VALID_Pos) /*!< EADC_T::DAT21: VALID Mask */ 2536 2537 #define EADC_DAT22_RESULT_Pos (0) /*!< EADC_T::DAT22: RESULT Position */ 2538 #define EADC_DAT22_RESULT_Msk (0xfffful << EADC_DAT22_RESULT_Pos) /*!< EADC_T::DAT22: RESULT Mask */ 2539 2540 #define EADC_DAT22_OV_Pos (16) /*!< EADC_T::DAT22: OV Position */ 2541 #define EADC_DAT22_OV_Msk (0x1ul << EADC_DAT22_OV_Pos) /*!< EADC_T::DAT22: OV Mask */ 2542 2543 #define EADC_DAT22_VALID_Pos (17) /*!< EADC_T::DAT22: VALID Position */ 2544 #define EADC_DAT22_VALID_Msk (0x1ul << EADC_DAT22_VALID_Pos) /*!< EADC_T::DAT22: VALID Mask */ 2545 2546 #define EADC_DAT23_RESULT_Pos (0) /*!< EADC_T::DAT23: RESULT Position */ 2547 #define EADC_DAT23_RESULT_Msk (0xfffful << EADC_DAT23_RESULT_Pos) /*!< EADC_T::DAT23: RESULT Mask */ 2548 2549 #define EADC_DAT23_OV_Pos (16) /*!< EADC_T::DAT23: OV Position */ 2550 #define EADC_DAT23_OV_Msk (0x1ul << EADC_DAT23_OV_Pos) /*!< EADC_T::DAT23: OV Mask */ 2551 2552 #define EADC_DAT23_VALID_Pos (17) /*!< EADC_T::DAT23: VALID Position */ 2553 #define EADC_DAT23_VALID_Msk (0x1ul << EADC_DAT23_VALID_Pos) /*!< EADC_T::DAT23: VALID Mask */ 2554 2555 #define EADC_DAT24_RESULT_Pos (0) /*!< EADC_T::DAT24: RESULT Position */ 2556 #define EADC_DAT24_RESULT_Msk (0xfffful << EADC_DAT24_RESULT_Pos) /*!< EADC_T::DAT24: RESULT Mask */ 2557 2558 #define EADC_DAT24_OV_Pos (16) /*!< EADC_T::DAT24: OV Position */ 2559 #define EADC_DAT24_OV_Msk (0x1ul << EADC_DAT24_OV_Pos) /*!< EADC_T::DAT24: OV Mask */ 2560 2561 #define EADC_DAT24_VALID_Pos (17) /*!< EADC_T::DAT24: VALID Position */ 2562 #define EADC_DAT24_VALID_Msk (0x1ul << EADC_DAT24_VALID_Pos) /*!< EADC_T::DAT24: VALID Mask */ 2563 2564 #define EADC_DAT25_RESULT_Pos (0) /*!< EADC_T::DAT25: RESULT Position */ 2565 #define EADC_DAT25_RESULT_Msk (0xfffful << EADC_DAT25_RESULT_Pos) /*!< EADC_T::DAT25: RESULT Mask */ 2566 2567 #define EADC_DAT25_OV_Pos (16) /*!< EADC_T::DAT25: OV Position */ 2568 #define EADC_DAT25_OV_Msk (0x1ul << EADC_DAT25_OV_Pos) /*!< EADC_T::DAT25: OV Mask */ 2569 2570 #define EADC_DAT25_VALID_Pos (17) /*!< EADC_T::DAT25: VALID Position */ 2571 #define EADC_DAT25_VALID_Msk (0x1ul << EADC_DAT25_VALID_Pos) /*!< EADC_T::DAT25: VALID Mask */ 2572 2573 #define EADC_DAT26_RESULT_Pos (0) /*!< EADC_T::DAT26: RESULT Position */ 2574 #define EADC_DAT26_RESULT_Msk (0xfffful << EADC_DAT26_RESULT_Pos) /*!< EADC_T::DAT26: RESULT Mask */ 2575 2576 #define EADC_DAT26_OV_Pos (16) /*!< EADC_T::DAT26: OV Position */ 2577 #define EADC_DAT26_OV_Msk (0x1ul << EADC_DAT26_OV_Pos) /*!< EADC_T::DAT26: OV Mask */ 2578 2579 #define EADC_DAT26_VALID_Pos (17) /*!< EADC_T::DAT26: VALID Position */ 2580 #define EADC_DAT26_VALID_Msk (0x1ul << EADC_DAT26_VALID_Pos) /*!< EADC_T::DAT26: VALID Mask */ 2581 2582 #define EADC_DAT27_RESULT_Pos (0) /*!< EADC_T::DAT27: RESULT Position */ 2583 #define EADC_DAT27_RESULT_Msk (0xfffful << EADC_DAT27_RESULT_Pos) /*!< EADC_T::DAT27: RESULT Mask */ 2584 2585 #define EADC_DAT27_OV_Pos (16) /*!< EADC_T::DAT27: OV Position */ 2586 #define EADC_DAT27_OV_Msk (0x1ul << EADC_DAT27_OV_Pos) /*!< EADC_T::DAT27: OV Mask */ 2587 2588 #define EADC_DAT27_VALID_Pos (17) /*!< EADC_T::DAT27: VALID Position */ 2589 #define EADC_DAT27_VALID_Msk (0x1ul << EADC_DAT27_VALID_Pos) /*!< EADC_T::DAT27: VALID Mask */ 2590 2591 #define EADC_DAT28_RESULT_Pos (0) /*!< EADC_T::DAT28: RESULT Position */ 2592 #define EADC_DAT28_RESULT_Msk (0xfffful << EADC_DAT28_RESULT_Pos) /*!< EADC_T::DAT28: RESULT Mask */ 2593 2594 #define EADC_DAT28_OV_Pos (16) /*!< EADC_T::DAT28: OV Position */ 2595 #define EADC_DAT28_OV_Msk (0x1ul << EADC_DAT28_OV_Pos) /*!< EADC_T::DAT28: OV Mask */ 2596 2597 #define EADC_DAT28_VALID_Pos (17) /*!< EADC_T::DAT28: VALID Position */ 2598 #define EADC_DAT28_VALID_Msk (0x1ul << EADC_DAT28_VALID_Pos) /*!< EADC_T::DAT28: VALID Mask */ 2599 2600 #define EADC_DAT29_RESULT_Pos (0) /*!< EADC_T::DAT29: RESULT Position */ 2601 #define EADC_DAT29_RESULT_Msk (0xfffful << EADC_DAT29_RESULT_Pos) /*!< EADC_T::DAT29: RESULT Mask */ 2602 2603 #define EADC_DAT29_OV_Pos (16) /*!< EADC_T::DAT29: OV Position */ 2604 #define EADC_DAT29_OV_Msk (0x1ul << EADC_DAT29_OV_Pos) /*!< EADC_T::DAT29: OV Mask */ 2605 2606 #define EADC_DAT29_VALID_Pos (17) /*!< EADC_T::DAT29: VALID Position */ 2607 #define EADC_DAT29_VALID_Msk (0x1ul << EADC_DAT29_VALID_Pos) /*!< EADC_T::DAT29: VALID Mask */ 2608 2609 #define EADC_DAT30_RESULT_Pos (0) /*!< EADC_T::DAT30: RESULT Position */ 2610 #define EADC_DAT30_RESULT_Msk (0xfffful << EADC_DAT30_RESULT_Pos) /*!< EADC_T::DAT30: RESULT Mask */ 2611 2612 #define EADC_DAT30_OV_Pos (16) /*!< EADC_T::DAT30: OV Position */ 2613 #define EADC_DAT30_OV_Msk (0x1ul << EADC_DAT30_OV_Pos) /*!< EADC_T::DAT30: OV Mask */ 2614 2615 #define EADC_DAT30_VALID_Pos (17) /*!< EADC_T::DAT30: VALID Position */ 2616 #define EADC_DAT30_VALID_Msk (0x1ul << EADC_DAT30_VALID_Pos) /*!< EADC_T::DAT30: VALID Mask */ 2617 2618 #define EADC_SCTL19_CHSEL_Pos (0) /*!< EADC_T::SCTL19: CHSEL Position */ 2619 #define EADC_SCTL19_CHSEL_Msk (0x1ful << EADC_SCTL19_CHSEL_Pos) /*!< EADC_T::SCTL19: CHSEL Mask */ 2620 2621 #define EADC_SCTL19_INTPOS_Pos (5) /*!< EADC_T::SCTL19: INTPOS Position */ 2622 #define EADC_SCTL19_INTPOS_Msk (0x1ul << EADC_SCTL19_INTPOS_Pos) /*!< EADC_T::SCTL19: INTPOS Mask */ 2623 2624 #define EADC_SCTL19_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL19: TRGDLYDIV Position */ 2625 #define EADC_SCTL19_TRGDLYDIV_Msk (0x3ul << EADC_SCTL19_TRGDLYDIV_Pos) /*!< EADC_T::SCTL19: TRGDLYDIV Mask */ 2626 2627 #define EADC_SCTL19_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL19: TRGDLYCNT Position */ 2628 #define EADC_SCTL19_TRGDLYCNT_Msk (0xfful << EADC_SCTL19_TRGDLYCNT_Pos) /*!< EADC_T::SCTL19: TRGDLYCNT Mask */ 2629 2630 #define EADC_SCTL19_TRGSEL_Pos (16) /*!< EADC_T::SCTL19: TRGSEL Position */ 2631 #define EADC_SCTL19_TRGSEL_Msk (0x3ful << EADC_SCTL19_TRGSEL_Pos) /*!< EADC_T::SCTL19: TRGSEL Mask */ 2632 2633 #define EADC_SCTL19_EXTREN_Pos (22) /*!< EADC_T::SCTL19: EXTREN Position */ 2634 #define EADC_SCTL19_EXTREN_Msk (0x1ul << EADC_SCTL19_EXTREN_Pos) /*!< EADC_T::SCTL19: EXTREN Mask */ 2635 2636 #define EADC_SCTL19_EXTFEN_Pos (23) /*!< EADC_T::SCTL19: EXTFEN Position */ 2637 #define EADC_SCTL19_EXTFEN_Msk (0x1ul << EADC_SCTL19_EXTFEN_Pos) /*!< EADC_T::SCTL19: EXTFEN Mask */ 2638 2639 #define EADC_SCTL19_EXTSMPT_Pos (24) /*!< EADC_T::SCTL19: EXTSMPT Position */ 2640 #define EADC_SCTL19_EXTSMPT_Msk (0xfful << EADC_SCTL19_EXTSMPT_Pos) /*!< EADC_T::SCTL19: EXTSMPT Mask */ 2641 2642 #define EADC_SCTL20_CHSEL_Pos (0) /*!< EADC_T::SCTL20: CHSEL Position */ 2643 #define EADC_SCTL20_CHSEL_Msk (0x1ful << EADC_SCTL20_CHSEL_Pos) /*!< EADC_T::SCTL20: CHSEL Mask */ 2644 2645 #define EADC_SCTL20_INTPOS_Pos (5) /*!< EADC_T::SCTL20: INTPOS Position */ 2646 #define EADC_SCTL20_INTPOS_Msk (0x1ul << EADC_SCTL20_INTPOS_Pos) /*!< EADC_T::SCTL20: INTPOS Mask */ 2647 2648 #define EADC_SCTL20_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL20: TRGDLYDIV Position */ 2649 #define EADC_SCTL20_TRGDLYDIV_Msk (0x3ul << EADC_SCTL20_TRGDLYDIV_Pos) /*!< EADC_T::SCTL20: TRGDLYDIV Mask */ 2650 2651 #define EADC_SCTL20_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL20: TRGDLYCNT Position */ 2652 #define EADC_SCTL20_TRGDLYCNT_Msk (0xfful << EADC_SCTL20_TRGDLYCNT_Pos) /*!< EADC_T::SCTL20: TRGDLYCNT Mask */ 2653 2654 #define EADC_SCTL20_TRGSEL_Pos (16) /*!< EADC_T::SCTL20: TRGSEL Position */ 2655 #define EADC_SCTL20_TRGSEL_Msk (0x3ful << EADC_SCTL20_TRGSEL_Pos) /*!< EADC_T::SCTL20: TRGSEL Mask */ 2656 2657 #define EADC_SCTL20_EXTREN_Pos (22) /*!< EADC_T::SCTL20: EXTREN Position */ 2658 #define EADC_SCTL20_EXTREN_Msk (0x1ul << EADC_SCTL20_EXTREN_Pos) /*!< EADC_T::SCTL20: EXTREN Mask */ 2659 2660 #define EADC_SCTL20_EXTFEN_Pos (23) /*!< EADC_T::SCTL20: EXTFEN Position */ 2661 #define EADC_SCTL20_EXTFEN_Msk (0x1ul << EADC_SCTL20_EXTFEN_Pos) /*!< EADC_T::SCTL20: EXTFEN Mask */ 2662 2663 #define EADC_SCTL20_EXTSMPT_Pos (24) /*!< EADC_T::SCTL20: EXTSMPT Position */ 2664 #define EADC_SCTL20_EXTSMPT_Msk (0xfful << EADC_SCTL20_EXTSMPT_Pos) /*!< EADC_T::SCTL20: EXTSMPT Mask */ 2665 2666 #define EADC_SCTL21_CHSEL_Pos (0) /*!< EADC_T::SCTL21: CHSEL Position */ 2667 #define EADC_SCTL21_CHSEL_Msk (0x1ful << EADC_SCTL21_CHSEL_Pos) /*!< EADC_T::SCTL21: CHSEL Mask */ 2668 2669 #define EADC_SCTL21_INTPOS_Pos (5) /*!< EADC_T::SCTL21: INTPOS Position */ 2670 #define EADC_SCTL21_INTPOS_Msk (0x1ul << EADC_SCTL21_INTPOS_Pos) /*!< EADC_T::SCTL21: INTPOS Mask */ 2671 2672 #define EADC_SCTL21_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL21: TRGDLYDIV Position */ 2673 #define EADC_SCTL21_TRGDLYDIV_Msk (0x3ul << EADC_SCTL21_TRGDLYDIV_Pos) /*!< EADC_T::SCTL21: TRGDLYDIV Mask */ 2674 2675 #define EADC_SCTL21_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL21: TRGDLYCNT Position */ 2676 #define EADC_SCTL21_TRGDLYCNT_Msk (0xfful << EADC_SCTL21_TRGDLYCNT_Pos) /*!< EADC_T::SCTL21: TRGDLYCNT Mask */ 2677 2678 #define EADC_SCTL21_TRGSEL_Pos (16) /*!< EADC_T::SCTL21: TRGSEL Position */ 2679 #define EADC_SCTL21_TRGSEL_Msk (0x3ful << EADC_SCTL21_TRGSEL_Pos) /*!< EADC_T::SCTL21: TRGSEL Mask */ 2680 2681 #define EADC_SCTL21_EXTREN_Pos (22) /*!< EADC_T::SCTL21: EXTREN Position */ 2682 #define EADC_SCTL21_EXTREN_Msk (0x1ul << EADC_SCTL21_EXTREN_Pos) /*!< EADC_T::SCTL21: EXTREN Mask */ 2683 2684 #define EADC_SCTL21_EXTFEN_Pos (23) /*!< EADC_T::SCTL21: EXTFEN Position */ 2685 #define EADC_SCTL21_EXTFEN_Msk (0x1ul << EADC_SCTL21_EXTFEN_Pos) /*!< EADC_T::SCTL21: EXTFEN Mask */ 2686 2687 #define EADC_SCTL21_EXTSMPT_Pos (24) /*!< EADC_T::SCTL21: EXTSMPT Position */ 2688 #define EADC_SCTL21_EXTSMPT_Msk (0xfful << EADC_SCTL21_EXTSMPT_Pos) /*!< EADC_T::SCTL21: EXTSMPT Mask */ 2689 2690 #define EADC_SCTL22_CHSEL_Pos (0) /*!< EADC_T::SCTL22: CHSEL Position */ 2691 #define EADC_SCTL22_CHSEL_Msk (0x1ful << EADC_SCTL22_CHSEL_Pos) /*!< EADC_T::SCTL22: CHSEL Mask */ 2692 2693 #define EADC_SCTL22_INTPOS_Pos (5) /*!< EADC_T::SCTL22: INTPOS Position */ 2694 #define EADC_SCTL22_INTPOS_Msk (0x1ul << EADC_SCTL22_INTPOS_Pos) /*!< EADC_T::SCTL22: INTPOS Mask */ 2695 2696 #define EADC_SCTL22_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL22: TRGDLYDIV Position */ 2697 #define EADC_SCTL22_TRGDLYDIV_Msk (0x3ul << EADC_SCTL22_TRGDLYDIV_Pos) /*!< EADC_T::SCTL22: TRGDLYDIV Mask */ 2698 2699 #define EADC_SCTL22_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL22: TRGDLYCNT Position */ 2700 #define EADC_SCTL22_TRGDLYCNT_Msk (0xfful << EADC_SCTL22_TRGDLYCNT_Pos) /*!< EADC_T::SCTL22: TRGDLYCNT Mask */ 2701 2702 #define EADC_SCTL22_TRGSEL_Pos (16) /*!< EADC_T::SCTL22: TRGSEL Position */ 2703 #define EADC_SCTL22_TRGSEL_Msk (0x3ful << EADC_SCTL22_TRGSEL_Pos) /*!< EADC_T::SCTL22: TRGSEL Mask */ 2704 2705 #define EADC_SCTL22_EXTREN_Pos (22) /*!< EADC_T::SCTL22: EXTREN Position */ 2706 #define EADC_SCTL22_EXTREN_Msk (0x1ul << EADC_SCTL22_EXTREN_Pos) /*!< EADC_T::SCTL22: EXTREN Mask */ 2707 2708 #define EADC_SCTL22_EXTFEN_Pos (23) /*!< EADC_T::SCTL22: EXTFEN Position */ 2709 #define EADC_SCTL22_EXTFEN_Msk (0x1ul << EADC_SCTL22_EXTFEN_Pos) /*!< EADC_T::SCTL22: EXTFEN Mask */ 2710 2711 #define EADC_SCTL22_EXTSMPT_Pos (24) /*!< EADC_T::SCTL22: EXTSMPT Position */ 2712 #define EADC_SCTL22_EXTSMPT_Msk (0xfful << EADC_SCTL22_EXTSMPT_Pos) /*!< EADC_T::SCTL22: EXTSMPT Mask */ 2713 2714 #define EADC_SCTL23_CHSEL_Pos (0) /*!< EADC_T::SCTL23: CHSEL Position */ 2715 #define EADC_SCTL23_CHSEL_Msk (0x1ful << EADC_SCTL23_CHSEL_Pos) /*!< EADC_T::SCTL23: CHSEL Mask */ 2716 2717 #define EADC_SCTL23_INTPOS_Pos (5) /*!< EADC_T::SCTL23: INTPOS Position */ 2718 #define EADC_SCTL23_INTPOS_Msk (0x1ul << EADC_SCTL23_INTPOS_Pos) /*!< EADC_T::SCTL23: INTPOS Mask */ 2719 2720 #define EADC_SCTL23_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL23: TRGDLYDIV Position */ 2721 #define EADC_SCTL23_TRGDLYDIV_Msk (0x3ul << EADC_SCTL23_TRGDLYDIV_Pos) /*!< EADC_T::SCTL23: TRGDLYDIV Mask */ 2722 2723 #define EADC_SCTL23_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL23: TRGDLYCNT Position */ 2724 #define EADC_SCTL23_TRGDLYCNT_Msk (0xfful << EADC_SCTL23_TRGDLYCNT_Pos) /*!< EADC_T::SCTL23: TRGDLYCNT Mask */ 2725 2726 #define EADC_SCTL23_TRGSEL_Pos (16) /*!< EADC_T::SCTL23: TRGSEL Position */ 2727 #define EADC_SCTL23_TRGSEL_Msk (0x3ful << EADC_SCTL23_TRGSEL_Pos) /*!< EADC_T::SCTL23: TRGSEL Mask */ 2728 2729 #define EADC_SCTL23_EXTREN_Pos (22) /*!< EADC_T::SCTL23: EXTREN Position */ 2730 #define EADC_SCTL23_EXTREN_Msk (0x1ul << EADC_SCTL23_EXTREN_Pos) /*!< EADC_T::SCTL23: EXTREN Mask */ 2731 2732 #define EADC_SCTL23_EXTFEN_Pos (23) /*!< EADC_T::SCTL23: EXTFEN Position */ 2733 #define EADC_SCTL23_EXTFEN_Msk (0x1ul << EADC_SCTL23_EXTFEN_Pos) /*!< EADC_T::SCTL23: EXTFEN Mask */ 2734 2735 #define EADC_SCTL23_EXTSMPT_Pos (24) /*!< EADC_T::SCTL23: EXTSMPT Position */ 2736 #define EADC_SCTL23_EXTSMPT_Msk (0xfful << EADC_SCTL23_EXTSMPT_Pos) /*!< EADC_T::SCTL23: EXTSMPT Mask */ 2737 2738 #define EADC_SCTL24_CHSEL_Pos (0) /*!< EADC_T::SCTL24: CHSEL Position */ 2739 #define EADC_SCTL24_CHSEL_Msk (0x1ful << EADC_SCTL24_CHSEL_Pos) /*!< EADC_T::SCTL24: CHSEL Mask */ 2740 2741 #define EADC_SCTL24_INTPOS_Pos (5) /*!< EADC_T::SCTL24: INTPOS Position */ 2742 #define EADC_SCTL24_INTPOS_Msk (0x1ul << EADC_SCTL24_INTPOS_Pos) /*!< EADC_T::SCTL24: INTPOS Mask */ 2743 2744 #define EADC_SCTL24_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL24: TRGDLYDIV Position */ 2745 #define EADC_SCTL24_TRGDLYDIV_Msk (0x3ul << EADC_SCTL24_TRGDLYDIV_Pos) /*!< EADC_T::SCTL24: TRGDLYDIV Mask */ 2746 2747 #define EADC_SCTL24_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL24: TRGDLYCNT Position */ 2748 #define EADC_SCTL24_TRGDLYCNT_Msk (0xfful << EADC_SCTL24_TRGDLYCNT_Pos) /*!< EADC_T::SCTL24: TRGDLYCNT Mask */ 2749 2750 #define EADC_SCTL24_TRGSEL_Pos (16) /*!< EADC_T::SCTL24: TRGSEL Position */ 2751 #define EADC_SCTL24_TRGSEL_Msk (0x3ful << EADC_SCTL24_TRGSEL_Pos) /*!< EADC_T::SCTL24: TRGSEL Mask */ 2752 2753 #define EADC_SCTL24_EXTREN_Pos (22) /*!< EADC_T::SCTL24: EXTREN Position */ 2754 #define EADC_SCTL24_EXTREN_Msk (0x1ul << EADC_SCTL24_EXTREN_Pos) /*!< EADC_T::SCTL24: EXTREN Mask */ 2755 2756 #define EADC_SCTL24_EXTFEN_Pos (23) /*!< EADC_T::SCTL24: EXTFEN Position */ 2757 #define EADC_SCTL24_EXTFEN_Msk (0x1ul << EADC_SCTL24_EXTFEN_Pos) /*!< EADC_T::SCTL24: EXTFEN Mask */ 2758 2759 #define EADC_SCTL24_EXTSMPT_Pos (24) /*!< EADC_T::SCTL24: EXTSMPT Position */ 2760 #define EADC_SCTL24_EXTSMPT_Msk (0xfful << EADC_SCTL24_EXTSMPT_Pos) /*!< EADC_T::SCTL24: EXTSMPT Mask */ 2761 2762 #define EADC_SCTL25_CHSEL_Pos (0) /*!< EADC_T::SCTL25: CHSEL Position */ 2763 #define EADC_SCTL25_CHSEL_Msk (0x1ful << EADC_SCTL25_CHSEL_Pos) /*!< EADC_T::SCTL25: CHSEL Mask */ 2764 2765 #define EADC_SCTL25_INTPOS_Pos (5) /*!< EADC_T::SCTL25: INTPOS Position */ 2766 #define EADC_SCTL25_INTPOS_Msk (0x1ul << EADC_SCTL25_INTPOS_Pos) /*!< EADC_T::SCTL25: INTPOS Mask */ 2767 2768 #define EADC_SCTL25_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL25: TRGDLYDIV Position */ 2769 #define EADC_SCTL25_TRGDLYDIV_Msk (0x3ul << EADC_SCTL25_TRGDLYDIV_Pos) /*!< EADC_T::SCTL25: TRGDLYDIV Mask */ 2770 2771 #define EADC_SCTL25_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL25: TRGDLYCNT Position */ 2772 #define EADC_SCTL25_TRGDLYCNT_Msk (0xfful << EADC_SCTL25_TRGDLYCNT_Pos) /*!< EADC_T::SCTL25: TRGDLYCNT Mask */ 2773 2774 #define EADC_SCTL25_TRGSEL_Pos (16) /*!< EADC_T::SCTL25: TRGSEL Position */ 2775 #define EADC_SCTL25_TRGSEL_Msk (0x3ful << EADC_SCTL25_TRGSEL_Pos) /*!< EADC_T::SCTL25: TRGSEL Mask */ 2776 2777 #define EADC_SCTL25_EXTREN_Pos (22) /*!< EADC_T::SCTL25: EXTREN Position */ 2778 #define EADC_SCTL25_EXTREN_Msk (0x1ul << EADC_SCTL25_EXTREN_Pos) /*!< EADC_T::SCTL25: EXTREN Mask */ 2779 2780 #define EADC_SCTL25_EXTFEN_Pos (23) /*!< EADC_T::SCTL25: EXTFEN Position */ 2781 #define EADC_SCTL25_EXTFEN_Msk (0x1ul << EADC_SCTL25_EXTFEN_Pos) /*!< EADC_T::SCTL25: EXTFEN Mask */ 2782 2783 #define EADC_SCTL25_EXTSMPT_Pos (24) /*!< EADC_T::SCTL25: EXTSMPT Position */ 2784 #define EADC_SCTL25_EXTSMPT_Msk (0xfful << EADC_SCTL25_EXTSMPT_Pos) /*!< EADC_T::SCTL25: EXTSMPT Mask */ 2785 2786 #define EADC_SCTL26_CHSEL_Pos (0) /*!< EADC_T::SCTL26: CHSEL Position */ 2787 #define EADC_SCTL26_CHSEL_Msk (0x1ful << EADC_SCTL26_CHSEL_Pos) /*!< EADC_T::SCTL26: CHSEL Mask */ 2788 2789 #define EADC_SCTL26_INTPOS_Pos (5) /*!< EADC_T::SCTL26: INTPOS Position */ 2790 #define EADC_SCTL26_INTPOS_Msk (0x1ul << EADC_SCTL26_INTPOS_Pos) /*!< EADC_T::SCTL26: INTPOS Mask */ 2791 2792 #define EADC_SCTL26_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL26: TRGDLYDIV Position */ 2793 #define EADC_SCTL26_TRGDLYDIV_Msk (0x3ul << EADC_SCTL26_TRGDLYDIV_Pos) /*!< EADC_T::SCTL26: TRGDLYDIV Mask */ 2794 2795 #define EADC_SCTL26_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL26: TRGDLYCNT Position */ 2796 #define EADC_SCTL26_TRGDLYCNT_Msk (0xfful << EADC_SCTL26_TRGDLYCNT_Pos) /*!< EADC_T::SCTL26: TRGDLYCNT Mask */ 2797 2798 #define EADC_SCTL26_TRGSEL_Pos (16) /*!< EADC_T::SCTL26: TRGSEL Position */ 2799 #define EADC_SCTL26_TRGSEL_Msk (0x3ful << EADC_SCTL26_TRGSEL_Pos) /*!< EADC_T::SCTL26: TRGSEL Mask */ 2800 2801 #define EADC_SCTL26_EXTREN_Pos (22) /*!< EADC_T::SCTL26: EXTREN Position */ 2802 #define EADC_SCTL26_EXTREN_Msk (0x1ul << EADC_SCTL26_EXTREN_Pos) /*!< EADC_T::SCTL26: EXTREN Mask */ 2803 2804 #define EADC_SCTL26_EXTFEN_Pos (23) /*!< EADC_T::SCTL26: EXTFEN Position */ 2805 #define EADC_SCTL26_EXTFEN_Msk (0x1ul << EADC_SCTL26_EXTFEN_Pos) /*!< EADC_T::SCTL26: EXTFEN Mask */ 2806 2807 #define EADC_SCTL26_EXTSMPT_Pos (24) /*!< EADC_T::SCTL26: EXTSMPT Position */ 2808 #define EADC_SCTL26_EXTSMPT_Msk (0xfful << EADC_SCTL26_EXTSMPT_Pos) /*!< EADC_T::SCTL26: EXTSMPT Mask */ 2809 2810 #define EADC_SCTL27_EXTSMPT_Pos (24) /*!< EADC_T::SCTL27: EXTSMPT Position */ 2811 #define EADC_SCTL27_EXTSMPT_Msk (0xfful << EADC_SCTL27_EXTSMPT_Pos) /*!< EADC_T::SCTL27: EXTSMPT Mask */ 2812 2813 #define EADC_SCTL28_EXTSMPT_Pos (24) /*!< EADC_T::SCTL28: EXTSMPT Position */ 2814 #define EADC_SCTL28_EXTSMPT_Msk (0xfful << EADC_SCTL28_EXTSMPT_Pos) /*!< EADC_T::SCTL28: EXTSMPT Mask */ 2815 2816 #define EADC_SCTL29_EXTSMPT_Pos (24) /*!< EADC_T::SCTL29: EXTSMPT Position */ 2817 #define EADC_SCTL29_EXTSMPT_Msk (0xfful << EADC_SCTL29_EXTSMPT_Pos) /*!< EADC_T::SCTL29: EXTSMPT Mask */ 2818 2819 #define EADC_SCTL30_EXTSMPT_Pos (24) /*!< EADC_T::SCTL30: EXTSMPT Position */ 2820 #define EADC_SCTL30_EXTSMPT_Msk (0xfful << EADC_SCTL30_EXTSMPT_Pos) /*!< EADC_T::SCTL30: EXTSMPT Mask */ 2821 2822 #define EADC_M19CTL1_ALIGN_Pos (0) /*!< EADC_T::M19CTL1: ALIGN Position */ 2823 #define EADC_M19CTL1_ALIGN_Msk (0x1ul << EADC_M19CTL1_ALIGN_Pos) /*!< EADC_T::M19CTL1: ALIGN Mask */ 2824 2825 #define EADC_M19CTL1_AVG_Pos (1) /*!< EADC_T::M19CTL1: AVG Position */ 2826 #define EADC_M19CTL1_AVG_Msk (0x1ul << EADC_M19CTL1_AVG_Pos) /*!< EADC_T::M19CTL1: AVG Mask */ 2827 2828 #define EADC_M19CTL1_ACU_Pos (4) /*!< EADC_T::M19CTL1: ACU Position */ 2829 #define EADC_M19CTL1_ACU_Msk (0xful << EADC_M19CTL1_ACU_Pos) /*!< EADC_T::M19CTL1: ACU Mask */ 2830 2831 #define EADC_M19CTL1_EXTSTDIV_Pos (16) /*!< EADC_T::M19CTL1: EXTSTDIV Position */ 2832 #define EADC_M19CTL1_EXTSTDIV_Msk (0x3ul << EADC_M19CTL1_EXTSTDIV_Pos) /*!< EADC_T::M19CTL1: EXTSTDIV Mask */ 2833 2834 #define EADC_M20CTL1_ALIGN_Pos (0) /*!< EADC_T::M20CTL1: ALIGN Position */ 2835 #define EADC_M20CTL1_ALIGN_Msk (0x1ul << EADC_M20CTL1_ALIGN_Pos) /*!< EADC_T::M20CTL1: ALIGN Mask */ 2836 2837 #define EADC_M20CTL1_AVG_Pos (1) /*!< EADC_T::M20CTL1: AVG Position */ 2838 #define EADC_M20CTL1_AVG_Msk (0x1ul << EADC_M20CTL1_AVG_Pos) /*!< EADC_T::M20CTL1: AVG Mask */ 2839 2840 #define EADC_M20CTL1_ACU_Pos (4) /*!< EADC_T::M20CTL1: ACU Position */ 2841 #define EADC_M20CTL1_ACU_Msk (0xful << EADC_M20CTL1_ACU_Pos) /*!< EADC_T::M20CTL1: ACU Mask */ 2842 2843 #define EADC_M20CTL1_EXTSTDIV_Pos (16) /*!< EADC_T::M20CTL1: EXTSTDIV Position */ 2844 #define EADC_M20CTL1_EXTSTDIV_Msk (0x3ul << EADC_M20CTL1_EXTSTDIV_Pos) /*!< EADC_T::M20CTL1: EXTSTDIV Mask */ 2845 2846 #define EADC_M21CTL1_ALIGN_Pos (0) /*!< EADC_T::M21CTL1: ALIGN Position */ 2847 #define EADC_M21CTL1_ALIGN_Msk (0x1ul << EADC_M21CTL1_ALIGN_Pos) /*!< EADC_T::M21CTL1: ALIGN Mask */ 2848 2849 #define EADC_M21CTL1_AVG_Pos (1) /*!< EADC_T::M21CTL1: AVG Position */ 2850 #define EADC_M21CTL1_AVG_Msk (0x1ul << EADC_M21CTL1_AVG_Pos) /*!< EADC_T::M21CTL1: AVG Mask */ 2851 2852 #define EADC_M21CTL1_ACU_Pos (4) /*!< EADC_T::M21CTL1: ACU Position */ 2853 #define EADC_M21CTL1_ACU_Msk (0xful << EADC_M21CTL1_ACU_Pos) /*!< EADC_T::M21CTL1: ACU Mask */ 2854 2855 #define EADC_M21CTL1_EXTSTDIV_Pos (16) /*!< EADC_T::M21CTL1: EXTSTDIV Position */ 2856 #define EADC_M21CTL1_EXTSTDIV_Msk (0x3ul << EADC_M21CTL1_EXTSTDIV_Pos) /*!< EADC_T::M21CTL1: EXTSTDIV Mask */ 2857 2858 #define EADC_M22CTL1_ALIGN_Pos (0) /*!< EADC_T::M22CTL1: ALIGN Position */ 2859 #define EADC_M22CTL1_ALIGN_Msk (0x1ul << EADC_M22CTL1_ALIGN_Pos) /*!< EADC_T::M22CTL1: ALIGN Mask */ 2860 2861 #define EADC_M22CTL1_AVG_Pos (1) /*!< EADC_T::M22CTL1: AVG Position */ 2862 #define EADC_M22CTL1_AVG_Msk (0x1ul << EADC_M22CTL1_AVG_Pos) /*!< EADC_T::M22CTL1: AVG Mask */ 2863 2864 #define EADC_M22CTL1_ACU_Pos (4) /*!< EADC_T::M22CTL1: ACU Position */ 2865 #define EADC_M22CTL1_ACU_Msk (0xful << EADC_M22CTL1_ACU_Pos) /*!< EADC_T::M22CTL1: ACU Mask */ 2866 2867 #define EADC_M22CTL1_EXTSTDIV_Pos (16) /*!< EADC_T::M22CTL1: EXTSTDIV Position */ 2868 #define EADC_M22CTL1_EXTSTDIV_Msk (0x3ul << EADC_M22CTL1_EXTSTDIV_Pos) /*!< EADC_T::M22CTL1: EXTSTDIV Mask */ 2869 2870 #define EADC_M23CTL1_ALIGN_Pos (0) /*!< EADC_T::M23CTL1: ALIGN Position */ 2871 #define EADC_M23CTL1_ALIGN_Msk (0x1ul << EADC_M23CTL1_ALIGN_Pos) /*!< EADC_T::M23CTL1: ALIGN Mask */ 2872 2873 #define EADC_M23CTL1_AVG_Pos (1) /*!< EADC_T::M23CTL1: AVG Position */ 2874 #define EADC_M23CTL1_AVG_Msk (0x1ul << EADC_M23CTL1_AVG_Pos) /*!< EADC_T::M23CTL1: AVG Mask */ 2875 2876 #define EADC_M23CTL1_ACU_Pos (4) /*!< EADC_T::M23CTL1: ACU Position */ 2877 #define EADC_M23CTL1_ACU_Msk (0xful << EADC_M23CTL1_ACU_Pos) /*!< EADC_T::M23CTL1: ACU Mask */ 2878 2879 #define EADC_M23CTL1_EXTSTDIV_Pos (16) /*!< EADC_T::M23CTL1: EXTSTDIV Position */ 2880 #define EADC_M23CTL1_EXTSTDIV_Msk (0x3ul << EADC_M23CTL1_EXTSTDIV_Pos) /*!< EADC_T::M23CTL1: EXTSTDIV Mask */ 2881 2882 #define EADC_M24CTL1_ALIGN_Pos (0) /*!< EADC_T::M24CTL1: ALIGN Position */ 2883 #define EADC_M24CTL1_ALIGN_Msk (0x1ul << EADC_M24CTL1_ALIGN_Pos) /*!< EADC_T::M24CTL1: ALIGN Mask */ 2884 2885 #define EADC_M24CTL1_AVG_Pos (1) /*!< EADC_T::M24CTL1: AVG Position */ 2886 #define EADC_M24CTL1_AVG_Msk (0x1ul << EADC_M24CTL1_AVG_Pos) /*!< EADC_T::M24CTL1: AVG Mask */ 2887 2888 #define EADC_M24CTL1_ACU_Pos (4) /*!< EADC_T::M24CTL1: ACU Position */ 2889 #define EADC_M24CTL1_ACU_Msk (0xful << EADC_M24CTL1_ACU_Pos) /*!< EADC_T::M24CTL1: ACU Mask */ 2890 2891 #define EADC_M24CTL1_EXTSTDIV_Pos (16) /*!< EADC_T::M24CTL1: EXTSTDIV Position */ 2892 #define EADC_M24CTL1_EXTSTDIV_Msk (0x3ul << EADC_M24CTL1_EXTSTDIV_Pos) /*!< EADC_T::M24CTL1: EXTSTDIV Mask */ 2893 2894 #define EADC_M25CTL1_ALIGN_Pos (0) /*!< EADC_T::M25CTL1: ALIGN Position */ 2895 #define EADC_M25CTL1_ALIGN_Msk (0x1ul << EADC_M25CTL1_ALIGN_Pos) /*!< EADC_T::M25CTL1: ALIGN Mask */ 2896 2897 #define EADC_M25CTL1_AVG_Pos (1) /*!< EADC_T::M25CTL1: AVG Position */ 2898 #define EADC_M25CTL1_AVG_Msk (0x1ul << EADC_M25CTL1_AVG_Pos) /*!< EADC_T::M25CTL1: AVG Mask */ 2899 2900 #define EADC_M25CTL1_ACU_Pos (4) /*!< EADC_T::M25CTL1: ACU Position */ 2901 #define EADC_M25CTL1_ACU_Msk (0xful << EADC_M25CTL1_ACU_Pos) /*!< EADC_T::M25CTL1: ACU Mask */ 2902 2903 #define EADC_M25CTL1_EXTSTDIV_Pos (16) /*!< EADC_T::M25CTL1: EXTSTDIV Position */ 2904 #define EADC_M25CTL1_EXTSTDIV_Msk (0x3ul << EADC_M25CTL1_EXTSTDIV_Pos) /*!< EADC_T::M25CTL1: EXTSTDIV Mask */ 2905 2906 #define EADC_M26CTL1_ALIGN_Pos (0) /*!< EADC_T::M26CTL1: ALIGN Position */ 2907 #define EADC_M26CTL1_ALIGN_Msk (0x1ul << EADC_M26CTL1_ALIGN_Pos) /*!< EADC_T::M26CTL1: ALIGN Mask */ 2908 2909 #define EADC_M26CTL1_AVG_Pos (1) /*!< EADC_T::M26CTL1: AVG Position */ 2910 #define EADC_M26CTL1_AVG_Msk (0x1ul << EADC_M26CTL1_AVG_Pos) /*!< EADC_T::M26CTL1: AVG Mask */ 2911 2912 #define EADC_M26CTL1_ACU_Pos (4) /*!< EADC_T::M26CTL1: ACU Position */ 2913 #define EADC_M26CTL1_ACU_Msk (0xful << EADC_M26CTL1_ACU_Pos) /*!< EADC_T::M26CTL1: ACU Mask */ 2914 2915 #define EADC_M26CTL1_EXTSTDIV_Pos (16) /*!< EADC_T::M26CTL1: EXTSTDIV Position */ 2916 #define EADC_M26CTL1_EXTSTDIV_Msk (0x3ul << EADC_M26CTL1_EXTSTDIV_Pos) /*!< EADC_T::M26CTL1: EXTSTDIV Mask */ 2917 2918 #define EADC_M27CTL1_EXTSTDIV_Pos (16) /*!< EADC_T::M27CTL1: EXTSTDIV Position */ 2919 #define EADC_M27CTL1_EXTSTDIV_Msk (0x3ul << EADC_M27CTL1_EXTSTDIV_Pos) /*!< EADC_T::M27CTL1: EXTSTDIV Mask */ 2920 2921 #define EADC_M28CTL1_EXTSTDIV_Pos (16) /*!< EADC_T::M28CTL1: EXTSTDIV Position */ 2922 #define EADC_M28CTL1_EXTSTDIV_Msk (0x3ul << EADC_M28CTL1_EXTSTDIV_Pos) /*!< EADC_T::M28CTL1: EXTSTDIV Mask */ 2923 2924 #define EADC_M29CTL1_EXTSTDIV_Pos (16) /*!< EADC_T::M29CTL1: EXTSTDIV Position */ 2925 #define EADC_M29CTL1_EXTSTDIV_Msk (0x3ul << EADC_M29CTL1_EXTSTDIV_Pos) /*!< EADC_T::M29CTL1: EXTSTDIV Mask */ 2926 2927 #define EADC_M30CTL1_EXTSTDIV_Pos (16) /*!< EADC_T::M30CTL1: EXTSTDIV Position */ 2928 #define EADC_M30CTL1_EXTSTDIV_Msk (0x3ul << EADC_M30CTL1_EXTSTDIV_Pos) /*!< EADC_T::M30CTL1: EXTSTDIV Mask */ 2929 2930 /**@}*/ /* EADC_CONST */ 2931 /**@}*/ /* end of EADC register group */ 2932 /**@}*/ /* end of REGISTER group */ 2933 2934 #if defined ( __CC_ARM ) 2935 #pragma no_anon_unions 2936 #endif 2937 2938 #endif /* __EADC_REG_H__ */ 2939
