1 /**************************************************************************//** 2 * @file eadc_reg.h 3 * @version V1.00 4 * @brief EADC register definition header file 5 * 6 * @copyright SPDX-License-Identifier: Apache-2.0 7 * @copyright Copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. 8 *****************************************************************************/ 9 #ifndef __EADC_REG_H__ 10 #define __EADC_REG_H__ 11 12 /** @addtogroup REGISTER Control Register 13 14 @{ 15 16 */ 17 18 /*---------------------- Enhanced Analog to Digital Converter -------------------------*/ 19 /** 20 @addtogroup EADC Enhanced Analog to Digital Converter(EADC) 21 Memory Mapped Structure for EADC Controller 22 @{ */ 23 24 25 typedef struct 26 { 27 28 29 /** 30 * @var EADC_T::DAT[19] 31 * Offset: 0x00 ADC Data Register 0~18 for Sample Module 0~18 32 * --------------------------------------------------------------------------------------------------- 33 * |Bits |Field |Descriptions 34 * | :----: | :----: | :---- | 35 * |[15:0] |RESULT |ADC Conversion Result 36 * | | |This field contains 12 bits conversion result. 37 * | | |When DMOF (EADC_CTL[9]) is set to 0, 12-bit ADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12]. 38 * | | |When DMOF (EADC_CTL[9]) set to 1, 12-bit ADC conversion result with 2'complement format will be filled in RESULT[11:0] and signed bits to will be filled in RESULT[15:12]. 39 * |[16] |OV |Overrun Flag 40 * | | |If converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register, OV is set to 1. 41 * | | |0 = Data in RESULT[11:0] is recent conversion result. 42 * | | |1 = Data in RESULT[11:0] is overwrite. 43 * | | |Note: It is cleared by hardware after EADC_DAT register is read. 44 * |[17] |VALID |Valid Flag 45 * | | |This bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read. 46 * | | |0 = Data in RESULT[11:0] bits is not valid. 47 * | | |1 = Data in RESULT[11:0] bits is valid. 48 * @var EADC_T::CURDAT 49 * Offset: 0x4C ADC PDMA Current Transfer Data Register 50 * --------------------------------------------------------------------------------------------------- 51 * |Bits |Field |Descriptions 52 * | :----: | :----: | :---- | 53 * |[17:0] |CURDAT |ADC PDMA Current Transfer Data Register 54 * | | |This register is a shadow register of EADC_DATn (n=0~18) for PDMA support. 55 * | | |This is a read only register. 56 * @var EADC_T::CTL 57 * Offset: 0x50 ADC Control Register 58 * --------------------------------------------------------------------------------------------------- 59 * |Bits |Field |Descriptions 60 * | :----: | :----: | :---- | 61 * |[0] |ADCEN |ADC Converter Enable Bit 62 * | | |0 = Disabled EADC. 63 * | | |1 = Enabled EADC. 64 * | | |Note: Before starting ADC conversion function, this bit should be set to 1 65 * | | |Clear it to 0 to disable ADC converter analog circuit power consumption. 66 * |[1] |ADCRST |ADC Converter Control Circuits Reset 67 * | | |0 = No effect. 68 * | | |1 = Cause ADC control circuits reset to initial state, but not change the ADC registers value. 69 * | | |Note: ADCRST bit remains 1 during ADC reset, when ADC reset end, the ADCRST bit is automatically cleared to 0. 70 * |[2] |ADCIEN0 |Specific Sample Module ADC ADINT0 Interrupt Enable Bit 71 * | | |The ADC converter generates a conversion end ADIF0 (EADC_STATUS2[0]) upon the end of specific sample module ADC conversion 72 * | | |If ADCIEN0 bit is set then conversion end interrupt request ADINT0 is generated. 73 * | | |0 = Specific sample module ADC ADINT0 interrupt function Disabled. 74 * | | |1 = Specific sample module ADC ADINT0 interrupt function Enabled. 75 * |[3] |ADCIEN1 |Specific Sample Module ADC ADINT1 Interrupt Enable Bit 76 * | | |The ADC converter generates a conversion end ADIF1 (EADC_STATUS2[1]) upon the end of specific sample module ADC conversion 77 * | | |If ADCIEN1 bit is set then conversion end interrupt request ADINT1 is generated. 78 * | | |0 = Specific sample module ADC ADINT1 interrupt function Disabled. 79 * | | |1 = Specific sample module ADC ADINT1 interrupt function Enabled. 80 * |[4] |ADCIEN2 |Specific Sample Module ADC ADINT2 Interrupt Enable Bit 81 * | | |The ADC converter generates a conversion end ADIF2 (EADC_STATUS2[2]) upon the end of specific sample module ADC conversion 82 * | | |If ADCIEN2 bit is set then conversion end interrupt request ADINT2 is generated. 83 * | | |0 = Specific sample module ADC ADINT2 interrupt function Disabled. 84 * | | |1 = Specific sample module ADC ADINT2 interrupt function Enabled. 85 * |[5] |ADCIEN3 |Specific Sample Module ADC ADINT3 Interrupt Enable Bit 86 * | | |The ADC converter generates a conversion end ADIF3 (EADC_STATUS2[3]) upon the end of specific sample module ADC conversion 87 * | | |If ADCIEN3 bit is set then conversion end interrupt request ADINT3 is generated. 88 * | | |0 = Specific sample module ADC ADINT3 interrupt function Disabled. 89 * | | |1 = Specific sample module ADC ADINT3 interrupt function Enabled. 90 * |[7:6] |RESSEL |Resolution Selection 91 * | | |00 = 6-bit ADC result will be put at RESULT (EADC_DATn[5:0]). 92 * | | |01 = 8-bit ADC result will be put at RESULT (EADC_DATn[7:0]). 93 * | | |10 = 10-bit ADC result will be put at RESULT (EADC_DATn[9:0]). 94 * | | |11 = 12-bit ADC result will be put at RESULT (EADC_DATn[11:0]). 95 * |[8] |DIFFEN |Differential Analog Input Mode Enable Bit 96 * | | |0 = Single-end analog input mode. 97 * | | |1 = Differential analog input mode. 98 * |[9] |DMOF |ADC Differential Input Mode Output Format 99 * | | |0 = ADC conversion result will be filled in RESULT (EADC_DATn[15:0] , n= 0 ~18) with unsigned format. 100 * | | |1 = ADC conversion result will be filled in RESULT (EADC_DATn[15:0] , n= 0 ~18) with 2'complement format. 101 * |[11] |PDMAEN |PDMA Transfer Enable Bit 102 * | | |When ADC conversion is completed, the converted data is loaded into EADC_DATn (n: 0 ~ 18) register, user can enable this bit to generate a PDMA data transfer request. 103 * | | |0 = PDMA data transfer Disabled. 104 * | | |1 = PDMA data transfer Enabled. 105 * | | |Note: When set this bit field to 1, user must set ADCIENn (EADC_CTL[5:2], n=0~3) = 0 to disable interrupt. 106 * @var EADC_T::SWTRG 107 * Offset: 0x54 ADC Sample Module Software Start Register 108 * --------------------------------------------------------------------------------------------------- 109 * |Bits |Field |Descriptions 110 * | :----: | :----: | :---- | 111 * |[18:0] |SWTRG |ADC Sample Module 0~18 Software Force to Start ADC Conversion 112 * | | |0 = No effect. 113 * | | |1 = Cause an ADC conversion when the priority is given to sample module. 114 * | | |Note: After write this register to start ADC conversion, the EADC_PENDSTS register will show which sample module will conversion 115 * | | |If user want to disable the conversion of the sample module, user can write EADC_PENDSTS register to clear it. 116 * @var EADC_T::PENDSTS 117 * Offset: 0x58 ADC Start of Conversion Pending Flag Register 118 * --------------------------------------------------------------------------------------------------- 119 * |Bits |Field |Descriptions 120 * | :----: | :----: | :---- | 121 * |[18:0] |STPF |ADC Sample Module 0~18 Start of Conversion Pending Flag 122 * | | |Read: 123 * | | |0 = There is no pending conversion for sample module. 124 * | | |1 = Sample module ADC start of conversion is pending. 125 * | | |Write: 126 * | | |1 = clear pending flag and cancel the conversion for sample module. 127 * | | |Note: This bit remains 1 during pending state, when the respective ADC conversion is end, the STPFn (n=0~18) bit is automatically cleared to 0 128 * @var EADC_T::OVSTS 129 * Offset: 0x5C ADC Sample Module Start of Conversion Overrun Flag Register 130 * --------------------------------------------------------------------------------------------------- 131 * |Bits |Field |Descriptions 132 * | :----: | :----: | :---- | 133 * |[18:0] |SPOVF |ADC SAMPLE0~18 Overrun Flag 134 * | | |0 = No sample module event overrun. 135 * | | |1 = Indicates a new sample module event is generated while an old one event is pending. 136 * | | |Note: This bit is cleared by writing 1 to it. 137 * @var EADC_T::SCTL[19] 138 * Offset: 0x80 ADC Sample Module 0~18 Control Register 139 * --------------------------------------------------------------------------------------------------- 140 * |Bits |Field |Descriptions 141 * | :----: | :----: | :---- | 142 * |[3:0] |CHSEL |ADC Sample Module Channel Selection 143 * | | |00H = EADC_CH0 (slow channel). 144 * | | |01H = EADC_CH1 (slow channel). 145 * | | |02H = EADC_CH2 (slow channel). 146 * | | |03H = EADC_CH3 (slow channel). 147 * | | |04H = EADC_CH4 (slow channel). 148 * | | |05H = EADC_CH5 (slow channel). 149 * | | |06H = EADC_CH6 (slow channel). 150 * | | |07H = EADC_CH7 (slow channel). 151 * | | |08H = EADC_CH8 (slow channel). 152 * | | |09H = EADC_CH9 (slow channel). 153 * | | |0AH = EADC_CH10 (fast channel). 154 * | | |0BH = EADC_CH11 (fast channel). 155 * | | |0CH = EADC_CH12 (fast channel). 156 * | | |0DH = EADC_CH13 (fast channel). 157 * | | |0EH = EADC_CH14 (fast channel). 158 * | | |0FH = EADC_CH15 (fast channel). 159 * |[4] |EXTREN |ADC External Trigger Rising Edge Enable Bit 160 * | | |0 = Rising edge Disabled when ADC selects EADC0_ST as trigger source. 161 * | | |1 = Rising edge Enabled when ADC selects EADC0_ST as trigger source. 162 * |[5] |EXTFEN |ADC External Trigger Falling Edge Enable Bit 163 * | | |0 = Falling edge Disabled when ADC selects EADC0_ST as trigger source. 164 * | | |1 = Falling edge Enabled when ADC selects EADC0_ST as trigger source. 165 * |[7:6] |TRGDLYDIV |ADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection 166 * | | |Trigger delay clock frequency: 167 * | | |00 = ADC_CLK/1. 168 * | | |01 = ADC_CLK/2. 169 * | | |10 = ADC_CLK/4. 170 * | | |11 = ADC_CLK/16. 171 * |[15:8] |TRGDLYCNT |ADC Sample Module Start of Conversion Trigger Delay Time 172 * | | |Trigger delay time = TRGDLYCNT x ADC_CLK x n (n=1,2,4,16 from TRGDLYDIV setting). 173 * |[20:16] |TRGSEL |ADC Sample Module Start of Conversion Trigger Source Selection 174 * | | |0H = Disable trigger. 175 * | | |1H = External trigger from EADC0_ST pin input. 176 * | | |2H = ADC ADINT0 interrupt EOC (End of conversion) pulse trigger. 177 * | | |3H = ADC ADINT1 interrupt EOC (End of conversion) pulse trigger. 178 * | | |4H = Timer0 overflow pulse trigger. 179 * | | |5H = Timer1 overflow pulse trigger. 180 * | | |6H = Timer2 overflow pulse trigger. 181 * | | |7H = Timer3 overflow pulse trigger. 182 * | | |8H = EPWM0TG0. 183 * | | |9H = EPWM0TG1. 184 * | | |AH = EPWM0TG2. 185 * | | |BH = EPWM0TG3. 186 * | | |CH = EPWM0TG4. 187 * | | |DH = EPWM0TG5. 188 * | | |EH = EPWM1TG0. 189 * | | |FH = EPWM1TG1. 190 * | | |10H = EPWM1TG2. 191 * | | |11H = EPWM1TG3. 192 * | | |12H = EPWM1TG4. 193 * | | |13H = EPWM1TG5. 194 * | | |14H = BPWM0TG. 195 * | | |15H = BPWM1TG. 196 * | | |other = Reserved. 197 * |[22] |INTPOS |Interrupt Flag Position Select 198 * | | |0 = Set ADIFn (EADC_STATUS2[n], n=0~3) at ADC end of conversion. 199 * | | |1 = Set ADIFn (EADC_STATUS2[n], n=0~3) at ADC start of conversion. 200 * |[23] |DBMEN |Double Buffer Mode Enable Bit 201 * | | |0 = Sample has one sample result register. (default). 202 * | | |1 = Sample has two sample result registers. 203 * |[31:24] |EXTSMPT |ADC Sampling Time Extend 204 * | | |When ADC converting at high conversion rate, the sampling time of analog input voltage may not enough if input channel loading is heavy, user can extend ADC sampling time after trigger source is coming to get enough sampling time. 205 * | | |The range of start delay time is from 0~255 ADC clock. 206 * @var EADC_T::INTSRC[4] 207 * Offset: 0xD0 ADC interrupt 0~3 Source Enable Control Register. 208 * --------------------------------------------------------------------------------------------------- 209 * |Bits |Field |Descriptions 210 * | :----: | :----: | :---- | 211 * |[0] |SPLIE0 |Sample Module 0 Interrupt Enable Bit 212 * | | |0 = Sample Module 0 interrupt Disabled. 213 * | | |1 = Sample Module 0 interrupt Enabled. 214 * |[1] |SPLIE1 |Sample Module 1 Interrupt Enable Bit 215 * | | |0 = Sample Module 1 interrupt Disabled. 216 * | | |1 = Sample Module 1 interrupt Enabled. 217 * |[2] |SPLIE2 |Sample Module 2 Interrupt Enable Bit 218 * | | |0 = Sample Module 2 interrupt Disabled. 219 * | | |1 = Sample Module 2 interrupt Enabled. 220 * |[3] |SPLIE3 |Sample Module 3 Interrupt Enable Bit 221 * | | |0 = Sample Module 3 interrupt Disabled. 222 * | | |1 = Sample Module 3 interrupt Enabled. 223 * |[4] |SPLIE4 |Sample Module 4 Interrupt Enable Bit 224 * | | |0 = Sample Module 4 interrupt Disabled. 225 * | | |1 = Sample Module 4 interrupt Enabled. 226 * |[5] |SPLIE5 |Sample Module 5 Interrupt Enable Bit 227 * | | |0 = Sample Module 5 interrupt Disabled. 228 * | | |1 = Sample Module 5 interrupt Enabled. 229 * |[6] |SPLIE6 |Sample Module 6 Interrupt Enable Bit 230 * | | |0 = Sample Module 6 interrupt Disabled. 231 * | | |1 = Sample Module 6 interrupt Enabled. 232 * |[7] |SPLIE7 |Sample Module 7 Interrupt Enable Bit 233 * | | |0 = Sample Module 7 interrupt Disabled. 234 * | | |1 = Sample Module 7 interrupt Enabled. 235 * |[8] |SPLIE8 |Sample Module 8 Interrupt Enable Bit 236 * | | |0 = Sample Module 8 interrupt Disabled. 237 * | | |1 = Sample Module 8 interrupt Enabled. 238 * |[9] |SPLIE9 |Sample Module 9 Interrupt Enable Bit 239 * | | |0 = Sample Module 9 interrupt Disabled. 240 * | | |1 = Sample Module 9 interrupt Enabled. 241 * |[10] |SPLIE10 |Sample Module 10 Interrupt Enable Bit 242 * | | |0 = Sample Module 10 interrupt Disabled. 243 * | | |1 = Sample Module 10 interrupt Enabled. 244 * |[11] |SPLIE11 |Sample Module 11 Interrupt Enable Bit 245 * | | |0 = Sample Module 11 interrupt Disabled. 246 * | | |1 = Sample Module 11 interrupt Enabled. 247 * |[12] |SPLIE12 |Sample Module 12 Interrupt Enable Bit 248 * | | |0 = Sample Module 12 interrupt Disabled. 249 * | | |1 = Sample Module 12 interrupt Enabled. 250 * |[13] |SPLIE13 |Sample Module 13 Interrupt Enable Bit 251 * | | |0 = Sample Module 13 interrupt Disabled. 252 * | | |1 = Sample Module 13 interrupt Enabled. 253 * |[14] |SPLIE14 |Sample Module 14 Interrupt Enable Bit 254 * | | |0 = Sample Module 14 interrupt Disabled. 255 * | | |1 = Sample Module 14 interrupt Enabled. 256 * |[15] |SPLIE15 |Sample Module 15 Interrupt Enable Bit 257 * | | |0 = Sample Module 15 interrupt Disabled. 258 * | | |1 = Sample Module 15 interrupt Enabled. 259 * |[16] |SPLIE16 |Sample Module 16 Interrupt Enable Bit 260 * | | |0 = Sample Module 16 interrupt Disabled. 261 * | | |1 = Sample Module 16 interrupt Enabled. 262 * |[17] |SPLIE17 |Sample Module 17 Interrupt Enable Bit 263 * | | |0 = Sample Module 17 interrupt Disabled. 264 * | | |1 = Sample Module 17 interrupt Enabled. 265 * |[18] |SPLIE18 |Sample Module 18 Interrupt Enable Bit 266 * | | |0 = Sample Module 18 interrupt Disabled. 267 * | | |1 = Sample Module 18 interrupt Enabled. 268 * @var EADC_T::CMP[4] 269 * Offset: 0xE0 ADC Result Compare Register 0~3 270 * --------------------------------------------------------------------------------------------------- 271 * |Bits |Field |Descriptions 272 * | :----: | :----: | :---- | 273 * |[0] |ADCMPEN |ADC Result Compare Enable Bit 274 * | | |0 = Compare Disabled. 275 * | | |1 = Compare Enabled. 276 * | | |Set this bit to 1 to enable compare CMPDAT (EADC_CMPn[27:16], n=0~3) with specified sample module conversion result when converted data is loaded into EADC_DAT register. 277 * |[1] |ADCMPIE |ADC Result Compare Interrupt Enable Bit 278 * | | |0 = Compare function interrupt Disabled. 279 * | | |1 = Compare function interrupt Enabled. 280 * | | |If the compare function is enabled and the compare condition matches the setting of CMPCOND (EADC_CMPn[2], n=0~3) and CMPMCNT (EADC_CMPn[11:8], n=0~3), ADCMPFn (EADC_STATUS2[7:4], n=0~3) will be asserted, in the meanwhile, if ADCMPIE is set to 1, a compare interrupt request is generated. 281 * |[2] |CMPCOND |Compare Condition 282 * | | |0= Set the compare condition as that when a 12-bit ADC conversion result is less than the 12-bit CMPDAT (EADC_CMPn [27:16]), the internal match counter will increase one. 283 * | | |1= Set the compare condition as that when a 12-bit ADC conversion result is greater or equal to the 12-bit CMPDAT (EADC_CMPn [27:16]), the internal match counter will increase one. 284 * | | |Note: When the internal counter reaches the value to (CMPMCNT (EADC_CMPn[11:8], n=0~3) +1), the CMPF bit will be set. 285 * |[7:3] |CMPSPL |Compare Sample Module Selection 286 * | | |00000 = Sample Module 0 conversion result EADC_DAT0 is selected to be compared. 287 * | | |00001 = Sample Module 1 conversion result EADC_DAT1 is selected to be compared. 288 * | | |00010 = Sample Module 2 conversion result EADC_DAT2 is selected to be compared. 289 * | | |00011 = Sample Module 3 conversion result EADC_DAT3 is selected to be compared. 290 * | | |00100 = Sample Module 4 conversion result EADC_DAT4 is selected to be compared. 291 * | | |00101 = Sample Module 5 conversion result EADC_DAT5 is selected to be compared. 292 * | | |00110 = Sample Module 6 conversion result EADC_DAT6 is selected to be compared. 293 * | | |00111 = Sample Module 7 conversion result EADC_DAT7 is selected to be compared. 294 * | | |01000 = Sample Module 8 conversion result EADC_DAT8 is selected to be compared. 295 * | | |01001 = Sample Module 9 conversion result EADC_DAT9 is selected to be compared. 296 * | | |01010 = Sample Module 10 conversion result EADC_DAT10 is selected to be compared. 297 * | | |01011 = Sample Module 11 conversion result EADC_DAT11 is selected to be compared. 298 * | | |01100 = Sample Module 12 conversion result EADC_DAT12 is selected to be compared. 299 * | | |01101 = Sample Module 13 conversion result EADC_DAT13 is selected to be compared. 300 * | | |01110 = Sample Module 14 conversion result EADC_DAT14 is selected to be compared. 301 * | | |01111 = Sample Module 15 conversion result EADC_DAT15 is selected to be compared. 302 * | | |10000 = Sample Module 16 conversion result EADC_DAT16 is selected to be compared. 303 * | | |10001 = Sample Module 17 conversion result EADC_DAT17 is selected to be compared. 304 * | | |10010 = Sample Module 18 conversion result EADC_DAT18 is selected to be compared. 305 * |[11:8] |CMPMCNT |Compare Match Count 306 * | | |When the specified ADC sample module analog conversion result matches the compare condition defined by CMPCOND (EADC_CMPn[2], n=0~3), the internal match counter will increase 1 307 * | | |If the compare result does not meet the compare condition, the internal compare match counter will reset to 0 308 * | | |When the internal counter reaches the value to (CMPMCNT +1), the ADCMPFn (EADC_STATUS2[7:4], n=0~3) will be set. 309 * |[15] |CMPWEN |Compare Window Mode Enable Bit 310 * | | |0 = ADCMPF0 (EADC_STATUS2[4]) will be set when EADC_CMP0 compared condition matched 311 * | | |ADCMPF2 (EADC_STATUS2[6]) will be set when EADC_CMP2 compared condition matched 312 * | | |1 = ADCMPF0 (EADC_STATUS2[4]) will be set when both EADC_CMP0 and EADC_CMP1 compared condition matched 313 * | | |ADCMPF2 (EADC_STATUS2[6]) will be set when both EADC_CMP2 and EADC_CMP3 compared condition matched. 314 * | | |Note: This bit is only present in EADC_CMP0 and EADC_CMP2 register. 315 * |[27:16] |CMPDAT |Comparison Data 316 * | | |The 12 bits data is used to compare with conversion result of specified sample module 317 * | | |User can use it to monitor the external analog input pin voltage transition without imposing a load on software. 318 * @var EADC_T::STATUS0 319 * Offset: 0xF0 ADC Status Register 0 320 * --------------------------------------------------------------------------------------------------- 321 * |Bits |Field |Descriptions 322 * | :----: | :----: | :---- | 323 * |[15:0] |VALID |EADC_DAT0~15 Data Valid Flag 324 * | | |It is a mirror of VALID bit in sample module ADC result data register EADC_DATn. (n=0~18). 325 * |[31:16] |OV |EADC_DAT0~15 Overrun Flag 326 * | | |It is a mirror to OV bit in sample module ADC result data register EADC_DATn. (n=0~18). 327 * @var EADC_T::STATUS1 328 * Offset: 0xF4 ADC Status Register 1 329 * --------------------------------------------------------------------------------------------------- 330 * |Bits |Field |Descriptions 331 * | :----: | :----: | :---- | 332 * |[2:0] |VALID |EADC_DAT16~18 Data Valid Flag 333 * | | |It is a mirror of VALID bit in sample module ADC result data register EADC_DATn. (n=0~18). 334 * |[18:16] |OV |EADC_DAT16~18 Overrun Flag 335 * | | |It is a mirror to OV bit in sample module ADC result data register EADC_DATn. (n=0~18). 336 * @var EADC_T::STATUS2 337 * Offset: 0xF8 ADC Status Register 2 338 * --------------------------------------------------------------------------------------------------- 339 * |Bits |Field |Descriptions 340 * | :----: | :----: | :---- | 341 * |[0] |ADIF0 |ADC ADINT0 Interrupt Flag 342 * | | |0 = No ADINT0 interrupt pulse received. 343 * | | |1 = ADINT0 interrupt pulse has been received. 344 * | | |Note1: This bit is cleared by writing 1 to it. 345 * | | |Note2:This bit indicates whether an ADC conversion of specific sample module has been completed 346 * |[1] |ADIF1 |ADC ADINT1 Interrupt Flag 347 * | | |0 = No ADINT1 interrupt pulse received. 348 * | | |1 = ADINT1 interrupt pulse has been received. 349 * | | |Note1: This bit is cleared by writing 1 to it. 350 * | | |Note2:This bit indicates whether an ADC conversion of specific sample module has been completed 351 * |[2] |ADIF2 |ADC ADINT2 Interrupt Flag 352 * | | |0 = No ADINT2 interrupt pulse received. 353 * | | |1 = ADINT2 interrupt pulse has been received. 354 * | | |Note1: This bit is cleared by writing 1 to it. 355 * | | |Note2:This bit indicates whether an ADC conversion of specific sample module has been completed 356 * |[3] |ADIF3 |ADC ADINT3 Interrupt Flag 357 * | | |0 = No ADINT3 interrupt pulse received. 358 * | | |1 = ADINT3 interrupt pulse has been received. 359 * | | |Note1: This bit is cleared by writing 1 to it. 360 * | | |Note2:This bit indicates whether an ADC conversion of specific sample module has been completed 361 * |[4] |ADCMPF0 |ADC Compare 0 Flag 362 * | | |When the specific sample module ADC conversion result meets setting condition in EADC_CMP0 then this bit is set to 1. 363 * | | |0 = Conversion result in EADC_DAT does not meet EADC_CMP0 register setting. 364 * | | |1 = Conversion result in EADC_DAT meets EADC_CMP0 register setting. 365 * | | |Note: This bit is cleared by writing 1 to it. 366 * |[5] |ADCMPF1 |ADC Compare 1 Flag 367 * | | |When the specific sample module ADC conversion result meets setting condition in EADC_CMP1 then this bit is set to 1. 368 * | | |0 = Conversion result in EADC_DAT does not meet EADC_CMP1 register setting. 369 * | | |1 = Conversion result in EADC_DAT meets EADC_CMP1 register setting. 370 * | | |Note: This bit is cleared by writing 1 to it. 371 * |[6] |ADCMPF2 |ADC Compare 2 Flag 372 * | | |When the specific sample module ADC conversion result meets setting condition in EADC_CMP2 then this bit is set to 1. 373 * | | |0 = Conversion result in EADC_DAT does not meet EADC_CMP2 register setting. 374 * | | |1 = Conversion result in EADC_DAT meets EADC_CMP2 register setting. 375 * | | |Note: This bit is cleared by writing 1 to it. 376 * |[7] |ADCMPF3 |ADC Compare 3 Flag 377 * | | |When the specific sample module ADC conversion result meets setting condition in EADC_CMP3 then this bit is set to 1. 378 * | | |0 = Conversion result in EADC_DAT does not meet EADC_CMP3 register setting. 379 * | | |1 = Conversion result in EADC_DAT meets EADC_CMP3 register setting. 380 * | | |Note: This bit is cleared by writing 1 to it. 381 * |[8] |ADOVIF0 |ADC ADINT0 Interrupt Flag Overrun 382 * | | |0 = ADINT0 interrupt flag is not overwritten to 1. 383 * | | |1 = ADINT0 interrupt flag is overwritten to 1. 384 * | | |Note: This bit is cleared by writing 1 to it. 385 * |[9] |ADOVIF1 |ADC ADINT1 Interrupt Flag Overrun 386 * | | |0 = ADINT1 interrupt flag is not overwritten to 1. 387 * | | |1 = ADINT1 interrupt flag is overwritten to 1. 388 * | | |Note: This bit is cleared by writing 1 to it. 389 * |[10] |ADOVIF2 |ADC ADINT2 Interrupt Flag Overrun 390 * | | |0 = ADINT2 interrupt flag is not overwritten to 1. 391 * | | |1 = ADINT2 interrupt flag is s overwritten to 1. 392 * | | |Note: This bit is cleared by writing 1 to it. 393 * |[11] |ADOVIF3 |ADC ADINT3 Interrupt Flag Overrun 394 * | | |0 = ADINT3 interrupt flag is not overwritten to 1. 395 * | | |1 = ADINT3 interrupt flag is overwritten to 1. 396 * | | |Note: This bit is cleared by writing 1 to it. 397 * |[12] |ADCMPO0 |ADC Compare 0 Output Status (Read Only) 398 * | | |The 12 bits compare0 data CMPDAT0 (EADC_CMP0[27:16]) is used to compare with conversion result of specified sample module. 399 * | | |User can use it to monitor the external analog input pin voltage status. 400 * | | |0 = Conversion result in EADC_DAT less than CMPDAT0 setting. 401 * | | |1 = Conversion result in EADC_DAT great than or equal CMPDAT0 setting. 402 * |[13] |ADCMPO1 |ADC Compare 1 Output Status (Read Only) 403 * | | |The 12 bits compare1 data CMPDAT1 (EADC_CMP1[27:16]) is used to compare with conversion result of specified sample module. 404 * | | |User can use it to monitor the external analog input pin voltage status. 405 * | | |0 = Conversion result in EADC_DAT less than CMPDAT1 setting. 406 * | | |1 = Conversion result in EADC_DAT great than or equal CMPDAT1 setting. 407 * |[14] |ADCMPO2 |ADC Compare 2 Output Status (Read Only) 408 * | | |The 12 bits compare2 data CMPDAT2 (EADC_CMP2[27:16]) is used to compare with conversion result of specified sample module. 409 * | | |User can use it to monitor the external analog input pin voltage status. 410 * | | |0 = Conversion result in EADC_DAT less than CMPDAT2 setting. 411 * | | |1 = Conversion result in EADC_DAT great than or equal CMPDAT2 setting. 412 * |[15] |ADCMPO3 |ADC Compare 3 Output Status (Read Only) 413 * | | |The 12 bits compare3 data CMPDAT3 (EADC_CMP3[27:16]) is used to compare with conversion result of specified sample module. 414 * | | |User can use it to monitor the external analog input pin voltage status. 415 * | | |0 = Conversion result in EADC_DAT less than CMPDAT3 setting. 416 * | | |1 = Conversion result in EADC_DAT great than or equal CMPDAT3 setting. 417 * |[20:16] |CHANNEL |Current Conversion Channel (Read Only) 418 * | | |This filed reflects ADC current conversion channel when BUSY=1. 419 * | | |It is read only. 420 * | | |00H = EADC_CH0. 421 * | | |01H = EADC_CH1. 422 * | | |02H = EADC_CH2. 423 * | | |03H = EADC_CH3. 424 * | | |04H = EADC_CH4. 425 * | | |05H = EADC_CH5. 426 * | | |06H = EADC_CH6. 427 * | | |07H = EADC_CH7. 428 * | | |08H = EADC_CH8. 429 * | | |09H = EADC_CH9. 430 * | | |0AH = EADC_CH10. 431 * | | |0BH = EADC_CH11. 432 * | | |0CH = EADC_CH12. 433 * | | |0DH = EADC_CH13. 434 * | | |0EH = EADC_CH14. 435 * | | |0FH = EADC_CH15. 436 * | | |10H = VBG. 437 * | | |11H = VTEMP. 438 * | | |12H = VBAT/4. 439 * |[23] |BUSY |Busy/Idle (Read Only) 440 * | | |0 = EADC is in idle state. 441 * | | |1 = EADC is busy at conversion. 442 * |[24] |ADOVIF |All ADC Interrupt Flag Overrun Bits Check (Read Only) 443 * | | |n=0~3. 444 * | | |0 = None of ADINT interrupt flag ADOVIFn (EADC_STATUS2[11:8]) is overwritten to 1. 445 * | | |1 = Any one of ADINT interrupt flag ADOVIFn (EADC_STATUS2[11:8]) is overwritten to 1. 446 * | | |Note: This bit will keep 1 when any ADOVIFn Flag is equal to 1. 447 * |[25] |STOVF |for All ADC Sample Module Start of Conversion Overrun Flags Check (Read Only) 448 * | | |n=0~18. 449 * | | |0 = None of sample module event overrun flag SPOVFn (EADC_OVSTS[n]) is set to 1. 450 * | | |1 = Any one of sample module event overrun flag SPOVFn (EADC_OVSTS[n]) is set to 1. 451 * | | |Note: This bit will keep 1 when any SPOVFn Flag is equal to 1. 452 * |[26] |AVALID |for All Sample Module ADC Result Data Register EADC_DAT Data Valid Flag Check (Read Only) 453 * | | |n=0~18. 454 * | | |0 = None of sample module data register valid flag VALIDn (EADC_DATn[17]) is set to 1. 455 * | | |1 = Any one of sample module data register valid flag VALIDn (EADC_DATn[17]) is set to 1. 456 * | | |Note: This bit will keep 1 when any VALIDn Flag is equal to 1. 457 * |[27] |AOV |for All Sample Module ADC Result Data Register Overrun Flags Check (Read Only) 458 * | | |n=0~18. 459 * | | |0 = None of sample module data register overrun flag OVn (EADC_DATn[16]) is set to 1. 460 * | | |1 = Any one of sample module data register overrun flag OVn (EADC_DATn[16]) is set to 1. 461 * | | |Note: This bit will keep 1 when any OVn Flag is equal to 1. 462 * @var EADC_T::STATUS3 463 * Offset: 0xFC ADC Status Register 3 464 * --------------------------------------------------------------------------------------------------- 465 * |Bits |Field |Descriptions 466 * | :----: | :----: | :---- | 467 * |[4:0] |CURSPL |ADC Current Sample Module 468 * | | |This register show the current ADC is controlled by which sample module control logic modules. 469 * | | |If the ADC is Idle, this bit filed will set to 0x1F. 470 * | | |This is a read only register. 471 * @var EADC_T::DDAT 472 * Offset: 0x100-0x10C ADC Double Data Register n for Sample Module n, n=0~3 473 * --------------------------------------------------------------------------------------------------- 474 * |Bits |Field |Descriptions 475 * | :----: | :----: | :---- | 476 * |[15:0] |RESULT |ADC Conversion Results 477 * | | |This field contains 12 bits conversion results. 478 * | | |When the DMOF (EADC_CTL[9]) is set to 0, 12-bit ADC conversion result with unsigned format will be filled in RESULT [11:0] and zero will be filled in RESULT [15:12]. 479 * | | |When DMOF (EADC_CTL[9]) set to 1, 12-bit ADC conversion result with 2'complement format will be filled in RESULT [11:0] and signed bits to will be filled in RESULT [15:12]. 480 * |[16] |OV |Overrun Flag 481 * | | |0 = Data in RESULT (EADC_DATn[15:0], n=0~3) is recent conversion result. 482 * | | |1 = Data in RESULT (EADC_DATn[15:0], n=0~3) is overwrite. 483 * | | |If converted data in RESULT[15:0] has not been read before new conversion result is loaded to this register, OV is set to 1. 484 * | | |It is cleared by hardware after EADC_DDAT register is read. 485 * |[17] |VALID |Valid Flag 486 * | | |0 = Double data in RESULT (EADC_DDATn[15:0]) is not valid. 487 * | | |1 = Double data in RESULT (EADC_DDATn[15:0]) is valid. 488 * | | |This bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DDATn register is read. 489 * | | |(n=0~3). 490 * @var EADC_T::PWRM 491 * Offset: 0x110 ADC Power Management Register 492 * --------------------------------------------------------------------------------------------------- 493 * |Bits |Field |Descriptions 494 * | :----: | :----: | :---- | 495 * |[0] |PWUPRDY |ADC Power-up Sequence Completed and Ready for Conversion (Read Only) 496 * | | |0 = ADC is not ready for conversion may be in power down state or in the progress of power up. 497 * | | |1 = ADC is ready for conversion. 498 * |[1] |PWUCALEN |Power Up Calibration Function Enable Control 499 * | | |0 = Disable the function of calibration at power up. 500 * | | |1 = Enable the function of calibration at power up. 501 * | | |Note: This bit work together with CALSEL (EADC_CALCTL [3]), see the following 502 * | | |{PWUCALEN, CALSEL } Description: 503 * | | |PWUCALEN is 0 and CALSEL is 0: No need to calibrate. 504 * | | |PWUCALEN is 0 and CALSEL is 1: No need to calibrate. 505 * | | |PWUCALEN is 1 and CALSEL is 0: Load calibration word when power up. 506 * | | |PWUCALEN is 1 and CALSEL is 1: Calibrate when power up. 507 * |[3:2] |PWDMOD |ADC Power-down Mode 508 * | | |Set this bit fields to select ADC power down mode when system power-down. 509 * | | |00 = ADC Deep power down mode. 510 * | | |01 = ADC Power down. 511 * | | |10 = ADC Standby mode. 512 * | | |11 = ADC Deep power down mode. 513 * | | |Note: Different PWDMOD has different power down/up sequence, in order to avoid ADC powering up with wrong sequence; user must keep PWMOD consistent each time in power down and start up 514 * |[19:8] |LDOSUT |ADC Internal LDO Start-up Time 515 * | | |Set this bit fields to control LDO start-up time 516 * | | |The minimum required LDO start-up time is 20us 517 * | | |LDO start-up time = (1/ADC_CLK) x LDOSUT. 518 * @var EADC_T::CALCTL 519 * Offset: 0x114 ADC Calibration Control Register 520 * --------------------------------------------------------------------------------------------------- 521 * |Bits |Field |Descriptions 522 * | :----: | :----: | :---- | 523 * |[1] |CALSTART |Calibration Functional Block Start 524 * | | |0 = Stops calibration functional block. 525 * | | |1 = Starts calibration functional block. 526 * | | |Note: This bit is set by SW and clear by HW after re-calibration finish 527 * |[2] |CALDONE |Calibration Functional Block Complete (Read Only) 528 * | | |0 = During a calibration. 529 * | | |1 = Calibration is completed. 530 * |[3] |CALSEL |Select Calibration Functional Block 531 * | | |0 = Load calibration word when calibration functional block is active. 532 * | | |1 = Execute calibration when calibration functional block is active. 533 * @var EADC_T::CALDWRD 534 * Offset: 0x118 ADC Calibration Load Word Register 535 * --------------------------------------------------------------------------------------------------- 536 * |Bits |Field |Descriptions 537 * | :----: | :----: | :---- | 538 * |[6:0] |CALWORD |Calibration Word Bits 539 * | | |Write to this register with the previous calibration word before load calibration action. 540 * | | |Read this register after calibration done. 541 * | | |Note: The calibration block contains two parts CALIBRATION and LOAD CALIBRATION; if the calibration block configure as CALIBRATION; then this register represent the result of calibration when calibration is completed; if configure as LOAD CALIBRATION ; configure this register before loading calibration action, after loading calibration complete, the laoded calibration word will apply to the ADC; while in loading calibration function the loaded value will not be equal to the original CALWORD until calibration is done. 542 */ 543 544 __I uint32_t DAT[19]; /*!< [0x0000~0x0048] ADC Data Register n for Sample Module n, n=0~18 */ 545 __I uint32_t CURDAT; /*!< [0x004c] ADC PDMA Current Transfer Data Register */ 546 __IO uint32_t CTL; /*!< [0x0050] ADC Control Register */ 547 __O uint32_t SWTRG; /*!< [0x0054] ADC Sample Module Software Start Register */ 548 __IO uint32_t PENDSTS; /*!< [0x0058] ADC Start of Conversion Pending Flag Register */ 549 __IO uint32_t OVSTS; /*!< [0x005c] ADC Sample Module Start of Conversion Overrun Flag Register */ 550 __I uint32_t RESERVE0[8]; 551 __IO uint32_t SCTL[19]; /*!< [0x0080~0x00c8] ADC Sample Module n Control Register, n=0~18 */ 552 __I uint32_t RESERVE1[1]; 553 __IO uint32_t INTSRC[4]; /*!< [0x00d0~0x00dc] ADC interrupt n Source Enable Control Register, n=0~3 */ 554 __IO uint32_t CMP[4]; /*!< [0x00e0~0x00ec] ADC Result Compare Register n, n=0~3 */ 555 __I uint32_t STATUS0; /*!< [0x00f0] ADC Status Register 0 */ 556 __I uint32_t STATUS1; /*!< [0x00f4] ADC Status Register 1 */ 557 __IO uint32_t STATUS2; /*!< [0x00f8] ADC Status Register 2 */ 558 __I uint32_t STATUS3; /*!< [0x00fc] ADC Status Register 3 */ 559 __I uint32_t DDAT[4]; /*!< [0x0100~0x010c] ADC Double Data Register n for Sample Module n, n=0~3 */ 560 __IO uint32_t PWRM; /*!< [0x0110] ADC Power Management Register */ 561 __IO uint32_t CALCTL; /*!< [0x0114] ADC Calibration Control Register */ 562 __IO uint32_t CALDWRD; /*!< [0x0118] ADC Calibration Load Word Register */ 563 564 } EADC_T; 565 566 /** 567 @addtogroup EADC_CONST EADC Bit Field Definition 568 Constant Definitions for EADC Controller 569 @{ */ 570 571 #define EADC_DAT_RESULT_Pos (0) /*!< EADC_T::DAT: RESULT Position */ 572 #define EADC_DAT_RESULT_Msk (0xfffful << EADC_DAT_RESULT_Pos) /*!< EADC_T::DAT: RESULT Mask */ 573 574 #define EADC_DAT_OV_Pos (16) /*!< EADC_T::DAT: OV Position */ 575 #define EADC_DAT_OV_Msk (0x1ul << EADC_DAT_OV_Pos) /*!< EADC_T::DAT: OV Mask */ 576 577 #define EADC_DAT_VALID_Pos (17) /*!< EADC_T::DAT: VALID Position */ 578 #define EADC_DAT_VALID_Msk (0x1ul << EADC_DAT_VALID_Pos) /*!< EADC_T::DAT: VALID Mask */ 579 580 #define EADC_DAT0_RESULT_Pos (0) /*!< EADC_T::DAT0: RESULT Position */ 581 #define EADC_DAT0_RESULT_Msk (0xfffful << EADC_DAT0_RESULT_Pos) /*!< EADC_T::DAT0: RESULT Mask */ 582 583 #define EADC_DAT0_OV_Pos (16) /*!< EADC_T::DAT0: OV Position */ 584 #define EADC_DAT0_OV_Msk (0x1ul << EADC_DAT0_OV_Pos) /*!< EADC_T::DAT0: OV Mask */ 585 586 #define EADC_DAT0_VALID_Pos (17) /*!< EADC_T::DAT0: VALID Position */ 587 #define EADC_DAT0_VALID_Msk (0x1ul << EADC_DAT0_VALID_Pos) /*!< EADC_T::DAT0: VALID Mask */ 588 589 #define EADC_DAT1_RESULT_Pos (0) /*!< EADC_T::DAT1: RESULT Position */ 590 #define EADC_DAT1_RESULT_Msk (0xfffful << EADC_DAT1_RESULT_Pos) /*!< EADC_T::DAT1: RESULT Mask */ 591 592 #define EADC_DAT1_OV_Pos (16) /*!< EADC_T::DAT1: OV Position */ 593 #define EADC_DAT1_OV_Msk (0x1ul << EADC_DAT1_OV_Pos) /*!< EADC_T::DAT1: OV Mask */ 594 595 #define EADC_DAT1_VALID_Pos (17) /*!< EADC_T::DAT1: VALID Position */ 596 #define EADC_DAT1_VALID_Msk (0x1ul << EADC_DAT1_VALID_Pos) /*!< EADC_T::DAT1: VALID Mask */ 597 598 #define EADC_DAT2_RESULT_Pos (0) /*!< EADC_T::DAT2: RESULT Position */ 599 #define EADC_DAT2_RESULT_Msk (0xfffful << EADC_DAT2_RESULT_Pos) /*!< EADC_T::DAT2: RESULT Mask */ 600 601 #define EADC_DAT2_OV_Pos (16) /*!< EADC_T::DAT2: OV Position */ 602 #define EADC_DAT2_OV_Msk (0x1ul << EADC_DAT2_OV_Pos) /*!< EADC_T::DAT2: OV Mask */ 603 604 #define EADC_DAT2_VALID_Pos (17) /*!< EADC_T::DAT2: VALID Position */ 605 #define EADC_DAT2_VALID_Msk (0x1ul << EADC_DAT2_VALID_Pos) /*!< EADC_T::DAT2: VALID Mask */ 606 607 #define EADC_DAT3_RESULT_Pos (0) /*!< EADC_T::DAT3: RESULT Position */ 608 #define EADC_DAT3_RESULT_Msk (0xfffful << EADC_DAT3_RESULT_Pos) /*!< EADC_T::DAT3: RESULT Mask */ 609 610 #define EADC_DAT3_OV_Pos (16) /*!< EADC_T::DAT3: OV Position */ 611 #define EADC_DAT3_OV_Msk (0x1ul << EADC_DAT3_OV_Pos) /*!< EADC_T::DAT3: OV Mask */ 612 613 #define EADC_DAT3_VALID_Pos (17) /*!< EADC_T::DAT3: VALID Position */ 614 #define EADC_DAT3_VALID_Msk (0x1ul << EADC_DAT3_VALID_Pos) /*!< EADC_T::DAT3: VALID Mask */ 615 616 #define EADC_DAT4_RESULT_Pos (0) /*!< EADC_T::DAT4: RESULT Position */ 617 #define EADC_DAT4_RESULT_Msk (0xfffful << EADC_DAT4_RESULT_Pos) /*!< EADC_T::DAT4: RESULT Mask */ 618 619 #define EADC_DAT4_OV_Pos (16) /*!< EADC_T::DAT4: OV Position */ 620 #define EADC_DAT4_OV_Msk (0x1ul << EADC_DAT4_OV_Pos) /*!< EADC_T::DAT4: OV Mask */ 621 622 #define EADC_DAT4_VALID_Pos (17) /*!< EADC_T::DAT4: VALID Position */ 623 #define EADC_DAT4_VALID_Msk (0x1ul << EADC_DAT4_VALID_Pos) /*!< EADC_T::DAT4: VALID Mask */ 624 625 #define EADC_DAT5_RESULT_Pos (0) /*!< EADC_T::DAT5: RESULT Position */ 626 #define EADC_DAT5_RESULT_Msk (0xfffful << EADC_DAT5_RESULT_Pos) /*!< EADC_T::DAT5: RESULT Mask */ 627 628 #define EADC_DAT5_OV_Pos (16) /*!< EADC_T::DAT5: OV Position */ 629 #define EADC_DAT5_OV_Msk (0x1ul << EADC_DAT5_OV_Pos) /*!< EADC_T::DAT5: OV Mask */ 630 631 #define EADC_DAT5_VALID_Pos (17) /*!< EADC_T::DAT5: VALID Position */ 632 #define EADC_DAT5_VALID_Msk (0x1ul << EADC_DAT5_VALID_Pos) /*!< EADC_T::DAT5: VALID Mask */ 633 634 #define EADC_DAT6_RESULT_Pos (0) /*!< EADC_T::DAT6: RESULT Position */ 635 #define EADC_DAT6_RESULT_Msk (0xfffful << EADC_DAT6_RESULT_Pos) /*!< EADC_T::DAT6: RESULT Mask */ 636 637 #define EADC_DAT6_OV_Pos (16) /*!< EADC_T::DAT6: OV Position */ 638 #define EADC_DAT6_OV_Msk (0x1ul << EADC_DAT6_OV_Pos) /*!< EADC_T::DAT6: OV Mask */ 639 640 #define EADC_DAT6_VALID_Pos (17) /*!< EADC_T::DAT6: VALID Position */ 641 #define EADC_DAT6_VALID_Msk (0x1ul << EADC_DAT6_VALID_Pos) /*!< EADC_T::DAT6: VALID Mask */ 642 643 #define EADC_DAT7_RESULT_Pos (0) /*!< EADC_T::DAT7: RESULT Position */ 644 #define EADC_DAT7_RESULT_Msk (0xfffful << EADC_DAT7_RESULT_Pos) /*!< EADC_T::DAT7: RESULT Mask */ 645 646 #define EADC_DAT7_OV_Pos (16) /*!< EADC_T::DAT7: OV Position */ 647 #define EADC_DAT7_OV_Msk (0x1ul << EADC_DAT7_OV_Pos) /*!< EADC_T::DAT7: OV Mask */ 648 649 #define EADC_DAT7_VALID_Pos (17) /*!< EADC_T::DAT7: VALID Position */ 650 #define EADC_DAT7_VALID_Msk (0x1ul << EADC_DAT7_VALID_Pos) /*!< EADC_T::DAT7: VALID Mask */ 651 652 #define EADC_DAT8_RESULT_Pos (0) /*!< EADC_T::DAT8: RESULT Position */ 653 #define EADC_DAT8_RESULT_Msk (0xfffful << EADC_DAT8_RESULT_Pos) /*!< EADC_T::DAT8: RESULT Mask */ 654 655 #define EADC_DAT8_OV_Pos (16) /*!< EADC_T::DAT8: OV Position */ 656 #define EADC_DAT8_OV_Msk (0x1ul << EADC_DAT8_OV_Pos) /*!< EADC_T::DAT8: OV Mask */ 657 658 #define EADC_DAT8_VALID_Pos (17) /*!< EADC_T::DAT8: VALID Position */ 659 #define EADC_DAT8_VALID_Msk (0x1ul << EADC_DAT8_VALID_Pos) /*!< EADC_T::DAT8: VALID Mask */ 660 661 #define EADC_DAT9_RESULT_Pos (0) /*!< EADC_T::DAT9: RESULT Position */ 662 #define EADC_DAT9_RESULT_Msk (0xfffful << EADC_DAT9_RESULT_Pos) /*!< EADC_T::DAT9: RESULT Mask */ 663 664 #define EADC_DAT9_OV_Pos (16) /*!< EADC_T::DAT9: OV Position */ 665 #define EADC_DAT9_OV_Msk (0x1ul << EADC_DAT9_OV_Pos) /*!< EADC_T::DAT9: OV Mask */ 666 667 #define EADC_DAT9_VALID_Pos (17) /*!< EADC_T::DAT9: VALID Position */ 668 #define EADC_DAT9_VALID_Msk (0x1ul << EADC_DAT9_VALID_Pos) /*!< EADC_T::DAT9: VALID Mask */ 669 670 #define EADC_DAT10_RESULT_Pos (0) /*!< EADC_T::DAT10: RESULT Position */ 671 #define EADC_DAT10_RESULT_Msk (0xfffful << EADC_DAT10_RESULT_Pos) /*!< EADC_T::DAT10: RESULT Mask */ 672 673 #define EADC_DAT10_OV_Pos (16) /*!< EADC_T::DAT10: OV Position */ 674 #define EADC_DAT10_OV_Msk (0x1ul << EADC_DAT10_OV_Pos) /*!< EADC_T::DAT10: OV Mask */ 675 676 #define EADC_DAT10_VALID_Pos (17) /*!< EADC_T::DAT10: VALID Position */ 677 #define EADC_DAT10_VALID_Msk (0x1ul << EADC_DAT10_VALID_Pos) /*!< EADC_T::DAT10: VALID Mask */ 678 679 #define EADC_DAT11_RESULT_Pos (0) /*!< EADC_T::DAT11: RESULT Position */ 680 #define EADC_DAT11_RESULT_Msk (0xfffful << EADC_DAT11_RESULT_Pos) /*!< EADC_T::DAT11: RESULT Mask */ 681 682 #define EADC_DAT11_OV_Pos (16) /*!< EADC_T::DAT11: OV Position */ 683 #define EADC_DAT11_OV_Msk (0x1ul << EADC_DAT11_OV_Pos) /*!< EADC_T::DAT11: OV Mask */ 684 685 #define EADC_DAT11_VALID_Pos (17) /*!< EADC_T::DAT11: VALID Position */ 686 #define EADC_DAT11_VALID_Msk (0x1ul << EADC_DAT11_VALID_Pos) /*!< EADC_T::DAT11: VALID Mask */ 687 688 #define EADC_DAT12_RESULT_Pos (0) /*!< EADC_T::DAT12: RESULT Position */ 689 #define EADC_DAT12_RESULT_Msk (0xfffful << EADC_DAT12_RESULT_Pos) /*!< EADC_T::DAT12: RESULT Mask */ 690 691 #define EADC_DAT12_OV_Pos (16) /*!< EADC_T::DAT12: OV Position */ 692 #define EADC_DAT12_OV_Msk (0x1ul << EADC_DAT12_OV_Pos) /*!< EADC_T::DAT12: OV Mask */ 693 694 #define EADC_DAT12_VALID_Pos (17) /*!< EADC_T::DAT12: VALID Position */ 695 #define EADC_DAT12_VALID_Msk (0x1ul << EADC_DAT12_VALID_Pos) /*!< EADC_T::DAT12: VALID Mask */ 696 697 #define EADC_DAT13_RESULT_Pos (0) /*!< EADC_T::DAT13: RESULT Position */ 698 #define EADC_DAT13_RESULT_Msk (0xfffful << EADC_DAT13_RESULT_Pos) /*!< EADC_T::DAT13: RESULT Mask */ 699 700 #define EADC_DAT13_OV_Pos (16) /*!< EADC_T::DAT13: OV Position */ 701 #define EADC_DAT13_OV_Msk (0x1ul << EADC_DAT13_OV_Pos) /*!< EADC_T::DAT13: OV Mask */ 702 703 #define EADC_DAT13_VALID_Pos (17) /*!< EADC_T::DAT13: VALID Position */ 704 #define EADC_DAT13_VALID_Msk (0x1ul << EADC_DAT13_VALID_Pos) /*!< EADC_T::DAT13: VALID Mask */ 705 706 #define EADC_DAT14_RESULT_Pos (0) /*!< EADC_T::DAT14: RESULT Position */ 707 #define EADC_DAT14_RESULT_Msk (0xfffful << EADC_DAT14_RESULT_Pos) /*!< EADC_T::DAT14: RESULT Mask */ 708 709 #define EADC_DAT14_OV_Pos (16) /*!< EADC_T::DAT14: OV Position */ 710 #define EADC_DAT14_OV_Msk (0x1ul << EADC_DAT14_OV_Pos) /*!< EADC_T::DAT14: OV Mask */ 711 712 #define EADC_DAT14_VALID_Pos (17) /*!< EADC_T::DAT14: VALID Position */ 713 #define EADC_DAT14_VALID_Msk (0x1ul << EADC_DAT14_VALID_Pos) /*!< EADC_T::DAT14: VALID Mask */ 714 715 #define EADC_DAT15_RESULT_Pos (0) /*!< EADC_T::DAT15: RESULT Position */ 716 #define EADC_DAT15_RESULT_Msk (0xfffful << EADC_DAT15_RESULT_Pos) /*!< EADC_T::DAT15: RESULT Mask */ 717 718 #define EADC_DAT15_OV_Pos (16) /*!< EADC_T::DAT15: OV Position */ 719 #define EADC_DAT15_OV_Msk (0x1ul << EADC_DAT15_OV_Pos) /*!< EADC_T::DAT15: OV Mask */ 720 721 #define EADC_DAT15_VALID_Pos (17) /*!< EADC_T::DAT15: VALID Position */ 722 #define EADC_DAT15_VALID_Msk (0x1ul << EADC_DAT15_VALID_Pos) /*!< EADC_T::DAT15: VALID Mask */ 723 724 #define EADC_DAT16_RESULT_Pos (0) /*!< EADC_T::DAT16: RESULT Position */ 725 #define EADC_DAT16_RESULT_Msk (0xfffful << EADC_DAT16_RESULT_Pos) /*!< EADC_T::DAT16: RESULT Mask */ 726 727 #define EADC_DAT16_OV_Pos (16) /*!< EADC_T::DAT16: OV Position */ 728 #define EADC_DAT16_OV_Msk (0x1ul << EADC_DAT16_OV_Pos) /*!< EADC_T::DAT16: OV Mask */ 729 730 #define EADC_DAT16_VALID_Pos (17) /*!< EADC_T::DAT16: VALID Position */ 731 #define EADC_DAT16_VALID_Msk (0x1ul << EADC_DAT16_VALID_Pos) /*!< EADC_T::DAT16: VALID Mask */ 732 733 #define EADC_DAT17_RESULT_Pos (0) /*!< EADC_T::DAT17: RESULT Position */ 734 #define EADC_DAT17_RESULT_Msk (0xfffful << EADC_DAT17_RESULT_Pos) /*!< EADC_T::DAT17: RESULT Mask */ 735 736 #define EADC_DAT17_OV_Pos (16) /*!< EADC_T::DAT17: OV Position */ 737 #define EADC_DAT17_OV_Msk (0x1ul << EADC_DAT17_OV_Pos) /*!< EADC_T::DAT17: OV Mask */ 738 739 #define EADC_DAT17_VALID_Pos (17) /*!< EADC_T::DAT17: VALID Position */ 740 #define EADC_DAT17_VALID_Msk (0x1ul << EADC_DAT17_VALID_Pos) /*!< EADC_T::DAT17: VALID Mask */ 741 742 #define EADC_DAT18_RESULT_Pos (0) /*!< EADC_T::DAT18: RESULT Position */ 743 #define EADC_DAT18_RESULT_Msk (0xfffful << EADC_DAT18_RESULT_Pos) /*!< EADC_T::DAT18: RESULT Mask */ 744 745 #define EADC_DAT18_OV_Pos (16) /*!< EADC_T::DAT18: OV Position */ 746 #define EADC_DAT18_OV_Msk (0x1ul << EADC_DAT18_OV_Pos) /*!< EADC_T::DAT18: OV Mask */ 747 748 #define EADC_DAT18_VALID_Pos (17) /*!< EADC_T::DAT18: VALID Position */ 749 #define EADC_DAT18_VALID_Msk (0x1ul << EADC_DAT18_VALID_Pos) /*!< EADC_T::DAT18: VALID Mask */ 750 751 #define EADC_CURDAT_CURDAT_Pos (0) /*!< EADC_T::CURDAT: CURDAT Position */ 752 #define EADC_CURDAT_CURDAT_Msk (0x3fffful << EADC_CURDAT_CURDAT_Pos) /*!< EADC_T::CURDAT: CURDAT Mask */ 753 754 #define EADC_CTL_ADCEN_Pos (0) /*!< EADC_T::CTL: ADCEN Position */ 755 #define EADC_CTL_ADCEN_Msk (0x1ul << EADC_CTL_ADCEN_Pos) /*!< EADC_T::CTL: ADCEN Mask */ 756 757 #define EADC_CTL_ADCRST_Pos (1) /*!< EADC_T::CTL: ADCRST Position */ 758 #define EADC_CTL_ADCRST_Msk (0x1ul << EADC_CTL_ADCRST_Pos) /*!< EADC_T::CTL: ADCRST Mask */ 759 760 #define EADC_CTL_ADCIEN0_Pos (2) /*!< EADC_T::CTL: ADCIEN0 Position */ 761 #define EADC_CTL_ADCIEN0_Msk (0x1ul << EADC_CTL_ADCIEN0_Pos) /*!< EADC_T::CTL: ADCIEN0 Mask */ 762 763 #define EADC_CTL_ADCIEN1_Pos (3) /*!< EADC_T::CTL: ADCIEN1 Position */ 764 #define EADC_CTL_ADCIEN1_Msk (0x1ul << EADC_CTL_ADCIEN1_Pos) /*!< EADC_T::CTL: ADCIEN1 Mask */ 765 766 #define EADC_CTL_ADCIEN2_Pos (4) /*!< EADC_T::CTL: ADCIEN2 Position */ 767 #define EADC_CTL_ADCIEN2_Msk (0x1ul << EADC_CTL_ADCIEN2_Pos) /*!< EADC_T::CTL: ADCIEN2 Mask */ 768 769 #define EADC_CTL_ADCIEN3_Pos (5) /*!< EADC_T::CTL: ADCIEN3 Position */ 770 #define EADC_CTL_ADCIEN3_Msk (0x1ul << EADC_CTL_ADCIEN3_Pos) /*!< EADC_T::CTL: ADCIEN3 Mask */ 771 772 #define EADC_CTL_RESSEL_Pos (6) /*!< EADC_T::CTL: RESSEL Position */ 773 #define EADC_CTL_RESSEL_Msk (0x3ul << EADC_CTL_RESSEL_Pos) /*!< EADC_T::CTL: RESSEL Mask */ 774 775 #define EADC_CTL_DIFFEN_Pos (8) /*!< EADC_T::CTL: DIFFEN Position */ 776 #define EADC_CTL_DIFFEN_Msk (0x1ul << EADC_CTL_DIFFEN_Pos) /*!< EADC_T::CTL: DIFFEN Mask */ 777 778 #define EADC_CTL_DMOF_Pos (9) /*!< EADC_T::CTL: DMOF Position */ 779 #define EADC_CTL_DMOF_Msk (0x1ul << EADC_CTL_DMOF_Pos) /*!< EADC_T::CTL: DMOF Mask */ 780 781 #define EADC_CTL_PDMAEN_Pos (11) /*!< EADC_T::CTL: PDMAEN Position */ 782 #define EADC_CTL_PDMAEN_Msk (0x1ul << EADC_CTL_PDMAEN_Pos) /*!< EADC_T::CTL: PDMAEN Mask */ 783 784 #define EADC_SWTRG_SWTRG_Pos (0) /*!< EADC_T::SWTRG: SWTRG Position */ 785 #define EADC_SWTRG_SWTRG_Msk (0x7fffful << EADC_SWTRG_SWTRG_Pos) /*!< EADC_T::SWTRG: SWTRG Mask */ 786 787 #define EADC_PENDSTS_STPF_Pos (0) /*!< EADC_T::PENDSTS: STPF Position */ 788 #define EADC_PENDSTS_STPF_Msk (0x7fffful << EADC_PENDSTS_STPF_Pos) /*!< EADC_T::PENDSTS: STPF Mask */ 789 790 #define EADC_OVSTS_SPOVF_Pos (0) /*!< EADC_T::OVSTS: SPOVF Position */ 791 #define EADC_OVSTS_SPOVF_Msk (0x7fffful << EADC_OVSTS_SPOVF_Pos) /*!< EADC_T::OVSTS: SPOVF Mask */ 792 793 #define EADC_SCTL_CHSEL_Pos (0) /*!< EADC_T::SCTL: CHSEL Position */ 794 #define EADC_SCTL_CHSEL_Msk (0xful << EADC_SCTL_CHSEL_Pos) /*!< EADC_T::SCTL: CHSEL Mask */ 795 796 #define EADC_SCTL_EXTREN_Pos (4) /*!< EADC_T::SCTL: EXTREN Position */ 797 #define EADC_SCTL_EXTREN_Msk (0x1ul << EADC_SCTL_EXTREN_Pos) /*!< EADC_T::SCTL: EXTREN Mask */ 798 799 #define EADC_SCTL_EXTFEN_Pos (5) /*!< EADC_T::SCTL: EXTFEN Position */ 800 #define EADC_SCTL_EXTFEN_Msk (0x1ul << EADC_SCTL_EXTFEN_Pos) /*!< EADC_T::SCTL: EXTFEN Mask */ 801 802 #define EADC_SCTL_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL: TRGDLYDIV Position */ 803 #define EADC_SCTL_TRGDLYDIV_Msk (0x3ul << EADC_SCTL_TRGDLYDIV_Pos) /*!< EADC_T::SCTL: TRGDLYDIV Mask */ 804 805 #define EADC_SCTL_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL: TRGDLYCNT Position */ 806 #define EADC_SCTL_TRGDLYCNT_Msk (0xfful << EADC_SCTL_TRGDLYCNT_Pos) /*!< EADC_T::SCTL: TRGDLYCNT Mask */ 807 808 #define EADC_SCTL_TRGSEL_Pos (16) /*!< EADC_T::SCTL: TRGSEL Position */ 809 #define EADC_SCTL_TRGSEL_Msk (0x1ful << EADC_SCTL_TRGSEL_Pos) /*!< EADC_T::SCTL: TRGSEL Mask */ 810 811 #define EADC_SCTL_INTPOS_Pos (22) /*!< EADC_T::SCTL: INTPOS Position */ 812 #define EADC_SCTL_INTPOS_Msk (0x1ul << EADC_SCTL_INTPOS_Pos) /*!< EADC_T::SCTL: INTPOS Mask */ 813 814 #define EADC_SCTL_DBMEN_Pos (23) /*!< EADC_T::SCTL: DBMEN Position */ 815 #define EADC_SCTL_DBMEN_Msk (0x1ul << EADC_SCTL_DBMEN_Pos) /*!< EADC_T::SCTL: DBMEN Mask */ 816 817 #define EADC_SCTL_EXTSMPT_Pos (24) /*!< EADC_T::SCTL: EXTSMPT Position */ 818 #define EADC_SCTL_EXTSMPT_Msk (0xfful << EADC_SCTL_EXTSMPT_Pos) /*!< EADC_T::SCTL: EXTSMPT Mask */ 819 820 #define EADC_SCTL0_CHSEL_Pos (0) /*!< EADC_T::SCTL0: CHSEL Position */ 821 #define EADC_SCTL0_CHSEL_Msk (0xful << EADC_SCTL0_CHSEL_Pos) /*!< EADC_T::SCTL0: CHSEL Mask */ 822 823 #define EADC_SCTL0_EXTREN_Pos (4) /*!< EADC_T::SCTL0: EXTREN Position */ 824 #define EADC_SCTL0_EXTREN_Msk (0x1ul << EADC_SCTL0_EXTREN_Pos) /*!< EADC_T::SCTL0: EXTREN Mask */ 825 826 #define EADC_SCTL0_EXTFEN_Pos (5) /*!< EADC_T::SCTL0: EXTFEN Position */ 827 #define EADC_SCTL0_EXTFEN_Msk (0x1ul << EADC_SCTL0_EXTFEN_Pos) /*!< EADC_T::SCTL0: EXTFEN Mask */ 828 829 #define EADC_SCTL0_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL0: TRGDLYDIV Position */ 830 #define EADC_SCTL0_TRGDLYDIV_Msk (0x3ul << EADC_SCTL0_TRGDLYDIV_Pos) /*!< EADC_T::SCTL0: TRGDLYDIV Mask */ 831 832 #define EADC_SCTL0_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL0: TRGDLYCNT Position */ 833 #define EADC_SCTL0_TRGDLYCNT_Msk (0xfful << EADC_SCTL0_TRGDLYCNT_Pos) /*!< EADC_T::SCTL0: TRGDLYCNT Mask */ 834 835 #define EADC_SCTL0_TRGSEL_Pos (16) /*!< EADC_T::SCTL0: TRGSEL Position */ 836 #define EADC_SCTL0_TRGSEL_Msk (0x1ful << EADC_SCTL0_TRGSEL_Pos) /*!< EADC_T::SCTL0: TRGSEL Mask */ 837 838 #define EADC_SCTL0_INTPOS_Pos (22) /*!< EADC_T::SCTL0: INTPOS Position */ 839 #define EADC_SCTL0_INTPOS_Msk (0x1ul << EADC_SCTL0_INTPOS_Pos) /*!< EADC_T::SCTL0: INTPOS Mask */ 840 841 #define EADC_SCTL0_DBMEN_Pos (23) /*!< EADC_T::SCTL0: DBMEN Position */ 842 #define EADC_SCTL0_DBMEN_Msk (0x1ul << EADC_SCTL0_DBMEN_Pos) /*!< EADC_T::SCTL0: DBMEN Mask */ 843 844 #define EADC_SCTL0_EXTSMPT_Pos (24) /*!< EADC_T::SCTL0: EXTSMPT Position */ 845 #define EADC_SCTL0_EXTSMPT_Msk (0xfful << EADC_SCTL0_EXTSMPT_Pos) /*!< EADC_T::SCTL0: EXTSMPT Mask */ 846 847 #define EADC_SCTL1_CHSEL_Pos (0) /*!< EADC_T::SCTL1: CHSEL Position */ 848 #define EADC_SCTL1_CHSEL_Msk (0xful << EADC_SCTL1_CHSEL_Pos) /*!< EADC_T::SCTL1: CHSEL Mask */ 849 850 #define EADC_SCTL1_EXTREN_Pos (4) /*!< EADC_T::SCTL1: EXTREN Position */ 851 #define EADC_SCTL1_EXTREN_Msk (0x1ul << EADC_SCTL1_EXTREN_Pos) /*!< EADC_T::SCTL1: EXTREN Mask */ 852 853 #define EADC_SCTL1_EXTFEN_Pos (5) /*!< EADC_T::SCTL1: EXTFEN Position */ 854 #define EADC_SCTL1_EXTFEN_Msk (0x1ul << EADC_SCTL1_EXTFEN_Pos) /*!< EADC_T::SCTL1: EXTFEN Mask */ 855 856 #define EADC_SCTL1_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL1: TRGDLYDIV Position */ 857 #define EADC_SCTL1_TRGDLYDIV_Msk (0x3ul << EADC_SCTL1_TRGDLYDIV_Pos) /*!< EADC_T::SCTL1: TRGDLYDIV Mask */ 858 859 #define EADC_SCTL1_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL1: TRGDLYCNT Position */ 860 #define EADC_SCTL1_TRGDLYCNT_Msk (0xfful << EADC_SCTL1_TRGDLYCNT_Pos) /*!< EADC_T::SCTL1: TRGDLYCNT Mask */ 861 862 #define EADC_SCTL1_TRGSEL_Pos (16) /*!< EADC_T::SCTL1: TRGSEL Position */ 863 #define EADC_SCTL1_TRGSEL_Msk (0x1ful << EADC_SCTL1_TRGSEL_Pos) /*!< EADC_T::SCTL1: TRGSEL Mask */ 864 865 #define EADC_SCTL1_INTPOS_Pos (22) /*!< EADC_T::SCTL1: INTPOS Position */ 866 #define EADC_SCTL1_INTPOS_Msk (0x1ul << EADC_SCTL1_INTPOS_Pos) /*!< EADC_T::SCTL1: INTPOS Mask */ 867 868 #define EADC_SCTL1_DBMEN_Pos (23) /*!< EADC_T::SCTL1: DBMEN Position */ 869 #define EADC_SCTL1_DBMEN_Msk (0x1ul << EADC_SCTL1_DBMEN_Pos) /*!< EADC_T::SCTL1: DBMEN Mask */ 870 871 #define EADC_SCTL1_EXTSMPT_Pos (24) /*!< EADC_T::SCTL1: EXTSMPT Position */ 872 #define EADC_SCTL1_EXTSMPT_Msk (0xfful << EADC_SCTL1_EXTSMPT_Pos) /*!< EADC_T::SCTL1: EXTSMPT Mask */ 873 874 #define EADC_SCTL2_CHSEL_Pos (0) /*!< EADC_T::SCTL2: CHSEL Position */ 875 #define EADC_SCTL2_CHSEL_Msk (0xful << EADC_SCTL2_CHSEL_Pos) /*!< EADC_T::SCTL2: CHSEL Mask */ 876 877 #define EADC_SCTL2_EXTREN_Pos (4) /*!< EADC_T::SCTL2: EXTREN Position */ 878 #define EADC_SCTL2_EXTREN_Msk (0x1ul << EADC_SCTL2_EXTREN_Pos) /*!< EADC_T::SCTL2: EXTREN Mask */ 879 880 #define EADC_SCTL2_EXTFEN_Pos (5) /*!< EADC_T::SCTL2: EXTFEN Position */ 881 #define EADC_SCTL2_EXTFEN_Msk (0x1ul << EADC_SCTL2_EXTFEN_Pos) /*!< EADC_T::SCTL2: EXTFEN Mask */ 882 883 #define EADC_SCTL2_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL2: TRGDLYDIV Position */ 884 #define EADC_SCTL2_TRGDLYDIV_Msk (0x3ul << EADC_SCTL2_TRGDLYDIV_Pos) /*!< EADC_T::SCTL2: TRGDLYDIV Mask */ 885 886 #define EADC_SCTL2_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL2: TRGDLYCNT Position */ 887 #define EADC_SCTL2_TRGDLYCNT_Msk (0xfful << EADC_SCTL2_TRGDLYCNT_Pos) /*!< EADC_T::SCTL2: TRGDLYCNT Mask */ 888 889 #define EADC_SCTL2_TRGSEL_Pos (16) /*!< EADC_T::SCTL2: TRGSEL Position */ 890 #define EADC_SCTL2_TRGSEL_Msk (0x1ful << EADC_SCTL2_TRGSEL_Pos) /*!< EADC_T::SCTL2: TRGSEL Mask */ 891 892 #define EADC_SCTL2_INTPOS_Pos (22) /*!< EADC_T::SCTL2: INTPOS Position */ 893 #define EADC_SCTL2_INTPOS_Msk (0x1ul << EADC_SCTL2_INTPOS_Pos) /*!< EADC_T::SCTL2: INTPOS Mask */ 894 895 #define EADC_SCTL2_DBMEN_Pos (23) /*!< EADC_T::SCTL2: DBMEN Position */ 896 #define EADC_SCTL2_DBMEN_Msk (0x1ul << EADC_SCTL2_DBMEN_Pos) /*!< EADC_T::SCTL2: DBMEN Mask */ 897 898 #define EADC_SCTL2_EXTSMPT_Pos (24) /*!< EADC_T::SCTL2: EXTSMPT Position */ 899 #define EADC_SCTL2_EXTSMPT_Msk (0xfful << EADC_SCTL2_EXTSMPT_Pos) /*!< EADC_T::SCTL2: EXTSMPT Mask */ 900 901 #define EADC_SCTL3_CHSEL_Pos (0) /*!< EADC_T::SCTL3: CHSEL Position */ 902 #define EADC_SCTL3_CHSEL_Msk (0xful << EADC_SCTL3_CHSEL_Pos) /*!< EADC_T::SCTL3: CHSEL Mask */ 903 904 #define EADC_SCTL3_EXTREN_Pos (4) /*!< EADC_T::SCTL3: EXTREN Position */ 905 #define EADC_SCTL3_EXTREN_Msk (0x1ul << EADC_SCTL3_EXTREN_Pos) /*!< EADC_T::SCTL3: EXTREN Mask */ 906 907 #define EADC_SCTL3_EXTFEN_Pos (5) /*!< EADC_T::SCTL3: EXTFEN Position */ 908 #define EADC_SCTL3_EXTFEN_Msk (0x1ul << EADC_SCTL3_EXTFEN_Pos) /*!< EADC_T::SCTL3: EXTFEN Mask */ 909 910 #define EADC_SCTL3_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL3: TRGDLYDIV Position */ 911 #define EADC_SCTL3_TRGDLYDIV_Msk (0x3ul << EADC_SCTL3_TRGDLYDIV_Pos) /*!< EADC_T::SCTL3: TRGDLYDIV Mask */ 912 913 #define EADC_SCTL3_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL3: TRGDLYCNT Position */ 914 #define EADC_SCTL3_TRGDLYCNT_Msk (0xfful << EADC_SCTL3_TRGDLYCNT_Pos) /*!< EADC_T::SCTL3: TRGDLYCNT Mask */ 915 916 #define EADC_SCTL3_TRGSEL_Pos (16) /*!< EADC_T::SCTL3: TRGSEL Position */ 917 #define EADC_SCTL3_TRGSEL_Msk (0x1ful << EADC_SCTL3_TRGSEL_Pos) /*!< EADC_T::SCTL3: TRGSEL Mask */ 918 919 #define EADC_SCTL3_INTPOS_Pos (22) /*!< EADC_T::SCTL3: INTPOS Position */ 920 #define EADC_SCTL3_INTPOS_Msk (0x1ul << EADC_SCTL3_INTPOS_Pos) /*!< EADC_T::SCTL3: INTPOS Mask */ 921 922 #define EADC_SCTL3_DBMEN_Pos (23) /*!< EADC_T::SCTL3: DBMEN Position */ 923 #define EADC_SCTL3_DBMEN_Msk (0x1ul << EADC_SCTL3_DBMEN_Pos) /*!< EADC_T::SCTL3: DBMEN Mask */ 924 925 #define EADC_SCTL3_EXTSMPT_Pos (24) /*!< EADC_T::SCTL3: EXTSMPT Position */ 926 #define EADC_SCTL3_EXTSMPT_Msk (0xfful << EADC_SCTL3_EXTSMPT_Pos) /*!< EADC_T::SCTL3: EXTSMPT Mask */ 927 928 #define EADC_SCTL4_CHSEL_Pos (0) /*!< EADC_T::SCTL4: CHSEL Position */ 929 #define EADC_SCTL4_CHSEL_Msk (0xful << EADC_SCTL4_CHSEL_Pos) /*!< EADC_T::SCTL4: CHSEL Mask */ 930 931 #define EADC_SCTL4_EXTREN_Pos (4) /*!< EADC_T::SCTL4: EXTREN Position */ 932 #define EADC_SCTL4_EXTREN_Msk (0x1ul << EADC_SCTL4_EXTREN_Pos) /*!< EADC_T::SCTL4: EXTREN Mask */ 933 934 #define EADC_SCTL4_EXTFEN_Pos (5) /*!< EADC_T::SCTL4: EXTFEN Position */ 935 #define EADC_SCTL4_EXTFEN_Msk (0x1ul << EADC_SCTL4_EXTFEN_Pos) /*!< EADC_T::SCTL4: EXTFEN Mask */ 936 937 #define EADC_SCTL4_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL4: TRGDLYDIV Position */ 938 #define EADC_SCTL4_TRGDLYDIV_Msk (0x3ul << EADC_SCTL4_TRGDLYDIV_Pos) /*!< EADC_T::SCTL4: TRGDLYDIV Mask */ 939 940 #define EADC_SCTL4_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL4: TRGDLYCNT Position */ 941 #define EADC_SCTL4_TRGDLYCNT_Msk (0xfful << EADC_SCTL4_TRGDLYCNT_Pos) /*!< EADC_T::SCTL4: TRGDLYCNT Mask */ 942 943 #define EADC_SCTL4_TRGSEL_Pos (16) /*!< EADC_T::SCTL4: TRGSEL Position */ 944 #define EADC_SCTL4_TRGSEL_Msk (0x1ful << EADC_SCTL4_TRGSEL_Pos) /*!< EADC_T::SCTL4: TRGSEL Mask */ 945 946 #define EADC_SCTL4_INTPOS_Pos (22) /*!< EADC_T::SCTL4: INTPOS Position */ 947 #define EADC_SCTL4_INTPOS_Msk (0x1ul << EADC_SCTL4_INTPOS_Pos) /*!< EADC_T::SCTL4: INTPOS Mask */ 948 949 #define EADC_SCTL4_EXTSMPT_Pos (24) /*!< EADC_T::SCTL4: EXTSMPT Position */ 950 #define EADC_SCTL4_EXTSMPT_Msk (0xfful << EADC_SCTL4_EXTSMPT_Pos) /*!< EADC_T::SCTL4: EXTSMPT Mask */ 951 952 #define EADC_SCTL5_CHSEL_Pos (0) /*!< EADC_T::SCTL5: CHSEL Position */ 953 #define EADC_SCTL5_CHSEL_Msk (0xful << EADC_SCTL5_CHSEL_Pos) /*!< EADC_T::SCTL5: CHSEL Mask */ 954 955 #define EADC_SCTL5_EXTREN_Pos (4) /*!< EADC_T::SCTL5: EXTREN Position */ 956 #define EADC_SCTL5_EXTREN_Msk (0x1ul << EADC_SCTL5_EXTREN_Pos) /*!< EADC_T::SCTL5: EXTREN Mask */ 957 958 #define EADC_SCTL5_EXTFEN_Pos (5) /*!< EADC_T::SCTL5: EXTFEN Position */ 959 #define EADC_SCTL5_EXTFEN_Msk (0x1ul << EADC_SCTL5_EXTFEN_Pos) /*!< EADC_T::SCTL5: EXTFEN Mask */ 960 961 #define EADC_SCTL5_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL5: TRGDLYDIV Position */ 962 #define EADC_SCTL5_TRGDLYDIV_Msk (0x3ul << EADC_SCTL5_TRGDLYDIV_Pos) /*!< EADC_T::SCTL5: TRGDLYDIV Mask */ 963 964 #define EADC_SCTL5_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL5: TRGDLYCNT Position */ 965 #define EADC_SCTL5_TRGDLYCNT_Msk (0xfful << EADC_SCTL5_TRGDLYCNT_Pos) /*!< EADC_T::SCTL5: TRGDLYCNT Mask */ 966 967 #define EADC_SCTL5_TRGSEL_Pos (16) /*!< EADC_T::SCTL5: TRGSEL Position */ 968 #define EADC_SCTL5_TRGSEL_Msk (0x1ful << EADC_SCTL5_TRGSEL_Pos) /*!< EADC_T::SCTL5: TRGSEL Mask */ 969 970 #define EADC_SCTL5_INTPOS_Pos (22) /*!< EADC_T::SCTL5: INTPOS Position */ 971 #define EADC_SCTL5_INTPOS_Msk (0x1ul << EADC_SCTL5_INTPOS_Pos) /*!< EADC_T::SCTL5: INTPOS Mask */ 972 973 #define EADC_SCTL5_EXTSMPT_Pos (24) /*!< EADC_T::SCTL5: EXTSMPT Position */ 974 #define EADC_SCTL5_EXTSMPT_Msk (0xfful << EADC_SCTL5_EXTSMPT_Pos) /*!< EADC_T::SCTL5: EXTSMPT Mask */ 975 976 #define EADC_SCTL6_CHSEL_Pos (0) /*!< EADC_T::SCTL6: CHSEL Position */ 977 #define EADC_SCTL6_CHSEL_Msk (0xful << EADC_SCTL6_CHSEL_Pos) /*!< EADC_T::SCTL6: CHSEL Mask */ 978 979 #define EADC_SCTL6_EXTREN_Pos (4) /*!< EADC_T::SCTL6: EXTREN Position */ 980 #define EADC_SCTL6_EXTREN_Msk (0x1ul << EADC_SCTL6_EXTREN_Pos) /*!< EADC_T::SCTL6: EXTREN Mask */ 981 982 #define EADC_SCTL6_EXTFEN_Pos (5) /*!< EADC_T::SCTL6: EXTFEN Position */ 983 #define EADC_SCTL6_EXTFEN_Msk (0x1ul << EADC_SCTL6_EXTFEN_Pos) /*!< EADC_T::SCTL6: EXTFEN Mask */ 984 985 #define EADC_SCTL6_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL6: TRGDLYDIV Position */ 986 #define EADC_SCTL6_TRGDLYDIV_Msk (0x3ul << EADC_SCTL6_TRGDLYDIV_Pos) /*!< EADC_T::SCTL6: TRGDLYDIV Mask */ 987 988 #define EADC_SCTL6_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL6: TRGDLYCNT Position */ 989 #define EADC_SCTL6_TRGDLYCNT_Msk (0xfful << EADC_SCTL6_TRGDLYCNT_Pos) /*!< EADC_T::SCTL6: TRGDLYCNT Mask */ 990 991 #define EADC_SCTL6_TRGSEL_Pos (16) /*!< EADC_T::SCTL6: TRGSEL Position */ 992 #define EADC_SCTL6_TRGSEL_Msk (0x1ful << EADC_SCTL6_TRGSEL_Pos) /*!< EADC_T::SCTL6: TRGSEL Mask */ 993 994 #define EADC_SCTL6_INTPOS_Pos (22) /*!< EADC_T::SCTL6: INTPOS Position */ 995 #define EADC_SCTL6_INTPOS_Msk (0x1ul << EADC_SCTL6_INTPOS_Pos) /*!< EADC_T::SCTL6: INTPOS Mask */ 996 997 #define EADC_SCTL6_EXTSMPT_Pos (24) /*!< EADC_T::SCTL6: EXTSMPT Position */ 998 #define EADC_SCTL6_EXTSMPT_Msk (0xfful << EADC_SCTL6_EXTSMPT_Pos) /*!< EADC_T::SCTL6: EXTSMPT Mask */ 999 1000 #define EADC_SCTL7_CHSEL_Pos (0) /*!< EADC_T::SCTL7: CHSEL Position */ 1001 #define EADC_SCTL7_CHSEL_Msk (0xful << EADC_SCTL7_CHSEL_Pos) /*!< EADC_T::SCTL7: CHSEL Mask */ 1002 1003 #define EADC_SCTL7_EXTREN_Pos (4) /*!< EADC_T::SCTL7: EXTREN Position */ 1004 #define EADC_SCTL7_EXTREN_Msk (0x1ul << EADC_SCTL7_EXTREN_Pos) /*!< EADC_T::SCTL7: EXTREN Mask */ 1005 1006 #define EADC_SCTL7_EXTFEN_Pos (5) /*!< EADC_T::SCTL7: EXTFEN Position */ 1007 #define EADC_SCTL7_EXTFEN_Msk (0x1ul << EADC_SCTL7_EXTFEN_Pos) /*!< EADC_T::SCTL7: EXTFEN Mask */ 1008 1009 #define EADC_SCTL7_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL7: TRGDLYDIV Position */ 1010 #define EADC_SCTL7_TRGDLYDIV_Msk (0x3ul << EADC_SCTL7_TRGDLYDIV_Pos) /*!< EADC_T::SCTL7: TRGDLYDIV Mask */ 1011 1012 #define EADC_SCTL7_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL7: TRGDLYCNT Position */ 1013 #define EADC_SCTL7_TRGDLYCNT_Msk (0xfful << EADC_SCTL7_TRGDLYCNT_Pos) /*!< EADC_T::SCTL7: TRGDLYCNT Mask */ 1014 1015 #define EADC_SCTL7_TRGSEL_Pos (16) /*!< EADC_T::SCTL7: TRGSEL Position */ 1016 #define EADC_SCTL7_TRGSEL_Msk (0x1ful << EADC_SCTL7_TRGSEL_Pos) /*!< EADC_T::SCTL7: TRGSEL Mask */ 1017 1018 #define EADC_SCTL7_INTPOS_Pos (22) /*!< EADC_T::SCTL7: INTPOS Position */ 1019 #define EADC_SCTL7_INTPOS_Msk (0x1ul << EADC_SCTL7_INTPOS_Pos) /*!< EADC_T::SCTL7: INTPOS Mask */ 1020 1021 #define EADC_SCTL7_EXTSMPT_Pos (24) /*!< EADC_T::SCTL7: EXTSMPT Position */ 1022 #define EADC_SCTL7_EXTSMPT_Msk (0xfful << EADC_SCTL7_EXTSMPT_Pos) /*!< EADC_T::SCTL7: EXTSMPT Mask */ 1023 1024 #define EADC_SCTL8_CHSEL_Pos (0) /*!< EADC_T::SCTL8: CHSEL Position */ 1025 #define EADC_SCTL8_CHSEL_Msk (0xful << EADC_SCTL8_CHSEL_Pos) /*!< EADC_T::SCTL8: CHSEL Mask */ 1026 1027 #define EADC_SCTL8_EXTREN_Pos (4) /*!< EADC_T::SCTL8: EXTREN Position */ 1028 #define EADC_SCTL8_EXTREN_Msk (0x1ul << EADC_SCTL8_EXTREN_Pos) /*!< EADC_T::SCTL8: EXTREN Mask */ 1029 1030 #define EADC_SCTL8_EXTFEN_Pos (5) /*!< EADC_T::SCTL8: EXTFEN Position */ 1031 #define EADC_SCTL8_EXTFEN_Msk (0x1ul << EADC_SCTL8_EXTFEN_Pos) /*!< EADC_T::SCTL8: EXTFEN Mask */ 1032 1033 #define EADC_SCTL8_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL8: TRGDLYDIV Position */ 1034 #define EADC_SCTL8_TRGDLYDIV_Msk (0x3ul << EADC_SCTL8_TRGDLYDIV_Pos) /*!< EADC_T::SCTL8: TRGDLYDIV Mask */ 1035 1036 #define EADC_SCTL8_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL8: TRGDLYCNT Position */ 1037 #define EADC_SCTL8_TRGDLYCNT_Msk (0xfful << EADC_SCTL8_TRGDLYCNT_Pos) /*!< EADC_T::SCTL8: TRGDLYCNT Mask */ 1038 1039 #define EADC_SCTL8_TRGSEL_Pos (16) /*!< EADC_T::SCTL8: TRGSEL Position */ 1040 #define EADC_SCTL8_TRGSEL_Msk (0x1ful << EADC_SCTL8_TRGSEL_Pos) /*!< EADC_T::SCTL8: TRGSEL Mask */ 1041 1042 #define EADC_SCTL8_INTPOS_Pos (22) /*!< EADC_T::SCTL8: INTPOS Position */ 1043 #define EADC_SCTL8_INTPOS_Msk (0x1ul << EADC_SCTL8_INTPOS_Pos) /*!< EADC_T::SCTL8: INTPOS Mask */ 1044 1045 #define EADC_SCTL8_EXTSMPT_Pos (24) /*!< EADC_T::SCTL8: EXTSMPT Position */ 1046 #define EADC_SCTL8_EXTSMPT_Msk (0xfful << EADC_SCTL8_EXTSMPT_Pos) /*!< EADC_T::SCTL8: EXTSMPT Mask */ 1047 1048 #define EADC_SCTL9_CHSEL_Pos (0) /*!< EADC_T::SCTL9: CHSEL Position */ 1049 #define EADC_SCTL9_CHSEL_Msk (0xful << EADC_SCTL9_CHSEL_Pos) /*!< EADC_T::SCTL9: CHSEL Mask */ 1050 1051 #define EADC_SCTL9_EXTREN_Pos (4) /*!< EADC_T::SCTL9: EXTREN Position */ 1052 #define EADC_SCTL9_EXTREN_Msk (0x1ul << EADC_SCTL9_EXTREN_Pos) /*!< EADC_T::SCTL9: EXTREN Mask */ 1053 1054 #define EADC_SCTL9_EXTFEN_Pos (5) /*!< EADC_T::SCTL9: EXTFEN Position */ 1055 #define EADC_SCTL9_EXTFEN_Msk (0x1ul << EADC_SCTL9_EXTFEN_Pos) /*!< EADC_T::SCTL9: EXTFEN Mask */ 1056 1057 #define EADC_SCTL9_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL9: TRGDLYDIV Position */ 1058 #define EADC_SCTL9_TRGDLYDIV_Msk (0x3ul << EADC_SCTL9_TRGDLYDIV_Pos) /*!< EADC_T::SCTL9: TRGDLYDIV Mask */ 1059 1060 #define EADC_SCTL9_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL9: TRGDLYCNT Position */ 1061 #define EADC_SCTL9_TRGDLYCNT_Msk (0xfful << EADC_SCTL9_TRGDLYCNT_Pos) /*!< EADC_T::SCTL9: TRGDLYCNT Mask */ 1062 1063 #define EADC_SCTL9_TRGSEL_Pos (16) /*!< EADC_T::SCTL9: TRGSEL Position */ 1064 #define EADC_SCTL9_TRGSEL_Msk (0x1ful << EADC_SCTL9_TRGSEL_Pos) /*!< EADC_T::SCTL9: TRGSEL Mask */ 1065 1066 #define EADC_SCTL9_INTPOS_Pos (22) /*!< EADC_T::SCTL9: INTPOS Position */ 1067 #define EADC_SCTL9_INTPOS_Msk (0x1ul << EADC_SCTL9_INTPOS_Pos) /*!< EADC_T::SCTL9: INTPOS Mask */ 1068 1069 #define EADC_SCTL9_EXTSMPT_Pos (24) /*!< EADC_T::SCTL9: EXTSMPT Position */ 1070 #define EADC_SCTL9_EXTSMPT_Msk (0xfful << EADC_SCTL9_EXTSMPT_Pos) /*!< EADC_T::SCTL9: EXTSMPT Mask */ 1071 1072 #define EADC_SCTL10_CHSEL_Pos (0) /*!< EADC_T::SCTL10: CHSEL Position */ 1073 #define EADC_SCTL10_CHSEL_Msk (0xful << EADC_SCTL10_CHSEL_Pos) /*!< EADC_T::SCTL10: CHSEL Mask */ 1074 1075 #define EADC_SCTL10_EXTREN_Pos (4) /*!< EADC_T::SCTL10: EXTREN Position */ 1076 #define EADC_SCTL10_EXTREN_Msk (0x1ul << EADC_SCTL10_EXTREN_Pos) /*!< EADC_T::SCTL10: EXTREN Mask */ 1077 1078 #define EADC_SCTL10_EXTFEN_Pos (5) /*!< EADC_T::SCTL10: EXTFEN Position */ 1079 #define EADC_SCTL10_EXTFEN_Msk (0x1ul << EADC_SCTL10_EXTFEN_Pos) /*!< EADC_T::SCTL10: EXTFEN Mask */ 1080 1081 #define EADC_SCTL10_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL10: TRGDLYDIV Position */ 1082 #define EADC_SCTL10_TRGDLYDIV_Msk (0x3ul << EADC_SCTL10_TRGDLYDIV_Pos) /*!< EADC_T::SCTL10: TRGDLYDIV Mask */ 1083 1084 #define EADC_SCTL10_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL10: TRGDLYCNT Position */ 1085 #define EADC_SCTL10_TRGDLYCNT_Msk (0xfful << EADC_SCTL10_TRGDLYCNT_Pos) /*!< EADC_T::SCTL10: TRGDLYCNT Mask */ 1086 1087 #define EADC_SCTL10_TRGSEL_Pos (16) /*!< EADC_T::SCTL10: TRGSEL Position */ 1088 #define EADC_SCTL10_TRGSEL_Msk (0x1ful << EADC_SCTL10_TRGSEL_Pos) /*!< EADC_T::SCTL10: TRGSEL Mask */ 1089 1090 #define EADC_SCTL10_INTPOS_Pos (22) /*!< EADC_T::SCTL10: INTPOS Position */ 1091 #define EADC_SCTL10_INTPOS_Msk (0x1ul << EADC_SCTL10_INTPOS_Pos) /*!< EADC_T::SCTL10: INTPOS Mask */ 1092 1093 #define EADC_SCTL10_EXTSMPT_Pos (24) /*!< EADC_T::SCTL10: EXTSMPT Position */ 1094 #define EADC_SCTL10_EXTSMPT_Msk (0xfful << EADC_SCTL10_EXTSMPT_Pos) /*!< EADC_T::SCTL10: EXTSMPT Mask */ 1095 1096 #define EADC_SCTL11_CHSEL_Pos (0) /*!< EADC_T::SCTL11: CHSEL Position */ 1097 #define EADC_SCTL11_CHSEL_Msk (0xful << EADC_SCTL11_CHSEL_Pos) /*!< EADC_T::SCTL11: CHSEL Mask */ 1098 1099 #define EADC_SCTL11_EXTREN_Pos (4) /*!< EADC_T::SCTL11: EXTREN Position */ 1100 #define EADC_SCTL11_EXTREN_Msk (0x1ul << EADC_SCTL11_EXTREN_Pos) /*!< EADC_T::SCTL11: EXTREN Mask */ 1101 1102 #define EADC_SCTL11_EXTFEN_Pos (5) /*!< EADC_T::SCTL11: EXTFEN Position */ 1103 #define EADC_SCTL11_EXTFEN_Msk (0x1ul << EADC_SCTL11_EXTFEN_Pos) /*!< EADC_T::SCTL11: EXTFEN Mask */ 1104 1105 #define EADC_SCTL11_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL11: TRGDLYDIV Position */ 1106 #define EADC_SCTL11_TRGDLYDIV_Msk (0x3ul << EADC_SCTL11_TRGDLYDIV_Pos) /*!< EADC_T::SCTL11: TRGDLYDIV Mask */ 1107 1108 #define EADC_SCTL11_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL11: TRGDLYCNT Position */ 1109 #define EADC_SCTL11_TRGDLYCNT_Msk (0xfful << EADC_SCTL11_TRGDLYCNT_Pos) /*!< EADC_T::SCTL11: TRGDLYCNT Mask */ 1110 1111 #define EADC_SCTL11_TRGSEL_Pos (16) /*!< EADC_T::SCTL11: TRGSEL Position */ 1112 #define EADC_SCTL11_TRGSEL_Msk (0x1ful << EADC_SCTL11_TRGSEL_Pos) /*!< EADC_T::SCTL11: TRGSEL Mask */ 1113 1114 #define EADC_SCTL11_INTPOS_Pos (22) /*!< EADC_T::SCTL11: INTPOS Position */ 1115 #define EADC_SCTL11_INTPOS_Msk (0x1ul << EADC_SCTL11_INTPOS_Pos) /*!< EADC_T::SCTL11: INTPOS Mask */ 1116 1117 #define EADC_SCTL11_EXTSMPT_Pos (24) /*!< EADC_T::SCTL11: EXTSMPT Position */ 1118 #define EADC_SCTL11_EXTSMPT_Msk (0xfful << EADC_SCTL11_EXTSMPT_Pos) /*!< EADC_T::SCTL11: EXTSMPT Mask */ 1119 1120 #define EADC_SCTL12_CHSEL_Pos (0) /*!< EADC_T::SCTL12: CHSEL Position */ 1121 #define EADC_SCTL12_CHSEL_Msk (0xful << EADC_SCTL12_CHSEL_Pos) /*!< EADC_T::SCTL12: CHSEL Mask */ 1122 1123 #define EADC_SCTL12_EXTREN_Pos (4) /*!< EADC_T::SCTL12: EXTREN Position */ 1124 #define EADC_SCTL12_EXTREN_Msk (0x1ul << EADC_SCTL12_EXTREN_Pos) /*!< EADC_T::SCTL12: EXTREN Mask */ 1125 1126 #define EADC_SCTL12_EXTFEN_Pos (5) /*!< EADC_T::SCTL12: EXTFEN Position */ 1127 #define EADC_SCTL12_EXTFEN_Msk (0x1ul << EADC_SCTL12_EXTFEN_Pos) /*!< EADC_T::SCTL12: EXTFEN Mask */ 1128 1129 #define EADC_SCTL12_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL12: TRGDLYDIV Position */ 1130 #define EADC_SCTL12_TRGDLYDIV_Msk (0x3ul << EADC_SCTL12_TRGDLYDIV_Pos) /*!< EADC_T::SCTL12: TRGDLYDIV Mask */ 1131 1132 #define EADC_SCTL12_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL12: TRGDLYCNT Position */ 1133 #define EADC_SCTL12_TRGDLYCNT_Msk (0xfful << EADC_SCTL12_TRGDLYCNT_Pos) /*!< EADC_T::SCTL12: TRGDLYCNT Mask */ 1134 1135 #define EADC_SCTL12_TRGSEL_Pos (16) /*!< EADC_T::SCTL12: TRGSEL Position */ 1136 #define EADC_SCTL12_TRGSEL_Msk (0x1ful << EADC_SCTL12_TRGSEL_Pos) /*!< EADC_T::SCTL12: TRGSEL Mask */ 1137 1138 #define EADC_SCTL12_INTPOS_Pos (22) /*!< EADC_T::SCTL12: INTPOS Position */ 1139 #define EADC_SCTL12_INTPOS_Msk (0x1ul << EADC_SCTL12_INTPOS_Pos) /*!< EADC_T::SCTL12: INTPOS Mask */ 1140 1141 #define EADC_SCTL12_EXTSMPT_Pos (24) /*!< EADC_T::SCTL12: EXTSMPT Position */ 1142 #define EADC_SCTL12_EXTSMPT_Msk (0xfful << EADC_SCTL12_EXTSMPT_Pos) /*!< EADC_T::SCTL12: EXTSMPT Mask */ 1143 1144 #define EADC_SCTL13_CHSEL_Pos (0) /*!< EADC_T::SCTL13: CHSEL Position */ 1145 #define EADC_SCTL13_CHSEL_Msk (0xful << EADC_SCTL13_CHSEL_Pos) /*!< EADC_T::SCTL13: CHSEL Mask */ 1146 1147 #define EADC_SCTL13_EXTREN_Pos (4) /*!< EADC_T::SCTL13: EXTREN Position */ 1148 #define EADC_SCTL13_EXTREN_Msk (0x1ul << EADC_SCTL13_EXTREN_Pos) /*!< EADC_T::SCTL13: EXTREN Mask */ 1149 1150 #define EADC_SCTL13_EXTFEN_Pos (5) /*!< EADC_T::SCTL13: EXTFEN Position */ 1151 #define EADC_SCTL13_EXTFEN_Msk (0x1ul << EADC_SCTL13_EXTFEN_Pos) /*!< EADC_T::SCTL13: EXTFEN Mask */ 1152 1153 #define EADC_SCTL13_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL13: TRGDLYDIV Position */ 1154 #define EADC_SCTL13_TRGDLYDIV_Msk (0x3ul << EADC_SCTL13_TRGDLYDIV_Pos) /*!< EADC_T::SCTL13: TRGDLYDIV Mask */ 1155 1156 #define EADC_SCTL13_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL13: TRGDLYCNT Position */ 1157 #define EADC_SCTL13_TRGDLYCNT_Msk (0xfful << EADC_SCTL13_TRGDLYCNT_Pos) /*!< EADC_T::SCTL13: TRGDLYCNT Mask */ 1158 1159 #define EADC_SCTL13_TRGSEL_Pos (16) /*!< EADC_T::SCTL13: TRGSEL Position */ 1160 #define EADC_SCTL13_TRGSEL_Msk (0x1ful << EADC_SCTL13_TRGSEL_Pos) /*!< EADC_T::SCTL13: TRGSEL Mask */ 1161 1162 #define EADC_SCTL13_INTPOS_Pos (22) /*!< EADC_T::SCTL13: INTPOS Position */ 1163 #define EADC_SCTL13_INTPOS_Msk (0x1ul << EADC_SCTL13_INTPOS_Pos) /*!< EADC_T::SCTL13: INTPOS Mask */ 1164 1165 #define EADC_SCTL13_EXTSMPT_Pos (24) /*!< EADC_T::SCTL13: EXTSMPT Position */ 1166 #define EADC_SCTL13_EXTSMPT_Msk (0xfful << EADC_SCTL13_EXTSMPT_Pos) /*!< EADC_T::SCTL13: EXTSMPT Mask */ 1167 1168 #define EADC_SCTL14_CHSEL_Pos (0) /*!< EADC_T::SCTL14: CHSEL Position */ 1169 #define EADC_SCTL14_CHSEL_Msk (0xful << EADC_SCTL14_CHSEL_Pos) /*!< EADC_T::SCTL14: CHSEL Mask */ 1170 1171 #define EADC_SCTL14_EXTREN_Pos (4) /*!< EADC_T::SCTL14: EXTREN Position */ 1172 #define EADC_SCTL14_EXTREN_Msk (0x1ul << EADC_SCTL14_EXTREN_Pos) /*!< EADC_T::SCTL14: EXTREN Mask */ 1173 1174 #define EADC_SCTL14_EXTFEN_Pos (5) /*!< EADC_T::SCTL14: EXTFEN Position */ 1175 #define EADC_SCTL14_EXTFEN_Msk (0x1ul << EADC_SCTL14_EXTFEN_Pos) /*!< EADC_T::SCTL14: EXTFEN Mask */ 1176 1177 #define EADC_SCTL14_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL14: TRGDLYDIV Position */ 1178 #define EADC_SCTL14_TRGDLYDIV_Msk (0x3ul << EADC_SCTL14_TRGDLYDIV_Pos) /*!< EADC_T::SCTL14: TRGDLYDIV Mask */ 1179 1180 #define EADC_SCTL14_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL14: TRGDLYCNT Position */ 1181 #define EADC_SCTL14_TRGDLYCNT_Msk (0xfful << EADC_SCTL14_TRGDLYCNT_Pos) /*!< EADC_T::SCTL14: TRGDLYCNT Mask */ 1182 1183 #define EADC_SCTL14_TRGSEL_Pos (16) /*!< EADC_T::SCTL14: TRGSEL Position */ 1184 #define EADC_SCTL14_TRGSEL_Msk (0x1ful << EADC_SCTL14_TRGSEL_Pos) /*!< EADC_T::SCTL14: TRGSEL Mask */ 1185 1186 #define EADC_SCTL14_INTPOS_Pos (22) /*!< EADC_T::SCTL14: INTPOS Position */ 1187 #define EADC_SCTL14_INTPOS_Msk (0x1ul << EADC_SCTL14_INTPOS_Pos) /*!< EADC_T::SCTL14: INTPOS Mask */ 1188 1189 #define EADC_SCTL14_EXTSMPT_Pos (24) /*!< EADC_T::SCTL14: EXTSMPT Position */ 1190 #define EADC_SCTL14_EXTSMPT_Msk (0xfful << EADC_SCTL14_EXTSMPT_Pos) /*!< EADC_T::SCTL14: EXTSMPT Mask */ 1191 1192 #define EADC_SCTL15_CHSEL_Pos (0) /*!< EADC_T::SCTL15: CHSEL Position */ 1193 #define EADC_SCTL15_CHSEL_Msk (0xful << EADC_SCTL15_CHSEL_Pos) /*!< EADC_T::SCTL15: CHSEL Mask */ 1194 1195 #define EADC_SCTL15_EXTREN_Pos (4) /*!< EADC_T::SCTL15: EXTREN Position */ 1196 #define EADC_SCTL15_EXTREN_Msk (0x1ul << EADC_SCTL15_EXTREN_Pos) /*!< EADC_T::SCTL15: EXTREN Mask */ 1197 1198 #define EADC_SCTL15_EXTFEN_Pos (5) /*!< EADC_T::SCTL15: EXTFEN Position */ 1199 #define EADC_SCTL15_EXTFEN_Msk (0x1ul << EADC_SCTL15_EXTFEN_Pos) /*!< EADC_T::SCTL15: EXTFEN Mask */ 1200 1201 #define EADC_SCTL15_TRGDLYDIV_Pos (6) /*!< EADC_T::SCTL15: TRGDLYDIV Position */ 1202 #define EADC_SCTL15_TRGDLYDIV_Msk (0x3ul << EADC_SCTL15_TRGDLYDIV_Pos) /*!< EADC_T::SCTL15: TRGDLYDIV Mask */ 1203 1204 #define EADC_SCTL15_TRGDLYCNT_Pos (8) /*!< EADC_T::SCTL15: TRGDLYCNT Position */ 1205 #define EADC_SCTL15_TRGDLYCNT_Msk (0xfful << EADC_SCTL15_TRGDLYCNT_Pos) /*!< EADC_T::SCTL15: TRGDLYCNT Mask */ 1206 1207 #define EADC_SCTL15_TRGSEL_Pos (16) /*!< EADC_T::SCTL15: TRGSEL Position */ 1208 #define EADC_SCTL15_TRGSEL_Msk (0x1ful << EADC_SCTL15_TRGSEL_Pos) /*!< EADC_T::SCTL15: TRGSEL Mask */ 1209 1210 #define EADC_SCTL15_INTPOS_Pos (22) /*!< EADC_T::SCTL15: INTPOS Position */ 1211 #define EADC_SCTL15_INTPOS_Msk (0x1ul << EADC_SCTL15_INTPOS_Pos) /*!< EADC_T::SCTL15: INTPOS Mask */ 1212 1213 #define EADC_SCTL15_EXTSMPT_Pos (24) /*!< EADC_T::SCTL15: EXTSMPT Position */ 1214 #define EADC_SCTL15_EXTSMPT_Msk (0xfful << EADC_SCTL15_EXTSMPT_Pos) /*!< EADC_T::SCTL15: EXTSMPT Mask */ 1215 1216 #define EADC_SCTL16_EXTSMPT_Pos (24) /*!< EADC_T::SCTL16: EXTSMPT Position */ 1217 #define EADC_SCTL16_EXTSMPT_Msk (0xfful << EADC_SCTL16_EXTSMPT_Pos) /*!< EADC_T::SCTL16: EXTSMPT Mask */ 1218 1219 #define EADC_SCTL17_EXTSMPT_Pos (24) /*!< EADC_T::SCTL17: EXTSMPT Position */ 1220 #define EADC_SCTL17_EXTSMPT_Msk (0xfful << EADC_SCTL17_EXTSMPT_Pos) /*!< EADC_T::SCTL17: EXTSMPT Mask */ 1221 1222 #define EADC_SCTL18_EXTSMPT_Pos (24) /*!< EADC_T::SCTL18: EXTSMPT Position */ 1223 #define EADC_SCTL18_EXTSMPT_Msk (0xfful << EADC_SCTL18_EXTSMPT_Pos) /*!< EADC_T::SCTL18: EXTSMPT Mask */ 1224 1225 #define EADC_INTSRC0_SPLIE0_Pos (0) /*!< EADC_T::INTSRC0: SPLIE0 Position */ 1226 #define EADC_INTSRC0_SPLIE0_Msk (0x1ul << EADC_INTSRC0_SPLIE0_Pos) /*!< EADC_T::INTSRC0: SPLIE0 Mask */ 1227 1228 #define EADC_INTSRC0_SPLIE1_Pos (1) /*!< EADC_T::INTSRC0: SPLIE1 Position */ 1229 #define EADC_INTSRC0_SPLIE1_Msk (0x1ul << EADC_INTSRC0_SPLIE1_Pos) /*!< EADC_T::INTSRC0: SPLIE1 Mask */ 1230 1231 #define EADC_INTSRC0_SPLIE2_Pos (2) /*!< EADC_T::INTSRC0: SPLIE2 Position */ 1232 #define EADC_INTSRC0_SPLIE2_Msk (0x1ul << EADC_INTSRC0_SPLIE2_Pos) /*!< EADC_T::INTSRC0: SPLIE2 Mask */ 1233 1234 #define EADC_INTSRC0_SPLIE3_Pos (3) /*!< EADC_T::INTSRC0: SPLIE3 Position */ 1235 #define EADC_INTSRC0_SPLIE3_Msk (0x1ul << EADC_INTSRC0_SPLIE3_Pos) /*!< EADC_T::INTSRC0: SPLIE3 Mask */ 1236 1237 #define EADC_INTSRC0_SPLIE4_Pos (4) /*!< EADC_T::INTSRC0: SPLIE4 Position */ 1238 #define EADC_INTSRC0_SPLIE4_Msk (0x1ul << EADC_INTSRC0_SPLIE4_Pos) /*!< EADC_T::INTSRC0: SPLIE4 Mask */ 1239 1240 #define EADC_INTSRC0_SPLIE5_Pos (5) /*!< EADC_T::INTSRC0: SPLIE5 Position */ 1241 #define EADC_INTSRC0_SPLIE5_Msk (0x1ul << EADC_INTSRC0_SPLIE5_Pos) /*!< EADC_T::INTSRC0: SPLIE5 Mask */ 1242 1243 #define EADC_INTSRC0_SPLIE6_Pos (6) /*!< EADC_T::INTSRC0: SPLIE6 Position */ 1244 #define EADC_INTSRC0_SPLIE6_Msk (0x1ul << EADC_INTSRC0_SPLIE6_Pos) /*!< EADC_T::INTSRC0: SPLIE6 Mask */ 1245 1246 #define EADC_INTSRC0_SPLIE7_Pos (7) /*!< EADC_T::INTSRC0: SPLIE7 Position */ 1247 #define EADC_INTSRC0_SPLIE7_Msk (0x1ul << EADC_INTSRC0_SPLIE7_Pos) /*!< EADC_T::INTSRC0: SPLIE7 Mask */ 1248 1249 #define EADC_INTSRC0_SPLIE8_Pos (8) /*!< EADC_T::INTSRC0: SPLIE8 Position */ 1250 #define EADC_INTSRC0_SPLIE8_Msk (0x1ul << EADC_INTSRC0_SPLIE8_Pos) /*!< EADC_T::INTSRC0: SPLIE8 Mask */ 1251 1252 #define EADC_INTSRC0_SPLIE9_Pos (9) /*!< EADC_T::INTSRC0: SPLIE9 Position */ 1253 #define EADC_INTSRC0_SPLIE9_Msk (0x1ul << EADC_INTSRC0_SPLIE9_Pos) /*!< EADC_T::INTSRC0: SPLIE9 Mask */ 1254 1255 #define EADC_INTSRC0_SPLIE10_Pos (10) /*!< EADC_T::INTSRC0: SPLIE10 Position */ 1256 #define EADC_INTSRC0_SPLIE10_Msk (0x1ul << EADC_INTSRC0_SPLIE10_Pos) /*!< EADC_T::INTSRC0: SPLIE10 Mask */ 1257 1258 #define EADC_INTSRC0_SPLIE11_Pos (11) /*!< EADC_T::INTSRC0: SPLIE11 Position */ 1259 #define EADC_INTSRC0_SPLIE11_Msk (0x1ul << EADC_INTSRC0_SPLIE11_Pos) /*!< EADC_T::INTSRC0: SPLIE11 Mask */ 1260 1261 #define EADC_INTSRC0_SPLIE12_Pos (12) /*!< EADC_T::INTSRC0: SPLIE12 Position */ 1262 #define EADC_INTSRC0_SPLIE12_Msk (0x1ul << EADC_INTSRC0_SPLIE12_Pos) /*!< EADC_T::INTSRC0: SPLIE12 Mask */ 1263 1264 #define EADC_INTSRC0_SPLIE13_Pos (13) /*!< EADC_T::INTSRC0: SPLIE13 Position */ 1265 #define EADC_INTSRC0_SPLIE13_Msk (0x1ul << EADC_INTSRC0_SPLIE13_Pos) /*!< EADC_T::INTSRC0: SPLIE13 Mask */ 1266 1267 #define EADC_INTSRC0_SPLIE14_Pos (14) /*!< EADC_T::INTSRC0: SPLIE14 Position */ 1268 #define EADC_INTSRC0_SPLIE14_Msk (0x1ul << EADC_INTSRC0_SPLIE14_Pos) /*!< EADC_T::INTSRC0: SPLIE14 Mask */ 1269 1270 #define EADC_INTSRC0_SPLIE15_Pos (15) /*!< EADC_T::INTSRC0: SPLIE15 Position */ 1271 #define EADC_INTSRC0_SPLIE15_Msk (0x1ul << EADC_INTSRC0_SPLIE15_Pos) /*!< EADC_T::INTSRC0: SPLIE15 Mask */ 1272 1273 #define EADC_INTSRC0_SPLIE16_Pos (16) /*!< EADC_T::INTSRC0: SPLIE16 Position */ 1274 #define EADC_INTSRC0_SPLIE16_Msk (0x1ul << EADC_INTSRC0_SPLIE16_Pos) /*!< EADC_T::INTSRC0: SPLIE16 Mask */ 1275 1276 #define EADC_INTSRC0_SPLIE17_Pos (17) /*!< EADC_T::INTSRC0: SPLIE17 Position */ 1277 #define EADC_INTSRC0_SPLIE17_Msk (0x1ul << EADC_INTSRC0_SPLIE17_Pos) /*!< EADC_T::INTSRC0: SPLIE17 Mask */ 1278 1279 #define EADC_INTSRC0_SPLIE18_Pos (18) /*!< EADC_T::INTSRC0: SPLIE18 Position */ 1280 #define EADC_INTSRC0_SPLIE18_Msk (0x1ul << EADC_INTSRC0_SPLIE18_Pos) /*!< EADC_T::INTSRC0: SPLIE18 Mask */ 1281 1282 #define EADC_INTSRC1_SPLIE0_Pos (0) /*!< EADC_T::INTSRC1: SPLIE0 Position */ 1283 #define EADC_INTSRC1_SPLIE0_Msk (0x1ul << EADC_INTSRC1_SPLIE0_Pos) /*!< EADC_T::INTSRC1: SPLIE0 Mask */ 1284 1285 #define EADC_INTSRC1_SPLIE1_Pos (1) /*!< EADC_T::INTSRC1: SPLIE1 Position */ 1286 #define EADC_INTSRC1_SPLIE1_Msk (0x1ul << EADC_INTSRC1_SPLIE1_Pos) /*!< EADC_T::INTSRC1: SPLIE1 Mask */ 1287 1288 #define EADC_INTSRC1_SPLIE2_Pos (2) /*!< EADC_T::INTSRC1: SPLIE2 Position */ 1289 #define EADC_INTSRC1_SPLIE2_Msk (0x1ul << EADC_INTSRC1_SPLIE2_Pos) /*!< EADC_T::INTSRC1: SPLIE2 Mask */ 1290 1291 #define EADC_INTSRC1_SPLIE3_Pos (3) /*!< EADC_T::INTSRC1: SPLIE3 Position */ 1292 #define EADC_INTSRC1_SPLIE3_Msk (0x1ul << EADC_INTSRC1_SPLIE3_Pos) /*!< EADC_T::INTSRC1: SPLIE3 Mask */ 1293 1294 #define EADC_INTSRC1_SPLIE4_Pos (4) /*!< EADC_T::INTSRC1: SPLIE4 Position */ 1295 #define EADC_INTSRC1_SPLIE4_Msk (0x1ul << EADC_INTSRC1_SPLIE4_Pos) /*!< EADC_T::INTSRC1: SPLIE4 Mask */ 1296 1297 #define EADC_INTSRC1_SPLIE5_Pos (5) /*!< EADC_T::INTSRC1: SPLIE5 Position */ 1298 #define EADC_INTSRC1_SPLIE5_Msk (0x1ul << EADC_INTSRC1_SPLIE5_Pos) /*!< EADC_T::INTSRC1: SPLIE5 Mask */ 1299 1300 #define EADC_INTSRC1_SPLIE6_Pos (6) /*!< EADC_T::INTSRC1: SPLIE6 Position */ 1301 #define EADC_INTSRC1_SPLIE6_Msk (0x1ul << EADC_INTSRC1_SPLIE6_Pos) /*!< EADC_T::INTSRC1: SPLIE6 Mask */ 1302 1303 #define EADC_INTSRC1_SPLIE7_Pos (7) /*!< EADC_T::INTSRC1: SPLIE7 Position */ 1304 #define EADC_INTSRC1_SPLIE7_Msk (0x1ul << EADC_INTSRC1_SPLIE7_Pos) /*!< EADC_T::INTSRC1: SPLIE7 Mask */ 1305 1306 #define EADC_INTSRC1_SPLIE8_Pos (8) /*!< EADC_T::INTSRC1: SPLIE8 Position */ 1307 #define EADC_INTSRC1_SPLIE8_Msk (0x1ul << EADC_INTSRC1_SPLIE8_Pos) /*!< EADC_T::INTSRC1: SPLIE8 Mask */ 1308 1309 #define EADC_INTSRC1_SPLIE9_Pos (9) /*!< EADC_T::INTSRC1: SPLIE9 Position */ 1310 #define EADC_INTSRC1_SPLIE9_Msk (0x1ul << EADC_INTSRC1_SPLIE9_Pos) /*!< EADC_T::INTSRC1: SPLIE9 Mask */ 1311 1312 #define EADC_INTSRC1_SPLIE10_Pos (10) /*!< EADC_T::INTSRC1: SPLIE10 Position */ 1313 #define EADC_INTSRC1_SPLIE10_Msk (0x1ul << EADC_INTSRC1_SPLIE10_Pos) /*!< EADC_T::INTSRC1: SPLIE10 Mask */ 1314 1315 #define EADC_INTSRC1_SPLIE11_Pos (11) /*!< EADC_T::INTSRC1: SPLIE11 Position */ 1316 #define EADC_INTSRC1_SPLIE11_Msk (0x1ul << EADC_INTSRC1_SPLIE11_Pos) /*!< EADC_T::INTSRC1: SPLIE11 Mask */ 1317 1318 #define EADC_INTSRC1_SPLIE12_Pos (12) /*!< EADC_T::INTSRC1: SPLIE12 Position */ 1319 #define EADC_INTSRC1_SPLIE12_Msk (0x1ul << EADC_INTSRC1_SPLIE12_Pos) /*!< EADC_T::INTSRC1: SPLIE12 Mask */ 1320 1321 #define EADC_INTSRC1_SPLIE13_Pos (13) /*!< EADC_T::INTSRC1: SPLIE13 Position */ 1322 #define EADC_INTSRC1_SPLIE13_Msk (0x1ul << EADC_INTSRC1_SPLIE13_Pos) /*!< EADC_T::INTSRC1: SPLIE13 Mask */ 1323 1324 #define EADC_INTSRC1_SPLIE14_Pos (14) /*!< EADC_T::INTSRC1: SPLIE14 Position */ 1325 #define EADC_INTSRC1_SPLIE14_Msk (0x1ul << EADC_INTSRC1_SPLIE14_Pos) /*!< EADC_T::INTSRC1: SPLIE14 Mask */ 1326 1327 #define EADC_INTSRC1_SPLIE15_Pos (15) /*!< EADC_T::INTSRC1: SPLIE15 Position */ 1328 #define EADC_INTSRC1_SPLIE15_Msk (0x1ul << EADC_INTSRC1_SPLIE15_Pos) /*!< EADC_T::INTSRC1: SPLIE15 Mask */ 1329 1330 #define EADC_INTSRC1_SPLIE16_Pos (16) /*!< EADC_T::INTSRC1: SPLIE16 Position */ 1331 #define EADC_INTSRC1_SPLIE16_Msk (0x1ul << EADC_INTSRC1_SPLIE16_Pos) /*!< EADC_T::INTSRC1: SPLIE16 Mask */ 1332 1333 #define EADC_INTSRC1_SPLIE17_Pos (17) /*!< EADC_T::INTSRC1: SPLIE17 Position */ 1334 #define EADC_INTSRC1_SPLIE17_Msk (0x1ul << EADC_INTSRC1_SPLIE17_Pos) /*!< EADC_T::INTSRC1: SPLIE17 Mask */ 1335 1336 #define EADC_INTSRC1_SPLIE18_Pos (18) /*!< EADC_T::INTSRC1: SPLIE18 Position */ 1337 #define EADC_INTSRC1_SPLIE18_Msk (0x1ul << EADC_INTSRC1_SPLIE18_Pos) /*!< EADC_T::INTSRC1: SPLIE18 Mask */ 1338 1339 #define EADC_INTSRC2_SPLIE0_Pos (0) /*!< EADC_T::INTSRC2: SPLIE0 Position */ 1340 #define EADC_INTSRC2_SPLIE0_Msk (0x1ul << EADC_INTSRC2_SPLIE0_Pos) /*!< EADC_T::INTSRC2: SPLIE0 Mask */ 1341 1342 #define EADC_INTSRC2_SPLIE1_Pos (1) /*!< EADC_T::INTSRC2: SPLIE1 Position */ 1343 #define EADC_INTSRC2_SPLIE1_Msk (0x1ul << EADC_INTSRC2_SPLIE1_Pos) /*!< EADC_T::INTSRC2: SPLIE1 Mask */ 1344 1345 #define EADC_INTSRC2_SPLIE2_Pos (2) /*!< EADC_T::INTSRC2: SPLIE2 Position */ 1346 #define EADC_INTSRC2_SPLIE2_Msk (0x1ul << EADC_INTSRC2_SPLIE2_Pos) /*!< EADC_T::INTSRC2: SPLIE2 Mask */ 1347 1348 #define EADC_INTSRC2_SPLIE3_Pos (3) /*!< EADC_T::INTSRC2: SPLIE3 Position */ 1349 #define EADC_INTSRC2_SPLIE3_Msk (0x1ul << EADC_INTSRC2_SPLIE3_Pos) /*!< EADC_T::INTSRC2: SPLIE3 Mask */ 1350 1351 #define EADC_INTSRC2_SPLIE4_Pos (4) /*!< EADC_T::INTSRC2: SPLIE4 Position */ 1352 #define EADC_INTSRC2_SPLIE4_Msk (0x1ul << EADC_INTSRC2_SPLIE4_Pos) /*!< EADC_T::INTSRC2: SPLIE4 Mask */ 1353 1354 #define EADC_INTSRC2_SPLIE5_Pos (5) /*!< EADC_T::INTSRC2: SPLIE5 Position */ 1355 #define EADC_INTSRC2_SPLIE5_Msk (0x1ul << EADC_INTSRC2_SPLIE5_Pos) /*!< EADC_T::INTSRC2: SPLIE5 Mask */ 1356 1357 #define EADC_INTSRC2_SPLIE6_Pos (6) /*!< EADC_T::INTSRC2: SPLIE6 Position */ 1358 #define EADC_INTSRC2_SPLIE6_Msk (0x1ul << EADC_INTSRC2_SPLIE6_Pos) /*!< EADC_T::INTSRC2: SPLIE6 Mask */ 1359 1360 #define EADC_INTSRC2_SPLIE7_Pos (7) /*!< EADC_T::INTSRC2: SPLIE7 Position */ 1361 #define EADC_INTSRC2_SPLIE7_Msk (0x1ul << EADC_INTSRC2_SPLIE7_Pos) /*!< EADC_T::INTSRC2: SPLIE7 Mask */ 1362 1363 #define EADC_INTSRC2_SPLIE8_Pos (8) /*!< EADC_T::INTSRC2: SPLIE8 Position */ 1364 #define EADC_INTSRC2_SPLIE8_Msk (0x1ul << EADC_INTSRC2_SPLIE8_Pos) /*!< EADC_T::INTSRC2: SPLIE8 Mask */ 1365 1366 #define EADC_INTSRC2_SPLIE9_Pos (9) /*!< EADC_T::INTSRC2: SPLIE9 Position */ 1367 #define EADC_INTSRC2_SPLIE9_Msk (0x1ul << EADC_INTSRC2_SPLIE9_Pos) /*!< EADC_T::INTSRC2: SPLIE9 Mask */ 1368 1369 #define EADC_INTSRC2_SPLIE10_Pos (10) /*!< EADC_T::INTSRC2: SPLIE10 Position */ 1370 #define EADC_INTSRC2_SPLIE10_Msk (0x1ul << EADC_INTSRC2_SPLIE10_Pos) /*!< EADC_T::INTSRC2: SPLIE10 Mask */ 1371 1372 #define EADC_INTSRC2_SPLIE11_Pos (11) /*!< EADC_T::INTSRC2: SPLIE11 Position */ 1373 #define EADC_INTSRC2_SPLIE11_Msk (0x1ul << EADC_INTSRC2_SPLIE11_Pos) /*!< EADC_T::INTSRC2: SPLIE11 Mask */ 1374 1375 #define EADC_INTSRC2_SPLIE12_Pos (12) /*!< EADC_T::INTSRC2: SPLIE12 Position */ 1376 #define EADC_INTSRC2_SPLIE12_Msk (0x1ul << EADC_INTSRC2_SPLIE12_Pos) /*!< EADC_T::INTSRC2: SPLIE12 Mask */ 1377 1378 #define EADC_INTSRC2_SPLIE13_Pos (13) /*!< EADC_T::INTSRC2: SPLIE13 Position */ 1379 #define EADC_INTSRC2_SPLIE13_Msk (0x1ul << EADC_INTSRC2_SPLIE13_Pos) /*!< EADC_T::INTSRC2: SPLIE13 Mask */ 1380 1381 #define EADC_INTSRC2_SPLIE14_Pos (14) /*!< EADC_T::INTSRC2: SPLIE14 Position */ 1382 #define EADC_INTSRC2_SPLIE14_Msk (0x1ul << EADC_INTSRC2_SPLIE14_Pos) /*!< EADC_T::INTSRC2: SPLIE14 Mask */ 1383 1384 #define EADC_INTSRC2_SPLIE15_Pos (15) /*!< EADC_T::INTSRC2: SPLIE15 Position */ 1385 #define EADC_INTSRC2_SPLIE15_Msk (0x1ul << EADC_INTSRC2_SPLIE15_Pos) /*!< EADC_T::INTSRC2: SPLIE15 Mask */ 1386 1387 #define EADC_INTSRC2_SPLIE16_Pos (16) /*!< EADC_T::INTSRC2: SPLIE16 Position */ 1388 #define EADC_INTSRC2_SPLIE16_Msk (0x1ul << EADC_INTSRC2_SPLIE16_Pos) /*!< EADC_T::INTSRC2: SPLIE16 Mask */ 1389 1390 #define EADC_INTSRC2_SPLIE17_Pos (17) /*!< EADC_T::INTSRC2: SPLIE17 Position */ 1391 #define EADC_INTSRC2_SPLIE17_Msk (0x1ul << EADC_INTSRC2_SPLIE17_Pos) /*!< EADC_T::INTSRC2: SPLIE17 Mask */ 1392 1393 #define EADC_INTSRC2_SPLIE18_Pos (18) /*!< EADC_T::INTSRC2: SPLIE18 Position */ 1394 #define EADC_INTSRC2_SPLIE18_Msk (0x1ul << EADC_INTSRC2_SPLIE18_Pos) /*!< EADC_T::INTSRC2: SPLIE18 Mask */ 1395 1396 #define EADC_INTSRC3_SPLIE0_Pos (0) /*!< EADC_T::INTSRC3: SPLIE0 Position */ 1397 #define EADC_INTSRC3_SPLIE0_Msk (0x1ul << EADC_INTSRC3_SPLIE0_Pos) /*!< EADC_T::INTSRC3: SPLIE0 Mask */ 1398 1399 #define EADC_INTSRC3_SPLIE1_Pos (1) /*!< EADC_T::INTSRC3: SPLIE1 Position */ 1400 #define EADC_INTSRC3_SPLIE1_Msk (0x1ul << EADC_INTSRC3_SPLIE1_Pos) /*!< EADC_T::INTSRC3: SPLIE1 Mask */ 1401 1402 #define EADC_INTSRC3_SPLIE2_Pos (2) /*!< EADC_T::INTSRC3: SPLIE2 Position */ 1403 #define EADC_INTSRC3_SPLIE2_Msk (0x1ul << EADC_INTSRC3_SPLIE2_Pos) /*!< EADC_T::INTSRC3: SPLIE2 Mask */ 1404 1405 #define EADC_INTSRC3_SPLIE3_Pos (3) /*!< EADC_T::INTSRC3: SPLIE3 Position */ 1406 #define EADC_INTSRC3_SPLIE3_Msk (0x1ul << EADC_INTSRC3_SPLIE3_Pos) /*!< EADC_T::INTSRC3: SPLIE3 Mask */ 1407 1408 #define EADC_INTSRC3_SPLIE4_Pos (4) /*!< EADC_T::INTSRC3: SPLIE4 Position */ 1409 #define EADC_INTSRC3_SPLIE4_Msk (0x1ul << EADC_INTSRC3_SPLIE4_Pos) /*!< EADC_T::INTSRC3: SPLIE4 Mask */ 1410 1411 #define EADC_INTSRC3_SPLIE5_Pos (5) /*!< EADC_T::INTSRC3: SPLIE5 Position */ 1412 #define EADC_INTSRC3_SPLIE5_Msk (0x1ul << EADC_INTSRC3_SPLIE5_Pos) /*!< EADC_T::INTSRC3: SPLIE5 Mask */ 1413 1414 #define EADC_INTSRC3_SPLIE6_Pos (6) /*!< EADC_T::INTSRC3: SPLIE6 Position */ 1415 #define EADC_INTSRC3_SPLIE6_Msk (0x1ul << EADC_INTSRC3_SPLIE6_Pos) /*!< EADC_T::INTSRC3: SPLIE6 Mask */ 1416 1417 #define EADC_INTSRC3_SPLIE7_Pos (7) /*!< EADC_T::INTSRC3: SPLIE7 Position */ 1418 #define EADC_INTSRC3_SPLIE7_Msk (0x1ul << EADC_INTSRC3_SPLIE7_Pos) /*!< EADC_T::INTSRC3: SPLIE7 Mask */ 1419 1420 #define EADC_INTSRC3_SPLIE8_Pos (8) /*!< EADC_T::INTSRC3: SPLIE8 Position */ 1421 #define EADC_INTSRC3_SPLIE8_Msk (0x1ul << EADC_INTSRC3_SPLIE8_Pos) /*!< EADC_T::INTSRC3: SPLIE8 Mask */ 1422 1423 #define EADC_INTSRC3_SPLIE9_Pos (9) /*!< EADC_T::INTSRC3: SPLIE9 Position */ 1424 #define EADC_INTSRC3_SPLIE9_Msk (0x1ul << EADC_INTSRC3_SPLIE9_Pos) /*!< EADC_T::INTSRC3: SPLIE9 Mask */ 1425 1426 #define EADC_INTSRC3_SPLIE10_Pos (10) /*!< EADC_T::INTSRC3: SPLIE10 Position */ 1427 #define EADC_INTSRC3_SPLIE10_Msk (0x1ul << EADC_INTSRC3_SPLIE10_Pos) /*!< EADC_T::INTSRC3: SPLIE10 Mask */ 1428 1429 #define EADC_INTSRC3_SPLIE11_Pos (11) /*!< EADC_T::INTSRC3: SPLIE11 Position */ 1430 #define EADC_INTSRC3_SPLIE11_Msk (0x1ul << EADC_INTSRC3_SPLIE11_Pos) /*!< EADC_T::INTSRC3: SPLIE11 Mask */ 1431 1432 #define EADC_INTSRC3_SPLIE12_Pos (12) /*!< EADC_T::INTSRC3: SPLIE12 Position */ 1433 #define EADC_INTSRC3_SPLIE12_Msk (0x1ul << EADC_INTSRC3_SPLIE12_Pos) /*!< EADC_T::INTSRC3: SPLIE12 Mask */ 1434 1435 #define EADC_INTSRC3_SPLIE13_Pos (13) /*!< EADC_T::INTSRC3: SPLIE13 Position */ 1436 #define EADC_INTSRC3_SPLIE13_Msk (0x1ul << EADC_INTSRC3_SPLIE13_Pos) /*!< EADC_T::INTSRC3: SPLIE13 Mask */ 1437 1438 #define EADC_INTSRC3_SPLIE14_Pos (14) /*!< EADC_T::INTSRC3: SPLIE14 Position */ 1439 #define EADC_INTSRC3_SPLIE14_Msk (0x1ul << EADC_INTSRC3_SPLIE14_Pos) /*!< EADC_T::INTSRC3: SPLIE14 Mask */ 1440 1441 #define EADC_INTSRC3_SPLIE15_Pos (15) /*!< EADC_T::INTSRC3: SPLIE15 Position */ 1442 #define EADC_INTSRC3_SPLIE15_Msk (0x1ul << EADC_INTSRC3_SPLIE15_Pos) /*!< EADC_T::INTSRC3: SPLIE15 Mask */ 1443 1444 #define EADC_INTSRC3_SPLIE16_Pos (16) /*!< EADC_T::INTSRC3: SPLIE16 Position */ 1445 #define EADC_INTSRC3_SPLIE16_Msk (0x1ul << EADC_INTSRC3_SPLIE16_Pos) /*!< EADC_T::INTSRC3: SPLIE16 Mask */ 1446 1447 #define EADC_INTSRC3_SPLIE17_Pos (17) /*!< EADC_T::INTSRC3: SPLIE17 Position */ 1448 #define EADC_INTSRC3_SPLIE17_Msk (0x1ul << EADC_INTSRC3_SPLIE17_Pos) /*!< EADC_T::INTSRC3: SPLIE17 Mask */ 1449 1450 #define EADC_INTSRC3_SPLIE18_Pos (18) /*!< EADC_T::INTSRC3: SPLIE18 Position */ 1451 #define EADC_INTSRC3_SPLIE18_Msk (0x1ul << EADC_INTSRC3_SPLIE18_Pos) /*!< EADC_T::INTSRC3: SPLIE18 Mask */ 1452 1453 #define EADC_CMP_ADCMPEN_Pos (0) /*!< EADC_T::CMP: ADCMPEN Position */ 1454 #define EADC_CMP_ADCMPEN_Msk (0x1ul << EADC_CMP_ADCMPEN_Pos) /*!< EADC_T::CMP: ADCMPEN Mask */ 1455 1456 #define EADC_CMP_ADCMPIE_Pos (1) /*!< EADC_T::CMP: ADCMPIE Position */ 1457 #define EADC_CMP_ADCMPIE_Msk (0x1ul << EADC_CMP_ADCMPIE_Pos) /*!< EADC_T::CMP: ADCMPIE Mask */ 1458 1459 #define EADC_CMP_CMPCOND_Pos (2) /*!< EADC_T::CMP: CMPCOND Position */ 1460 #define EADC_CMP_CMPCOND_Msk (0x1ul << EADC_CMP_CMPCOND_Pos) /*!< EADC_T::CMP: CMPCOND Mask */ 1461 1462 #define EADC_CMP_CMPSPL_Pos (3) /*!< EADC_T::CMP: CMPSPL Position */ 1463 #define EADC_CMP_CMPSPL_Msk (0x1ful << EADC_CMP_CMPSPL_Pos) /*!< EADC_T::CMP: CMPSPL Mask */ 1464 1465 #define EADC_CMP_CMPMCNT_Pos (8) /*!< EADC_T::CMP: CMPMCNT Position */ 1466 #define EADC_CMP_CMPMCNT_Msk (0xful << EADC_CMP_CMPMCNT_Pos) /*!< EADC_T::CMP: CMPMCNT Mask */ 1467 1468 #define EADC_CMP_CMPWEN_Pos (15) /*!< EADC_T::CMP: CMPWEN Position */ 1469 #define EADC_CMP_CMPWEN_Msk (0x1ul << EADC_CMP_CMPWEN_Pos) /*!< EADC_T::CMP: CMPWEN Mask */ 1470 1471 #define EADC_CMP_CMPDAT_Pos (16) /*!< EADC_T::CMP: CMPDAT Position */ 1472 #define EADC_CMP_CMPDAT_Msk (0xffful << EADC_CMP_CMPDAT_Pos) /*!< EADC_T::CMP: CMPDAT Mask */ 1473 1474 #define EADC_CMP0_ADCMPEN_Pos (0) /*!< EADC_T::CMP0: ADCMPEN Position */ 1475 #define EADC_CMP0_ADCMPEN_Msk (0x1ul << EADC_CMP0_ADCMPEN_Pos) /*!< EADC_T::CMP0: ADCMPEN Mask */ 1476 1477 #define EADC_CMP0_ADCMPIE_Pos (1) /*!< EADC_T::CMP0: ADCMPIE Position */ 1478 #define EADC_CMP0_ADCMPIE_Msk (0x1ul << EADC_CMP0_ADCMPIE_Pos) /*!< EADC_T::CMP0: ADCMPIE Mask */ 1479 1480 #define EADC_CMP0_CMPCOND_Pos (2) /*!< EADC_T::CMP0: CMPCOND Position */ 1481 #define EADC_CMP0_CMPCOND_Msk (0x1ul << EADC_CMP0_CMPCOND_Pos) /*!< EADC_T::CMP0: CMPCOND Mask */ 1482 1483 #define EADC_CMP0_CMPSPL_Pos (3) /*!< EADC_T::CMP0: CMPSPL Position */ 1484 #define EADC_CMP0_CMPSPL_Msk (0x1ful << EADC_CMP0_CMPSPL_Pos) /*!< EADC_T::CMP0: CMPSPL Mask */ 1485 1486 #define EADC_CMP0_CMPMCNT_Pos (8) /*!< EADC_T::CMP0: CMPMCNT Position */ 1487 #define EADC_CMP0_CMPMCNT_Msk (0xful << EADC_CMP0_CMPMCNT_Pos) /*!< EADC_T::CMP0: CMPMCNT Mask */ 1488 1489 #define EADC_CMP0_CMPWEN_Pos (15) /*!< EADC_T::CMP0: CMPWEN Position */ 1490 #define EADC_CMP0_CMPWEN_Msk (0x1ul << EADC_CMP0_CMPWEN_Pos) /*!< EADC_T::CMP0: CMPWEN Mask */ 1491 1492 #define EADC_CMP0_CMPDAT_Pos (16) /*!< EADC_T::CMP0: CMPDAT Position */ 1493 #define EADC_CMP0_CMPDAT_Msk (0xffful << EADC_CMP0_CMPDAT_Pos) /*!< EADC_T::CMP0: CMPDAT Mask */ 1494 1495 #define EADC_CMP1_ADCMPEN_Pos (0) /*!< EADC_T::CMP1: ADCMPEN Position */ 1496 #define EADC_CMP1_ADCMPEN_Msk (0x1ul << EADC_CMP1_ADCMPEN_Pos) /*!< EADC_T::CMP1: ADCMPEN Mask */ 1497 1498 #define EADC_CMP1_ADCMPIE_Pos (1) /*!< EADC_T::CMP1: ADCMPIE Position */ 1499 #define EADC_CMP1_ADCMPIE_Msk (0x1ul << EADC_CMP1_ADCMPIE_Pos) /*!< EADC_T::CMP1: ADCMPIE Mask */ 1500 1501 #define EADC_CMP1_CMPCOND_Pos (2) /*!< EADC_T::CMP1: CMPCOND Position */ 1502 #define EADC_CMP1_CMPCOND_Msk (0x1ul << EADC_CMP1_CMPCOND_Pos) /*!< EADC_T::CMP1: CMPCOND Mask */ 1503 1504 #define EADC_CMP1_CMPSPL_Pos (3) /*!< EADC_T::CMP1: CMPSPL Position */ 1505 #define EADC_CMP1_CMPSPL_Msk (0x1ful << EADC_CMP1_CMPSPL_Pos) /*!< EADC_T::CMP1: CMPSPL Mask */ 1506 1507 #define EADC_CMP1_CMPMCNT_Pos (8) /*!< EADC_T::CMP1: CMPMCNT Position */ 1508 #define EADC_CMP1_CMPMCNT_Msk (0xful << EADC_CMP1_CMPMCNT_Pos) /*!< EADC_T::CMP1: CMPMCNT Mask */ 1509 1510 #define EADC_CMP1_CMPWEN_Pos (15) /*!< EADC_T::CMP1: CMPWEN Position */ 1511 #define EADC_CMP1_CMPWEN_Msk (0x1ul << EADC_CMP1_CMPWEN_Pos) /*!< EADC_T::CMP1: CMPWEN Mask */ 1512 1513 #define EADC_CMP1_CMPDAT_Pos (16) /*!< EADC_T::CMP1: CMPDAT Position */ 1514 #define EADC_CMP1_CMPDAT_Msk (0xffful << EADC_CMP1_CMPDAT_Pos) /*!< EADC_T::CMP1: CMPDAT Mask */ 1515 1516 #define EADC_CMP2_ADCMPEN_Pos (0) /*!< EADC_T::CMP2: ADCMPEN Position */ 1517 #define EADC_CMP2_ADCMPEN_Msk (0x1ul << EADC_CMP2_ADCMPEN_Pos) /*!< EADC_T::CMP2: ADCMPEN Mask */ 1518 1519 #define EADC_CMP2_ADCMPIE_Pos (1) /*!< EADC_T::CMP2: ADCMPIE Position */ 1520 #define EADC_CMP2_ADCMPIE_Msk (0x1ul << EADC_CMP2_ADCMPIE_Pos) /*!< EADC_T::CMP2: ADCMPIE Mask */ 1521 1522 #define EADC_CMP2_CMPCOND_Pos (2) /*!< EADC_T::CMP2: CMPCOND Position */ 1523 #define EADC_CMP2_CMPCOND_Msk (0x1ul << EADC_CMP2_CMPCOND_Pos) /*!< EADC_T::CMP2: CMPCOND Mask */ 1524 1525 #define EADC_CMP2_CMPSPL_Pos (3) /*!< EADC_T::CMP2: CMPSPL Position */ 1526 #define EADC_CMP2_CMPSPL_Msk (0x1ful << EADC_CMP2_CMPSPL_Pos) /*!< EADC_T::CMP2: CMPSPL Mask */ 1527 1528 #define EADC_CMP2_CMPMCNT_Pos (8) /*!< EADC_T::CMP2: CMPMCNT Position */ 1529 #define EADC_CMP2_CMPMCNT_Msk (0xful << EADC_CMP2_CMPMCNT_Pos) /*!< EADC_T::CMP2: CMPMCNT Mask */ 1530 1531 #define EADC_CMP2_CMPWEN_Pos (15) /*!< EADC_T::CMP2: CMPWEN Position */ 1532 #define EADC_CMP2_CMPWEN_Msk (0x1ul << EADC_CMP2_CMPWEN_Pos) /*!< EADC_T::CMP2: CMPWEN Mask */ 1533 1534 #define EADC_CMP2_CMPDAT_Pos (16) /*!< EADC_T::CMP2: CMPDAT Position */ 1535 #define EADC_CMP2_CMPDAT_Msk (0xffful << EADC_CMP2_CMPDAT_Pos) /*!< EADC_T::CMP2: CMPDAT Mask */ 1536 1537 #define EADC_CMP3_ADCMPEN_Pos (0) /*!< EADC_T::CMP3: ADCMPEN Position */ 1538 #define EADC_CMP3_ADCMPEN_Msk (0x1ul << EADC_CMP3_ADCMPEN_Pos) /*!< EADC_T::CMP3: ADCMPEN Mask */ 1539 1540 #define EADC_CMP3_ADCMPIE_Pos (1) /*!< EADC_T::CMP3: ADCMPIE Position */ 1541 #define EADC_CMP3_ADCMPIE_Msk (0x1ul << EADC_CMP3_ADCMPIE_Pos) /*!< EADC_T::CMP3: ADCMPIE Mask */ 1542 1543 #define EADC_CMP3_CMPCOND_Pos (2) /*!< EADC_T::CMP3: CMPCOND Position */ 1544 #define EADC_CMP3_CMPCOND_Msk (0x1ul << EADC_CMP3_CMPCOND_Pos) /*!< EADC_T::CMP3: CMPCOND Mask */ 1545 1546 #define EADC_CMP3_CMPSPL_Pos (3) /*!< EADC_T::CMP3: CMPSPL Position */ 1547 #define EADC_CMP3_CMPSPL_Msk (0x1ful << EADC_CMP3_CMPSPL_Pos) /*!< EADC_T::CMP3: CMPSPL Mask */ 1548 1549 #define EADC_CMP3_CMPMCNT_Pos (8) /*!< EADC_T::CMP3: CMPMCNT Position */ 1550 #define EADC_CMP3_CMPMCNT_Msk (0xful << EADC_CMP3_CMPMCNT_Pos) /*!< EADC_T::CMP3: CMPMCNT Mask */ 1551 1552 #define EADC_CMP3_CMPWEN_Pos (15) /*!< EADC_T::CMP3: CMPWEN Position */ 1553 #define EADC_CMP3_CMPWEN_Msk (0x1ul << EADC_CMP3_CMPWEN_Pos) /*!< EADC_T::CMP3: CMPWEN Mask */ 1554 1555 #define EADC_CMP3_CMPDAT_Pos (16) /*!< EADC_T::CMP3: CMPDAT Position */ 1556 #define EADC_CMP3_CMPDAT_Msk (0xffful << EADC_CMP3_CMPDAT_Pos) /*!< EADC_T::CMP3: CMPDAT Mask */ 1557 1558 #define EADC_STATUS0_VALID_Pos (0) /*!< EADC_T::STATUS0: VALID Position */ 1559 #define EADC_STATUS0_VALID_Msk (0xfffful << EADC_STATUS0_VALID_Pos) /*!< EADC_T::STATUS0: VALID Mask */ 1560 1561 #define EADC_STATUS0_OV_Pos (16) /*!< EADC_T::STATUS0: OV Position */ 1562 #define EADC_STATUS0_OV_Msk (0xfffful << EADC_STATUS0_OV_Pos) /*!< EADC_T::STATUS0: OV Mask */ 1563 1564 #define EADC_STATUS1_VALID_Pos (0) /*!< EADC_T::STATUS1: VALID Position */ 1565 #define EADC_STATUS1_VALID_Msk (0x7ul << EADC_STATUS1_VALID_Pos) /*!< EADC_T::STATUS1: VALID Mask */ 1566 1567 #define EADC_STATUS1_OV_Pos (16) /*!< EADC_T::STATUS1: OV Position */ 1568 #define EADC_STATUS1_OV_Msk (0x7ul << EADC_STATUS1_OV_Pos) /*!< EADC_T::STATUS1: OV Mask */ 1569 1570 #define EADC_STATUS2_ADIF0_Pos (0) /*!< EADC_T::STATUS2: ADIF0 Position */ 1571 #define EADC_STATUS2_ADIF0_Msk (0x1ul << EADC_STATUS2_ADIF0_Pos) /*!< EADC_T::STATUS2: ADIF0 Mask */ 1572 1573 #define EADC_STATUS2_ADIF1_Pos (1) /*!< EADC_T::STATUS2: ADIF1 Position */ 1574 #define EADC_STATUS2_ADIF1_Msk (0x1ul << EADC_STATUS2_ADIF1_Pos) /*!< EADC_T::STATUS2: ADIF1 Mask */ 1575 1576 #define EADC_STATUS2_ADIF2_Pos (2) /*!< EADC_T::STATUS2: ADIF2 Position */ 1577 #define EADC_STATUS2_ADIF2_Msk (0x1ul << EADC_STATUS2_ADIF2_Pos) /*!< EADC_T::STATUS2: ADIF2 Mask */ 1578 1579 #define EADC_STATUS2_ADIF3_Pos (3) /*!< EADC_T::STATUS2: ADIF3 Position */ 1580 #define EADC_STATUS2_ADIF3_Msk (0x1ul << EADC_STATUS2_ADIF3_Pos) /*!< EADC_T::STATUS2: ADIF3 Mask */ 1581 1582 #define EADC_STATUS2_ADCMPF0_Pos (4) /*!< EADC_T::STATUS2: ADCMPF0 Position */ 1583 #define EADC_STATUS2_ADCMPF0_Msk (0x1ul << EADC_STATUS2_ADCMPF0_Pos) /*!< EADC_T::STATUS2: ADCMPF0 Mask */ 1584 1585 #define EADC_STATUS2_ADCMPF1_Pos (5) /*!< EADC_T::STATUS2: ADCMPF1 Position */ 1586 #define EADC_STATUS2_ADCMPF1_Msk (0x1ul << EADC_STATUS2_ADCMPF1_Pos) /*!< EADC_T::STATUS2: ADCMPF1 Mask */ 1587 1588 #define EADC_STATUS2_ADCMPF2_Pos (6) /*!< EADC_T::STATUS2: ADCMPF2 Position */ 1589 #define EADC_STATUS2_ADCMPF2_Msk (0x1ul << EADC_STATUS2_ADCMPF2_Pos) /*!< EADC_T::STATUS2: ADCMPF2 Mask */ 1590 1591 #define EADC_STATUS2_ADCMPF3_Pos (7) /*!< EADC_T::STATUS2: ADCMPF3 Position */ 1592 #define EADC_STATUS2_ADCMPF3_Msk (0x1ul << EADC_STATUS2_ADCMPF3_Pos) /*!< EADC_T::STATUS2: ADCMPF3 Mask */ 1593 1594 #define EADC_STATUS2_ADOVIF0_Pos (8) /*!< EADC_T::STATUS2: ADOVIF0 Position */ 1595 #define EADC_STATUS2_ADOVIF0_Msk (0x1ul << EADC_STATUS2_ADOVIF0_Pos) /*!< EADC_T::STATUS2: ADOVIF0 Mask */ 1596 1597 #define EADC_STATUS2_ADOVIF1_Pos (9) /*!< EADC_T::STATUS2: ADOVIF1 Position */ 1598 #define EADC_STATUS2_ADOVIF1_Msk (0x1ul << EADC_STATUS2_ADOVIF1_Pos) /*!< EADC_T::STATUS2: ADOVIF1 Mask */ 1599 1600 #define EADC_STATUS2_ADOVIF2_Pos (10) /*!< EADC_T::STATUS2: ADOVIF2 Position */ 1601 #define EADC_STATUS2_ADOVIF2_Msk (0x1ul << EADC_STATUS2_ADOVIF2_Pos) /*!< EADC_T::STATUS2: ADOVIF2 Mask */ 1602 1603 #define EADC_STATUS2_ADOVIF3_Pos (11) /*!< EADC_T::STATUS2: ADOVIF3 Position */ 1604 #define EADC_STATUS2_ADOVIF3_Msk (0x1ul << EADC_STATUS2_ADOVIF3_Pos) /*!< EADC_T::STATUS2: ADOVIF3 Mask */ 1605 1606 #define EADC_STATUS2_ADCMPO0_Pos (12) /*!< EADC_T::STATUS2: ADCMPO0 Position */ 1607 #define EADC_STATUS2_ADCMPO0_Msk (0x1ul << EADC_STATUS2_ADCMPO0_Pos) /*!< EADC_T::STATUS2: ADCMPO0 Mask */ 1608 1609 #define EADC_STATUS2_ADCMPO1_Pos (13) /*!< EADC_T::STATUS2: ADCMPO1 Position */ 1610 #define EADC_STATUS2_ADCMPO1_Msk (0x1ul << EADC_STATUS2_ADCMPO1_Pos) /*!< EADC_T::STATUS2: ADCMPO1 Mask */ 1611 1612 #define EADC_STATUS2_ADCMPO2_Pos (14) /*!< EADC_T::STATUS2: ADCMPO2 Position */ 1613 #define EADC_STATUS2_ADCMPO2_Msk (0x1ul << EADC_STATUS2_ADCMPO2_Pos) /*!< EADC_T::STATUS2: ADCMPO2 Mask */ 1614 1615 #define EADC_STATUS2_ADCMPO3_Pos (15) /*!< EADC_T::STATUS2: ADCMPO3 Position */ 1616 #define EADC_STATUS2_ADCMPO3_Msk (0x1ul << EADC_STATUS2_ADCMPO3_Pos) /*!< EADC_T::STATUS2: ADCMPO3 Mask */ 1617 1618 #define EADC_STATUS2_CHANNEL_Pos (16) /*!< EADC_T::STATUS2: CHANNEL Position */ 1619 #define EADC_STATUS2_CHANNEL_Msk (0x1ful << EADC_STATUS2_CHANNEL_Pos) /*!< EADC_T::STATUS2: CHANNEL Mask */ 1620 1621 #define EADC_STATUS2_BUSY_Pos (23) /*!< EADC_T::STATUS2: BUSY Position */ 1622 #define EADC_STATUS2_BUSY_Msk (0x1ul << EADC_STATUS2_BUSY_Pos) /*!< EADC_T::STATUS2: BUSY Mask */ 1623 1624 #define EADC_STATUS2_ADOVIF_Pos (24) /*!< EADC_T::STATUS2: ADOVIF Position */ 1625 #define EADC_STATUS2_ADOVIF_Msk (0x1ul << EADC_STATUS2_ADOVIF_Pos) /*!< EADC_T::STATUS2: ADOVIF Mask */ 1626 1627 #define EADC_STATUS2_STOVF_Pos (25) /*!< EADC_T::STATUS2: STOVF Position */ 1628 #define EADC_STATUS2_STOVF_Msk (0x1ul << EADC_STATUS2_STOVF_Pos) /*!< EADC_T::STATUS2: STOVF Mask */ 1629 1630 #define EADC_STATUS2_AVALID_Pos (26) /*!< EADC_T::STATUS2: AVALID Position */ 1631 #define EADC_STATUS2_AVALID_Msk (0x1ul << EADC_STATUS2_AVALID_Pos) /*!< EADC_T::STATUS2: AVALID Mask */ 1632 1633 #define EADC_STATUS2_AOV_Pos (27) /*!< EADC_T::STATUS2: AOV Position */ 1634 #define EADC_STATUS2_AOV_Msk (0x1ul << EADC_STATUS2_AOV_Pos) /*!< EADC_T::STATUS2: AOV Mask */ 1635 1636 #define EADC_STATUS3_CURSPL_Pos (0) /*!< EADC_T::STATUS3: CURSPL Position */ 1637 #define EADC_STATUS3_CURSPL_Msk (0x1ful << EADC_STATUS3_CURSPL_Pos) /*!< EADC_T::STATUS3: CURSPL Mask */ 1638 1639 #define EADC_DDAT0_RESULT_Pos (0) /*!< EADC_T::DDAT0: RESULT Position */ 1640 #define EADC_DDAT0_RESULT_Msk (0xfffful << EADC_DDAT0_RESULT_Pos) /*!< EADC_T::DDAT0: RESULT Mask */ 1641 1642 #define EADC_DDAT0_OV_Pos (16) /*!< EADC_T::DDAT0: OV Position */ 1643 #define EADC_DDAT0_OV_Msk (0x1ul << EADC_DDAT0_OV_Pos) /*!< EADC_T::DDAT0: OV Mask */ 1644 1645 #define EADC_DDAT0_VALID_Pos (17) /*!< EADC_T::DDAT0: VALID Position */ 1646 #define EADC_DDAT0_VALID_Msk (0x1ul << EADC_DDAT0_VALID_Pos) /*!< EADC_T::DDAT0: VALID Mask */ 1647 1648 #define EADC_DDAT1_RESULT_Pos (0) /*!< EADC_T::DDAT1: RESULT Position */ 1649 #define EADC_DDAT1_RESULT_Msk (0xfffful << EADC_DDAT1_RESULT_Pos) /*!< EADC_T::DDAT1: RESULT Mask */ 1650 1651 #define EADC_DDAT1_OV_Pos (16) /*!< EADC_T::DDAT1: OV Position */ 1652 #define EADC_DDAT1_OV_Msk (0x1ul << EADC_DDAT1_OV_Pos) /*!< EADC_T::DDAT1: OV Mask */ 1653 1654 #define EADC_DDAT1_VALID_Pos (17) /*!< EADC_T::DDAT1: VALID Position */ 1655 #define EADC_DDAT1_VALID_Msk (0x1ul << EADC_DDAT1_VALID_Pos) /*!< EADC_T::DDAT1: VALID Mask */ 1656 1657 #define EADC_DDAT2_RESULT_Pos (0) /*!< EADC_T::DDAT2: RESULT Position */ 1658 #define EADC_DDAT2_RESULT_Msk (0xfffful << EADC_DDAT2_RESULT_Pos) /*!< EADC_T::DDAT2: RESULT Mask */ 1659 1660 #define EADC_DDAT2_OV_Pos (16) /*!< EADC_T::DDAT2: OV Position */ 1661 #define EADC_DDAT2_OV_Msk (0x1ul << EADC_DDAT2_OV_Pos) /*!< EADC_T::DDAT2: OV Mask */ 1662 1663 #define EADC_DDAT2_VALID_Pos (17) /*!< EADC_T::DDAT2: VALID Position */ 1664 #define EADC_DDAT2_VALID_Msk (0x1ul << EADC_DDAT2_VALID_Pos) /*!< EADC_T::DDAT2: VALID Mask */ 1665 1666 #define EADC_DDAT3_RESULT_Pos (0) /*!< EADC_T::DDAT3: RESULT Position */ 1667 #define EADC_DDAT3_RESULT_Msk (0xfffful << EADC_DDAT3_RESULT_Pos) /*!< EADC_T::DDAT3: RESULT Mask */ 1668 1669 #define EADC_DDAT3_OV_Pos (16) /*!< EADC_T::DDAT3: OV Position */ 1670 #define EADC_DDAT3_OV_Msk (0x1ul << EADC_DDAT3_OV_Pos) /*!< EADC_T::DDAT3: OV Mask */ 1671 1672 #define EADC_DDAT3_VALID_Pos (17) /*!< EADC_T::DDAT3: VALID Position */ 1673 #define EADC_DDAT3_VALID_Msk (0x1ul << EADC_DDAT3_VALID_Pos) /*!< EADC_T::DDAT3: VALID Mask */ 1674 1675 #define EADC_PWRM_PWUPRDY_Pos (0) /*!< EADC_T::PWRM: PWUPRDY Position */ 1676 #define EADC_PWRM_PWUPRDY_Msk (0x1ul << EADC_PWRM_PWUPRDY_Pos) /*!< EADC_T::PWRM: PWUPRDY Mask */ 1677 1678 #define EADC_PWRM_PWUCALEN_Pos (1) /*!< EADC_T::PWRM: PWUCALEN Position */ 1679 #define EADC_PWRM_PWUCALEN_Msk (0x1ul << EADC_PWRM_PWUCALEN_Pos) /*!< EADC_T::PWRM: PWUCALEN Mask */ 1680 1681 #define EADC_PWRM_PWDMOD_Pos (2) /*!< EADC_T::PWRM: PWDMOD Position */ 1682 #define EADC_PWRM_PWDMOD_Msk (0x3ul << EADC_PWRM_PWDMOD_Pos) /*!< EADC_T::PWRM: PWDMOD Mask */ 1683 1684 #define EADC_PWRM_LDOSUT_Pos (8) /*!< EADC_T::PWRM: LDOSUT Position */ 1685 #define EADC_PWRM_LDOSUT_Msk (0xffful << EADC_PWRM_LDOSUT_Pos) /*!< EADC_T::PWRM: LDOSUT Mask */ 1686 1687 #define EADC_CALCTL_CALSTART_Pos (1) /*!< EADC_T::CALCTL: CALSTART Position */ 1688 #define EADC_CALCTL_CALSTART_Msk (0x1ul << EADC_CALCTL_CALSTART_Pos) /*!< EADC_T::CALCTL: CALSTART Mask */ 1689 1690 #define EADC_CALCTL_CALDONE_Pos (2) /*!< EADC_T::CALCTL: CALDONE Position */ 1691 #define EADC_CALCTL_CALDONE_Msk (0x1ul << EADC_CALCTL_CALDONE_Pos) /*!< EADC_T::CALCTL: CALDONE Mask */ 1692 1693 #define EADC_CALCTL_CALSEL_Pos (3) /*!< EADC_T::CALCTL: CALSEL Position */ 1694 #define EADC_CALCTL_CALSEL_Msk (0x1ul << EADC_CALCTL_CALSEL_Pos) /*!< EADC_T::CALCTL: CALSEL Mask */ 1695 1696 #define EADC_CALDWRD_CALWORD_Pos (0) /*!< EADC_T::CALDWRD: CALWORD Position */ 1697 #define EADC_CALDWRD_CALWORD_Msk (0x7ful << EADC_CALDWRD_CALWORD_Pos) /*!< EADC_T::CALDWRD: CALWORD Mask */ 1698 1699 /**@}*/ /* EADC_CONST */ 1700 /**@}*/ /* end of EADC register group */ 1701 /**@}*/ /* end of REGISTER group */ 1702 1703 1704 1705 #endif /* __EADC_REG_H__ */ 1706
