1 /** 2 * \file 3 * 4 * \brief Component description for DSU 5 * 6 * Copyright (c) 2016 Atmel Corporation, 7 * a wholly owned subsidiary of Microchip Technology Inc. 8 * 9 * \asf_license_start 10 * 11 * \page License 12 * 13 * Licensed under the Apache License, Version 2.0 (the "License"); 14 * you may not use this file except in compliance with the License. 15 * You may obtain a copy of the Licence at 16 * 17 * http://www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an "AS IS" BASIS, 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 * 25 * \asf_license_stop 26 * 27 */ 28 29 #ifndef _SAML21_DSU_COMPONENT_ 30 #define _SAML21_DSU_COMPONENT_ 31 32 /* ========================================================================== */ 33 /** SOFTWARE API DEFINITION FOR DSU */ 34 /* ========================================================================== */ 35 /** \addtogroup SAML21_DSU Device Service Unit */ 36 /*@{*/ 37 38 #define DSU_U2209 39 #define REV_DSU 0x250 40 41 /* -------- DSU_CTRL : (DSU Offset: 0x0000) ( /W 8) Control -------- */ 42 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 43 typedef union { 44 struct { 45 uint8_t SWRST:1; /*!< bit: 0 Software Reset */ 46 uint8_t :1; /*!< bit: 1 Reserved */ 47 uint8_t CRC:1; /*!< bit: 2 32-bit Cyclic Redundancy Code */ 48 uint8_t MBIST:1; /*!< bit: 3 Memory built-in self-test */ 49 uint8_t CE:1; /*!< bit: 4 Chip-Erase */ 50 uint8_t :1; /*!< bit: 5 Reserved */ 51 uint8_t ARR:1; /*!< bit: 6 Auxiliary Row Read */ 52 uint8_t SMSA:1; /*!< bit: 7 Start Memory Stream Access */ 53 } bit; /*!< Structure used for bit access */ 54 uint8_t reg; /*!< Type used for register access */ 55 } DSU_CTRL_Type; 56 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 57 58 #define DSU_CTRL_OFFSET 0x0000 /**< \brief (DSU_CTRL offset) Control */ 59 #define DSU_CTRL_RESETVALUE _U(0x00) /**< \brief (DSU_CTRL reset_value) Control */ 60 61 #define DSU_CTRL_SWRST_Pos 0 /**< \brief (DSU_CTRL) Software Reset */ 62 #define DSU_CTRL_SWRST (_U(0x1) << DSU_CTRL_SWRST_Pos) 63 #define DSU_CTRL_CRC_Pos 2 /**< \brief (DSU_CTRL) 32-bit Cyclic Redundancy Code */ 64 #define DSU_CTRL_CRC (_U(0x1) << DSU_CTRL_CRC_Pos) 65 #define DSU_CTRL_MBIST_Pos 3 /**< \brief (DSU_CTRL) Memory built-in self-test */ 66 #define DSU_CTRL_MBIST (_U(0x1) << DSU_CTRL_MBIST_Pos) 67 #define DSU_CTRL_CE_Pos 4 /**< \brief (DSU_CTRL) Chip-Erase */ 68 #define DSU_CTRL_CE (_U(0x1) << DSU_CTRL_CE_Pos) 69 #define DSU_CTRL_ARR_Pos 6 /**< \brief (DSU_CTRL) Auxiliary Row Read */ 70 #define DSU_CTRL_ARR (_U(0x1) << DSU_CTRL_ARR_Pos) 71 #define DSU_CTRL_SMSA_Pos 7 /**< \brief (DSU_CTRL) Start Memory Stream Access */ 72 #define DSU_CTRL_SMSA (_U(0x1) << DSU_CTRL_SMSA_Pos) 73 #define DSU_CTRL_MASK _U(0xDD) /**< \brief (DSU_CTRL) MASK Register */ 74 75 /* -------- DSU_STATUSA : (DSU Offset: 0x0001) (R/W 8) Status A -------- */ 76 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 77 typedef union { 78 struct { 79 uint8_t DONE:1; /*!< bit: 0 Done */ 80 uint8_t CRSTEXT:1; /*!< bit: 1 CPU Reset Phase Extension */ 81 uint8_t BERR:1; /*!< bit: 2 Bus Error */ 82 uint8_t FAIL:1; /*!< bit: 3 Failure */ 83 uint8_t PERR:1; /*!< bit: 4 Protection Error */ 84 uint8_t :3; /*!< bit: 5.. 7 Reserved */ 85 } bit; /*!< Structure used for bit access */ 86 uint8_t reg; /*!< Type used for register access */ 87 } DSU_STATUSA_Type; 88 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 89 90 #define DSU_STATUSA_OFFSET 0x0001 /**< \brief (DSU_STATUSA offset) Status A */ 91 #define DSU_STATUSA_RESETVALUE _U(0x00) /**< \brief (DSU_STATUSA reset_value) Status A */ 92 93 #define DSU_STATUSA_DONE_Pos 0 /**< \brief (DSU_STATUSA) Done */ 94 #define DSU_STATUSA_DONE (_U(0x1) << DSU_STATUSA_DONE_Pos) 95 #define DSU_STATUSA_CRSTEXT_Pos 1 /**< \brief (DSU_STATUSA) CPU Reset Phase Extension */ 96 #define DSU_STATUSA_CRSTEXT (_U(0x1) << DSU_STATUSA_CRSTEXT_Pos) 97 #define DSU_STATUSA_BERR_Pos 2 /**< \brief (DSU_STATUSA) Bus Error */ 98 #define DSU_STATUSA_BERR (_U(0x1) << DSU_STATUSA_BERR_Pos) 99 #define DSU_STATUSA_FAIL_Pos 3 /**< \brief (DSU_STATUSA) Failure */ 100 #define DSU_STATUSA_FAIL (_U(0x1) << DSU_STATUSA_FAIL_Pos) 101 #define DSU_STATUSA_PERR_Pos 4 /**< \brief (DSU_STATUSA) Protection Error */ 102 #define DSU_STATUSA_PERR (_U(0x1) << DSU_STATUSA_PERR_Pos) 103 #define DSU_STATUSA_MASK _U(0x1F) /**< \brief (DSU_STATUSA) MASK Register */ 104 105 /* -------- DSU_STATUSB : (DSU Offset: 0x0002) (R/ 8) Status B -------- */ 106 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 107 typedef union { 108 struct { 109 uint8_t PROT:1; /*!< bit: 0 Protected */ 110 uint8_t DBGPRES:1; /*!< bit: 1 Debugger Present */ 111 uint8_t DCCD0:1; /*!< bit: 2 Debug Communication Channel 0 Dirty */ 112 uint8_t DCCD1:1; /*!< bit: 3 Debug Communication Channel 1 Dirty */ 113 uint8_t HPE:1; /*!< bit: 4 Hot-Plugging Enable */ 114 uint8_t :3; /*!< bit: 5.. 7 Reserved */ 115 } bit; /*!< Structure used for bit access */ 116 struct { 117 uint8_t :2; /*!< bit: 0.. 1 Reserved */ 118 uint8_t DCCD:2; /*!< bit: 2.. 3 Debug Communication Channel x Dirty */ 119 uint8_t :4; /*!< bit: 4.. 7 Reserved */ 120 } vec; /*!< Structure used for vec access */ 121 uint8_t reg; /*!< Type used for register access */ 122 } DSU_STATUSB_Type; 123 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 124 125 #define DSU_STATUSB_OFFSET 0x0002 /**< \brief (DSU_STATUSB offset) Status B */ 126 #define DSU_STATUSB_RESETVALUE _U(0x00) /**< \brief (DSU_STATUSB reset_value) Status B */ 127 128 #define DSU_STATUSB_PROT_Pos 0 /**< \brief (DSU_STATUSB) Protected */ 129 #define DSU_STATUSB_PROT (_U(0x1) << DSU_STATUSB_PROT_Pos) 130 #define DSU_STATUSB_DBGPRES_Pos 1 /**< \brief (DSU_STATUSB) Debugger Present */ 131 #define DSU_STATUSB_DBGPRES (_U(0x1) << DSU_STATUSB_DBGPRES_Pos) 132 #define DSU_STATUSB_DCCD0_Pos 2 /**< \brief (DSU_STATUSB) Debug Communication Channel 0 Dirty */ 133 #define DSU_STATUSB_DCCD0 (1 << DSU_STATUSB_DCCD0_Pos) 134 #define DSU_STATUSB_DCCD1_Pos 3 /**< \brief (DSU_STATUSB) Debug Communication Channel 1 Dirty */ 135 #define DSU_STATUSB_DCCD1 (1 << DSU_STATUSB_DCCD1_Pos) 136 #define DSU_STATUSB_DCCD_Pos 2 /**< \brief (DSU_STATUSB) Debug Communication Channel x Dirty */ 137 #define DSU_STATUSB_DCCD_Msk (_U(0x3) << DSU_STATUSB_DCCD_Pos) 138 #define DSU_STATUSB_DCCD(value) (DSU_STATUSB_DCCD_Msk & ((value) << DSU_STATUSB_DCCD_Pos)) 139 #define DSU_STATUSB_HPE_Pos 4 /**< \brief (DSU_STATUSB) Hot-Plugging Enable */ 140 #define DSU_STATUSB_HPE (_U(0x1) << DSU_STATUSB_HPE_Pos) 141 #define DSU_STATUSB_MASK _U(0x1F) /**< \brief (DSU_STATUSB) MASK Register */ 142 143 /* -------- DSU_ADDR : (DSU Offset: 0x0004) (R/W 32) Address -------- */ 144 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 145 typedef union { 146 struct { 147 uint32_t AMOD:2; /*!< bit: 0.. 1 Access Mode */ 148 uint32_t ADDR:30; /*!< bit: 2..31 Address */ 149 } bit; /*!< Structure used for bit access */ 150 uint32_t reg; /*!< Type used for register access */ 151 } DSU_ADDR_Type; 152 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 153 154 #define DSU_ADDR_OFFSET 0x0004 /**< \brief (DSU_ADDR offset) Address */ 155 #define DSU_ADDR_RESETVALUE _U(0x00000000) /**< \brief (DSU_ADDR reset_value) Address */ 156 157 #define DSU_ADDR_AMOD_Pos 0 /**< \brief (DSU_ADDR) Access Mode */ 158 #define DSU_ADDR_AMOD_Msk (_U(0x3) << DSU_ADDR_AMOD_Pos) 159 #define DSU_ADDR_AMOD(value) (DSU_ADDR_AMOD_Msk & ((value) << DSU_ADDR_AMOD_Pos)) 160 #define DSU_ADDR_ADDR_Pos 2 /**< \brief (DSU_ADDR) Address */ 161 #define DSU_ADDR_ADDR_Msk (_U(0x3FFFFFFF) << DSU_ADDR_ADDR_Pos) 162 #define DSU_ADDR_ADDR(value) (DSU_ADDR_ADDR_Msk & ((value) << DSU_ADDR_ADDR_Pos)) 163 #define DSU_ADDR_MASK _U(0xFFFFFFFF) /**< \brief (DSU_ADDR) MASK Register */ 164 165 /* -------- DSU_LENGTH : (DSU Offset: 0x0008) (R/W 32) Length -------- */ 166 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 167 typedef union { 168 struct { 169 uint32_t :2; /*!< bit: 0.. 1 Reserved */ 170 uint32_t LENGTH:30; /*!< bit: 2..31 Length */ 171 } bit; /*!< Structure used for bit access */ 172 uint32_t reg; /*!< Type used for register access */ 173 } DSU_LENGTH_Type; 174 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 175 176 #define DSU_LENGTH_OFFSET 0x0008 /**< \brief (DSU_LENGTH offset) Length */ 177 #define DSU_LENGTH_RESETVALUE _U(0x00000000) /**< \brief (DSU_LENGTH reset_value) Length */ 178 179 #define DSU_LENGTH_LENGTH_Pos 2 /**< \brief (DSU_LENGTH) Length */ 180 #define DSU_LENGTH_LENGTH_Msk (_U(0x3FFFFFFF) << DSU_LENGTH_LENGTH_Pos) 181 #define DSU_LENGTH_LENGTH(value) (DSU_LENGTH_LENGTH_Msk & ((value) << DSU_LENGTH_LENGTH_Pos)) 182 #define DSU_LENGTH_MASK _U(0xFFFFFFFC) /**< \brief (DSU_LENGTH) MASK Register */ 183 184 /* -------- DSU_DATA : (DSU Offset: 0x000C) (R/W 32) Data -------- */ 185 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 186 typedef union { 187 struct { 188 uint32_t DATA:32; /*!< bit: 0..31 Data */ 189 } bit; /*!< Structure used for bit access */ 190 uint32_t reg; /*!< Type used for register access */ 191 } DSU_DATA_Type; 192 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 193 194 #define DSU_DATA_OFFSET 0x000C /**< \brief (DSU_DATA offset) Data */ 195 #define DSU_DATA_RESETVALUE _U(0x00000000) /**< \brief (DSU_DATA reset_value) Data */ 196 197 #define DSU_DATA_DATA_Pos 0 /**< \brief (DSU_DATA) Data */ 198 #define DSU_DATA_DATA_Msk (_U(0xFFFFFFFF) << DSU_DATA_DATA_Pos) 199 #define DSU_DATA_DATA(value) (DSU_DATA_DATA_Msk & ((value) << DSU_DATA_DATA_Pos)) 200 #define DSU_DATA_MASK _U(0xFFFFFFFF) /**< \brief (DSU_DATA) MASK Register */ 201 202 /* -------- DSU_DCC : (DSU Offset: 0x0010) (R/W 32) Debug Communication Channel n -------- */ 203 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 204 typedef union { 205 struct { 206 uint32_t DATA:32; /*!< bit: 0..31 Data */ 207 } bit; /*!< Structure used for bit access */ 208 uint32_t reg; /*!< Type used for register access */ 209 } DSU_DCC_Type; 210 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 211 212 #define DSU_DCC_OFFSET 0x0010 /**< \brief (DSU_DCC offset) Debug Communication Channel n */ 213 #define DSU_DCC_RESETVALUE _U(0x00000000) /**< \brief (DSU_DCC reset_value) Debug Communication Channel n */ 214 215 #define DSU_DCC_DATA_Pos 0 /**< \brief (DSU_DCC) Data */ 216 #define DSU_DCC_DATA_Msk (_U(0xFFFFFFFF) << DSU_DCC_DATA_Pos) 217 #define DSU_DCC_DATA(value) (DSU_DCC_DATA_Msk & ((value) << DSU_DCC_DATA_Pos)) 218 #define DSU_DCC_MASK _U(0xFFFFFFFF) /**< \brief (DSU_DCC) MASK Register */ 219 220 /* -------- DSU_DID : (DSU Offset: 0x0018) (R/ 32) Device Identification -------- */ 221 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 222 typedef union { 223 struct { 224 uint32_t DEVSEL:8; /*!< bit: 0.. 7 Device Select */ 225 uint32_t REVISION:4; /*!< bit: 8..11 Revision Number */ 226 uint32_t DIE:4; /*!< bit: 12..15 Die Number */ 227 uint32_t SERIES:6; /*!< bit: 16..21 Series */ 228 uint32_t :1; /*!< bit: 22 Reserved */ 229 uint32_t FAMILY:5; /*!< bit: 23..27 Family */ 230 uint32_t PROCESSOR:4; /*!< bit: 28..31 Processor */ 231 } bit; /*!< Structure used for bit access */ 232 uint32_t reg; /*!< Type used for register access */ 233 } DSU_DID_Type; 234 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 235 236 #define DSU_DID_OFFSET 0x0018 /**< \brief (DSU_DID offset) Device Identification */ 237 238 #define DSU_DID_DEVSEL_Pos 0 /**< \brief (DSU_DID) Device Select */ 239 #define DSU_DID_DEVSEL_Msk (_U(0xFF) << DSU_DID_DEVSEL_Pos) 240 #define DSU_DID_DEVSEL(value) (DSU_DID_DEVSEL_Msk & ((value) << DSU_DID_DEVSEL_Pos)) 241 #define DSU_DID_REVISION_Pos 8 /**< \brief (DSU_DID) Revision Number */ 242 #define DSU_DID_REVISION_Msk (_U(0xF) << DSU_DID_REVISION_Pos) 243 #define DSU_DID_REVISION(value) (DSU_DID_REVISION_Msk & ((value) << DSU_DID_REVISION_Pos)) 244 #define DSU_DID_DIE_Pos 12 /**< \brief (DSU_DID) Die Number */ 245 #define DSU_DID_DIE_Msk (_U(0xF) << DSU_DID_DIE_Pos) 246 #define DSU_DID_DIE(value) (DSU_DID_DIE_Msk & ((value) << DSU_DID_DIE_Pos)) 247 #define DSU_DID_SERIES_Pos 16 /**< \brief (DSU_DID) Series */ 248 #define DSU_DID_SERIES_Msk (_U(0x3F) << DSU_DID_SERIES_Pos) 249 #define DSU_DID_SERIES(value) (DSU_DID_SERIES_Msk & ((value) << DSU_DID_SERIES_Pos)) 250 #define DSU_DID_SERIES_0_Val _U(0x0) /**< \brief (DSU_DID) Cortex-M0+ processor, basic feature set */ 251 #define DSU_DID_SERIES_1_Val _U(0x1) /**< \brief (DSU_DID) Cortex-M0+ processor, USB */ 252 #define DSU_DID_SERIES_0 (DSU_DID_SERIES_0_Val << DSU_DID_SERIES_Pos) 253 #define DSU_DID_SERIES_1 (DSU_DID_SERIES_1_Val << DSU_DID_SERIES_Pos) 254 #define DSU_DID_FAMILY_Pos 23 /**< \brief (DSU_DID) Family */ 255 #define DSU_DID_FAMILY_Msk (_U(0x1F) << DSU_DID_FAMILY_Pos) 256 #define DSU_DID_FAMILY(value) (DSU_DID_FAMILY_Msk & ((value) << DSU_DID_FAMILY_Pos)) 257 #define DSU_DID_FAMILY_0_Val _U(0x0) /**< \brief (DSU_DID) General purpose microcontroller */ 258 #define DSU_DID_FAMILY_1_Val _U(0x1) /**< \brief (DSU_DID) PicoPower */ 259 #define DSU_DID_FAMILY_0 (DSU_DID_FAMILY_0_Val << DSU_DID_FAMILY_Pos) 260 #define DSU_DID_FAMILY_1 (DSU_DID_FAMILY_1_Val << DSU_DID_FAMILY_Pos) 261 #define DSU_DID_PROCESSOR_Pos 28 /**< \brief (DSU_DID) Processor */ 262 #define DSU_DID_PROCESSOR_Msk (_U(0xF) << DSU_DID_PROCESSOR_Pos) 263 #define DSU_DID_PROCESSOR(value) (DSU_DID_PROCESSOR_Msk & ((value) << DSU_DID_PROCESSOR_Pos)) 264 #define DSU_DID_PROCESSOR_0_Val _U(0x0) /**< \brief (DSU_DID) Cortex-M0 */ 265 #define DSU_DID_PROCESSOR_1_Val _U(0x1) /**< \brief (DSU_DID) Cortex-M0+ */ 266 #define DSU_DID_PROCESSOR_2_Val _U(0x2) /**< \brief (DSU_DID) Cortex-M3 */ 267 #define DSU_DID_PROCESSOR_3_Val _U(0x3) /**< \brief (DSU_DID) Cortex-M4 */ 268 #define DSU_DID_PROCESSOR_0 (DSU_DID_PROCESSOR_0_Val << DSU_DID_PROCESSOR_Pos) 269 #define DSU_DID_PROCESSOR_1 (DSU_DID_PROCESSOR_1_Val << DSU_DID_PROCESSOR_Pos) 270 #define DSU_DID_PROCESSOR_2 (DSU_DID_PROCESSOR_2_Val << DSU_DID_PROCESSOR_Pos) 271 #define DSU_DID_PROCESSOR_3 (DSU_DID_PROCESSOR_3_Val << DSU_DID_PROCESSOR_Pos) 272 #define DSU_DID_MASK _U(0xFFBFFFFF) /**< \brief (DSU_DID) MASK Register */ 273 274 /* -------- DSU_DCFG : (DSU Offset: 0x00F0) (R/W 32) Device Configuration -------- */ 275 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 276 typedef union { 277 struct { 278 uint32_t DCFG:32; /*!< bit: 0..31 Device Configuration */ 279 } bit; /*!< Structure used for bit access */ 280 uint32_t reg; /*!< Type used for register access */ 281 } DSU_DCFG_Type; 282 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 283 284 #define DSU_DCFG_OFFSET 0x00F0 /**< \brief (DSU_DCFG offset) Device Configuration */ 285 #define DSU_DCFG_RESETVALUE _U(0x00000000) /**< \brief (DSU_DCFG reset_value) Device Configuration */ 286 287 #define DSU_DCFG_DCFG_Pos 0 /**< \brief (DSU_DCFG) Device Configuration */ 288 #define DSU_DCFG_DCFG_Msk (_U(0xFFFFFFFF) << DSU_DCFG_DCFG_Pos) 289 #define DSU_DCFG_DCFG(value) (DSU_DCFG_DCFG_Msk & ((value) << DSU_DCFG_DCFG_Pos)) 290 #define DSU_DCFG_MASK _U(0xFFFFFFFF) /**< \brief (DSU_DCFG) MASK Register */ 291 292 /* -------- DSU_ENTRY : (DSU Offset: 0x1000) (R/ 32) Coresight ROM Table Entry n -------- */ 293 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 294 typedef union { 295 struct { 296 uint32_t EPRES:1; /*!< bit: 0 Entry Present */ 297 uint32_t FMT:1; /*!< bit: 1 Format */ 298 uint32_t :10; /*!< bit: 2..11 Reserved */ 299 uint32_t ADDOFF:20; /*!< bit: 12..31 Address Offset */ 300 } bit; /*!< Structure used for bit access */ 301 uint32_t reg; /*!< Type used for register access */ 302 } DSU_ENTRY_Type; 303 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 304 305 #define DSU_ENTRY_OFFSET 0x1000 /**< \brief (DSU_ENTRY offset) Coresight ROM Table Entry n */ 306 307 #define DSU_ENTRY_EPRES_Pos 0 /**< \brief (DSU_ENTRY) Entry Present */ 308 #define DSU_ENTRY_EPRES (_U(0x1) << DSU_ENTRY_EPRES_Pos) 309 #define DSU_ENTRY_FMT_Pos 1 /**< \brief (DSU_ENTRY) Format */ 310 #define DSU_ENTRY_FMT (_U(0x1) << DSU_ENTRY_FMT_Pos) 311 #define DSU_ENTRY_ADDOFF_Pos 12 /**< \brief (DSU_ENTRY) Address Offset */ 312 #define DSU_ENTRY_ADDOFF_Msk (_U(0xFFFFF) << DSU_ENTRY_ADDOFF_Pos) 313 #define DSU_ENTRY_ADDOFF(value) (DSU_ENTRY_ADDOFF_Msk & ((value) << DSU_ENTRY_ADDOFF_Pos)) 314 #define DSU_ENTRY_MASK _U(0xFFFFF003) /**< \brief (DSU_ENTRY) MASK Register */ 315 316 /* -------- DSU_END : (DSU Offset: 0x1008) (R/ 32) Coresight ROM Table End -------- */ 317 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 318 typedef union { 319 struct { 320 uint32_t END:32; /*!< bit: 0..31 End Marker */ 321 } bit; /*!< Structure used for bit access */ 322 uint32_t reg; /*!< Type used for register access */ 323 } DSU_END_Type; 324 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 325 326 #define DSU_END_OFFSET 0x1008 /**< \brief (DSU_END offset) Coresight ROM Table End */ 327 #define DSU_END_RESETVALUE _U(0x00000000) /**< \brief (DSU_END reset_value) Coresight ROM Table End */ 328 329 #define DSU_END_END_Pos 0 /**< \brief (DSU_END) End Marker */ 330 #define DSU_END_END_Msk (_U(0xFFFFFFFF) << DSU_END_END_Pos) 331 #define DSU_END_END(value) (DSU_END_END_Msk & ((value) << DSU_END_END_Pos)) 332 #define DSU_END_MASK _U(0xFFFFFFFF) /**< \brief (DSU_END) MASK Register */ 333 334 /* -------- DSU_MEMTYPE : (DSU Offset: 0x1FCC) (R/ 32) Coresight ROM Table Memory Type -------- */ 335 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 336 typedef union { 337 struct { 338 uint32_t SMEMP:1; /*!< bit: 0 System Memory Present */ 339 uint32_t :31; /*!< bit: 1..31 Reserved */ 340 } bit; /*!< Structure used for bit access */ 341 uint32_t reg; /*!< Type used for register access */ 342 } DSU_MEMTYPE_Type; 343 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 344 345 #define DSU_MEMTYPE_OFFSET 0x1FCC /**< \brief (DSU_MEMTYPE offset) Coresight ROM Table Memory Type */ 346 #define DSU_MEMTYPE_RESETVALUE _U(0x00000000) /**< \brief (DSU_MEMTYPE reset_value) Coresight ROM Table Memory Type */ 347 348 #define DSU_MEMTYPE_SMEMP_Pos 0 /**< \brief (DSU_MEMTYPE) System Memory Present */ 349 #define DSU_MEMTYPE_SMEMP (_U(0x1) << DSU_MEMTYPE_SMEMP_Pos) 350 #define DSU_MEMTYPE_MASK _U(0x00000001) /**< \brief (DSU_MEMTYPE) MASK Register */ 351 352 /* -------- DSU_PID4 : (DSU Offset: 0x1FD0) (R/ 32) Peripheral Identification 4 -------- */ 353 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 354 typedef union { 355 struct { 356 uint32_t JEPCC:4; /*!< bit: 0.. 3 JEP-106 Continuation Code */ 357 uint32_t FKBC:4; /*!< bit: 4.. 7 4KB count */ 358 uint32_t :24; /*!< bit: 8..31 Reserved */ 359 } bit; /*!< Structure used for bit access */ 360 uint32_t reg; /*!< Type used for register access */ 361 } DSU_PID4_Type; 362 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 363 364 #define DSU_PID4_OFFSET 0x1FD0 /**< \brief (DSU_PID4 offset) Peripheral Identification 4 */ 365 #define DSU_PID4_RESETVALUE _U(0x00000000) /**< \brief (DSU_PID4 reset_value) Peripheral Identification 4 */ 366 367 #define DSU_PID4_JEPCC_Pos 0 /**< \brief (DSU_PID4) JEP-106 Continuation Code */ 368 #define DSU_PID4_JEPCC_Msk (_U(0xF) << DSU_PID4_JEPCC_Pos) 369 #define DSU_PID4_JEPCC(value) (DSU_PID4_JEPCC_Msk & ((value) << DSU_PID4_JEPCC_Pos)) 370 #define DSU_PID4_FKBC_Pos 4 /**< \brief (DSU_PID4) 4KB count */ 371 #define DSU_PID4_FKBC_Msk (_U(0xF) << DSU_PID4_FKBC_Pos) 372 #define DSU_PID4_FKBC(value) (DSU_PID4_FKBC_Msk & ((value) << DSU_PID4_FKBC_Pos)) 373 #define DSU_PID4_MASK _U(0x000000FF) /**< \brief (DSU_PID4) MASK Register */ 374 375 /* -------- DSU_PID5 : (DSU Offset: 0x1FD4) (R/ 32) Peripheral Identification 5 -------- */ 376 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 377 typedef union { 378 uint32_t reg; /*!< Type used for register access */ 379 } DSU_PID5_Type; 380 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 381 382 #define DSU_PID5_OFFSET 0x1FD4 /**< \brief (DSU_PID5 offset) Peripheral Identification 5 */ 383 #define DSU_PID5_MASK _U(0x00000000) /**< \brief (DSU_PID5) MASK Register */ 384 385 /* -------- DSU_PID6 : (DSU Offset: 0x1FD8) (R/ 32) Peripheral Identification 6 -------- */ 386 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 387 typedef union { 388 uint32_t reg; /*!< Type used for register access */ 389 } DSU_PID6_Type; 390 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 391 392 #define DSU_PID6_OFFSET 0x1FD8 /**< \brief (DSU_PID6 offset) Peripheral Identification 6 */ 393 #define DSU_PID6_MASK _U(0x00000000) /**< \brief (DSU_PID6) MASK Register */ 394 395 /* -------- DSU_PID7 : (DSU Offset: 0x1FDC) (R/ 32) Peripheral Identification 7 -------- */ 396 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 397 typedef union { 398 uint32_t reg; /*!< Type used for register access */ 399 } DSU_PID7_Type; 400 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 401 402 #define DSU_PID7_OFFSET 0x1FDC /**< \brief (DSU_PID7 offset) Peripheral Identification 7 */ 403 #define DSU_PID7_MASK _U(0x00000000) /**< \brief (DSU_PID7) MASK Register */ 404 405 /* -------- DSU_PID0 : (DSU Offset: 0x1FE0) (R/ 32) Peripheral Identification 0 -------- */ 406 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 407 typedef union { 408 struct { 409 uint32_t PARTNBL:8; /*!< bit: 0.. 7 Part Number Low */ 410 uint32_t :24; /*!< bit: 8..31 Reserved */ 411 } bit; /*!< Structure used for bit access */ 412 uint32_t reg; /*!< Type used for register access */ 413 } DSU_PID0_Type; 414 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 415 416 #define DSU_PID0_OFFSET 0x1FE0 /**< \brief (DSU_PID0 offset) Peripheral Identification 0 */ 417 #define DSU_PID0_RESETVALUE _U(0x00000000) /**< \brief (DSU_PID0 reset_value) Peripheral Identification 0 */ 418 419 #define DSU_PID0_PARTNBL_Pos 0 /**< \brief (DSU_PID0) Part Number Low */ 420 #define DSU_PID0_PARTNBL_Msk (_U(0xFF) << DSU_PID0_PARTNBL_Pos) 421 #define DSU_PID0_PARTNBL(value) (DSU_PID0_PARTNBL_Msk & ((value) << DSU_PID0_PARTNBL_Pos)) 422 #define DSU_PID0_MASK _U(0x000000FF) /**< \brief (DSU_PID0) MASK Register */ 423 424 /* -------- DSU_PID1 : (DSU Offset: 0x1FE4) (R/ 32) Peripheral Identification 1 -------- */ 425 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 426 typedef union { 427 struct { 428 uint32_t PARTNBH:4; /*!< bit: 0.. 3 Part Number High */ 429 uint32_t JEPIDCL:4; /*!< bit: 4.. 7 Low part of the JEP-106 Identity Code */ 430 uint32_t :24; /*!< bit: 8..31 Reserved */ 431 } bit; /*!< Structure used for bit access */ 432 uint32_t reg; /*!< Type used for register access */ 433 } DSU_PID1_Type; 434 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 435 436 #define DSU_PID1_OFFSET 0x1FE4 /**< \brief (DSU_PID1 offset) Peripheral Identification 1 */ 437 #define DSU_PID1_RESETVALUE _U(0x000000FC) /**< \brief (DSU_PID1 reset_value) Peripheral Identification 1 */ 438 439 #define DSU_PID1_PARTNBH_Pos 0 /**< \brief (DSU_PID1) Part Number High */ 440 #define DSU_PID1_PARTNBH_Msk (_U(0xF) << DSU_PID1_PARTNBH_Pos) 441 #define DSU_PID1_PARTNBH(value) (DSU_PID1_PARTNBH_Msk & ((value) << DSU_PID1_PARTNBH_Pos)) 442 #define DSU_PID1_JEPIDCL_Pos 4 /**< \brief (DSU_PID1) Low part of the JEP-106 Identity Code */ 443 #define DSU_PID1_JEPIDCL_Msk (_U(0xF) << DSU_PID1_JEPIDCL_Pos) 444 #define DSU_PID1_JEPIDCL(value) (DSU_PID1_JEPIDCL_Msk & ((value) << DSU_PID1_JEPIDCL_Pos)) 445 #define DSU_PID1_MASK _U(0x000000FF) /**< \brief (DSU_PID1) MASK Register */ 446 447 /* -------- DSU_PID2 : (DSU Offset: 0x1FE8) (R/ 32) Peripheral Identification 2 -------- */ 448 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 449 typedef union { 450 struct { 451 uint32_t JEPIDCH:3; /*!< bit: 0.. 2 JEP-106 Identity Code High */ 452 uint32_t JEPU:1; /*!< bit: 3 JEP-106 Identity Code is used */ 453 uint32_t REVISION:4; /*!< bit: 4.. 7 Revision Number */ 454 uint32_t :24; /*!< bit: 8..31 Reserved */ 455 } bit; /*!< Structure used for bit access */ 456 uint32_t reg; /*!< Type used for register access */ 457 } DSU_PID2_Type; 458 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 459 460 #define DSU_PID2_OFFSET 0x1FE8 /**< \brief (DSU_PID2 offset) Peripheral Identification 2 */ 461 #define DSU_PID2_RESETVALUE _U(0x00000009) /**< \brief (DSU_PID2 reset_value) Peripheral Identification 2 */ 462 463 #define DSU_PID2_JEPIDCH_Pos 0 /**< \brief (DSU_PID2) JEP-106 Identity Code High */ 464 #define DSU_PID2_JEPIDCH_Msk (_U(0x7) << DSU_PID2_JEPIDCH_Pos) 465 #define DSU_PID2_JEPIDCH(value) (DSU_PID2_JEPIDCH_Msk & ((value) << DSU_PID2_JEPIDCH_Pos)) 466 #define DSU_PID2_JEPU_Pos 3 /**< \brief (DSU_PID2) JEP-106 Identity Code is used */ 467 #define DSU_PID2_JEPU (_U(0x1) << DSU_PID2_JEPU_Pos) 468 #define DSU_PID2_REVISION_Pos 4 /**< \brief (DSU_PID2) Revision Number */ 469 #define DSU_PID2_REVISION_Msk (_U(0xF) << DSU_PID2_REVISION_Pos) 470 #define DSU_PID2_REVISION(value) (DSU_PID2_REVISION_Msk & ((value) << DSU_PID2_REVISION_Pos)) 471 #define DSU_PID2_MASK _U(0x000000FF) /**< \brief (DSU_PID2) MASK Register */ 472 473 /* -------- DSU_PID3 : (DSU Offset: 0x1FEC) (R/ 32) Peripheral Identification 3 -------- */ 474 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 475 typedef union { 476 struct { 477 uint32_t CUSMOD:4; /*!< bit: 0.. 3 ARM CUSMOD */ 478 uint32_t REVAND:4; /*!< bit: 4.. 7 Revision Number */ 479 uint32_t :24; /*!< bit: 8..31 Reserved */ 480 } bit; /*!< Structure used for bit access */ 481 uint32_t reg; /*!< Type used for register access */ 482 } DSU_PID3_Type; 483 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 484 485 #define DSU_PID3_OFFSET 0x1FEC /**< \brief (DSU_PID3 offset) Peripheral Identification 3 */ 486 #define DSU_PID3_RESETVALUE _U(0x00000000) /**< \brief (DSU_PID3 reset_value) Peripheral Identification 3 */ 487 488 #define DSU_PID3_CUSMOD_Pos 0 /**< \brief (DSU_PID3) ARM CUSMOD */ 489 #define DSU_PID3_CUSMOD_Msk (_U(0xF) << DSU_PID3_CUSMOD_Pos) 490 #define DSU_PID3_CUSMOD(value) (DSU_PID3_CUSMOD_Msk & ((value) << DSU_PID3_CUSMOD_Pos)) 491 #define DSU_PID3_REVAND_Pos 4 /**< \brief (DSU_PID3) Revision Number */ 492 #define DSU_PID3_REVAND_Msk (_U(0xF) << DSU_PID3_REVAND_Pos) 493 #define DSU_PID3_REVAND(value) (DSU_PID3_REVAND_Msk & ((value) << DSU_PID3_REVAND_Pos)) 494 #define DSU_PID3_MASK _U(0x000000FF) /**< \brief (DSU_PID3) MASK Register */ 495 496 /* -------- DSU_CID0 : (DSU Offset: 0x1FF0) (R/ 32) Component Identification 0 -------- */ 497 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 498 typedef union { 499 struct { 500 uint32_t PREAMBLEB0:8; /*!< bit: 0.. 7 Preamble Byte 0 */ 501 uint32_t :24; /*!< bit: 8..31 Reserved */ 502 } bit; /*!< Structure used for bit access */ 503 uint32_t reg; /*!< Type used for register access */ 504 } DSU_CID0_Type; 505 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 506 507 #define DSU_CID0_OFFSET 0x1FF0 /**< \brief (DSU_CID0 offset) Component Identification 0 */ 508 #define DSU_CID0_RESETVALUE _U(0x00000000) /**< \brief (DSU_CID0 reset_value) Component Identification 0 */ 509 510 #define DSU_CID0_PREAMBLEB0_Pos 0 /**< \brief (DSU_CID0) Preamble Byte 0 */ 511 #define DSU_CID0_PREAMBLEB0_Msk (_U(0xFF) << DSU_CID0_PREAMBLEB0_Pos) 512 #define DSU_CID0_PREAMBLEB0(value) (DSU_CID0_PREAMBLEB0_Msk & ((value) << DSU_CID0_PREAMBLEB0_Pos)) 513 #define DSU_CID0_MASK _U(0x000000FF) /**< \brief (DSU_CID0) MASK Register */ 514 515 /* -------- DSU_CID1 : (DSU Offset: 0x1FF4) (R/ 32) Component Identification 1 -------- */ 516 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 517 typedef union { 518 struct { 519 uint32_t PREAMBLE:4; /*!< bit: 0.. 3 Preamble */ 520 uint32_t CCLASS:4; /*!< bit: 4.. 7 Component Class */ 521 uint32_t :24; /*!< bit: 8..31 Reserved */ 522 } bit; /*!< Structure used for bit access */ 523 uint32_t reg; /*!< Type used for register access */ 524 } DSU_CID1_Type; 525 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 526 527 #define DSU_CID1_OFFSET 0x1FF4 /**< \brief (DSU_CID1 offset) Component Identification 1 */ 528 #define DSU_CID1_RESETVALUE _U(0x00000000) /**< \brief (DSU_CID1 reset_value) Component Identification 1 */ 529 530 #define DSU_CID1_PREAMBLE_Pos 0 /**< \brief (DSU_CID1) Preamble */ 531 #define DSU_CID1_PREAMBLE_Msk (_U(0xF) << DSU_CID1_PREAMBLE_Pos) 532 #define DSU_CID1_PREAMBLE(value) (DSU_CID1_PREAMBLE_Msk & ((value) << DSU_CID1_PREAMBLE_Pos)) 533 #define DSU_CID1_CCLASS_Pos 4 /**< \brief (DSU_CID1) Component Class */ 534 #define DSU_CID1_CCLASS_Msk (_U(0xF) << DSU_CID1_CCLASS_Pos) 535 #define DSU_CID1_CCLASS(value) (DSU_CID1_CCLASS_Msk & ((value) << DSU_CID1_CCLASS_Pos)) 536 #define DSU_CID1_MASK _U(0x000000FF) /**< \brief (DSU_CID1) MASK Register */ 537 538 /* -------- DSU_CID2 : (DSU Offset: 0x1FF8) (R/ 32) Component Identification 2 -------- */ 539 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 540 typedef union { 541 struct { 542 uint32_t PREAMBLEB2:8; /*!< bit: 0.. 7 Preamble Byte 2 */ 543 uint32_t :24; /*!< bit: 8..31 Reserved */ 544 } bit; /*!< Structure used for bit access */ 545 uint32_t reg; /*!< Type used for register access */ 546 } DSU_CID2_Type; 547 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 548 549 #define DSU_CID2_OFFSET 0x1FF8 /**< \brief (DSU_CID2 offset) Component Identification 2 */ 550 #define DSU_CID2_RESETVALUE _U(0x00000000) /**< \brief (DSU_CID2 reset_value) Component Identification 2 */ 551 552 #define DSU_CID2_PREAMBLEB2_Pos 0 /**< \brief (DSU_CID2) Preamble Byte 2 */ 553 #define DSU_CID2_PREAMBLEB2_Msk (_U(0xFF) << DSU_CID2_PREAMBLEB2_Pos) 554 #define DSU_CID2_PREAMBLEB2(value) (DSU_CID2_PREAMBLEB2_Msk & ((value) << DSU_CID2_PREAMBLEB2_Pos)) 555 #define DSU_CID2_MASK _U(0x000000FF) /**< \brief (DSU_CID2) MASK Register */ 556 557 /* -------- DSU_CID3 : (DSU Offset: 0x1FFC) (R/ 32) Component Identification 3 -------- */ 558 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 559 typedef union { 560 struct { 561 uint32_t PREAMBLEB3:8; /*!< bit: 0.. 7 Preamble Byte 3 */ 562 uint32_t :24; /*!< bit: 8..31 Reserved */ 563 } bit; /*!< Structure used for bit access */ 564 uint32_t reg; /*!< Type used for register access */ 565 } DSU_CID3_Type; 566 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 567 568 #define DSU_CID3_OFFSET 0x1FFC /**< \brief (DSU_CID3 offset) Component Identification 3 */ 569 #define DSU_CID3_RESETVALUE _U(0x00000000) /**< \brief (DSU_CID3 reset_value) Component Identification 3 */ 570 571 #define DSU_CID3_PREAMBLEB3_Pos 0 /**< \brief (DSU_CID3) Preamble Byte 3 */ 572 #define DSU_CID3_PREAMBLEB3_Msk (_U(0xFF) << DSU_CID3_PREAMBLEB3_Pos) 573 #define DSU_CID3_PREAMBLEB3(value) (DSU_CID3_PREAMBLEB3_Msk & ((value) << DSU_CID3_PREAMBLEB3_Pos)) 574 #define DSU_CID3_MASK _U(0x000000FF) /**< \brief (DSU_CID3) MASK Register */ 575 576 /** \brief DSU hardware registers */ 577 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 578 typedef struct { 579 __O DSU_CTRL_Type CTRL; /**< \brief Offset: 0x0000 ( /W 8) Control */ 580 __IO DSU_STATUSA_Type STATUSA; /**< \brief Offset: 0x0001 (R/W 8) Status A */ 581 __I DSU_STATUSB_Type STATUSB; /**< \brief Offset: 0x0002 (R/ 8) Status B */ 582 RoReg8 Reserved1[0x1]; 583 __IO DSU_ADDR_Type ADDR; /**< \brief Offset: 0x0004 (R/W 32) Address */ 584 __IO DSU_LENGTH_Type LENGTH; /**< \brief Offset: 0x0008 (R/W 32) Length */ 585 __IO DSU_DATA_Type DATA; /**< \brief Offset: 0x000C (R/W 32) Data */ 586 __IO DSU_DCC_Type DCC[2]; /**< \brief Offset: 0x0010 (R/W 32) Debug Communication Channel n */ 587 __I DSU_DID_Type DID; /**< \brief Offset: 0x0018 (R/ 32) Device Identification */ 588 RoReg8 Reserved2[0xD4]; 589 __IO DSU_DCFG_Type DCFG[2]; /**< \brief Offset: 0x00F0 (R/W 32) Device Configuration */ 590 RoReg8 Reserved3[0xF08]; 591 __I DSU_ENTRY_Type ENTRY[2]; /**< \brief Offset: 0x1000 (R/ 32) Coresight ROM Table Entry n */ 592 __I DSU_END_Type END; /**< \brief Offset: 0x1008 (R/ 32) Coresight ROM Table End */ 593 RoReg8 Reserved4[0xFC0]; 594 __I DSU_MEMTYPE_Type MEMTYPE; /**< \brief Offset: 0x1FCC (R/ 32) Coresight ROM Table Memory Type */ 595 __I DSU_PID4_Type PID4; /**< \brief Offset: 0x1FD0 (R/ 32) Peripheral Identification 4 */ 596 __I DSU_PID5_Type PID5; /**< \brief Offset: 0x1FD4 (R/ 32) Peripheral Identification 5 */ 597 __I DSU_PID6_Type PID6; /**< \brief Offset: 0x1FD8 (R/ 32) Peripheral Identification 6 */ 598 __I DSU_PID7_Type PID7; /**< \brief Offset: 0x1FDC (R/ 32) Peripheral Identification 7 */ 599 __I DSU_PID0_Type PID0; /**< \brief Offset: 0x1FE0 (R/ 32) Peripheral Identification 0 */ 600 __I DSU_PID1_Type PID1; /**< \brief Offset: 0x1FE4 (R/ 32) Peripheral Identification 1 */ 601 __I DSU_PID2_Type PID2; /**< \brief Offset: 0x1FE8 (R/ 32) Peripheral Identification 2 */ 602 __I DSU_PID3_Type PID3; /**< \brief Offset: 0x1FEC (R/ 32) Peripheral Identification 3 */ 603 __I DSU_CID0_Type CID0; /**< \brief Offset: 0x1FF0 (R/ 32) Component Identification 0 */ 604 __I DSU_CID1_Type CID1; /**< \brief Offset: 0x1FF4 (R/ 32) Component Identification 1 */ 605 __I DSU_CID2_Type CID2; /**< \brief Offset: 0x1FF8 (R/ 32) Component Identification 2 */ 606 __I DSU_CID3_Type CID3; /**< \brief Offset: 0x1FFC (R/ 32) Component Identification 3 */ 607 } Dsu; 608 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 609 610 /*@}*/ 611 612 #endif /* _SAML21_DSU_COMPONENT_ */ 613
