1 /*
2 * Copyright (c) 2019-2022 Arm Limited
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17 #include "Driver_PPC.h"
18
19 #include "Driver_Common.h"
20 #include "tfm_hal_device_header.h"
21 #include "cmsis_driver_config.h"
22 #include "RTE_Device.h"
23 #include "ppc_rse_drv.h"
24
25 /* Driver version */
26 #define ARM_PPC_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1,0)
27
28 /* Driver Version */
29 static const ARM_DRIVER_VERSION DriverVersion = {
30 ARM_PPC_API_VERSION,
31 ARM_PPC_DRV_VERSION
32 };
33
PPC_RSE_GetVersion(void)34 ARM_DRIVER_VERSION PPC_RSE_GetVersion(void)
35 {
36 return DriverVersion;
37 }
38
39 typedef struct _RSE_PPC_Resources {
40 struct ppc_rse_dev_t* dev; /* PPC device structure */
41 } RSE_PPC_Resources;
42
43 #if (RTE_PPC_RSE_MAIN0)
44
45 static RSE_PPC_Resources MAIN0_PPC_DEV = {
46 .dev = &PPC_RSE_MAIN0_DEV,
47 };
48
49 /* MAIN0 PPC Driver wrapper functions */
PPC_RSE_MAIN0_Initialize(void)50 static int32_t PPC_RSE_MAIN0_Initialize(void)
51 {
52 ppc_rse_init(MAIN0_PPC_DEV.dev);
53
54 return ARM_DRIVER_OK;
55 }
56
PPC_RSE_MAIN0_Uninitialize(void)57 static int32_t PPC_RSE_MAIN0_Uninitialize(void)
58 {
59 /* Nothing to do */
60 return ARM_DRIVER_OK;
61 }
62
63 static int32_t
PPC_RSE_MAIN0_ConfigPrivilege(uint32_t periph,PPC_RSE_SecAttr sec_attr,PPC_RSE_PrivAttr priv_attr)64 PPC_RSE_MAIN0_ConfigPrivilege(uint32_t periph,
65 PPC_RSE_SecAttr sec_attr,
66 PPC_RSE_PrivAttr priv_attr)
67 {
68 enum ppc_rse_error_t ret;
69
70 ret = ppc_rse_config_privilege(MAIN0_PPC_DEV.dev, periph,
71 (enum ppc_rse_sec_attr_t)sec_attr,
72 (enum ppc_rse_priv_attr_t)priv_attr);
73
74 if( ret != PPC_RSE_ERR_NONE) {
75 return ARM_DRIVER_ERROR;
76 }
77
78 return ARM_DRIVER_OK;
79 }
80
PPC_RSE_MAIN0_IsPeriphPrivOnly(uint32_t periph)81 static bool PPC_RSE_MAIN0_IsPeriphPrivOnly(uint32_t periph)
82 {
83 return ppc_rse_is_periph_priv_only(MAIN0_PPC_DEV.dev, periph);
84 }
85
86 /* Secure only functions */
87 #if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U))
88
89 static int32_t
PPC_RSE_MAIN0_ConfigSecurity(uint32_t periph,PPC_RSE_SecAttr sec_attr)90 PPC_RSE_MAIN0_ConfigSecurity(uint32_t periph, PPC_RSE_SecAttr sec_attr)
91 {
92 enum ppc_rse_error_t ret;
93
94 ret = ppc_rse_config_security(MAIN0_PPC_DEV.dev, periph,
95 (enum ppc_rse_sec_attr_t)sec_attr);
96
97 if( ret != PPC_RSE_ERR_NONE) {
98 return ARM_DRIVER_ERROR;
99 }
100
101 return ARM_DRIVER_OK;
102 }
103
PPC_RSE_MAIN0_IsPeriphSecure(uint32_t periph)104 static bool PPC_RSE_MAIN0_IsPeriphSecure(uint32_t periph)
105 {
106 return ppc_rse_is_periph_secure(MAIN0_PPC_DEV.dev, periph);
107 }
108
PPC_RSE_MAIN0_EnableInterrupt(void)109 static int32_t PPC_RSE_MAIN0_EnableInterrupt(void)
110 {
111 enum ppc_rse_error_t ret;
112
113 ret = ppc_rse_irq_enable(MAIN0_PPC_DEV.dev);
114
115 if( ret != PPC_RSE_ERR_NONE) {
116 return ARM_DRIVER_ERROR;
117 }
118
119 return ARM_DRIVER_OK;
120 }
121
PPC_RSE_MAIN0_DisableInterrupt(void)122 static void PPC_RSE_MAIN0_DisableInterrupt(void)
123 {
124 ppc_rse_irq_disable(MAIN0_PPC_DEV.dev);
125 }
126
PPC_RSE_MAIN0_ClearInterrupt(void)127 static void PPC_RSE_MAIN0_ClearInterrupt(void)
128 {
129 ppc_rse_clear_irq(MAIN0_PPC_DEV.dev);
130 }
131
PPC_RSE_MAIN0_InterruptState(void)132 static bool PPC_RSE_MAIN0_InterruptState(void)
133 {
134 return ppc_rse_irq_state(MAIN0_PPC_DEV.dev);
135 }
136
137 #endif /* (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)) */
138
139 /* PPC RSE MAIN0 Driver CMSIS access structure */
140 DRIVER_PPC_RSE Driver_PPC_RSE_MAIN0 = {
141 .GetVersion = PPC_RSE_GetVersion,
142 .Initialize = PPC_RSE_MAIN0_Initialize,
143 .Uninitialize = PPC_RSE_MAIN0_Uninitialize,
144 .ConfigPrivilege = PPC_RSE_MAIN0_ConfigPrivilege,
145 .IsPeriphPrivOnly = PPC_RSE_MAIN0_IsPeriphPrivOnly,
146 #if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U))
147 .ConfigSecurity = PPC_RSE_MAIN0_ConfigSecurity,
148 .IsPeriphSecure = PPC_RSE_MAIN0_IsPeriphSecure,
149 .EnableInterrupt = PPC_RSE_MAIN0_EnableInterrupt,
150 .DisableInterrupt = PPC_RSE_MAIN0_DisableInterrupt,
151 .ClearInterrupt = PPC_RSE_MAIN0_ClearInterrupt,
152 .InterruptState = PPC_RSE_MAIN0_InterruptState
153 #endif /* (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)) */
154 };
155 #endif /* RTE_PPC_RSE_MAIN0 */
156
157 #if (RTE_PPC_RSE_MAIN_EXP0)
158
159 static RSE_PPC_Resources MAIN_EXP0_PPC_DEV = {
160 .dev = &PPC_RSE_MAIN_EXP0_DEV,
161 };
162
163 /* MAIN PPCEXP0 Driver wrapper functions */
PPC_RSE_MAIN_EXP0_Initialize(void)164 static int32_t PPC_RSE_MAIN_EXP0_Initialize(void)
165 {
166 ppc_rse_init(MAIN_EXP0_PPC_DEV.dev);
167
168 return ARM_DRIVER_OK;
169 }
170
PPC_RSE_MAIN_EXP0_Uninitialize(void)171 static int32_t PPC_RSE_MAIN_EXP0_Uninitialize(void)
172 {
173 /* Nothing to do */
174 return ARM_DRIVER_OK;
175 }
176
177 static int32_t
PPC_RSE_MAIN_EXP0_ConfigPrivilege(uint32_t periph,PPC_RSE_SecAttr sec_attr,PPC_RSE_PrivAttr priv_attr)178 PPC_RSE_MAIN_EXP0_ConfigPrivilege(uint32_t periph,
179 PPC_RSE_SecAttr sec_attr,
180 PPC_RSE_PrivAttr priv_attr)
181 {
182 enum ppc_rse_error_t ret;
183
184 ret = ppc_rse_config_privilege(MAIN_EXP0_PPC_DEV.dev, periph,
185 (enum ppc_rse_sec_attr_t)sec_attr,
186 (enum ppc_rse_priv_attr_t)priv_attr);
187
188 if( ret != PPC_RSE_ERR_NONE) {
189 return ARM_DRIVER_ERROR;
190 }
191
192 return ARM_DRIVER_OK;
193 }
194
PPC_RSE_MAIN_EXP0_IsPeriphPrivOnly(uint32_t periph)195 static bool PPC_RSE_MAIN_EXP0_IsPeriphPrivOnly(uint32_t periph)
196 {
197 return ppc_rse_is_periph_priv_only(MAIN_EXP0_PPC_DEV.dev, periph);
198 }
199
200 /* Secure only functions */
201 #if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U))
202
203 static int32_t
PPC_RSE_MAIN_EXP0_ConfigSecurity(uint32_t periph,PPC_RSE_SecAttr sec_attr)204 PPC_RSE_MAIN_EXP0_ConfigSecurity(uint32_t periph,
205 PPC_RSE_SecAttr sec_attr)
206 {
207 enum ppc_rse_error_t ret;
208
209 ret = ppc_rse_config_security(MAIN_EXP0_PPC_DEV.dev, periph,
210 (enum ppc_rse_sec_attr_t)sec_attr);
211
212 if( ret != PPC_RSE_ERR_NONE) {
213 return ARM_DRIVER_ERROR;
214 }
215
216 return ARM_DRIVER_OK;
217 }
218
PPC_RSE_MAIN_EXP0_IsPeriphSecure(uint32_t periph)219 static bool PPC_RSE_MAIN_EXP0_IsPeriphSecure(uint32_t periph)
220 {
221 return ppc_rse_is_periph_secure(MAIN_EXP0_PPC_DEV.dev, periph);
222 }
223
PPC_RSE_MAIN_EXP0_EnableInterrupt(void)224 static int32_t PPC_RSE_MAIN_EXP0_EnableInterrupt(void)
225 {
226 enum ppc_rse_error_t ret;
227
228 ret = ppc_rse_irq_enable(MAIN_EXP0_PPC_DEV.dev);
229
230 if( ret != PPC_RSE_ERR_NONE) {
231 return ARM_DRIVER_ERROR;
232 }
233
234 return ARM_DRIVER_OK;
235 }
236
PPC_RSE_MAIN_EXP0_DisableInterrupt(void)237 static void PPC_RSE_MAIN_EXP0_DisableInterrupt(void)
238 {
239 ppc_rse_irq_disable(MAIN_EXP0_PPC_DEV.dev);
240 }
241
PPC_RSE_MAIN_EXP0_ClearInterrupt(void)242 static void PPC_RSE_MAIN_EXP0_ClearInterrupt(void)
243 {
244 ppc_rse_clear_irq(MAIN_EXP0_PPC_DEV.dev);
245 }
246
PPC_RSE_MAIN_EXP0_InterruptState(void)247 static bool PPC_RSE_MAIN_EXP0_InterruptState(void)
248 {
249 return ppc_rse_irq_state(MAIN_EXP0_PPC_DEV.dev);
250 }
251
252 #endif /* (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)) */
253
254 /* PPC RSE MAIN EXP0 Driver CMSIS access structure */
255 DRIVER_PPC_RSE Driver_PPC_RSE_MAIN_EXP0 = {
256 .GetVersion = PPC_RSE_GetVersion,
257 .Initialize = PPC_RSE_MAIN_EXP0_Initialize,
258 .Uninitialize = PPC_RSE_MAIN_EXP0_Uninitialize,
259 .ConfigPrivilege = PPC_RSE_MAIN_EXP0_ConfigPrivilege,
260 .IsPeriphPrivOnly = PPC_RSE_MAIN_EXP0_IsPeriphPrivOnly,
261 #if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U))
262 .ConfigSecurity = PPC_RSE_MAIN_EXP0_ConfigSecurity,
263 .IsPeriphSecure = PPC_RSE_MAIN_EXP0_IsPeriphSecure,
264 .EnableInterrupt = PPC_RSE_MAIN_EXP0_EnableInterrupt,
265 .DisableInterrupt = PPC_RSE_MAIN_EXP0_DisableInterrupt,
266 .ClearInterrupt = PPC_RSE_MAIN_EXP0_ClearInterrupt,
267 .InterruptState = PPC_RSE_MAIN_EXP0_InterruptState
268 #endif /* (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)) */
269 };
270 #endif /* RTE_PPC_RSE_MAIN_EXP0 */
271
272 #if (RTE_PPC_RSE_MAIN_EXP1)
273
274 static RSE_PPC_Resources MAIN_EXP1_PPC_DEV = {
275 .dev = &PPC_RSE_MAIN_EXP1_DEV,
276 };
277
278 /* MAIN PPCEXP1 Driver wrapper functions */
PPC_RSE_MAIN_EXP1_Initialize(void)279 static int32_t PPC_RSE_MAIN_EXP1_Initialize(void)
280 {
281 ppc_rse_init(MAIN_EXP1_PPC_DEV.dev);
282
283 return ARM_DRIVER_OK;
284 }
285
PPC_RSE_MAIN_EXP1_Uninitialize(void)286 static int32_t PPC_RSE_MAIN_EXP1_Uninitialize(void)
287 {
288 /* Nothing to do */
289 return ARM_DRIVER_OK;
290 }
291
292 static int32_t
PPC_RSE_MAIN_EXP1_ConfigPrivilege(uint32_t periph,PPC_RSE_SecAttr sec_attr,PPC_RSE_PrivAttr priv_attr)293 PPC_RSE_MAIN_EXP1_ConfigPrivilege(uint32_t periph,
294 PPC_RSE_SecAttr sec_attr,
295 PPC_RSE_PrivAttr priv_attr)
296 {
297 enum ppc_rse_error_t ret;
298
299 ret = ppc_rse_config_privilege(MAIN_EXP1_PPC_DEV.dev, periph,
300 (enum ppc_rse_sec_attr_t)sec_attr,
301 (enum ppc_rse_priv_attr_t)priv_attr);
302
303 if( ret != PPC_RSE_ERR_NONE) {
304 return ARM_DRIVER_ERROR;
305 }
306
307 return ARM_DRIVER_OK;
308 }
309
PPC_RSE_MAIN_EXP1_IsPeriphPrivOnly(uint32_t periph)310 static bool PPC_RSE_MAIN_EXP1_IsPeriphPrivOnly(uint32_t periph)
311 {
312 return ppc_rse_is_periph_priv_only(MAIN_EXP1_PPC_DEV.dev, periph);
313 }
314
315 /* Secure only functions */
316 #if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U))
317
318 static int32_t
PPC_RSE_MAIN_EXP1_ConfigSecurity(uint32_t periph,PPC_RSE_SecAttr sec_attr)319 PPC_RSE_MAIN_EXP1_ConfigSecurity(uint32_t periph,
320 PPC_RSE_SecAttr sec_attr)
321 {
322 enum ppc_rse_error_t ret;
323
324 ret = ppc_rse_config_security(MAIN_EXP1_PPC_DEV.dev, periph,
325 (enum ppc_rse_sec_attr_t)sec_attr);
326
327 if( ret != PPC_RSE_ERR_NONE) {
328 return ARM_DRIVER_ERROR;
329 }
330
331 return ARM_DRIVER_OK;
332 }
333
PPC_RSE_MAIN_EXP1_IsPeriphSecure(uint32_t periph)334 static bool PPC_RSE_MAIN_EXP1_IsPeriphSecure(uint32_t periph)
335 {
336 return ppc_rse_is_periph_secure(MAIN_EXP1_PPC_DEV.dev, periph);
337 }
338
PPC_RSE_MAIN_EXP1_EnableInterrupt(void)339 static int32_t PPC_RSE_MAIN_EXP1_EnableInterrupt(void)
340 {
341 enum ppc_rse_error_t ret;
342
343 ret = ppc_rse_irq_enable(MAIN_EXP1_PPC_DEV.dev);
344
345 if( ret != PPC_RSE_ERR_NONE) {
346 return ARM_DRIVER_ERROR;
347 }
348
349 return ARM_DRIVER_OK;
350 }
351
PPC_RSE_MAIN_EXP1_DisableInterrupt(void)352 static void PPC_RSE_MAIN_EXP1_DisableInterrupt(void)
353 {
354 ppc_rse_irq_disable(MAIN_EXP1_PPC_DEV.dev);
355 }
356
PPC_RSE_MAIN_EXP1_ClearInterrupt(void)357 static void PPC_RSE_MAIN_EXP1_ClearInterrupt(void)
358 {
359 ppc_rse_clear_irq(MAIN_EXP1_PPC_DEV.dev);
360 }
361
PPC_RSE_MAIN_EXP1_InterruptState(void)362 static bool PPC_RSE_MAIN_EXP1_InterruptState(void)
363 {
364 return ppc_rse_irq_state(MAIN_EXP1_PPC_DEV.dev);
365 }
366
367 #endif /* (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)) */
368
369 /* PPC RSE MAIN EXP1 Driver CMSIS access structure */
370 DRIVER_PPC_RSE Driver_PPC_RSE_MAIN_EXP1 = {
371 .GetVersion = PPC_RSE_GetVersion,
372 .Initialize = PPC_RSE_MAIN_EXP1_Initialize,
373 .Uninitialize = PPC_RSE_MAIN_EXP1_Uninitialize,
374 .ConfigPrivilege = PPC_RSE_MAIN_EXP1_ConfigPrivilege,
375 .IsPeriphPrivOnly = PPC_RSE_MAIN_EXP1_IsPeriphPrivOnly,
376 #if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U))
377 .ConfigSecurity = PPC_RSE_MAIN_EXP1_ConfigSecurity,
378 .IsPeriphSecure = PPC_RSE_MAIN_EXP1_IsPeriphSecure,
379 .EnableInterrupt = PPC_RSE_MAIN_EXP1_EnableInterrupt,
380 .DisableInterrupt = PPC_RSE_MAIN_EXP1_DisableInterrupt,
381 .ClearInterrupt = PPC_RSE_MAIN_EXP1_ClearInterrupt,
382 .InterruptState = PPC_RSE_MAIN_EXP1_InterruptState
383 #endif /* (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)) */
384 };
385 #endif /* RTE_PPC_RSE_MAIN_EXP1 */
386
387 #if (RTE_PPC_RSE_MAIN_EXP2)
388
389 static RSE_PPC_Resources MAIN_EXP2_PPC_DEV = {
390 .dev = &PPC_RSE_MAIN_EXP2_DEV,
391 };
392
393 /* MAIN PPCEXP2 Driver wrapper functions */
PPC_RSE_MAIN_EXP2_Initialize(void)394 static int32_t PPC_RSE_MAIN_EXP2_Initialize(void)
395 {
396 ppc_rse_init(MAIN_EXP2_PPC_DEV.dev);
397
398 return ARM_DRIVER_OK;
399 }
400
PPC_RSE_MAIN_EXP2_Uninitialize(void)401 static int32_t PPC_RSE_MAIN_EXP2_Uninitialize(void)
402 {
403 /* Nothing to do */
404 return ARM_DRIVER_OK;
405 }
406
407 static int32_t
PPC_RSE_MAIN_EXP2_ConfigPrivilege(uint32_t periph,PPC_RSE_SecAttr sec_attr,PPC_RSE_PrivAttr priv_attr)408 PPC_RSE_MAIN_EXP2_ConfigPrivilege(uint32_t periph,
409 PPC_RSE_SecAttr sec_attr,
410 PPC_RSE_PrivAttr priv_attr)
411 {
412 enum ppc_rse_error_t ret;
413
414 ret = ppc_rse_config_privilege(MAIN_EXP2_PPC_DEV.dev, periph,
415 (enum ppc_rse_sec_attr_t)sec_attr,
416 (enum ppc_rse_priv_attr_t)priv_attr);
417
418 if( ret != PPC_RSE_ERR_NONE) {
419 return ARM_DRIVER_ERROR;
420 }
421
422 return ARM_DRIVER_OK;
423 }
424
PPC_RSE_MAIN_EXP2_IsPeriphPrivOnly(uint32_t periph)425 static bool PPC_RSE_MAIN_EXP2_IsPeriphPrivOnly(uint32_t periph)
426 {
427 return ppc_rse_is_periph_priv_only(MAIN_EXP2_PPC_DEV.dev, periph);
428 }
429
430 /* Secure only functions */
431 #if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U))
432
433 static int32_t
PPC_RSE_MAIN_EXP2_ConfigSecurity(uint32_t periph,PPC_RSE_SecAttr sec_attr)434 PPC_RSE_MAIN_EXP2_ConfigSecurity(uint32_t periph,
435 PPC_RSE_SecAttr sec_attr)
436 {
437 enum ppc_rse_error_t ret;
438
439 ret = ppc_rse_config_security(MAIN_EXP2_PPC_DEV.dev, periph,
440 (enum ppc_rse_sec_attr_t)sec_attr);
441
442 if( ret != PPC_RSE_ERR_NONE) {
443 return ARM_DRIVER_ERROR;
444 }
445
446 return ARM_DRIVER_OK;
447 }
448
PPC_RSE_MAIN_EXP2_IsPeriphSecure(uint32_t periph)449 static bool PPC_RSE_MAIN_EXP2_IsPeriphSecure(uint32_t periph)
450 {
451 return ppc_rse_is_periph_secure(MAIN_EXP2_PPC_DEV.dev, periph);
452 }
453
PPC_RSE_MAIN_EXP2_EnableInterrupt(void)454 static int32_t PPC_RSE_MAIN_EXP2_EnableInterrupt(void)
455 {
456 enum ppc_rse_error_t ret;
457
458 ret = ppc_rse_irq_enable(MAIN_EXP2_PPC_DEV.dev);
459
460 if( ret != PPC_RSE_ERR_NONE) {
461 return ARM_DRIVER_ERROR;
462 }
463
464 return ARM_DRIVER_OK;
465 }
466
PPC_RSE_MAIN_EXP2_DisableInterrupt(void)467 static void PPC_RSE_MAIN_EXP2_DisableInterrupt(void)
468 {
469 ppc_rse_irq_disable(MAIN_EXP2_PPC_DEV.dev);
470 }
471
PPC_RSE_MAIN_EXP2_ClearInterrupt(void)472 static void PPC_RSE_MAIN_EXP2_ClearInterrupt(void)
473 {
474 ppc_rse_clear_irq(MAIN_EXP2_PPC_DEV.dev);
475 }
476
PPC_RSE_MAIN_EXP2_InterruptState(void)477 static bool PPC_RSE_MAIN_EXP2_InterruptState(void)
478 {
479 return ppc_rse_irq_state(MAIN_EXP2_PPC_DEV.dev);
480 }
481
482 #endif /* (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)) */
483
484 /* PPC RSE MAIN EXP2 Driver CMSIS access structure */
485 DRIVER_PPC_RSE Driver_PPC_RSE_MAIN_EXP2 = {
486 .GetVersion = PPC_RSE_GetVersion,
487 .Initialize = PPC_RSE_MAIN_EXP2_Initialize,
488 .Uninitialize = PPC_RSE_MAIN_EXP2_Uninitialize,
489 .ConfigPrivilege = PPC_RSE_MAIN_EXP2_ConfigPrivilege,
490 .IsPeriphPrivOnly = PPC_RSE_MAIN_EXP2_IsPeriphPrivOnly,
491 #if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U))
492 .ConfigSecurity = PPC_RSE_MAIN_EXP2_ConfigSecurity,
493 .IsPeriphSecure = PPC_RSE_MAIN_EXP2_IsPeriphSecure,
494 .EnableInterrupt = PPC_RSE_MAIN_EXP2_EnableInterrupt,
495 .DisableInterrupt = PPC_RSE_MAIN_EXP2_DisableInterrupt,
496 .ClearInterrupt = PPC_RSE_MAIN_EXP2_ClearInterrupt,
497 .InterruptState = PPC_RSE_MAIN_EXP2_InterruptState
498 #endif /* (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)) */
499 };
500 #endif /* RTE_PPC_RSE_MAIN_EXP2 */
501
502 #if (RTE_PPC_RSE_MAIN_EXP3)
503
504 static RSE_PPC_Resources MAIN_EXP3_PPC_DEV = {
505 .dev = &PPC_RSE_MAIN_EXP3_DEV,
506 };
507
508 /* MAIN PPCEXP3 Driver wrapper functions */
PPC_RSE_MAIN_EXP3_Initialize(void)509 static int32_t PPC_RSE_MAIN_EXP3_Initialize(void)
510 {
511 ppc_rse_init(MAIN_EXP3_PPC_DEV.dev);
512
513 return ARM_DRIVER_OK;
514 }
515
PPC_RSE_MAIN_EXP3_Uninitialize(void)516 static int32_t PPC_RSE_MAIN_EXP3_Uninitialize(void)
517 {
518 /* Nothing to do */
519 return ARM_DRIVER_OK;
520 }
521
522 static int32_t
PPC_RSE_MAIN_EXP3_ConfigPrivilege(uint32_t periph,PPC_RSE_SecAttr sec_attr,PPC_RSE_PrivAttr priv_attr)523 PPC_RSE_MAIN_EXP3_ConfigPrivilege(uint32_t periph,
524 PPC_RSE_SecAttr sec_attr,
525 PPC_RSE_PrivAttr priv_attr)
526 {
527 enum ppc_rse_error_t ret;
528
529 ret = ppc_rse_config_privilege(MAIN_EXP3_PPC_DEV.dev, periph,
530 (enum ppc_rse_sec_attr_t)sec_attr,
531 (enum ppc_rse_priv_attr_t)priv_attr);
532
533 if( ret != PPC_RSE_ERR_NONE) {
534 return ARM_DRIVER_ERROR;
535 }
536
537 return ARM_DRIVER_OK;
538 }
539
PPC_RSE_MAIN_EXP3_IsPeriphPrivOnly(uint32_t periph)540 static bool PPC_RSE_MAIN_EXP3_IsPeriphPrivOnly(uint32_t periph)
541 {
542 return ppc_rse_is_periph_priv_only(MAIN_EXP3_PPC_DEV.dev, periph);
543 }
544
545 /* Secure only functions */
546 #if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U))
547
548 static int32_t
PPC_RSE_MAIN_EXP3_ConfigSecurity(uint32_t periph,PPC_RSE_SecAttr sec_attr)549 PPC_RSE_MAIN_EXP3_ConfigSecurity(uint32_t periph,
550 PPC_RSE_SecAttr sec_attr)
551 {
552 enum ppc_rse_error_t ret;
553
554 ret = ppc_rse_config_security(MAIN_EXP3_PPC_DEV.dev, periph,
555 (enum ppc_rse_sec_attr_t)sec_attr);
556
557 if( ret != PPC_RSE_ERR_NONE) {
558 return ARM_DRIVER_ERROR;
559 }
560
561 return ARM_DRIVER_OK;
562 }
563
PPC_RSE_MAIN_EXP3_IsPeriphSecure(uint32_t periph)564 static bool PPC_RSE_MAIN_EXP3_IsPeriphSecure(uint32_t periph)
565 {
566 return ppc_rse_is_periph_secure(MAIN_EXP3_PPC_DEV.dev, periph);
567 }
568
PPC_RSE_MAIN_EXP3_EnableInterrupt(void)569 static int32_t PPC_RSE_MAIN_EXP3_EnableInterrupt(void)
570 {
571 enum ppc_rse_error_t ret;
572
573 ret = ppc_rse_irq_enable(MAIN_EXP3_PPC_DEV.dev);
574
575 if( ret != PPC_RSE_ERR_NONE) {
576 return ARM_DRIVER_ERROR;
577 }
578
579 return ARM_DRIVER_OK;
580 }
581
PPC_RSE_MAIN_EXP3_DisableInterrupt(void)582 static void PPC_RSE_MAIN_EXP3_DisableInterrupt(void)
583 {
584 ppc_rse_irq_disable(MAIN_EXP3_PPC_DEV.dev);
585 }
586
PPC_RSE_MAIN_EXP3_ClearInterrupt(void)587 static void PPC_RSE_MAIN_EXP3_ClearInterrupt(void)
588 {
589 ppc_rse_clear_irq(MAIN_EXP3_PPC_DEV.dev);
590 }
591
PPC_RSE_MAIN_EXP3_InterruptState(void)592 static bool PPC_RSE_MAIN_EXP3_InterruptState(void)
593 {
594 return ppc_rse_irq_state(MAIN_EXP3_PPC_DEV.dev);
595 }
596
597 #endif /* (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)) */
598
599 /* PPC RSE MAIN EXP3 Driver CMSIS access structure */
600 DRIVER_PPC_RSE Driver_PPC_RSE_MAIN_EXP3 = {
601 .GetVersion = PPC_RSE_GetVersion,
602 .Initialize = PPC_RSE_MAIN_EXP3_Initialize,
603 .Uninitialize = PPC_RSE_MAIN_EXP3_Uninitialize,
604 .ConfigPrivilege = PPC_RSE_MAIN_EXP3_ConfigPrivilege,
605 .IsPeriphPrivOnly = PPC_RSE_MAIN_EXP3_IsPeriphPrivOnly,
606 #if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U))
607 .ConfigSecurity = PPC_RSE_MAIN_EXP3_ConfigSecurity,
608 .IsPeriphSecure = PPC_RSE_MAIN_EXP3_IsPeriphSecure,
609 .EnableInterrupt = PPC_RSE_MAIN_EXP3_EnableInterrupt,
610 .DisableInterrupt = PPC_RSE_MAIN_EXP3_DisableInterrupt,
611 .ClearInterrupt = PPC_RSE_MAIN_EXP3_ClearInterrupt,
612 .InterruptState = PPC_RSE_MAIN_EXP3_InterruptState
613 #endif /* (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)) */
614 };
615 #endif /* RTE_PPC_RSE_MAIN_EXP3 */
616
617 #if (RTE_PPC_RSE_PERIPH0)
618
619 static RSE_PPC_Resources PERIPH0_PPC_DEV = {
620 .dev = &PPC_RSE_PERIPH0_DEV,
621 };
622
623 /* PERIPH0 Driver wrapper functions */
PPC_RSE_PERIPH0_Initialize(void)624 static int32_t PPC_RSE_PERIPH0_Initialize(void)
625 {
626 ppc_rse_init(PERIPH0_PPC_DEV.dev);
627
628 return ARM_DRIVER_OK;
629 }
630
PPC_RSE_PERIPH0_Uninitialize(void)631 static int32_t PPC_RSE_PERIPH0_Uninitialize(void)
632 {
633 /* Nothing to do */
634 return ARM_DRIVER_OK;
635 }
636
637 static int32_t
PPC_RSE_PERIPH0_ConfigPrivilege(uint32_t periph,PPC_RSE_SecAttr sec_attr,PPC_RSE_PrivAttr priv_attr)638 PPC_RSE_PERIPH0_ConfigPrivilege(uint32_t periph,
639 PPC_RSE_SecAttr sec_attr,
640 PPC_RSE_PrivAttr priv_attr)
641 {
642 enum ppc_rse_error_t ret;
643
644 ret = ppc_rse_config_privilege(PERIPH0_PPC_DEV.dev, periph,
645 (enum ppc_rse_sec_attr_t)sec_attr,
646 (enum ppc_rse_priv_attr_t)priv_attr);
647
648 if( ret != PPC_RSE_ERR_NONE) {
649 return ARM_DRIVER_ERROR;
650 }
651
652 return ARM_DRIVER_OK;
653 }
654
PPC_RSE_PERIPH0_IsPeriphPrivOnly(uint32_t periph)655 static bool PPC_RSE_PERIPH0_IsPeriphPrivOnly(uint32_t periph)
656 {
657 return ppc_rse_is_periph_priv_only(PERIPH0_PPC_DEV.dev, periph);
658 }
659
660 /* Secure only functions */
661 #if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U))
662
663 static int32_t
PPC_RSE_PERIPH0_ConfigSecurity(uint32_t periph,PPC_RSE_SecAttr sec_attr)664 PPC_RSE_PERIPH0_ConfigSecurity(uint32_t periph,
665 PPC_RSE_SecAttr sec_attr)
666 {
667 enum ppc_rse_error_t ret;
668
669 ret = ppc_rse_config_security(PERIPH0_PPC_DEV.dev, periph,
670 (enum ppc_rse_sec_attr_t)sec_attr);
671
672 if( ret != PPC_RSE_ERR_NONE) {
673 return ARM_DRIVER_ERROR;
674 }
675
676 return ARM_DRIVER_OK;
677 }
678
PPC_RSE_PERIPH0_IsPeriphSecure(uint32_t periph)679 static bool PPC_RSE_PERIPH0_IsPeriphSecure(uint32_t periph)
680 {
681 return ppc_rse_is_periph_secure(PERIPH0_PPC_DEV.dev, periph);
682 }
683
PPC_RSE_PERIPH0_EnableInterrupt(void)684 static int32_t PPC_RSE_PERIPH0_EnableInterrupt(void)
685 {
686 enum ppc_rse_error_t ret;
687
688 ret = ppc_rse_irq_enable(PERIPH0_PPC_DEV.dev);
689
690 if( ret != PPC_RSE_ERR_NONE) {
691 return ARM_DRIVER_ERROR;
692 }
693
694 return ARM_DRIVER_OK;
695 }
696
PPC_RSE_PERIPH0_DisableInterrupt(void)697 static void PPC_RSE_PERIPH0_DisableInterrupt(void)
698 {
699 ppc_rse_irq_disable(PERIPH0_PPC_DEV.dev);
700 }
701
PPC_RSE_PERIPH0_ClearInterrupt(void)702 static void PPC_RSE_PERIPH0_ClearInterrupt(void)
703 {
704 ppc_rse_clear_irq(PERIPH0_PPC_DEV.dev);
705 }
706
PPC_RSE_PERIPH0_InterruptState(void)707 static bool PPC_RSE_PERIPH0_InterruptState(void)
708 {
709 return ppc_rse_irq_state(PERIPH0_PPC_DEV.dev);
710 }
711
712 #endif /* (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)) */
713
714 /* PPC RSE PERIPH0 Driver CMSIS access structure */
715 DRIVER_PPC_RSE Driver_PPC_RSE_PERIPH0 = {
716 .GetVersion = PPC_RSE_GetVersion,
717 .Initialize = PPC_RSE_PERIPH0_Initialize,
718 .Uninitialize = PPC_RSE_PERIPH0_Uninitialize,
719 .ConfigPrivilege = PPC_RSE_PERIPH0_ConfigPrivilege,
720 .IsPeriphPrivOnly = PPC_RSE_PERIPH0_IsPeriphPrivOnly,
721 #if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U))
722 .ConfigSecurity = PPC_RSE_PERIPH0_ConfigSecurity,
723 .IsPeriphSecure = PPC_RSE_PERIPH0_IsPeriphSecure,
724 .EnableInterrupt = PPC_RSE_PERIPH0_EnableInterrupt,
725 .DisableInterrupt = PPC_RSE_PERIPH0_DisableInterrupt,
726 .ClearInterrupt = PPC_RSE_PERIPH0_ClearInterrupt,
727 .InterruptState = PPC_RSE_PERIPH0_InterruptState
728 #endif /* (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)) */
729 };
730 #endif /* RTE_PPC_RSE_PERIPH0 */
731
732 #if (RTE_PPC_RSE_PERIPH1)
733
734 static RSE_PPC_Resources PERIPH1_PPC_DEV = {
735 .dev = &PPC_RSE_PERIPH1_DEV,
736 };
737
738 /* PERIPH1 Driver wrapper functions */
PPC_RSE_PERIPH1_Initialize(void)739 static int32_t PPC_RSE_PERIPH1_Initialize(void)
740 {
741 ppc_rse_init(PERIPH1_PPC_DEV.dev);
742
743 return ARM_DRIVER_OK;
744 }
745
PPC_RSE_PERIPH1_Uninitialize(void)746 static int32_t PPC_RSE_PERIPH1_Uninitialize(void)
747 {
748 /* Nothing to do */
749 return ARM_DRIVER_OK;
750 }
751
752 static int32_t
PPC_RSE_PERIPH1_ConfigPrivilege(uint32_t periph,PPC_RSE_SecAttr sec_attr,PPC_RSE_PrivAttr priv_attr)753 PPC_RSE_PERIPH1_ConfigPrivilege(uint32_t periph,
754 PPC_RSE_SecAttr sec_attr,
755 PPC_RSE_PrivAttr priv_attr)
756 {
757 enum ppc_rse_error_t ret;
758
759 ret = ppc_rse_config_privilege(PERIPH1_PPC_DEV.dev, periph,
760 (enum ppc_rse_sec_attr_t)sec_attr,
761 (enum ppc_rse_priv_attr_t)priv_attr);
762
763 if( ret != PPC_RSE_ERR_NONE) {
764 return ARM_DRIVER_ERROR;
765 }
766
767 return ARM_DRIVER_OK;
768 }
769
PPC_RSE_PERIPH1_IsPeriphPrivOnly(uint32_t periph)770 static bool PPC_RSE_PERIPH1_IsPeriphPrivOnly(uint32_t periph)
771 {
772 return ppc_rse_is_periph_priv_only(PERIPH1_PPC_DEV.dev, periph);
773 }
774
775 /* Secure only functions */
776 #if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U))
777
778 static int32_t
PPC_RSE_PERIPH1_ConfigSecurity(uint32_t periph,PPC_RSE_SecAttr sec_attr)779 PPC_RSE_PERIPH1_ConfigSecurity(uint32_t periph,
780 PPC_RSE_SecAttr sec_attr)
781 {
782 enum ppc_rse_error_t ret;
783
784 ret = ppc_rse_config_security(PERIPH1_PPC_DEV.dev, periph,
785 (enum ppc_rse_sec_attr_t)sec_attr);
786
787 if( ret != PPC_RSE_ERR_NONE) {
788 return ARM_DRIVER_ERROR;
789 }
790
791 return ARM_DRIVER_OK;
792 }
793
PPC_RSE_PERIPH1_IsPeriphSecure(uint32_t periph)794 static bool PPC_RSE_PERIPH1_IsPeriphSecure(uint32_t periph)
795 {
796 return ppc_rse_is_periph_secure(PERIPH1_PPC_DEV.dev, periph);
797 }
798
PPC_RSE_PERIPH1_EnableInterrupt(void)799 static int32_t PPC_RSE_PERIPH1_EnableInterrupt(void)
800 {
801 enum ppc_rse_error_t ret;
802
803 ret = ppc_rse_irq_enable(PERIPH1_PPC_DEV.dev);
804
805 if( ret != PPC_RSE_ERR_NONE) {
806 return ARM_DRIVER_ERROR;
807 }
808
809 return ARM_DRIVER_OK;
810 }
811
PPC_RSE_PERIPH1_DisableInterrupt(void)812 static void PPC_RSE_PERIPH1_DisableInterrupt(void)
813 {
814 ppc_rse_irq_disable(PERIPH1_PPC_DEV.dev);
815 }
816
PPC_RSE_PERIPH1_ClearInterrupt(void)817 static void PPC_RSE_PERIPH1_ClearInterrupt(void)
818 {
819 ppc_rse_clear_irq(PERIPH1_PPC_DEV.dev);
820 }
821
PPC_RSE_PERIPH1_InterruptState(void)822 static bool PPC_RSE_PERIPH1_InterruptState(void)
823 {
824 return ppc_rse_irq_state(PERIPH1_PPC_DEV.dev);
825 }
826
827 #endif /* (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)) */
828
829 /* PPC RSE PERIPH1 Driver CMSIS access structure */
830 DRIVER_PPC_RSE Driver_PPC_RSE_PERIPH1 = {
831 .GetVersion = PPC_RSE_GetVersion,
832 .Initialize = PPC_RSE_PERIPH1_Initialize,
833 .Uninitialize = PPC_RSE_PERIPH1_Uninitialize,
834 .ConfigPrivilege = PPC_RSE_PERIPH1_ConfigPrivilege,
835 .IsPeriphPrivOnly = PPC_RSE_PERIPH1_IsPeriphPrivOnly,
836 #if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U))
837 .ConfigSecurity = PPC_RSE_PERIPH1_ConfigSecurity,
838 .IsPeriphSecure = PPC_RSE_PERIPH1_IsPeriphSecure,
839 .EnableInterrupt = PPC_RSE_PERIPH1_EnableInterrupt,
840 .DisableInterrupt = PPC_RSE_PERIPH1_DisableInterrupt,
841 .ClearInterrupt = PPC_RSE_PERIPH1_ClearInterrupt,
842 .InterruptState = PPC_RSE_PERIPH1_InterruptState
843 #endif /* (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)) */
844 };
845 #endif /* RTE_PPC_RSE_PERIPH1 */
846
847 #if (RTE_PPC_RSE_PERIPH_EXP0)
848
849 static RSE_PPC_Resources PERIPH_EXP0_PPC_DEV = {
850 .dev = &PPC_RSE_PERIPH_EXP0_DEV,
851 };
852
853 /* PERIPH PPCEXP0 Driver wrapper functions */
PPC_RSE_PERIPH_EXP0_Initialize(void)854 static int32_t PPC_RSE_PERIPH_EXP0_Initialize(void)
855 {
856 ppc_rse_init(PERIPH_EXP0_PPC_DEV.dev);
857
858 return ARM_DRIVER_OK;
859 }
860
PPC_RSE_PERIPH_EXP0_Uninitialize(void)861 static int32_t PPC_RSE_PERIPH_EXP0_Uninitialize(void)
862 {
863 /* Nothing to do */
864 return ARM_DRIVER_OK;
865 }
866
867 static int32_t
PPC_RSE_PERIPH_EXP0_ConfigPrivilege(uint32_t periph,PPC_RSE_SecAttr sec_attr,PPC_RSE_PrivAttr priv_attr)868 PPC_RSE_PERIPH_EXP0_ConfigPrivilege(uint32_t periph,
869 PPC_RSE_SecAttr sec_attr,
870 PPC_RSE_PrivAttr priv_attr)
871 {
872 enum ppc_rse_error_t ret;
873
874 ret = ppc_rse_config_privilege(PERIPH_EXP0_PPC_DEV.dev, periph,
875 (enum ppc_rse_sec_attr_t)sec_attr,
876 (enum ppc_rse_priv_attr_t)priv_attr);
877
878 if( ret != PPC_RSE_ERR_NONE) {
879 return ARM_DRIVER_ERROR;
880 }
881
882 return ARM_DRIVER_OK;
883 }
884
PPC_RSE_PERIPH_EXP0_IsPeriphPrivOnly(uint32_t periph)885 static bool PPC_RSE_PERIPH_EXP0_IsPeriphPrivOnly(uint32_t periph)
886 {
887 return ppc_rse_is_periph_priv_only(PERIPH_EXP0_PPC_DEV.dev, periph);
888 }
889
890 /* Secure only functions */
891 #if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U))
892
893 static int32_t
PPC_RSE_PERIPH_EXP0_ConfigSecurity(uint32_t periph,PPC_RSE_SecAttr sec_attr)894 PPC_RSE_PERIPH_EXP0_ConfigSecurity(uint32_t periph,
895 PPC_RSE_SecAttr sec_attr)
896 {
897 enum ppc_rse_error_t ret;
898
899 ret = ppc_rse_config_security(PERIPH_EXP0_PPC_DEV.dev, periph,
900 (enum ppc_rse_sec_attr_t)sec_attr);
901
902 if( ret != PPC_RSE_ERR_NONE) {
903 return ARM_DRIVER_ERROR;
904 }
905
906 return ARM_DRIVER_OK;
907 }
908
PPC_RSE_PERIPH_EXP0_IsPeriphSecure(uint32_t periph)909 static bool PPC_RSE_PERIPH_EXP0_IsPeriphSecure(uint32_t periph)
910 {
911 return ppc_rse_is_periph_secure(PERIPH_EXP0_PPC_DEV.dev, periph);
912 }
913
PPC_RSE_PERIPH_EXP0_EnableInterrupt(void)914 static int32_t PPC_RSE_PERIPH_EXP0_EnableInterrupt(void)
915 {
916 enum ppc_rse_error_t ret;
917
918 ret = ppc_rse_irq_enable(PERIPH_EXP0_PPC_DEV.dev);
919
920 if( ret != PPC_RSE_ERR_NONE) {
921 return ARM_DRIVER_ERROR;
922 }
923
924 return ARM_DRIVER_OK;
925 }
926
PPC_RSE_PERIPH_EXP0_DisableInterrupt(void)927 static void PPC_RSE_PERIPH_EXP0_DisableInterrupt(void)
928 {
929 ppc_rse_irq_disable(PERIPH_EXP0_PPC_DEV.dev);
930 }
931
PPC_RSE_PERIPH_EXP0_ClearInterrupt(void)932 static void PPC_RSE_PERIPH_EXP0_ClearInterrupt(void)
933 {
934 ppc_rse_clear_irq(PERIPH_EXP0_PPC_DEV.dev);
935 }
936
PPC_RSE_PERIPH_EXP0_InterruptState(void)937 static bool PPC_RSE_PERIPH_EXP0_InterruptState(void)
938 {
939 return ppc_rse_irq_state(PERIPH_EXP0_PPC_DEV.dev);
940 }
941
942 #endif /* (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)) */
943
944 /* PPC RSE PERIPH EXP0 Driver CMSIS access structure */
945 DRIVER_PPC_RSE Driver_PPC_RSE_PERIPH_EXP0 = {
946 .GetVersion = PPC_RSE_GetVersion,
947 .Initialize = PPC_RSE_PERIPH_EXP0_Initialize,
948 .Uninitialize = PPC_RSE_PERIPH_EXP0_Uninitialize,
949 .ConfigPrivilege = PPC_RSE_PERIPH_EXP0_ConfigPrivilege,
950 .IsPeriphPrivOnly = PPC_RSE_PERIPH_EXP0_IsPeriphPrivOnly,
951 #if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U))
952 .ConfigSecurity = PPC_RSE_PERIPH_EXP0_ConfigSecurity,
953 .IsPeriphSecure = PPC_RSE_PERIPH_EXP0_IsPeriphSecure,
954 .EnableInterrupt = PPC_RSE_PERIPH_EXP0_EnableInterrupt,
955 .DisableInterrupt = PPC_RSE_PERIPH_EXP0_DisableInterrupt,
956 .ClearInterrupt = PPC_RSE_PERIPH_EXP0_ClearInterrupt,
957 .InterruptState = PPC_RSE_PERIPH_EXP0_InterruptState
958 #endif /* (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)) */
959 };
960 #endif /* RTE_PPC_RSE_PERIPH_EXP0 */
961
962 #if (RTE_PPC_RSE_PERIPH_EXP1)
963
964 static RSE_PPC_Resources PERIPH_EXP1_PPC_DEV = {
965 .dev = &PPC_RSE_PERIPH_EXP1_DEV,
966 };
967
968 /* PERIPH PPCEXP1 Driver wrapper functions */
PPC_RSE_PERIPH_EXP1_Initialize(void)969 static int32_t PPC_RSE_PERIPH_EXP1_Initialize(void)
970 {
971 ppc_rse_init(PERIPH_EXP1_PPC_DEV.dev);
972
973 return ARM_DRIVER_OK;
974 }
975
PPC_RSE_PERIPH_EXP1_Uninitialize(void)976 static int32_t PPC_RSE_PERIPH_EXP1_Uninitialize(void)
977 {
978 /* Nothing to do */
979 return ARM_DRIVER_OK;
980 }
981
982 static int32_t
PPC_RSE_PERIPH_EXP1_ConfigPrivilege(uint32_t periph,PPC_RSE_SecAttr sec_attr,PPC_RSE_PrivAttr priv_attr)983 PPC_RSE_PERIPH_EXP1_ConfigPrivilege(uint32_t periph,
984 PPC_RSE_SecAttr sec_attr,
985 PPC_RSE_PrivAttr priv_attr)
986 {
987 enum ppc_rse_error_t ret;
988
989 ret = ppc_rse_config_privilege(PERIPH_EXP1_PPC_DEV.dev, periph,
990 (enum ppc_rse_sec_attr_t)sec_attr,
991 (enum ppc_rse_priv_attr_t)priv_attr);
992
993 if( ret != PPC_RSE_ERR_NONE) {
994 return ARM_DRIVER_ERROR;
995 }
996
997 return ARM_DRIVER_OK;
998 }
999
PPC_RSE_PERIPH_EXP1_IsPeriphPrivOnly(uint32_t periph)1000 static bool PPC_RSE_PERIPH_EXP1_IsPeriphPrivOnly(uint32_t periph)
1001 {
1002 return ppc_rse_is_periph_priv_only(PERIPH_EXP1_PPC_DEV.dev, periph);
1003 }
1004
1005 /* Secure only functions */
1006 #if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U))
1007
1008 static int32_t
PPC_RSE_PERIPH_EXP1_ConfigSecurity(uint32_t periph,PPC_RSE_SecAttr sec_attr)1009 PPC_RSE_PERIPH_EXP1_ConfigSecurity(uint32_t periph,
1010 PPC_RSE_SecAttr sec_attr)
1011 {
1012 enum ppc_rse_error_t ret;
1013
1014 ret = ppc_rse_config_security(PERIPH_EXP1_PPC_DEV.dev, periph,
1015 (enum ppc_rse_sec_attr_t)sec_attr);
1016
1017 if( ret != PPC_RSE_ERR_NONE) {
1018 return ARM_DRIVER_ERROR;
1019 }
1020
1021 return ARM_DRIVER_OK;
1022 }
1023
PPC_RSE_PERIPH_EXP1_IsPeriphSecure(uint32_t periph)1024 static bool PPC_RSE_PERIPH_EXP1_IsPeriphSecure(uint32_t periph)
1025 {
1026 return ppc_rse_is_periph_secure(PERIPH_EXP1_PPC_DEV.dev, periph);
1027 }
1028
PPC_RSE_PERIPH_EXP1_EnableInterrupt(void)1029 static int32_t PPC_RSE_PERIPH_EXP1_EnableInterrupt(void)
1030 {
1031 enum ppc_rse_error_t ret;
1032
1033 ret = ppc_rse_irq_enable(PERIPH_EXP1_PPC_DEV.dev);
1034
1035 if( ret != PPC_RSE_ERR_NONE) {
1036 return ARM_DRIVER_ERROR;
1037 }
1038
1039 return ARM_DRIVER_OK;
1040 }
1041
PPC_RSE_PERIPH_EXP1_DisableInterrupt(void)1042 static void PPC_RSE_PERIPH_EXP1_DisableInterrupt(void)
1043 {
1044 ppc_rse_irq_disable(PERIPH_EXP1_PPC_DEV.dev);
1045 }
1046
PPC_RSE_PERIPH_EXP1_ClearInterrupt(void)1047 static void PPC_RSE_PERIPH_EXP1_ClearInterrupt(void)
1048 {
1049 ppc_rse_clear_irq(PERIPH_EXP1_PPC_DEV.dev);
1050 }
1051
PPC_RSE_PERIPH_EXP1_InterruptState(void)1052 static bool PPC_RSE_PERIPH_EXP1_InterruptState(void)
1053 {
1054 return ppc_rse_irq_state(PERIPH_EXP1_PPC_DEV.dev);
1055 }
1056
1057 #endif /* (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)) */
1058
1059 /* PPC RSE PERIPH EXP1 Driver CMSIS access structure */
1060 DRIVER_PPC_RSE Driver_PPC_RSE_PERIPH_EXP1 = {
1061 .GetVersion = PPC_RSE_GetVersion,
1062 .Initialize = PPC_RSE_PERIPH_EXP1_Initialize,
1063 .Uninitialize = PPC_RSE_PERIPH_EXP1_Uninitialize,
1064 .ConfigPrivilege = PPC_RSE_PERIPH_EXP1_ConfigPrivilege,
1065 .IsPeriphPrivOnly = PPC_RSE_PERIPH_EXP1_IsPeriphPrivOnly,
1066 #if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U))
1067 .ConfigSecurity = PPC_RSE_PERIPH_EXP1_ConfigSecurity,
1068 .IsPeriphSecure = PPC_RSE_PERIPH_EXP1_IsPeriphSecure,
1069 .EnableInterrupt = PPC_RSE_PERIPH_EXP1_EnableInterrupt,
1070 .DisableInterrupt = PPC_RSE_PERIPH_EXP1_DisableInterrupt,
1071 .ClearInterrupt = PPC_RSE_PERIPH_EXP1_ClearInterrupt,
1072 .InterruptState = PPC_RSE_PERIPH_EXP1_InterruptState
1073 #endif /* (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)) */
1074 };
1075 #endif /* RTE_PPC_RSE_PERIPH_EXP1 */
1076
1077 #if (RTE_PPC_RSE_PERIPH_EXP2)
1078
1079 static RSE_PPC_Resources PERIPH_EXP2_PPC_DEV = {
1080 .dev = &PPC_RSE_PERIPH_EXP2_DEV,
1081 };
1082
1083 /* PERIPH PPCEXP2 Driver wrapper functions */
PPC_RSE_PERIPH_EXP2_Initialize(void)1084 static int32_t PPC_RSE_PERIPH_EXP2_Initialize(void)
1085 {
1086 ppc_rse_init(PERIPH_EXP2_PPC_DEV.dev);
1087
1088 return ARM_DRIVER_OK;
1089 }
1090
PPC_RSE_PERIPH_EXP2_Uninitialize(void)1091 static int32_t PPC_RSE_PERIPH_EXP2_Uninitialize(void)
1092 {
1093 /* Nothing to do */
1094 return ARM_DRIVER_OK;
1095 }
1096
1097 static int32_t
PPC_RSE_PERIPH_EXP2_ConfigPrivilege(uint32_t periph,PPC_RSE_SecAttr sec_attr,PPC_RSE_PrivAttr priv_attr)1098 PPC_RSE_PERIPH_EXP2_ConfigPrivilege(uint32_t periph,
1099 PPC_RSE_SecAttr sec_attr,
1100 PPC_RSE_PrivAttr priv_attr)
1101 {
1102 enum ppc_rse_error_t ret;
1103
1104 ret = ppc_rse_config_privilege(PERIPH_EXP2_PPC_DEV.dev, periph,
1105 (enum ppc_rse_sec_attr_t)sec_attr,
1106 (enum ppc_rse_priv_attr_t)priv_attr);
1107
1108 if( ret != PPC_RSE_ERR_NONE) {
1109 return ARM_DRIVER_ERROR;
1110 }
1111
1112 return ARM_DRIVER_OK;
1113 }
1114
PPC_RSE_PERIPH_EXP2_IsPeriphPrivOnly(uint32_t periph)1115 static bool PPC_RSE_PERIPH_EXP2_IsPeriphPrivOnly(uint32_t periph)
1116 {
1117 return ppc_rse_is_periph_priv_only(PERIPH_EXP2_PPC_DEV.dev, periph);
1118 }
1119
1120 /* Secure only functions */
1121 #if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U))
1122
1123 static int32_t
PPC_RSE_PERIPH_EXP2_ConfigSecurity(uint32_t periph,PPC_RSE_SecAttr sec_attr)1124 PPC_RSE_PERIPH_EXP2_ConfigSecurity(uint32_t periph,
1125 PPC_RSE_SecAttr sec_attr)
1126 {
1127 enum ppc_rse_error_t ret;
1128
1129 ret = ppc_rse_config_security(PERIPH_EXP2_PPC_DEV.dev, periph,
1130 (enum ppc_rse_sec_attr_t)sec_attr);
1131
1132 if( ret != PPC_RSE_ERR_NONE) {
1133 return ARM_DRIVER_ERROR;
1134 }
1135
1136 return ARM_DRIVER_OK;
1137 }
1138
PPC_RSE_PERIPH_EXP2_IsPeriphSecure(uint32_t periph)1139 static bool PPC_RSE_PERIPH_EXP2_IsPeriphSecure(uint32_t periph)
1140 {
1141 return ppc_rse_is_periph_secure(PERIPH_EXP2_PPC_DEV.dev, periph);
1142 }
1143
PPC_RSE_PERIPH_EXP2_EnableInterrupt(void)1144 static int32_t PPC_RSE_PERIPH_EXP2_EnableInterrupt(void)
1145 {
1146 enum ppc_rse_error_t ret;
1147
1148 ret = ppc_rse_irq_enable(PERIPH_EXP2_PPC_DEV.dev);
1149
1150 if( ret != PPC_RSE_ERR_NONE) {
1151 return ARM_DRIVER_ERROR;
1152 }
1153
1154 return ARM_DRIVER_OK;
1155 }
1156
PPC_RSE_PERIPH_EXP2_DisableInterrupt(void)1157 static void PPC_RSE_PERIPH_EXP2_DisableInterrupt(void)
1158 {
1159 ppc_rse_irq_disable(PERIPH_EXP2_PPC_DEV.dev);
1160 }
1161
PPC_RSE_PERIPH_EXP2_ClearInterrupt(void)1162 static void PPC_RSE_PERIPH_EXP2_ClearInterrupt(void)
1163 {
1164 ppc_rse_clear_irq(PERIPH_EXP2_PPC_DEV.dev);
1165 }
1166
PPC_RSE_PERIPH_EXP2_InterruptState(void)1167 static bool PPC_RSE_PERIPH_EXP2_InterruptState(void)
1168 {
1169 return ppc_rse_irq_state(PERIPH_EXP2_PPC_DEV.dev);
1170 }
1171
1172 #endif /* (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)) */
1173
1174 /* PPC RSE PERIPH EXP2 Driver CMSIS access structure */
1175 DRIVER_PPC_RSE Driver_PPC_RSE_PERIPH_EXP2 = {
1176 .GetVersion = PPC_RSE_GetVersion,
1177 .Initialize = PPC_RSE_PERIPH_EXP2_Initialize,
1178 .Uninitialize = PPC_RSE_PERIPH_EXP2_Uninitialize,
1179 .ConfigPrivilege = PPC_RSE_PERIPH_EXP2_ConfigPrivilege,
1180 .IsPeriphPrivOnly = PPC_RSE_PERIPH_EXP2_IsPeriphPrivOnly,
1181 #if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U))
1182 .ConfigSecurity = PPC_RSE_PERIPH_EXP2_ConfigSecurity,
1183 .IsPeriphSecure = PPC_RSE_PERIPH_EXP2_IsPeriphSecure,
1184 .EnableInterrupt = PPC_RSE_PERIPH_EXP2_EnableInterrupt,
1185 .DisableInterrupt = PPC_RSE_PERIPH_EXP2_DisableInterrupt,
1186 .ClearInterrupt = PPC_RSE_PERIPH_EXP2_ClearInterrupt,
1187 .InterruptState = PPC_RSE_PERIPH_EXP2_InterruptState
1188 #endif /* (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)) */
1189 };
1190 #endif /* RTE_PPC_RSE_PERIPH_EXP2 */
1191
1192 #if (RTE_PPC_RSE_PERIPH_EXP3)
1193
1194 static RSE_PPC_Resources PERIPH_EXP3_PPC_DEV = {
1195 .dev = &PPC_RSE_PERIPH_EXP3_DEV,
1196 };
1197
1198 /* PERIPH PPCEXP3 Driver wrapper functions */
PPC_RSE_PERIPH_EXP3_Initialize(void)1199 static int32_t PPC_RSE_PERIPH_EXP3_Initialize(void)
1200 {
1201 ppc_rse_init(PERIPH_EXP3_PPC_DEV.dev);
1202
1203 return ARM_DRIVER_OK;
1204 }
1205
PPC_RSE_PERIPH_EXP3_Uninitialize(void)1206 static int32_t PPC_RSE_PERIPH_EXP3_Uninitialize(void)
1207 {
1208 /* Nothing to do */
1209 return ARM_DRIVER_OK;
1210 }
1211
1212 static int32_t
PPC_RSE_PERIPH_EXP3_ConfigPrivilege(uint32_t periph,PPC_RSE_SecAttr sec_attr,PPC_RSE_PrivAttr priv_attr)1213 PPC_RSE_PERIPH_EXP3_ConfigPrivilege(uint32_t periph,
1214 PPC_RSE_SecAttr sec_attr,
1215 PPC_RSE_PrivAttr priv_attr)
1216 {
1217 enum ppc_rse_error_t ret;
1218
1219 ret = ppc_rse_config_privilege(PERIPH_EXP3_PPC_DEV.dev, periph,
1220 (enum ppc_rse_sec_attr_t)sec_attr,
1221 (enum ppc_rse_priv_attr_t)priv_attr);
1222
1223 if( ret != PPC_RSE_ERR_NONE) {
1224 return ARM_DRIVER_ERROR;
1225 }
1226
1227 return ARM_DRIVER_OK;
1228 }
1229
PPC_RSE_PERIPH_EXP3_IsPeriphPrivOnly(uint32_t periph)1230 static bool PPC_RSE_PERIPH_EXP3_IsPeriphPrivOnly(uint32_t periph)
1231 {
1232 return ppc_rse_is_periph_priv_only(PERIPH_EXP3_PPC_DEV.dev, periph);
1233 }
1234
1235 /* Secure only functions */
1236 #if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U))
1237
1238 static int32_t
PPC_RSE_PERIPH_EXP3_ConfigSecurity(uint32_t periph,PPC_RSE_SecAttr sec_attr)1239 PPC_RSE_PERIPH_EXP3_ConfigSecurity(uint32_t periph,
1240 PPC_RSE_SecAttr sec_attr)
1241 {
1242 enum ppc_rse_error_t ret;
1243
1244 ret = ppc_rse_config_security(PERIPH_EXP3_PPC_DEV.dev, periph,
1245 (enum ppc_rse_sec_attr_t)sec_attr);
1246
1247 if( ret != PPC_RSE_ERR_NONE) {
1248 return ARM_DRIVER_ERROR;
1249 }
1250
1251 return ARM_DRIVER_OK;
1252 }
1253
PPC_RSE_PERIPH_EXP3_IsPeriphSecure(uint32_t periph)1254 static bool PPC_RSE_PERIPH_EXP3_IsPeriphSecure(uint32_t periph)
1255 {
1256 return ppc_rse_is_periph_secure(PERIPH_EXP3_PPC_DEV.dev, periph);
1257 }
1258
PPC_RSE_PERIPH_EXP3_EnableInterrupt(void)1259 static int32_t PPC_RSE_PERIPH_EXP3_EnableInterrupt(void)
1260 {
1261 enum ppc_rse_error_t ret;
1262
1263 ret = ppc_rse_irq_enable(PERIPH_EXP3_PPC_DEV.dev);
1264
1265 if( ret != PPC_RSE_ERR_NONE) {
1266 return ARM_DRIVER_ERROR;
1267 }
1268
1269 return ARM_DRIVER_OK;
1270 }
1271
PPC_RSE_PERIPH_EXP3_DisableInterrupt(void)1272 static void PPC_RSE_PERIPH_EXP3_DisableInterrupt(void)
1273 {
1274 ppc_rse_irq_disable(PERIPH_EXP3_PPC_DEV.dev);
1275 }
1276
PPC_RSE_PERIPH_EXP3_ClearInterrupt(void)1277 static void PPC_RSE_PERIPH_EXP3_ClearInterrupt(void)
1278 {
1279 ppc_rse_clear_irq(PERIPH_EXP3_PPC_DEV.dev);
1280 }
1281
PPC_RSE_PERIPH_EXP3_InterruptState(void)1282 static bool PPC_RSE_PERIPH_EXP3_InterruptState(void)
1283 {
1284 return ppc_rse_irq_state(PERIPH_EXP3_PPC_DEV.dev);
1285 }
1286
1287 #endif /* (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)) */
1288
1289 /* PPC RSE PERIPH EXP3 Driver CMSIS access structure */
1290 DRIVER_PPC_RSE Driver_PPC_RSE_PERIPH_EXP3 = {
1291 .GetVersion = PPC_RSE_GetVersion,
1292 .Initialize = PPC_RSE_PERIPH_EXP3_Initialize,
1293 .Uninitialize = PPC_RSE_PERIPH_EXP3_Uninitialize,
1294 .ConfigPrivilege = PPC_RSE_PERIPH_EXP3_ConfigPrivilege,
1295 .IsPeriphPrivOnly = PPC_RSE_PERIPH_EXP3_IsPeriphPrivOnly,
1296 #if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U))
1297 .ConfigSecurity = PPC_RSE_PERIPH_EXP3_ConfigSecurity,
1298 .IsPeriphSecure = PPC_RSE_PERIPH_EXP3_IsPeriphSecure,
1299 .EnableInterrupt = PPC_RSE_PERIPH_EXP3_EnableInterrupt,
1300 .DisableInterrupt = PPC_RSE_PERIPH_EXP3_DisableInterrupt,
1301 .ClearInterrupt = PPC_RSE_PERIPH_EXP3_ClearInterrupt,
1302 .InterruptState = PPC_RSE_PERIPH_EXP3_InterruptState
1303 #endif /* (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)) */
1304 };
1305 #endif /* RTE_PPC_RSE_PERIPH_EXP3 */
1306
