1 /*
2 * Copyright (c) 2016-2019 Arm Limited. All rights reserved.
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16 #include "Driver_MPC.h"
17
18 #include "cmsis_driver_config.h"
19 #include "RTE_Device.h"
20
21 /* driver version */
22 #define ARM_MPC_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(1,0)
23
24 /* Driver Version */
25 static const ARM_DRIVER_VERSION DriverVersion = {
26 ARM_MPC_API_VERSION,
27 ARM_MPC_DRV_VERSION
28 };
29
ARM_MPC_GetVersion(void)30 static ARM_DRIVER_VERSION ARM_MPC_GetVersion(void)
31 {
32 return DriverVersion;
33 }
34
35 /*
36 * \brief Translates error codes from native API to CMSIS API.
37 *
38 * \param[in] err Error code to translate (\ref mpc_sie200_error_t).
39 *
40 * \return Returns CMSIS error code.
41 */
error_trans(enum mpc_sie200_error_t err)42 static int32_t error_trans(enum mpc_sie200_error_t err)
43 {
44 switch(err) {
45 case MPC_SIE200_ERR_NONE:
46 return ARM_DRIVER_OK;
47 case MPC_SIE200_INVALID_ARG:
48 return ARM_DRIVER_ERROR_PARAMETER;
49 case MPC_SIE200_NOT_INIT:
50 return ARM_MPC_ERR_NOT_INIT;
51 case MPC_SIE200_ERR_NOT_IN_RANGE:
52 return ARM_MPC_ERR_NOT_IN_RANGE;
53 case MPC_SIE200_ERR_NOT_ALIGNED:
54 return ARM_MPC_ERR_NOT_ALIGNED;
55 case MPC_SIE200_ERR_INVALID_RANGE:
56 return ARM_MPC_ERR_INVALID_RANGE;
57 case MPC_SIE200_ERR_RANGE_SEC_ATTR_NON_COMPATIBLE:
58 return ARM_MPC_ERR_RANGE_SEC_ATTR_NON_COMPATIBLE;
59 default:
60 return ARM_MPC_ERR_UNSPECIFIED;
61 }
62 }
63
64 #if (RTE_ISRAM0_MPC)
65 /* Ranges controlled by this ISRAM0_MPC */
66 static const struct mpc_sie200_memory_range_t MPC_ISRAM0_RANGE_S = {
67 .base = MPC_ISRAM0_RANGE_BASE_S,
68 .limit = MPC_ISRAM0_RANGE_LIMIT_S,
69 .range_offset = 0,
70 .attr = MPC_SIE200_SEC_ATTR_SECURE
71 };
72
73 static const struct mpc_sie200_memory_range_t MPC_ISRAM0_RANGE_NS = {
74 .base = MPC_ISRAM0_RANGE_BASE_NS,
75 .limit = MPC_ISRAM0_RANGE_LIMIT_NS,
76 .range_offset = 0,
77 .attr = MPC_SIE200_SEC_ATTR_NONSECURE
78 };
79
80 #define MPC_ISRAM0_RANGE_LIST_LEN 2u
81 static const struct mpc_sie200_memory_range_t*
82 MPC_ISRAM0_RANGE_LIST[MPC_ISRAM0_RANGE_LIST_LEN] = {&MPC_ISRAM0_RANGE_S,
83 &MPC_ISRAM0_RANGE_NS};
84
85 /* ISRAM0_MPC Driver wrapper functions */
ISRAM0_MPC_Initialize(void)86 static int32_t ISRAM0_MPC_Initialize(void)
87 {
88 enum mpc_sie200_error_t ret;
89
90 ret = mpc_sie200_init(&MPC_ISRAM0_DEV,
91 MPC_ISRAM0_RANGE_LIST,
92 MPC_ISRAM0_RANGE_LIST_LEN);
93
94 return error_trans(ret);
95 }
96
ISRAM0_MPC_Uninitialize(void)97 static int32_t ISRAM0_MPC_Uninitialize(void)
98 {
99 /* Nothing to be done */
100 return ARM_DRIVER_OK;
101 }
102
ISRAM0_MPC_GetBlockSize(uint32_t * blk_size)103 static int32_t ISRAM0_MPC_GetBlockSize(uint32_t* blk_size)
104 {
105 enum mpc_sie200_error_t ret;
106
107 ret = mpc_sie200_get_block_size(&MPC_ISRAM0_DEV, blk_size);
108
109 return error_trans(ret);
110 }
111
ISRAM0_MPC_GetCtrlConfig(uint32_t * ctrl_val)112 static int32_t ISRAM0_MPC_GetCtrlConfig(uint32_t* ctrl_val)
113 {
114 enum mpc_sie200_error_t ret;
115
116 ret = mpc_sie200_get_ctrl(&MPC_ISRAM0_DEV, ctrl_val);
117
118 return error_trans(ret);
119 }
120
ISRAM0_MPC_SetCtrlConfig(uint32_t ctrl)121 static int32_t ISRAM0_MPC_SetCtrlConfig(uint32_t ctrl)
122 {
123 enum mpc_sie200_error_t ret;
124
125 ret = mpc_sie200_set_ctrl(&MPC_ISRAM0_DEV, ctrl);
126
127 return error_trans(ret);
128 }
129
ISRAM0_MPC_GetRegionConfig(uintptr_t base,uintptr_t limit,ARM_MPC_SEC_ATTR * attr)130 static int32_t ISRAM0_MPC_GetRegionConfig(uintptr_t base,
131 uintptr_t limit,
132 ARM_MPC_SEC_ATTR* attr)
133 {
134 enum mpc_sie200_error_t ret;
135
136 ret = mpc_sie200_get_region_config(&MPC_ISRAM0_DEV, base, limit,
137 (enum mpc_sie200_sec_attr_t*)attr);
138
139 return error_trans(ret);
140 }
141
ISRAM0_MPC_ConfigRegion(uintptr_t base,uintptr_t limit,ARM_MPC_SEC_ATTR attr)142 static int32_t ISRAM0_MPC_ConfigRegion(uintptr_t base,
143 uintptr_t limit,
144 ARM_MPC_SEC_ATTR attr)
145 {
146 enum mpc_sie200_error_t ret;
147
148 ret = mpc_sie200_config_region(&MPC_ISRAM0_DEV, base, limit,
149 (enum mpc_sie200_sec_attr_t)attr);
150
151 return error_trans(ret);
152 }
153
ISRAM0_MPC_EnableInterrupt(void)154 static int32_t ISRAM0_MPC_EnableInterrupt(void)
155 {
156 enum mpc_sie200_error_t ret;
157
158 ret = mpc_sie200_irq_enable(&MPC_ISRAM0_DEV);
159
160 return error_trans(ret);
161 }
162
ISRAM0_MPC_DisableInterrupt(void)163 static void ISRAM0_MPC_DisableInterrupt(void)
164 {
165 mpc_sie200_irq_disable(&MPC_ISRAM0_DEV);
166 }
167
168
ISRAM0_MPC_ClearInterrupt(void)169 static void ISRAM0_MPC_ClearInterrupt(void)
170 {
171 mpc_sie200_clear_irq(&MPC_ISRAM0_DEV);
172 }
173
ISRAM0_MPC_InterruptState(void)174 static uint32_t ISRAM0_MPC_InterruptState(void)
175 {
176 return mpc_sie200_irq_state(&MPC_ISRAM0_DEV);
177 }
178
ISRAM0_MPC_LockDown(void)179 static int32_t ISRAM0_MPC_LockDown(void)
180 {
181 return mpc_sie200_lock_down(&MPC_ISRAM0_DEV);
182 }
183
184 /* ISRAM0_MPC Driver CMSIS access structure */
185 extern ARM_DRIVER_MPC Driver_ISRAM0_MPC;
186 ARM_DRIVER_MPC Driver_ISRAM0_MPC = {
187 .GetVersion = ARM_MPC_GetVersion,
188 .Initialize = ISRAM0_MPC_Initialize,
189 .Uninitialize = ISRAM0_MPC_Uninitialize,
190 .GetBlockSize = ISRAM0_MPC_GetBlockSize,
191 .GetCtrlConfig = ISRAM0_MPC_GetCtrlConfig,
192 .SetCtrlConfig = ISRAM0_MPC_SetCtrlConfig,
193 .ConfigRegion = ISRAM0_MPC_ConfigRegion,
194 .GetRegionConfig = ISRAM0_MPC_GetRegionConfig,
195 .EnableInterrupt = ISRAM0_MPC_EnableInterrupt,
196 .DisableInterrupt = ISRAM0_MPC_DisableInterrupt,
197 .ClearInterrupt = ISRAM0_MPC_ClearInterrupt,
198 .InterruptState = ISRAM0_MPC_InterruptState,
199 .LockDown = ISRAM0_MPC_LockDown,
200 };
201 #endif /* RTE_ISRAM0_MPC */
202
203 #if (RTE_ISRAM1_MPC)
204 /* Ranges controlled by this ISRAM1_MPC */
205 static const struct mpc_sie200_memory_range_t MPC_ISRAM1_RANGE_S = {
206 .base = MPC_ISRAM1_RANGE_BASE_S,
207 .limit = MPC_ISRAM1_RANGE_LIMIT_S,
208 .range_offset = 0,
209 .attr = MPC_SIE200_SEC_ATTR_SECURE
210 };
211
212 static const struct mpc_sie200_memory_range_t MPC_ISRAM1_RANGE_NS = {
213 .base = MPC_ISRAM1_RANGE_BASE_NS,
214 .limit = MPC_ISRAM1_RANGE_LIMIT_NS,
215 .range_offset = 0,
216 .attr = MPC_SIE200_SEC_ATTR_NONSECURE
217 };
218
219 #define MPC_ISRAM1_RANGE_LIST_LEN 2u
220 static const struct mpc_sie200_memory_range_t*
221 MPC_ISRAM1_RANGE_LIST[MPC_ISRAM1_RANGE_LIST_LEN] = {&MPC_ISRAM1_RANGE_S,
222 &MPC_ISRAM1_RANGE_NS};
223
224 /* ISRAM1_MPC Driver wrapper functions */
ISRAM1_MPC_Initialize(void)225 static int32_t ISRAM1_MPC_Initialize(void)
226 {
227 enum mpc_sie200_error_t ret;
228
229 ret = mpc_sie200_init(&MPC_ISRAM1_DEV,
230 MPC_ISRAM1_RANGE_LIST,
231 MPC_ISRAM1_RANGE_LIST_LEN);
232
233 return error_trans(ret);
234 }
235
ISRAM1_MPC_Uninitialize(void)236 static int32_t ISRAM1_MPC_Uninitialize(void)
237 {
238 /* Nothing to be done */
239 return ARM_DRIVER_OK;
240 }
241
ISRAM1_MPC_GetBlockSize(uint32_t * blk_size)242 static int32_t ISRAM1_MPC_GetBlockSize(uint32_t* blk_size)
243 {
244 enum mpc_sie200_error_t ret;
245
246 ret = mpc_sie200_get_block_size(&MPC_ISRAM1_DEV, blk_size);
247
248 return error_trans(ret);
249 }
250
ISRAM1_MPC_GetCtrlConfig(uint32_t * ctrl_val)251 static int32_t ISRAM1_MPC_GetCtrlConfig(uint32_t* ctrl_val)
252 {
253 enum mpc_sie200_error_t ret;
254
255 ret = mpc_sie200_get_ctrl(&MPC_ISRAM1_DEV, ctrl_val);
256
257 return error_trans(ret);
258 }
259
ISRAM1_MPC_SetCtrlConfig(uint32_t ctrl)260 static int32_t ISRAM1_MPC_SetCtrlConfig(uint32_t ctrl)
261 {
262 enum mpc_sie200_error_t ret;
263
264 ret = mpc_sie200_set_ctrl(&MPC_ISRAM1_DEV, ctrl);
265
266 return error_trans(ret);
267 }
268
ISRAM1_MPC_GetRegionConfig(uintptr_t base,uintptr_t limit,ARM_MPC_SEC_ATTR * attr)269 static int32_t ISRAM1_MPC_GetRegionConfig(uintptr_t base,
270 uintptr_t limit,
271 ARM_MPC_SEC_ATTR* attr)
272 {
273 enum mpc_sie200_error_t ret;
274
275 ret = mpc_sie200_get_region_config(&MPC_ISRAM1_DEV, base, limit,
276 (enum mpc_sie200_sec_attr_t*)attr);
277
278 return error_trans(ret);
279 }
280
ISRAM1_MPC_ConfigRegion(uintptr_t base,uintptr_t limit,ARM_MPC_SEC_ATTR attr)281 static int32_t ISRAM1_MPC_ConfigRegion(uintptr_t base,
282 uintptr_t limit,
283 ARM_MPC_SEC_ATTR attr)
284 {
285 enum mpc_sie200_error_t ret;
286
287 ret = mpc_sie200_config_region(&MPC_ISRAM1_DEV, base, limit,
288 (enum mpc_sie200_sec_attr_t)attr);
289
290 return error_trans(ret);
291 }
292
ISRAM1_MPC_EnableInterrupt(void)293 static int32_t ISRAM1_MPC_EnableInterrupt(void)
294 {
295 enum mpc_sie200_error_t ret;
296
297 ret = mpc_sie200_irq_enable(&MPC_ISRAM1_DEV);
298
299 return error_trans(ret);
300 }
301
ISRAM1_MPC_DisableInterrupt(void)302 static void ISRAM1_MPC_DisableInterrupt(void)
303 {
304 mpc_sie200_irq_disable(&MPC_ISRAM1_DEV);
305 }
306
307
ISRAM1_MPC_ClearInterrupt(void)308 static void ISRAM1_MPC_ClearInterrupt(void)
309 {
310 mpc_sie200_clear_irq(&MPC_ISRAM1_DEV);
311 }
312
ISRAM1_MPC_InterruptState(void)313 static uint32_t ISRAM1_MPC_InterruptState(void)
314 {
315 return mpc_sie200_irq_state(&MPC_ISRAM1_DEV);
316 }
317
ISRAM1_MPC_LockDown(void)318 static int32_t ISRAM1_MPC_LockDown(void)
319 {
320 return mpc_sie200_lock_down(&MPC_ISRAM1_DEV);
321 }
322
323 /* ISRAM1_MPC Driver CMSIS access structure */
324 extern ARM_DRIVER_MPC Driver_ISRAM1_MPC;
325 ARM_DRIVER_MPC Driver_ISRAM1_MPC = {
326 .GetVersion = ARM_MPC_GetVersion,
327 .Initialize = ISRAM1_MPC_Initialize,
328 .Uninitialize = ISRAM1_MPC_Uninitialize,
329 .GetBlockSize = ISRAM1_MPC_GetBlockSize,
330 .GetCtrlConfig = ISRAM1_MPC_GetCtrlConfig,
331 .SetCtrlConfig = ISRAM1_MPC_SetCtrlConfig,
332 .ConfigRegion = ISRAM1_MPC_ConfigRegion,
333 .GetRegionConfig = ISRAM1_MPC_GetRegionConfig,
334 .EnableInterrupt = ISRAM1_MPC_EnableInterrupt,
335 .DisableInterrupt = ISRAM1_MPC_DisableInterrupt,
336 .ClearInterrupt = ISRAM1_MPC_ClearInterrupt,
337 .InterruptState = ISRAM1_MPC_InterruptState,
338 .LockDown = ISRAM1_MPC_LockDown,
339 };
340 #endif /* RTE_ISRAM1_MPC */
341
342 #if (RTE_ISRAM2_MPC)
343 /* Ranges controlled by this ISRAM2_MPC */
344 static const struct mpc_sie200_memory_range_t MPC_ISRAM2_RANGE_S = {
345 .base = MPC_ISRAM2_RANGE_BASE_S,
346 .limit = MPC_ISRAM2_RANGE_LIMIT_S,
347 .range_offset = 0,
348 .attr = MPC_SIE200_SEC_ATTR_SECURE
349 };
350
351 static const struct mpc_sie200_memory_range_t MPC_ISRAM2_RANGE_NS = {
352 .base = MPC_ISRAM2_RANGE_BASE_NS,
353 .limit = MPC_ISRAM2_RANGE_LIMIT_NS,
354 .range_offset = 0,
355 .attr = MPC_SIE200_SEC_ATTR_NONSECURE
356 };
357
358 #define MPC_ISRAM2_RANGE_LIST_LEN 2u
359 static const struct mpc_sie200_memory_range_t*
360 MPC_ISRAM2_RANGE_LIST[MPC_ISRAM2_RANGE_LIST_LEN] = {&MPC_ISRAM2_RANGE_S,
361 &MPC_ISRAM2_RANGE_NS};
362
363 /* ISRAM2_MPC Driver wrapper functions */
ISRAM2_MPC_Initialize(void)364 static int32_t ISRAM2_MPC_Initialize(void)
365 {
366 enum mpc_sie200_error_t ret;
367
368 ret = mpc_sie200_init(&MPC_ISRAM2_DEV,
369 MPC_ISRAM2_RANGE_LIST,
370 MPC_ISRAM2_RANGE_LIST_LEN);
371
372 return error_trans(ret);
373 }
374
ISRAM2_MPC_Uninitialize(void)375 static int32_t ISRAM2_MPC_Uninitialize(void)
376 {
377 /* Nothing to be done */
378 return ARM_DRIVER_OK;
379 }
380
ISRAM2_MPC_GetBlockSize(uint32_t * blk_size)381 static int32_t ISRAM2_MPC_GetBlockSize(uint32_t* blk_size)
382 {
383 enum mpc_sie200_error_t ret;
384
385 ret = mpc_sie200_get_block_size(&MPC_ISRAM2_DEV, blk_size);
386
387 return error_trans(ret);
388 }
389
ISRAM2_MPC_GetCtrlConfig(uint32_t * ctrl_val)390 static int32_t ISRAM2_MPC_GetCtrlConfig(uint32_t* ctrl_val)
391 {
392 enum mpc_sie200_error_t ret;
393
394 ret = mpc_sie200_get_ctrl(&MPC_ISRAM2_DEV, ctrl_val);
395
396 return error_trans(ret);
397 }
398
ISRAM2_MPC_SetCtrlConfig(uint32_t ctrl)399 static int32_t ISRAM2_MPC_SetCtrlConfig(uint32_t ctrl)
400 {
401 enum mpc_sie200_error_t ret;
402
403 ret = mpc_sie200_set_ctrl(&MPC_ISRAM2_DEV, ctrl);
404
405 return error_trans(ret);
406 }
407
ISRAM2_MPC_GetRegionConfig(uintptr_t base,uintptr_t limit,ARM_MPC_SEC_ATTR * attr)408 static int32_t ISRAM2_MPC_GetRegionConfig(uintptr_t base,
409 uintptr_t limit,
410 ARM_MPC_SEC_ATTR* attr)
411 {
412 enum mpc_sie200_error_t ret;
413
414 ret = mpc_sie200_get_region_config(&MPC_ISRAM2_DEV, base, limit,
415 (enum mpc_sie200_sec_attr_t*)attr);
416
417 return error_trans(ret);
418 }
419
ISRAM2_MPC_ConfigRegion(uintptr_t base,uintptr_t limit,ARM_MPC_SEC_ATTR attr)420 static int32_t ISRAM2_MPC_ConfigRegion(uintptr_t base,
421 uintptr_t limit,
422 ARM_MPC_SEC_ATTR attr)
423 {
424 enum mpc_sie200_error_t ret;
425
426 ret = mpc_sie200_config_region(&MPC_ISRAM2_DEV, base, limit,
427 (enum mpc_sie200_sec_attr_t)attr);
428
429 return error_trans(ret);
430 }
431
ISRAM2_MPC_EnableInterrupt(void)432 static int32_t ISRAM2_MPC_EnableInterrupt(void)
433 {
434 enum mpc_sie200_error_t ret;
435
436 ret = mpc_sie200_irq_enable(&MPC_ISRAM2_DEV);
437
438 return error_trans(ret);
439 }
440
ISRAM2_MPC_DisableInterrupt(void)441 static void ISRAM2_MPC_DisableInterrupt(void)
442 {
443 mpc_sie200_irq_disable(&MPC_ISRAM2_DEV);
444 }
445
ISRAM2_MPC_ClearInterrupt(void)446 static void ISRAM2_MPC_ClearInterrupt(void)
447 {
448 mpc_sie200_clear_irq(&MPC_ISRAM2_DEV);
449 }
450
ISRAM2_MPC_InterruptState(void)451 static uint32_t ISRAM2_MPC_InterruptState(void)
452 {
453 return mpc_sie200_irq_state(&MPC_ISRAM2_DEV);
454 }
455
ISRAM2_MPC_LockDown(void)456 static int32_t ISRAM2_MPC_LockDown(void)
457 {
458 return mpc_sie200_lock_down(&MPC_ISRAM2_DEV);
459 }
460
461 /* ISRAM2_MPC Driver CMSIS access structure */
462 extern ARM_DRIVER_MPC Driver_ISRAM2_MPC;
463 ARM_DRIVER_MPC Driver_ISRAM2_MPC = {
464 .GetVersion = ARM_MPC_GetVersion,
465 .Initialize = ISRAM2_MPC_Initialize,
466 .Uninitialize = ISRAM2_MPC_Uninitialize,
467 .GetBlockSize = ISRAM2_MPC_GetBlockSize,
468 .GetCtrlConfig = ISRAM2_MPC_GetCtrlConfig,
469 .SetCtrlConfig = ISRAM2_MPC_SetCtrlConfig,
470 .ConfigRegion = ISRAM2_MPC_ConfigRegion,
471 .GetRegionConfig = ISRAM2_MPC_GetRegionConfig,
472 .EnableInterrupt = ISRAM2_MPC_EnableInterrupt,
473 .DisableInterrupt = ISRAM2_MPC_DisableInterrupt,
474 .ClearInterrupt = ISRAM2_MPC_ClearInterrupt,
475 .InterruptState = ISRAM2_MPC_InterruptState,
476 .LockDown = ISRAM2_MPC_LockDown,
477 };
478 #endif /* RTE_ISRAM2_MPC */
479
480 #if (RTE_ISRAM3_MPC)
481 /* Ranges controlled by this ISRAM3_MPC */
482 static const struct mpc_sie200_memory_range_t MPC_ISRAM3_RANGE_S = {
483 .base = MPC_ISRAM3_RANGE_BASE_S,
484 .limit = MPC_ISRAM3_RANGE_LIMIT_S,
485 .range_offset = 0,
486 .attr = MPC_SIE200_SEC_ATTR_SECURE
487 };
488
489 static const struct mpc_sie200_memory_range_t MPC_ISRAM3_RANGE_NS = {
490 .base = MPC_ISRAM3_RANGE_BASE_NS,
491 .limit = MPC_ISRAM3_RANGE_LIMIT_NS,
492 .range_offset = 0,
493 .attr = MPC_SIE200_SEC_ATTR_NONSECURE
494 };
495
496 #define MPC_ISRAM3_RANGE_LIST_LEN 2u
497 static const struct mpc_sie200_memory_range_t*
498 MPC_ISRAM3_RANGE_LIST[MPC_ISRAM3_RANGE_LIST_LEN] = {&MPC_ISRAM3_RANGE_S,
499 &MPC_ISRAM3_RANGE_NS};
500
501 /* ISRAM3_MPC Driver wrapper functions */
ISRAM3_MPC_Initialize(void)502 static int32_t ISRAM3_MPC_Initialize(void)
503 {
504 enum mpc_sie200_error_t ret;
505
506 ret = mpc_sie200_init(&MPC_ISRAM3_DEV,
507 MPC_ISRAM3_RANGE_LIST,
508 MPC_ISRAM3_RANGE_LIST_LEN);
509
510 return error_trans(ret);
511 }
512
ISRAM3_MPC_Uninitialize(void)513 static int32_t ISRAM3_MPC_Uninitialize(void)
514 {
515 /* Nothing to be done */
516 return ARM_DRIVER_OK;
517 }
518
ISRAM3_MPC_GetBlockSize(uint32_t * blk_size)519 static int32_t ISRAM3_MPC_GetBlockSize(uint32_t* blk_size)
520 {
521 enum mpc_sie200_error_t ret;
522
523 ret = mpc_sie200_get_block_size(&MPC_ISRAM3_DEV, blk_size);
524
525 return error_trans(ret);
526 }
527
ISRAM3_MPC_GetCtrlConfig(uint32_t * ctrl_val)528 static int32_t ISRAM3_MPC_GetCtrlConfig(uint32_t* ctrl_val)
529 {
530 enum mpc_sie200_error_t ret;
531
532 ret = mpc_sie200_get_ctrl(&MPC_ISRAM3_DEV, ctrl_val);
533
534 return error_trans(ret);
535 }
536
ISRAM3_MPC_SetCtrlConfig(uint32_t ctrl)537 static int32_t ISRAM3_MPC_SetCtrlConfig(uint32_t ctrl)
538 {
539 enum mpc_sie200_error_t ret;
540
541 ret = mpc_sie200_set_ctrl(&MPC_ISRAM3_DEV, ctrl);
542
543 return error_trans(ret);
544 }
545
ISRAM3_MPC_GetRegionConfig(uintptr_t base,uintptr_t limit,ARM_MPC_SEC_ATTR * attr)546 static int32_t ISRAM3_MPC_GetRegionConfig(uintptr_t base,
547 uintptr_t limit,
548 ARM_MPC_SEC_ATTR* attr)
549 {
550 enum mpc_sie200_error_t ret;
551
552 ret = mpc_sie200_get_region_config(&MPC_ISRAM3_DEV, base, limit,
553 (enum mpc_sie200_sec_attr_t*)attr);
554
555 return error_trans(ret);
556 }
557
ISRAM3_MPC_ConfigRegion(uintptr_t base,uintptr_t limit,ARM_MPC_SEC_ATTR attr)558 static int32_t ISRAM3_MPC_ConfigRegion(uintptr_t base,
559 uintptr_t limit,
560 ARM_MPC_SEC_ATTR attr)
561 {
562 enum mpc_sie200_error_t ret;
563
564 ret = mpc_sie200_config_region(&MPC_ISRAM3_DEV, base, limit,
565 (enum mpc_sie200_sec_attr_t)attr);
566
567 return error_trans(ret);
568 }
569
ISRAM3_MPC_EnableInterrupt(void)570 static int32_t ISRAM3_MPC_EnableInterrupt(void)
571 {
572 enum mpc_sie200_error_t ret;
573
574 ret = mpc_sie200_irq_enable(&MPC_ISRAM3_DEV);
575
576 return error_trans(ret);
577 }
578
ISRAM3_MPC_DisableInterrupt(void)579 static void ISRAM3_MPC_DisableInterrupt(void)
580 {
581 mpc_sie200_irq_disable(&MPC_ISRAM3_DEV);
582 }
583
584
ISRAM3_MPC_ClearInterrupt(void)585 static void ISRAM3_MPC_ClearInterrupt(void)
586 {
587 mpc_sie200_clear_irq(&MPC_ISRAM3_DEV);
588 }
589
ISRAM3_MPC_InterruptState(void)590 static uint32_t ISRAM3_MPC_InterruptState(void)
591 {
592 return mpc_sie200_irq_state(&MPC_ISRAM3_DEV);
593 }
594
ISRAM3_MPC_LockDown(void)595 static int32_t ISRAM3_MPC_LockDown(void)
596 {
597 return mpc_sie200_lock_down(&MPC_ISRAM3_DEV);
598 }
599
600 /* ISRAM3_MPC Driver CMSIS access structure */
601 extern ARM_DRIVER_MPC Driver_ISRAM3_MPC;
602 ARM_DRIVER_MPC Driver_ISRAM3_MPC = {
603 .GetVersion = ARM_MPC_GetVersion,
604 .Initialize = ISRAM3_MPC_Initialize,
605 .Uninitialize = ISRAM3_MPC_Uninitialize,
606 .GetBlockSize = ISRAM3_MPC_GetBlockSize,
607 .GetCtrlConfig = ISRAM3_MPC_GetCtrlConfig,
608 .SetCtrlConfig = ISRAM3_MPC_SetCtrlConfig,
609 .ConfigRegion = ISRAM3_MPC_ConfigRegion,
610 .GetRegionConfig = ISRAM3_MPC_GetRegionConfig,
611 .EnableInterrupt = ISRAM3_MPC_EnableInterrupt,
612 .DisableInterrupt = ISRAM3_MPC_DisableInterrupt,
613 .ClearInterrupt = ISRAM3_MPC_ClearInterrupt,
614 .InterruptState = ISRAM3_MPC_InterruptState,
615 .LockDown = ISRAM3_MPC_LockDown,
616 };
617 #endif /* RTE_ISRAM3_MPC */
618
619 #if (RTE_CODE_SRAM_MPC)
620 /* Ranges controlled by this CODE_SRAM_MPC */
621 static const struct mpc_sie200_memory_range_t MPC_CODE_SRAM_RANGE_S = {
622 .base = MPC_CODE_SRAM_RANGE_BASE_S,
623 .limit = MPC_CODE_SRAM_RANGE_LIMIT_S,
624 .range_offset = 0,
625 .attr = MPC_SIE200_SEC_ATTR_SECURE
626 };
627
628 static const struct mpc_sie200_memory_range_t MPC_CODE_SRAM_RANGE_NS = {
629 .base = MPC_CODE_SRAM_RANGE_BASE_NS,
630 .limit = MPC_CODE_SRAM_RANGE_LIMIT_NS,
631 .range_offset = 0,
632 .attr = MPC_SIE200_SEC_ATTR_NONSECURE
633 };
634
635 #define MPC_CODE_SRAM_RANGE_LIST_LEN 2u
636 static const struct mpc_sie200_memory_range_t*
637 MPC_CODE_SRAM_RANGE_LIST[MPC_CODE_SRAM_RANGE_LIST_LEN] =
638 {&MPC_CODE_SRAM_RANGE_S, &MPC_CODE_SRAM_RANGE_NS};
639
640 /* CODE_SRAM_MPC Driver wrapper functions */
CODE_SRAM_MPC_Initialize(void)641 static int32_t CODE_SRAM_MPC_Initialize(void)
642 {
643 enum mpc_sie200_error_t ret;
644
645 ret = mpc_sie200_init(&MPC_CODE_SRAM_DEV,
646 MPC_CODE_SRAM_RANGE_LIST,
647 MPC_CODE_SRAM_RANGE_LIST_LEN);
648
649 return error_trans(ret);
650 }
651
CODE_SRAM_MPC_Uninitialize(void)652 static int32_t CODE_SRAM_MPC_Uninitialize(void)
653 {
654 /* Nothing to be done */
655 return ARM_DRIVER_OK;
656 }
657
CODE_SRAM_MPC_GetBlockSize(uint32_t * blk_size)658 static int32_t CODE_SRAM_MPC_GetBlockSize(uint32_t* blk_size)
659 {
660 enum mpc_sie200_error_t ret;
661
662 ret = mpc_sie200_get_block_size(&MPC_CODE_SRAM_DEV, blk_size);
663
664 return error_trans(ret);
665 }
666
CODE_SRAM_MPC_GetCtrlConfig(uint32_t * ctrl_val)667 static int32_t CODE_SRAM_MPC_GetCtrlConfig(uint32_t* ctrl_val)
668 {
669 enum mpc_sie200_error_t ret;
670
671 ret = mpc_sie200_get_ctrl(&MPC_CODE_SRAM_DEV, ctrl_val);
672
673 return error_trans(ret);
674 }
675
CODE_SRAM_MPC_SetCtrlConfig(uint32_t ctrl)676 static int32_t CODE_SRAM_MPC_SetCtrlConfig(uint32_t ctrl)
677 {
678 enum mpc_sie200_error_t ret;
679
680 ret = mpc_sie200_set_ctrl(&MPC_CODE_SRAM_DEV, ctrl);
681
682 return error_trans(ret);
683 }
684
CODE_SRAM_MPC_GetRegionConfig(uintptr_t base,uintptr_t limit,ARM_MPC_SEC_ATTR * attr)685 static int32_t CODE_SRAM_MPC_GetRegionConfig(uintptr_t base,
686 uintptr_t limit,
687 ARM_MPC_SEC_ATTR* attr)
688 {
689 enum mpc_sie200_error_t ret;
690
691 ret = mpc_sie200_get_region_config(&MPC_CODE_SRAM_DEV, base, limit,
692 (enum mpc_sie200_sec_attr_t*)attr);
693
694 return error_trans(ret);
695 }
696
CODE_SRAM_MPC_ConfigRegion(uintptr_t base,uintptr_t limit,ARM_MPC_SEC_ATTR attr)697 static int32_t CODE_SRAM_MPC_ConfigRegion(uintptr_t base,
698 uintptr_t limit,
699 ARM_MPC_SEC_ATTR attr)
700 {
701 enum mpc_sie200_error_t ret;
702
703 ret = mpc_sie200_config_region(&MPC_CODE_SRAM_DEV, base, limit,
704 (enum mpc_sie200_sec_attr_t)attr);
705
706 return error_trans(ret);
707 }
708
CODE_SRAM_MPC_EnableInterrupt(void)709 static int32_t CODE_SRAM_MPC_EnableInterrupt(void)
710 {
711 enum mpc_sie200_error_t ret;
712
713 ret = mpc_sie200_irq_enable(&MPC_CODE_SRAM_DEV);
714
715 return error_trans(ret);
716 }
717
CODE_SRAM_MPC_DisableInterrupt(void)718 static void CODE_SRAM_MPC_DisableInterrupt(void)
719 {
720 mpc_sie200_irq_disable(&MPC_CODE_SRAM_DEV);
721 }
722
723
CODE_SRAM_MPC_ClearInterrupt(void)724 static void CODE_SRAM_MPC_ClearInterrupt(void)
725 {
726 mpc_sie200_clear_irq(&MPC_CODE_SRAM_DEV);
727 }
728
CODE_SRAM_MPC_InterruptState(void)729 static uint32_t CODE_SRAM_MPC_InterruptState(void)
730 {
731 return mpc_sie200_irq_state(&MPC_CODE_SRAM_DEV);
732 }
733
CODE_SRAM_MPC_LockDown(void)734 static int32_t CODE_SRAM_MPC_LockDown(void)
735 {
736 return mpc_sie200_lock_down(&MPC_CODE_SRAM_DEV);
737 }
738
739 /* CODE_SRAM_MPC Driver CMSIS access structure */
740 extern ARM_DRIVER_MPC Driver_CODE_SRAM_MPC;
741 ARM_DRIVER_MPC Driver_CODE_SRAM_MPC = {
742 .GetVersion = ARM_MPC_GetVersion,
743 .Initialize = CODE_SRAM_MPC_Initialize,
744 .Uninitialize = CODE_SRAM_MPC_Uninitialize,
745 .GetBlockSize = CODE_SRAM_MPC_GetBlockSize,
746 .GetCtrlConfig = CODE_SRAM_MPC_GetCtrlConfig,
747 .SetCtrlConfig = CODE_SRAM_MPC_SetCtrlConfig,
748 .ConfigRegion = CODE_SRAM_MPC_ConfigRegion,
749 .GetRegionConfig = CODE_SRAM_MPC_GetRegionConfig,
750 .EnableInterrupt = CODE_SRAM_MPC_EnableInterrupt,
751 .DisableInterrupt = CODE_SRAM_MPC_DisableInterrupt,
752 .ClearInterrupt = CODE_SRAM_MPC_ClearInterrupt,
753 .InterruptState = CODE_SRAM_MPC_InterruptState,
754 .LockDown = CODE_SRAM_MPC_LockDown,
755 };
756 #endif /* RTE_CODE_SRAM_MPC */
757
758 #if (RTE_SSRAM1_MPC)
759 /* Ranges controlled by this SSRAM1_MPC */
760 static const struct mpc_sie200_memory_range_t MPC_SSRAM1_RANGE_S = {
761 .base = MPC_SSRAM1_RANGE_BASE_S,
762 .limit = MPC_SSRAM1_RANGE_LIMIT_S,
763 .range_offset = 0,
764 .attr = MPC_SIE200_SEC_ATTR_SECURE
765 };
766
767 static const struct mpc_sie200_memory_range_t MPC_SSRAM1_RANGE_NS = {
768 .base = MPC_SSRAM1_RANGE_BASE_NS,
769 .limit = MPC_SSRAM1_RANGE_LIMIT_NS,
770 .range_offset = 0,
771 .attr = MPC_SIE200_SEC_ATTR_NONSECURE
772 };
773
774 #define MPC_SSRAM1_RANGE_LIST_LEN 2u
775 static const struct mpc_sie200_memory_range_t*
776 MPC_SSRAM1_RANGE_LIST[MPC_SSRAM1_RANGE_LIST_LEN] = {&MPC_SSRAM1_RANGE_S,
777 &MPC_SSRAM1_RANGE_NS};
778
779 /* SSRAM1_MPC Driver wrapper functions */
SSRAM1_MPC_Initialize(void)780 static int32_t SSRAM1_MPC_Initialize(void)
781 {
782 enum mpc_sie200_error_t ret;
783
784 ret = mpc_sie200_init(&MPC_SSRAM1_DEV,
785 MPC_SSRAM1_RANGE_LIST,
786 MPC_SSRAM1_RANGE_LIST_LEN);
787
788 return error_trans(ret);
789 }
790
SSRAM1_MPC_Uninitialize(void)791 static int32_t SSRAM1_MPC_Uninitialize(void)
792 {
793 /* Nothing to be done */
794 return ARM_DRIVER_OK;
795 }
796
SSRAM1_MPC_GetBlockSize(uint32_t * blk_size)797 static int32_t SSRAM1_MPC_GetBlockSize(uint32_t* blk_size)
798 {
799 enum mpc_sie200_error_t ret;
800
801 ret = mpc_sie200_get_block_size(&MPC_SSRAM1_DEV, blk_size);
802
803 return error_trans(ret);
804 }
805
SSRAM1_MPC_GetCtrlConfig(uint32_t * ctrl_val)806 static int32_t SSRAM1_MPC_GetCtrlConfig(uint32_t* ctrl_val)
807 {
808 enum mpc_sie200_error_t ret;
809
810 ret = mpc_sie200_get_ctrl(&MPC_SSRAM1_DEV, ctrl_val);
811
812 return error_trans(ret);
813 }
814
SSRAM1_MPC_SetCtrlConfig(uint32_t ctrl)815 static int32_t SSRAM1_MPC_SetCtrlConfig(uint32_t ctrl)
816 {
817 enum mpc_sie200_error_t ret;
818
819 ret = mpc_sie200_set_ctrl(&MPC_SSRAM1_DEV, ctrl);
820
821 return error_trans(ret);
822 }
823
SSRAM1_MPC_GetRegionConfig(uintptr_t base,uintptr_t limit,ARM_MPC_SEC_ATTR * attr)824 static int32_t SSRAM1_MPC_GetRegionConfig(uintptr_t base,
825 uintptr_t limit,
826 ARM_MPC_SEC_ATTR* attr)
827 {
828 enum mpc_sie200_error_t ret;
829
830 ret = mpc_sie200_get_region_config(&MPC_SSRAM1_DEV, base, limit,
831 (enum mpc_sie200_sec_attr_t*)attr);
832
833 return error_trans(ret);
834 }
835
SSRAM1_MPC_ConfigRegion(uintptr_t base,uintptr_t limit,ARM_MPC_SEC_ATTR attr)836 static int32_t SSRAM1_MPC_ConfigRegion(uintptr_t base,
837 uintptr_t limit,
838 ARM_MPC_SEC_ATTR attr)
839 {
840 enum mpc_sie200_error_t ret;
841
842 ret = mpc_sie200_config_region(&MPC_SSRAM1_DEV, base, limit,
843 (enum mpc_sie200_sec_attr_t)attr);
844
845 return error_trans(ret);
846 }
847
SSRAM1_MPC_EnableInterrupt(void)848 static int32_t SSRAM1_MPC_EnableInterrupt(void)
849 {
850 enum mpc_sie200_error_t ret;
851
852 ret = mpc_sie200_irq_enable(&MPC_SSRAM1_DEV);
853
854 return error_trans(ret);
855 }
856
SSRAM1_MPC_DisableInterrupt(void)857 static void SSRAM1_MPC_DisableInterrupt(void)
858 {
859 mpc_sie200_irq_disable(&MPC_SSRAM1_DEV);
860 }
861
862
SSRAM1_MPC_ClearInterrupt(void)863 static void SSRAM1_MPC_ClearInterrupt(void)
864 {
865 mpc_sie200_clear_irq(&MPC_SSRAM1_DEV);
866 }
867
SSRAM1_MPC_InterruptState(void)868 static uint32_t SSRAM1_MPC_InterruptState(void)
869 {
870 return mpc_sie200_irq_state(&MPC_SSRAM1_DEV);
871 }
872
SSRAM1_MPC_LockDown(void)873 static int32_t SSRAM1_MPC_LockDown(void)
874 {
875 return mpc_sie200_lock_down(&MPC_SSRAM1_DEV);
876 }
877
878 /* SSRAM1_MPC Driver CMSIS access structure */
879 extern ARM_DRIVER_MPC Driver_SRAM1_MPC;
880 ARM_DRIVER_MPC Driver_SRAM1_MPC = {
881 .GetVersion = ARM_MPC_GetVersion,
882 .Initialize = SSRAM1_MPC_Initialize,
883 .Uninitialize = SSRAM1_MPC_Uninitialize,
884 .GetBlockSize = SSRAM1_MPC_GetBlockSize,
885 .GetCtrlConfig = SSRAM1_MPC_GetCtrlConfig,
886 .SetCtrlConfig = SSRAM1_MPC_SetCtrlConfig,
887 .ConfigRegion = SSRAM1_MPC_ConfigRegion,
888 .GetRegionConfig = SSRAM1_MPC_GetRegionConfig,
889 .EnableInterrupt = SSRAM1_MPC_EnableInterrupt,
890 .DisableInterrupt = SSRAM1_MPC_DisableInterrupt,
891 .ClearInterrupt = SSRAM1_MPC_ClearInterrupt,
892 .InterruptState = SSRAM1_MPC_InterruptState,
893 .LockDown = SSRAM1_MPC_LockDown,
894 };
895 #endif /* RTE_SSRAM1_MPC */
896
897 #if (RTE_SSRAM2_MPC)
898 /* Ranges controlled by this SSRAM2_MPC */
899 static const struct mpc_sie200_memory_range_t MPC_SSRAM2_RANGE_S = {
900 .base = MPC_SSRAM2_RANGE_BASE_S,
901 .limit = MPC_SSRAM2_RANGE_LIMIT_S,
902 .range_offset = 0,
903 .attr = MPC_SIE200_SEC_ATTR_SECURE
904 };
905
906 static const struct mpc_sie200_memory_range_t MPC_SSRAM2_RANGE_NS = {
907 .base = MPC_SSRAM2_RANGE_BASE_NS,
908 .limit = MPC_SSRAM2_RANGE_LIMIT_NS,
909 .range_offset = 0,
910 .attr = MPC_SIE200_SEC_ATTR_NONSECURE
911 };
912
913 #define MPC_SSRAM2_RANGE_LIST_LEN 2u
914 static const struct mpc_sie200_memory_range_t*
915 MPC_SSRAM2_RANGE_LIST[MPC_SSRAM2_RANGE_LIST_LEN] = {&MPC_SSRAM2_RANGE_S,
916 &MPC_SSRAM2_RANGE_NS};
917
918 /* SSRAM2_MPC Driver wrapper functions */
SSRAM2_MPC_Initialize(void)919 static int32_t SSRAM2_MPC_Initialize(void)
920 {
921 enum mpc_sie200_error_t ret;
922
923 ret = mpc_sie200_init(&MPC_SSRAM2_DEV,
924 MPC_SSRAM2_RANGE_LIST,
925 MPC_SSRAM2_RANGE_LIST_LEN);
926
927 return error_trans(ret);
928 }
929
SSRAM2_MPC_Uninitialize(void)930 static int32_t SSRAM2_MPC_Uninitialize(void)
931 {
932 /* Nothing to be done */
933 return ARM_DRIVER_OK;
934 }
935
SSRAM2_MPC_GetBlockSize(uint32_t * blk_size)936 static int32_t SSRAM2_MPC_GetBlockSize(uint32_t* blk_size)
937 {
938 enum mpc_sie200_error_t ret;
939
940 ret = mpc_sie200_get_block_size(&MPC_SSRAM2_DEV, blk_size);
941
942 return error_trans(ret);
943 }
944
SSRAM2_MPC_GetCtrlConfig(uint32_t * ctrl_val)945 static int32_t SSRAM2_MPC_GetCtrlConfig(uint32_t* ctrl_val)
946 {
947 enum mpc_sie200_error_t ret;
948
949 ret = mpc_sie200_get_ctrl(&MPC_SSRAM2_DEV, ctrl_val);
950
951 return error_trans(ret);
952 }
953
SSRAM2_MPC_SetCtrlConfig(uint32_t ctrl)954 static int32_t SSRAM2_MPC_SetCtrlConfig(uint32_t ctrl)
955 {
956 enum mpc_sie200_error_t ret;
957
958 ret = mpc_sie200_set_ctrl(&MPC_SSRAM2_DEV, ctrl);
959
960 return error_trans(ret);
961 }
962
SSRAM2_MPC_GetRegionConfig(uintptr_t base,uintptr_t limit,ARM_MPC_SEC_ATTR * attr)963 static int32_t SSRAM2_MPC_GetRegionConfig(uintptr_t base,
964 uintptr_t limit,
965 ARM_MPC_SEC_ATTR* attr)
966 {
967 enum mpc_sie200_error_t ret;
968
969 ret = mpc_sie200_get_region_config(&MPC_SSRAM2_DEV, base, limit,
970 (enum mpc_sie200_sec_attr_t*)attr);
971
972 return error_trans(ret);
973 }
974
SSRAM2_MPC_ConfigRegion(uintptr_t base,uintptr_t limit,ARM_MPC_SEC_ATTR attr)975 static int32_t SSRAM2_MPC_ConfigRegion(uintptr_t base,
976 uintptr_t limit,
977 ARM_MPC_SEC_ATTR attr)
978 {
979 enum mpc_sie200_error_t ret;
980
981 ret = mpc_sie200_config_region(&MPC_SSRAM2_DEV, base, limit,
982 (enum mpc_sie200_sec_attr_t)attr);
983
984 return error_trans(ret);
985 }
986
SSRAM2_MPC_EnableInterrupt(void)987 static int32_t SSRAM2_MPC_EnableInterrupt(void)
988 {
989 enum mpc_sie200_error_t ret;
990
991 ret = mpc_sie200_irq_enable(&MPC_SSRAM2_DEV);
992
993 return error_trans(ret);
994 }
995
SSRAM2_MPC_DisableInterrupt(void)996 static void SSRAM2_MPC_DisableInterrupt(void)
997 {
998 mpc_sie200_irq_disable(&MPC_SSRAM2_DEV);
999 }
1000
1001
SSRAM2_MPC_ClearInterrupt(void)1002 static void SSRAM2_MPC_ClearInterrupt(void)
1003 {
1004 mpc_sie200_clear_irq(&MPC_SSRAM2_DEV);
1005 }
1006
SSRAM2_MPC_InterruptState(void)1007 static uint32_t SSRAM2_MPC_InterruptState(void)
1008 {
1009 return mpc_sie200_irq_state(&MPC_SSRAM2_DEV);
1010 }
1011
SSRAM2_MPC_LockDown(void)1012 static int32_t SSRAM2_MPC_LockDown(void)
1013 {
1014 return mpc_sie200_lock_down(&MPC_SSRAM2_DEV);
1015 }
1016
1017 /* SSRAM2_MPC Driver CMSIS access structure */
1018 extern ARM_DRIVER_MPC Driver_SRAM2_MPC;
1019 ARM_DRIVER_MPC Driver_SRAM2_MPC = {
1020 .GetVersion = ARM_MPC_GetVersion,
1021 .Initialize = SSRAM2_MPC_Initialize,
1022 .Uninitialize = SSRAM2_MPC_Uninitialize,
1023 .GetBlockSize = SSRAM2_MPC_GetBlockSize,
1024 .GetCtrlConfig = SSRAM2_MPC_GetCtrlConfig,
1025 .SetCtrlConfig = SSRAM2_MPC_SetCtrlConfig,
1026 .ConfigRegion = SSRAM2_MPC_ConfigRegion,
1027 .GetRegionConfig = SSRAM2_MPC_GetRegionConfig,
1028 .EnableInterrupt = SSRAM2_MPC_EnableInterrupt,
1029 .DisableInterrupt = SSRAM2_MPC_DisableInterrupt,
1030 .ClearInterrupt = SSRAM2_MPC_ClearInterrupt,
1031 .InterruptState = SSRAM2_MPC_InterruptState,
1032 .LockDown = SSRAM2_MPC_LockDown,
1033 };
1034 #endif /* RTE_SSRAM2_MPC */
1035
1036 #if (RTE_SSRAM3_MPC)
1037 /* Ranges controlled by this SSRAM3_MPC */
1038 static const struct mpc_sie200_memory_range_t MPC_SSRAM3_RANGE_S = {
1039 .base = MPC_SSRAM3_RANGE_BASE_S,
1040 .limit = MPC_SSRAM3_RANGE_LIMIT_S,
1041 .range_offset = 0,
1042 .attr = MPC_SIE200_SEC_ATTR_SECURE
1043 };
1044
1045 static const struct mpc_sie200_memory_range_t MPC_SSRAM3_RANGE_NS = {
1046 .base = MPC_SSRAM3_RANGE_BASE_NS,
1047 .limit = MPC_SSRAM3_RANGE_LIMIT_NS,
1048 .range_offset = 0,
1049 .attr = MPC_SIE200_SEC_ATTR_NONSECURE
1050 };
1051
1052 #define MPC_SSRAM3_RANGE_LIST_LEN 2u
1053 static const struct mpc_sie200_memory_range_t*
1054 MPC_SSRAM3_RANGE_LIST[MPC_SSRAM3_RANGE_LIST_LEN] = {&MPC_SSRAM3_RANGE_S,
1055 &MPC_SSRAM3_RANGE_NS};
1056
1057 /* SSRAM3_MPC Driver wrapper functions */
SSRAM3_MPC_Initialize(void)1058 static int32_t SSRAM3_MPC_Initialize(void)
1059 {
1060 enum mpc_sie200_error_t ret;
1061
1062 ret = mpc_sie200_init(&MPC_SSRAM3_DEV,
1063 MPC_SSRAM3_RANGE_LIST,
1064 MPC_SSRAM3_RANGE_LIST_LEN);
1065
1066 return error_trans(ret);
1067 }
1068
SSRAM3_MPC_Uninitialize(void)1069 static int32_t SSRAM3_MPC_Uninitialize(void)
1070 {
1071 /* Nothing to be done */
1072 return ARM_DRIVER_OK;
1073 }
1074
SSRAM3_MPC_GetBlockSize(uint32_t * blk_size)1075 static int32_t SSRAM3_MPC_GetBlockSize(uint32_t* blk_size)
1076 {
1077 enum mpc_sie200_error_t ret;
1078
1079 ret = mpc_sie200_get_block_size(&MPC_SSRAM3_DEV, blk_size);
1080
1081 return error_trans(ret);
1082 }
1083
SSRAM3_MPC_GetCtrlConfig(uint32_t * ctrl_val)1084 static int32_t SSRAM3_MPC_GetCtrlConfig(uint32_t* ctrl_val)
1085 {
1086 enum mpc_sie200_error_t ret;
1087
1088 ret = mpc_sie200_get_ctrl(&MPC_SSRAM3_DEV, ctrl_val);
1089
1090 return error_trans(ret);
1091 }
1092
SSRAM3_MPC_SetCtrlConfig(uint32_t ctrl)1093 static int32_t SSRAM3_MPC_SetCtrlConfig(uint32_t ctrl)
1094 {
1095 enum mpc_sie200_error_t ret;
1096
1097 ret = mpc_sie200_set_ctrl(&MPC_SSRAM3_DEV, ctrl);
1098
1099 return error_trans(ret);
1100 }
1101
SSRAM3_MPC_GetRegionConfig(uintptr_t base,uintptr_t limit,ARM_MPC_SEC_ATTR * attr)1102 static int32_t SSRAM3_MPC_GetRegionConfig(uintptr_t base,
1103 uintptr_t limit,
1104 ARM_MPC_SEC_ATTR* attr)
1105 {
1106 enum mpc_sie200_error_t ret;
1107
1108 ret = mpc_sie200_get_region_config(&MPC_SSRAM3_DEV, base, limit,
1109 (enum mpc_sie200_sec_attr_t*)attr);
1110
1111 return error_trans(ret);
1112 }
1113
SSRAM3_MPC_ConfigRegion(uintptr_t base,uintptr_t limit,ARM_MPC_SEC_ATTR attr)1114 static int32_t SSRAM3_MPC_ConfigRegion(uintptr_t base,
1115 uintptr_t limit,
1116 ARM_MPC_SEC_ATTR attr)
1117 {
1118 enum mpc_sie200_error_t ret;
1119
1120 ret = mpc_sie200_config_region(&MPC_SSRAM3_DEV, base, limit,
1121 (enum mpc_sie200_sec_attr_t)attr);
1122
1123 return error_trans(ret);
1124 }
1125
SSRAM3_MPC_EnableInterrupt(void)1126 static int32_t SSRAM3_MPC_EnableInterrupt(void)
1127 {
1128 enum mpc_sie200_error_t ret;
1129
1130 ret = mpc_sie200_irq_enable(&MPC_SSRAM3_DEV);
1131
1132 return error_trans(ret);
1133 }
1134
SSRAM3_MPC_DisableInterrupt(void)1135 static void SSRAM3_MPC_DisableInterrupt(void)
1136 {
1137 mpc_sie200_irq_disable(&MPC_SSRAM3_DEV);
1138 }
1139
1140
SSRAM3_MPC_ClearInterrupt(void)1141 static void SSRAM3_MPC_ClearInterrupt(void)
1142 {
1143 mpc_sie200_clear_irq(&MPC_SSRAM3_DEV);
1144 }
1145
SSRAM3_MPC_InterruptState(void)1146 static uint32_t SSRAM3_MPC_InterruptState(void)
1147 {
1148 return mpc_sie200_irq_state(&MPC_SSRAM3_DEV);
1149 }
1150
SSRAM3_MPC_LockDown(void)1151 static int32_t SSRAM3_MPC_LockDown(void)
1152 {
1153 return mpc_sie200_lock_down(&MPC_SSRAM3_DEV);
1154 }
1155
1156 /* SSRAM3_MPC Driver CMSIS access structure */
1157 extern ARM_DRIVER_MPC Driver_SSRAM3_MPC;
1158 ARM_DRIVER_MPC Driver_SSRAM3_MPC = {
1159 .GetVersion = ARM_MPC_GetVersion,
1160 .Initialize = SSRAM3_MPC_Initialize,
1161 .Uninitialize = SSRAM3_MPC_Uninitialize,
1162 .GetBlockSize = SSRAM3_MPC_GetBlockSize,
1163 .GetCtrlConfig = SSRAM3_MPC_GetCtrlConfig,
1164 .SetCtrlConfig = SSRAM3_MPC_SetCtrlConfig,
1165 .ConfigRegion = SSRAM3_MPC_ConfigRegion,
1166 .GetRegionConfig = SSRAM3_MPC_GetRegionConfig,
1167 .EnableInterrupt = SSRAM3_MPC_EnableInterrupt,
1168 .DisableInterrupt = SSRAM3_MPC_DisableInterrupt,
1169 .ClearInterrupt = SSRAM3_MPC_ClearInterrupt,
1170 .InterruptState = SSRAM3_MPC_InterruptState,
1171 .LockDown = SSRAM3_MPC_LockDown,
1172 };
1173 #endif /* RTE_SSRAM3_MPC */
1174
1175 #if (RTE_QSPI_MPC)
1176 /* Ranges controlled by this QSPI_MPC */
1177 static const struct mpc_sie200_memory_range_t MPC_QSPI_RANGE_S = {
1178 .base = MPC_QSPI_RANGE_BASE_S,
1179 .limit = MPC_QSPI_RANGE_LIMIT_S,
1180 .range_offset = 0,
1181 .attr = MPC_SIE200_SEC_ATTR_SECURE
1182 };
1183
1184 static const struct mpc_sie200_memory_range_t MPC_QSPI_RANGE_NS = {
1185 .base = MPC_QSPI_RANGE_BASE_NS,
1186 .limit = MPC_QSPI_RANGE_LIMIT_NS,
1187 .range_offset = 0,
1188 .attr = MPC_SIE200_SEC_ATTR_NONSECURE
1189 };
1190
1191 #define MPC_QSPI_RANGE_LIST_LEN 2u
1192 static const struct mpc_sie200_memory_range_t*
1193 MPC_QSPI_RANGE_LIST[MPC_QSPI_RANGE_LIST_LEN] = {&MPC_QSPI_RANGE_S,
1194 &MPC_QSPI_RANGE_NS};
1195
1196 /* QSPI_MPC Driver wrapper functions */
QSPI_MPC_Initialize(void)1197 static int32_t QSPI_MPC_Initialize(void)
1198 {
1199 enum mpc_sie200_error_t ret;
1200
1201 ret = mpc_sie200_init(&MPC_QSPI_DEV,
1202 MPC_QSPI_RANGE_LIST,
1203 MPC_QSPI_RANGE_LIST_LEN);
1204
1205 return error_trans(ret);
1206 }
1207
QSPI_MPC_Uninitialize(void)1208 static int32_t QSPI_MPC_Uninitialize(void)
1209 {
1210 /* Nothing to be done */
1211 return ARM_DRIVER_OK;
1212 }
1213
QSPI_MPC_GetBlockSize(uint32_t * blk_size)1214 static int32_t QSPI_MPC_GetBlockSize(uint32_t* blk_size)
1215 {
1216 enum mpc_sie200_error_t ret;
1217
1218 ret = mpc_sie200_get_block_size(&MPC_QSPI_DEV, blk_size);
1219
1220 return error_trans(ret);
1221 }
1222
QSPI_MPC_GetCtrlConfig(uint32_t * ctrl_val)1223 static int32_t QSPI_MPC_GetCtrlConfig(uint32_t* ctrl_val)
1224 {
1225 enum mpc_sie200_error_t ret;
1226
1227 ret = mpc_sie200_get_ctrl(&MPC_QSPI_DEV, ctrl_val);
1228
1229 return error_trans(ret);
1230 }
1231
QSPI_MPC_SetCtrlConfig(uint32_t ctrl)1232 static int32_t QSPI_MPC_SetCtrlConfig(uint32_t ctrl)
1233 {
1234 enum mpc_sie200_error_t ret;
1235
1236 ret = mpc_sie200_set_ctrl(&MPC_QSPI_DEV, ctrl);
1237
1238 return error_trans(ret);
1239 }
1240
QSPI_MPC_GetRegionConfig(uintptr_t base,uintptr_t limit,ARM_MPC_SEC_ATTR * attr)1241 static int32_t QSPI_MPC_GetRegionConfig(uintptr_t base,
1242 uintptr_t limit,
1243 ARM_MPC_SEC_ATTR* attr)
1244 {
1245 enum mpc_sie200_error_t ret;
1246
1247 ret = mpc_sie200_get_region_config(&MPC_QSPI_DEV, base, limit,
1248 (enum mpc_sie200_sec_attr_t*)attr);
1249
1250 return error_trans(ret);
1251 }
1252
QSPI_MPC_ConfigRegion(uintptr_t base,uintptr_t limit,ARM_MPC_SEC_ATTR attr)1253 static int32_t QSPI_MPC_ConfigRegion(uintptr_t base,
1254 uintptr_t limit,
1255 ARM_MPC_SEC_ATTR attr)
1256 {
1257 enum mpc_sie200_error_t ret;
1258
1259 ret = mpc_sie200_config_region(&MPC_QSPI_DEV, base, limit,
1260 (enum mpc_sie200_sec_attr_t)attr);
1261
1262 return error_trans(ret);
1263 }
1264
QSPI_MPC_EnableInterrupt(void)1265 static int32_t QSPI_MPC_EnableInterrupt(void)
1266 {
1267 enum mpc_sie200_error_t ret;
1268
1269 ret = mpc_sie200_irq_enable(&MPC_QSPI_DEV);
1270
1271 return error_trans(ret);
1272 }
1273
QSPI_MPC_DisableInterrupt(void)1274 static void QSPI_MPC_DisableInterrupt(void)
1275 {
1276 mpc_sie200_irq_disable(&MPC_QSPI_DEV);
1277 }
1278
1279
QSPI_MPC_ClearInterrupt(void)1280 static void QSPI_MPC_ClearInterrupt(void)
1281 {
1282 mpc_sie200_clear_irq(&MPC_QSPI_DEV);
1283 }
1284
QSPI_MPC_InterruptState(void)1285 static uint32_t QSPI_MPC_InterruptState(void)
1286 {
1287 return mpc_sie200_irq_state(&MPC_QSPI_DEV);
1288 }
1289
QSPI_MPC_LockDown(void)1290 static int32_t QSPI_MPC_LockDown(void)
1291 {
1292 return mpc_sie200_lock_down(&MPC_QSPI_DEV);
1293 }
1294
1295 /* QSPI1_MPC Driver CMSIS access structure */
1296 extern ARM_DRIVER_MPC Driver_QSPI_MPC;
1297 ARM_DRIVER_MPC Driver_QSPI_MPC = {
1298 .GetVersion = ARM_MPC_GetVersion,
1299 .Initialize = QSPI_MPC_Initialize,
1300 .Uninitialize = QSPI_MPC_Uninitialize,
1301 .GetBlockSize = QSPI_MPC_GetBlockSize,
1302 .GetCtrlConfig = QSPI_MPC_GetCtrlConfig,
1303 .SetCtrlConfig = QSPI_MPC_SetCtrlConfig,
1304 .ConfigRegion = QSPI_MPC_ConfigRegion,
1305 .GetRegionConfig = QSPI_MPC_GetRegionConfig,
1306 .EnableInterrupt = QSPI_MPC_EnableInterrupt,
1307 .DisableInterrupt = QSPI_MPC_DisableInterrupt,
1308 .ClearInterrupt = QSPI_MPC_ClearInterrupt,
1309 .InterruptState = QSPI_MPC_InterruptState,
1310 .LockDown = QSPI_MPC_LockDown,
1311 };
1312 #endif /* RTE_QSPI_MPC */
1313
1314 #if (RTE_EFLASH0_MPC)
1315 /* Ranges controlled by this EFLASH0_MPC */
1316 static const struct mpc_sie200_memory_range_t MPC_EFLASH0_RANGE_S = {
1317 .base = MPC_EFLASH0_RANGE_BASE_S,
1318 .limit = MPC_EFLASH0_RANGE_LIMIT_S,
1319 .range_offset = 0,
1320 .attr = MPC_SIE200_SEC_ATTR_SECURE
1321 };
1322
1323 static const struct mpc_sie200_memory_range_t MPC_EFLASH0_RANGE_NS = {
1324 .base = MPC_EFLASH0_RANGE_BASE_NS,
1325 .limit = MPC_EFLASH0_RANGE_LIMIT_NS,
1326 .range_offset = 0,
1327 .attr = MPC_SIE200_SEC_ATTR_NONSECURE
1328 };
1329
1330 #define MPC_EFLASH0_RANGE_LIST_LEN 2u
1331 static const struct mpc_sie200_memory_range_t*
1332 MPC_EFLASH0_RANGE_LIST[MPC_EFLASH0_RANGE_LIST_LEN]=
1333 {&MPC_EFLASH0_RANGE_S, &MPC_EFLASH0_RANGE_NS};
1334
1335 /* EFLASH0_MPC Driver wrapper functions */
EFLASH0_MPC_Initialize(void)1336 static int32_t EFLASH0_MPC_Initialize(void)
1337 {
1338 enum mpc_sie200_error_t ret;
1339
1340 ret = mpc_sie200_init(&MPC_EFLASH0_DEV,
1341 MPC_EFLASH0_RANGE_LIST,
1342 MPC_EFLASH0_RANGE_LIST_LEN);
1343
1344 return error_trans(ret);
1345 }
1346
EFLASH0_MPC_Uninitialize(void)1347 static int32_t EFLASH0_MPC_Uninitialize(void)
1348 {
1349 /* Nothing to be done */
1350 return ARM_DRIVER_OK;
1351 }
1352
EFLASH0_MPC_GetBlockSize(uint32_t * blk_size)1353 static int32_t EFLASH0_MPC_GetBlockSize(uint32_t* blk_size)
1354 {
1355 enum mpc_sie200_error_t ret;
1356
1357 ret = mpc_sie200_get_block_size(&MPC_EFLASH0_DEV, blk_size);
1358
1359 return error_trans(ret);
1360 }
1361
EFLASH0_MPC_GetCtrlConfig(uint32_t * ctrl_val)1362 static int32_t EFLASH0_MPC_GetCtrlConfig(uint32_t* ctrl_val)
1363 {
1364 enum mpc_sie200_error_t ret;
1365
1366 ret = mpc_sie200_get_ctrl(&MPC_EFLASH0_DEV, ctrl_val);
1367
1368 return error_trans(ret);
1369 }
1370
EFLASH0_MPC_SetCtrlConfig(uint32_t ctrl)1371 static int32_t EFLASH0_MPC_SetCtrlConfig(uint32_t ctrl)
1372 {
1373 enum mpc_sie200_error_t ret;
1374
1375 ret = mpc_sie200_set_ctrl(&MPC_EFLASH0_DEV, ctrl);
1376
1377 return error_trans(ret);
1378 }
1379
EFLASH0_MPC_GetRegionConfig(uintptr_t base,uintptr_t limit,ARM_MPC_SEC_ATTR * attr)1380 static int32_t EFLASH0_MPC_GetRegionConfig(uintptr_t base,
1381 uintptr_t limit,
1382 ARM_MPC_SEC_ATTR* attr)
1383 {
1384 enum mpc_sie200_error_t ret;
1385
1386 ret = mpc_sie200_get_region_config(&MPC_EFLASH0_DEV, base, limit,
1387 (enum mpc_sie200_sec_attr_t*)attr);
1388
1389 return error_trans(ret);
1390 }
1391
EFLASH0_MPC_ConfigRegion(uintptr_t base,uintptr_t limit,ARM_MPC_SEC_ATTR attr)1392 static int32_t EFLASH0_MPC_ConfigRegion(uintptr_t base,
1393 uintptr_t limit,
1394 ARM_MPC_SEC_ATTR attr)
1395 {
1396 enum mpc_sie200_error_t ret;
1397
1398 ret = mpc_sie200_config_region(&MPC_EFLASH0_DEV, base, limit,
1399 (enum mpc_sie200_sec_attr_t)attr);
1400
1401 return error_trans(ret);
1402 }
1403
EFLASH0_MPC_EnableInterrupt(void)1404 static int32_t EFLASH0_MPC_EnableInterrupt(void)
1405 {
1406 enum mpc_sie200_error_t ret;
1407
1408 ret = mpc_sie200_irq_enable(&MPC_EFLASH0_DEV);
1409
1410 return error_trans(ret);
1411 }
1412
EFLASH0_MPC_DisableInterrupt(void)1413 static void EFLASH0_MPC_DisableInterrupt(void)
1414 {
1415 mpc_sie200_irq_disable(&MPC_EFLASH0_DEV);
1416 }
1417
1418
EFLASH0_MPC_ClearInterrupt(void)1419 static void EFLASH0_MPC_ClearInterrupt(void)
1420 {
1421 mpc_sie200_clear_irq(&MPC_EFLASH0_DEV);
1422 }
1423
EFLASH0_MPC_InterruptState(void)1424 static uint32_t EFLASH0_MPC_InterruptState(void)
1425 {
1426 return mpc_sie200_irq_state(&MPC_EFLASH0_DEV);
1427 }
1428
EFLASH0_MPC_LockDown(void)1429 static int32_t EFLASH0_MPC_LockDown(void)
1430 {
1431 return mpc_sie200_lock_down(&MPC_EFLASH0_DEV);
1432 }
1433
1434 /* EFLASH0_MPC Driver CMSIS access structure */
1435 extern ARM_DRIVER_MPC Driver_EFLASH0_MPC;
1436 ARM_DRIVER_MPC Driver_EFLASH0_MPC = {
1437 .GetVersion = ARM_MPC_GetVersion,
1438 .Initialize = EFLASH0_MPC_Initialize,
1439 .Uninitialize = EFLASH0_MPC_Uninitialize,
1440 .GetBlockSize = EFLASH0_MPC_GetBlockSize,
1441 .GetCtrlConfig = EFLASH0_MPC_GetCtrlConfig,
1442 .SetCtrlConfig = EFLASH0_MPC_SetCtrlConfig,
1443 .ConfigRegion = EFLASH0_MPC_ConfigRegion,
1444 .GetRegionConfig = EFLASH0_MPC_GetRegionConfig,
1445 .EnableInterrupt = EFLASH0_MPC_EnableInterrupt,
1446 .DisableInterrupt = EFLASH0_MPC_DisableInterrupt,
1447 .ClearInterrupt = EFLASH0_MPC_ClearInterrupt,
1448 .InterruptState = EFLASH0_MPC_InterruptState,
1449 .LockDown = EFLASH0_MPC_LockDown,
1450 };
1451 #endif /* RTE_EFLASH0_MPC */
1452
1453 #if (RTE_EFLASH1_MPC)
1454 /* Ranges controlled by this EFLASH1_MPC */
1455 static const struct mpc_sie200_memory_range_t MPC_EFLASH1_RANGE_S = {
1456 .base = MPC_EFLASH1_RANGE_BASE_S,
1457 .limit = MPC_EFLASH1_RANGE_LIMIT_S,
1458 .range_offset = 0,
1459 .attr = MPC_SIE200_SEC_ATTR_SECURE
1460 };
1461
1462 static const struct mpc_sie200_memory_range_t MPC_EFLASH1_RANGE_NS = {
1463 .base = MPC_EFLASH1_RANGE_BASE_NS,
1464 .limit = MPC_EFLASH1_RANGE_LIMIT_NS,
1465 .range_offset = 0,
1466 .attr = MPC_SIE200_SEC_ATTR_NONSECURE
1467 };
1468
1469 #define MPC_EFLASH1_RANGE_LIST_LEN 2u
1470 static const struct mpc_sie200_memory_range_t*
1471 MPC_EFLASH1_RANGE_LIST[MPC_EFLASH1_RANGE_LIST_LEN]=
1472 {&MPC_EFLASH1_RANGE_S, &MPC_EFLASH1_RANGE_NS};
1473
1474 /* EFLASH1_MPC Driver wrapper functions */
EFLASH1_MPC_Initialize(void)1475 static int32_t EFLASH1_MPC_Initialize(void)
1476 {
1477 enum mpc_sie200_error_t ret;
1478
1479 ret = mpc_sie200_init(&MPC_EFLASH1_DEV,
1480 MPC_EFLASH1_RANGE_LIST,
1481 MPC_EFLASH1_RANGE_LIST_LEN);
1482
1483 return error_trans(ret);
1484 }
1485
EFLASH1_MPC_Uninitialize(void)1486 static int32_t EFLASH1_MPC_Uninitialize(void)
1487 {
1488 /* Nothing to be done */
1489 return ARM_DRIVER_OK;
1490 }
1491
EFLASH1_MPC_GetBlockSize(uint32_t * blk_size)1492 static int32_t EFLASH1_MPC_GetBlockSize(uint32_t* blk_size)
1493 {
1494 enum mpc_sie200_error_t ret;
1495
1496 ret = mpc_sie200_get_block_size(&MPC_EFLASH1_DEV, blk_size);
1497
1498 return error_trans(ret);
1499 }
1500
EFLASH1_MPC_GetCtrlConfig(uint32_t * ctrl_val)1501 static int32_t EFLASH1_MPC_GetCtrlConfig(uint32_t* ctrl_val)
1502 {
1503 enum mpc_sie200_error_t ret;
1504
1505 ret = mpc_sie200_get_ctrl(&MPC_EFLASH1_DEV, ctrl_val);
1506
1507 return error_trans(ret);
1508 }
1509
EFLASH1_MPC_SetCtrlConfig(uint32_t ctrl)1510 static int32_t EFLASH1_MPC_SetCtrlConfig(uint32_t ctrl)
1511 {
1512 enum mpc_sie200_error_t ret;
1513
1514 ret = mpc_sie200_set_ctrl(&MPC_EFLASH1_DEV, ctrl);
1515
1516 return error_trans(ret);
1517 }
1518
EFLASH1_MPC_GetRegionConfig(uintptr_t base,uintptr_t limit,ARM_MPC_SEC_ATTR * attr)1519 static int32_t EFLASH1_MPC_GetRegionConfig(uintptr_t base,
1520 uintptr_t limit,
1521 ARM_MPC_SEC_ATTR* attr)
1522 {
1523 enum mpc_sie200_error_t ret;
1524
1525 ret = mpc_sie200_get_region_config(&MPC_EFLASH1_DEV, base, limit,
1526 (enum mpc_sie200_sec_attr_t*)attr);
1527
1528 return error_trans(ret);
1529 }
1530
EFLASH1_MPC_ConfigRegion(uintptr_t base,uintptr_t limit,ARM_MPC_SEC_ATTR attr)1531 static int32_t EFLASH1_MPC_ConfigRegion(uintptr_t base,
1532 uintptr_t limit,
1533 ARM_MPC_SEC_ATTR attr)
1534 {
1535 enum mpc_sie200_error_t ret;
1536
1537 ret = mpc_sie200_config_region(&MPC_EFLASH1_DEV, base, limit,
1538 (enum mpc_sie200_sec_attr_t)attr);
1539
1540 return error_trans(ret);
1541 }
1542
EFLASH1_MPC_EnableInterrupt(void)1543 static int32_t EFLASH1_MPC_EnableInterrupt(void)
1544 {
1545 enum mpc_sie200_error_t ret;
1546
1547 ret = mpc_sie200_irq_enable(&MPC_EFLASH1_DEV);
1548
1549 return error_trans(ret);
1550 }
1551
EFLASH1_MPC_DisableInterrupt(void)1552 static void EFLASH1_MPC_DisableInterrupt(void)
1553 {
1554 mpc_sie200_irq_disable(&MPC_EFLASH1_DEV);
1555 }
1556
1557
EFLASH1_MPC_ClearInterrupt(void)1558 static void EFLASH1_MPC_ClearInterrupt(void)
1559 {
1560 mpc_sie200_clear_irq(&MPC_EFLASH1_DEV);
1561 }
1562
EFLASH1_MPC_InterruptState(void)1563 static uint32_t EFLASH1_MPC_InterruptState(void)
1564 {
1565 return mpc_sie200_irq_state(&MPC_EFLASH1_DEV);
1566 }
1567
EFLASH1_MPC_LockDown(void)1568 static int32_t EFLASH1_MPC_LockDown(void)
1569 {
1570 return mpc_sie200_lock_down(&MPC_EFLASH1_DEV);
1571 }
1572
1573 /* EFLASH1_MPC Driver CMSIS access structure */
1574 extern ARM_DRIVER_MPC Driver_EFLASH1_MPC;
1575 ARM_DRIVER_MPC Driver_EFLASH1_MPC = {
1576 .GetVersion = ARM_MPC_GetVersion,
1577 .Initialize = EFLASH1_MPC_Initialize,
1578 .Uninitialize = EFLASH1_MPC_Uninitialize,
1579 .GetBlockSize = EFLASH1_MPC_GetBlockSize,
1580 .GetCtrlConfig = EFLASH1_MPC_GetCtrlConfig,
1581 .SetCtrlConfig = EFLASH1_MPC_SetCtrlConfig,
1582 .ConfigRegion = EFLASH1_MPC_ConfigRegion,
1583 .GetRegionConfig = EFLASH1_MPC_GetRegionConfig,
1584 .EnableInterrupt = EFLASH1_MPC_EnableInterrupt,
1585 .DisableInterrupt = EFLASH1_MPC_DisableInterrupt,
1586 .ClearInterrupt = EFLASH1_MPC_ClearInterrupt,
1587 .InterruptState = EFLASH1_MPC_InterruptState,
1588 .LockDown = EFLASH1_MPC_LockDown,
1589 };
1590 #endif /* RTE_EFLASH1_MPC */
1591
