1 /*
2 * Copyright 2020-2023 NXP
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6 /**
7 * @file Clock_Ip_Specific.c
8 * @version 3.0.0
9 *
10 * @brief CLOCK driver implementations.
11 * @details CLOCK driver implementations.
12 *
13 * @addtogroup CLOCK_DRIVER Clock Ip Driver
14 * @{
15 */
16
17 #ifdef __cplusplus
18 extern "C"{
19 #endif
20
21
22 /*==================================================================================================
23 * INCLUDE FILES
24 * 1) system and project includes
25 * 2) needed interfaces from external units
26 * 3) internal and external interfaces from this unit
27 ==================================================================================================*/
28 #include "Clock_Ip_Private.h"
29
30 #if (defined(CLOCK_IP_ENABLE_USER_MODE_SUPPORT))
31 #if (STD_ON == CLOCK_IP_ENABLE_USER_MODE_SUPPORT)
32 #define USER_MODE_REG_PROT_ENABLED (STD_ON)
33 #include "RegLockMacros.h"
34 #endif
35 #endif /* CLOCK_IP_ENABLE_USER_MODE_SUPPORT */
36
37 /*==================================================================================================
38 SOURCE FILE VERSION INFORMATION
39 ==================================================================================================*/
40 #define CLOCK_IP_SPECIFIC_VENDOR_ID_C 43
41 #define CLOCK_IP_SPECIFIC_AR_RELEASE_MAJOR_VERSION_C 4
42 #define CLOCK_IP_SPECIFIC_AR_RELEASE_MINOR_VERSION_C 7
43 #define CLOCK_IP_SPECIFIC_AR_RELEASE_REVISION_VERSION_C 0
44 #define CLOCK_IP_SPECIFIC_SW_MAJOR_VERSION_C 3
45 #define CLOCK_IP_SPECIFIC_SW_MINOR_VERSION_C 0
46 #define CLOCK_IP_SPECIFIC_SW_PATCH_VERSION_C 0
47
48 /*==================================================================================================
49 * FILE VERSION CHECKS
50 ==================================================================================================*/
51 /* Check if Clock_Ip_Specific.c file and Clock_Ip_Private.h file are of the same vendor */
52 #if (CLOCK_IP_SPECIFIC_VENDOR_ID_C != CLOCK_IP_PRIVATE_VENDOR_ID)
53 #error "Clock_Ip_Specific.c and Clock_Ip_Private.h have different vendor ids"
54 #endif
55
56 /* Check if Clock_Ip_Specific.c file and Clock_Ip_Private.h file are of the same Autosar version */
57 #if ((CLOCK_IP_SPECIFIC_AR_RELEASE_MAJOR_VERSION_C != CLOCK_IP_PRIVATE_AR_RELEASE_MAJOR_VERSION) || \
58 (CLOCK_IP_SPECIFIC_AR_RELEASE_MINOR_VERSION_C != CLOCK_IP_PRIVATE_AR_RELEASE_MINOR_VERSION) || \
59 (CLOCK_IP_SPECIFIC_AR_RELEASE_REVISION_VERSION_C != CLOCK_IP_PRIVATE_AR_RELEASE_REVISION_VERSION) \
60 )
61 #error "AutoSar Version Numbers of Clock_Ip_Specific.c and Clock_Ip_Private.h are different"
62 #endif
63
64 /* Check if Clock_Ip_Specific.c file and Clock_Ip_Private.h file are of the same Software version */
65 #if ((CLOCK_IP_SPECIFIC_SW_MAJOR_VERSION_C != CLOCK_IP_PRIVATE_SW_MAJOR_VERSION) || \
66 (CLOCK_IP_SPECIFIC_SW_MINOR_VERSION_C != CLOCK_IP_PRIVATE_SW_MINOR_VERSION) || \
67 (CLOCK_IP_SPECIFIC_SW_PATCH_VERSION_C != CLOCK_IP_PRIVATE_SW_PATCH_VERSION) \
68 )
69 #error "Software Version Numbers of Clock_Ip_Specific.c and Clock_Ip_Private.h are different"
70 #endif
71
72 #if (defined(CLOCK_IP_ENABLE_USER_MODE_SUPPORT))
73 #if (STD_ON == CLOCK_IP_ENABLE_USER_MODE_SUPPORT)
74 #ifndef DISABLE_MCAL_INTERMODULE_ASR_CHECK
75 /* Check if Clock_Ip_Specific.c file and RegLockMacros.h file are of the same Autosar version */
76 #if ((CLOCK_IP_SPECIFIC_AR_RELEASE_MAJOR_VERSION_C != REGLOCKMACROS_AR_RELEASE_MAJOR_VERSION) || \
77 (CLOCK_IP_SPECIFIC_AR_RELEASE_MINOR_VERSION_C != REGLOCKMACROS_AR_RELEASE_MINOR_VERSION))
78 #error "AutoSar Version Numbers of Clock_Ip_Specific.c and RegLockMacros.h are different"
79 #endif
80 #endif
81 #endif
82 #endif /* CLOCK_IP_ENABLE_USER_MODE_SUPPORT */
83
84
85 /*==================================================================================================
86 LOCAL TYPEDEFS (STRUCTURES, UNIONS, ENUMS)
87 ==================================================================================================*/
88 #ifdef CLOCK_IP_HAS_FLASH_WAIT_STATES
89 typedef void (*SetFlashWaitStatesCallbackType)(void);
90 #endif
91
92 /*==================================================================================================
93 * LOCAL MACROS
94 ==================================================================================================*/
95 #define CLOCK_IP_FIRCOSC_STDBY 2U
96 #define CLOCK_IP_SIRCOSC_STDBY 3U
97 /*==================================================================================================
98 LOCAL CONSTANTS
99 ==================================================================================================*/
100
101 /*==================================================================================================
102 * LOCAL FUNCTION PROTOTYPES
103 ==================================================================================================*/
104 /* Clock start ram section code */
105 #define MCU_START_SEC_RAMCODE
106 #include "Mcu_MemMap.h"
107
108 #ifdef CLOCK_IP_HAS_FLASH_WAIT_STATES
109 static void Clock_Ip_CodeInRamSetFlashWaitStates(void);
110 #endif
111
112 /* Clock stop ram section code */
113 #define MCU_STOP_SEC_RAMCODE
114 #include "Mcu_MemMap.h"
115
116 /* Clock start section code */
117 #define MCU_START_SEC_CODE
118 #include "Mcu_MemMap.h"
119
120 static void Clock_Ip_ClockInitializeObjects(void);
121
122 /* Clock stop section code */
123 #define MCU_STOP_SEC_CODE
124 #include "Mcu_MemMap.h"
125 /*==================================================================================================
126 LOCAL VARIABLES
127 ==================================================================================================*/
128 /* Clock start initialized section data */
129 #define MCU_START_SEC_VAR_CLEARED_UNSPECIFIED
130 #include "Mcu_MemMap.h"
131
132 static const Clock_Ip_IntOscCallbackType *Clock_Ip_pxSircStdbyClock;
133 static const Clock_Ip_IntOscCallbackType *Clock_Ip_pxFircStdbyClock;
134
135
136 /* Clock stop initialized section data */
137 #define MCU_STOP_SEC_VAR_CLEARED_UNSPECIFIED
138 #include "Mcu_MemMap.h"
139
140 /* Clock start initialized section data */
141 #define MCU_START_SEC_VAR_INIT_UNSPECIFIED
142 #include "Mcu_MemMap.h"
143
144 #ifdef CLOCK_IP_HAS_FLASH_WAIT_STATES
145 static SetFlashWaitStatesCallbackType Clock_Ip_SetFlashWaitStatesCallback = Clock_Ip_CodeInRamSetFlashWaitStates; /* Set Flash Wait States callback */
146 #endif
147
148 /* Clock stop initialized section data */
149 #define MCU_STOP_SEC_VAR_INIT_UNSPECIFIED
150 #include "Mcu_MemMap.h"
151
152 /* Clock start initialized section data */
153 #define MCU_START_SEC_VAR_CLEARED_BOOLEAN
154 #include "Mcu_MemMap.h"
155
156 static boolean Clock_Ip_bObjectsAreInitialized; /* Clock objects are initialized. */
157
158 /* Clock stop initialized section data */
159 #define MCU_STOP_SEC_VAR_CLEARED_BOOLEAN
160 #include "Mcu_MemMap.h"
161 /*==================================================================================================
162 GLOBAL CONSTANTS
163 ==================================================================================================*/
164
165 /*==================================================================================================
166 GLOBAL VARIABLES
167 ==================================================================================================*/
168
169 /*==================================================================================================
170 * GLOBAL FUNCTION PROTOTYPES
171 ==================================================================================================*/
172 /* Clock start rom section code */
173 #define MCU_START_SEC_CODE_AC
174 #include "Mcu_MemMap.h"
175
176 #ifdef CLOCK_IP_HAS_RAM_WAIT_STATES
177 void Clock_Ip_PRAMCSetRamIWS(void);
178 #endif
179
180 /* Clock stop rom section code */
181 #define MCU_STOP_SEC_CODE_AC
182 #include "Mcu_MemMap.h"
183
184
185 /* Clock start section code */
186 #define MCU_START_SEC_CODE
187 #include "Mcu_MemMap.h"
188
189 void Clock_Ip_PowerClockIpModules(void);
190 /*==================================================================================================
191 * LOCAL FUNCTION PROTOTYPES
192 ==================================================================================================*/
193
194 /*==================================================================================================
195 * LOCAL FUNCTIONS
196 ==================================================================================================*/
197
Clock_Ip_PllPowerClockIp(void)198 static void Clock_Ip_PllPowerClockIp(void)
199 {
200 uint32 StartTime;
201 uint32 ElapsedTime;
202 uint32 TimeoutTicks;
203 boolean TimeoutOccurred = FALSE;
204
205 /* PLL is not powered */
206 if (0U == (IP_MC_ME->PRTN1_COFB1_STAT & MC_ME_PRTN1_COFB1_STAT_BLOCK56_MASK))
207 {
208 /* Power PLL device */
209 IP_MC_ME->PRTN1_COFB1_CLKEN |= MC_ME_PRTN1_COFB1_CLKEN_REQ56(1U); /* REQ56: Frequency Modulated Phase-Locked Loop */
210 IP_MC_ME->PRTN1_PCONF |= MC_ME_PRTN1_PCONF_PCE_MASK; /* PCE=1: Enable the clock to Partition #1 */
211 IP_MC_ME->PRTN1_PUPD |= MC_ME_PRTN1_PUPD_PCUD_MASK; /* PCUD=1: Trigger the hardware process */
212 Clock_Ip_McMeEnterKey();
213 /* Wait until PLL clock is running */
214 Clock_Ip_StartTimeout(&StartTime, &ElapsedTime, &TimeoutTicks, CLOCK_IP_TIMEOUT_VALUE_US);
215 do
216 {
217 TimeoutOccurred = Clock_Ip_TimeoutExpired(&StartTime, &ElapsedTime, TimeoutTicks);
218 }
219 while((0U == (IP_MC_ME->PRTN1_COFB1_STAT & MC_ME_PRTN1_COFB1_STAT_BLOCK56_MASK)) && (FALSE == TimeoutOccurred));
220 /* timeout notification */
221 if (TRUE == TimeoutOccurred)
222 {
223 /* Report timeout error */
224 Clock_Ip_ReportClockErrors(CLOCK_IP_REPORT_TIMEOUT_ERROR, PLL_CLK);
225 }
226 }
227
228 /* PLLAUX is not powered */
229 #if defined(CLOCK_IP_HAS_PLLAUX_CLK)
230 if (0U == (IP_MC_ME->PRTN1_COFB1_STAT & MC_ME_PRTN1_COFB1_STAT_BLOCK57_MASK))
231 {
232 /* Power PLL device */
233 IP_MC_ME->PRTN1_COFB1_CLKEN |= MC_ME_PRTN1_COFB1_CLKEN_REQ57(1U); /* REQ57: Frequency Modulated Phase-Locked Loop */
234 IP_MC_ME->PRTN1_PCONF |= MC_ME_PRTN1_PCONF_PCE_MASK; /* PCE=1: Enable the clock to Partition #1 */
235 IP_MC_ME->PRTN1_PUPD |= MC_ME_PRTN1_PUPD_PCUD_MASK; /* PCUD=1: Trigger the hardware process */
236 Clock_Ip_McMeEnterKey();
237 /* Wait until PLL clock is running */
238 Clock_Ip_StartTimeout(&StartTime, &ElapsedTime, &TimeoutTicks, CLOCK_IP_TIMEOUT_VALUE_US);
239 do
240 {
241 TimeoutOccurred = Clock_Ip_TimeoutExpired(&StartTime, &ElapsedTime, TimeoutTicks);
242 }
243 while((0U == (IP_MC_ME->PRTN1_COFB1_STAT & MC_ME_PRTN1_COFB1_STAT_BLOCK57_MASK)) && (FALSE == TimeoutOccurred));
244 /* timeout notification */
245 if (TRUE == TimeoutOccurred)
246 {
247 /* Report timeout error */
248 Clock_Ip_ReportClockErrors(CLOCK_IP_REPORT_TIMEOUT_ERROR, PLLAUX_CLK);
249 }
250 }
251 #endif
252 }
253
254
255 /* Power clock ip modules */
Clock_Ip_PowerClockIpModules(void)256 void Clock_Ip_PowerClockIpModules(void)
257 {
258 uint32 StartTime;
259 uint32 ElapsedTime;
260 uint32 TimeoutTicks;
261 boolean TimeoutOccurred = FALSE;
262
263 Clock_Ip_PllPowerClockIp();
264
265 /* FXOSC is not powered */
266 if (0U == (IP_MC_ME->PRTN1_COFB1_STAT & MC_ME_PRTN1_COFB1_STAT_BLOCK53_MASK))
267 {
268 /* Power FXOSC device */
269 IP_MC_ME->PRTN1_COFB1_CLKEN |= MC_ME_PRTN1_COFB1_CLKEN_REQ53(1U); /* REQ53: Fast External Oscillator */
270 IP_MC_ME->PRTN1_PCONF |= MC_ME_PRTN1_PCONF_PCE_MASK; /* PCE=1: Enable the clock to Partition #1 */
271 IP_MC_ME->PRTN1_PUPD |= MC_ME_PRTN1_PUPD_PCUD_MASK; /* PCUD=1: Trigger the hardware process */
272 Clock_Ip_McMeEnterKey();
273 /* Wait until FXOSC clock is running */
274 Clock_Ip_StartTimeout(&StartTime, &ElapsedTime, &TimeoutTicks, CLOCK_IP_TIMEOUT_VALUE_US);
275 do
276 {
277 TimeoutOccurred = Clock_Ip_TimeoutExpired(&StartTime, &ElapsedTime, TimeoutTicks);
278 }
279 while((0U == (IP_MC_ME->PRTN1_COFB1_STAT & MC_ME_PRTN1_COFB1_STAT_BLOCK53_MASK)) && (FALSE == TimeoutOccurred));
280 /* timeout notification */
281 if (TRUE == TimeoutOccurred)
282 {
283 /* Report timeout error */
284 Clock_Ip_ReportClockErrors(CLOCK_IP_REPORT_TIMEOUT_ERROR, FXOSC_CLK);
285 }
286 }
287
288 #if defined(CLOCK_IP_HAS_SXOSC_CLK)
289 /* SXOSC is not powered */
290 if (0U == (IP_MC_ME->PRTN1_COFB1_STAT & MC_ME_PRTN1_COFB1_STAT_BLOCK51_MASK))
291 {
292 /* Power SXOSC device */
293 IP_MC_ME->PRTN1_COFB1_CLKEN |= MC_ME_PRTN1_COFB1_CLKEN_REQ51(1U); /* REQ51: Slow External Oscillator */
294 IP_MC_ME->PRTN1_PCONF |= MC_ME_PRTN1_PCONF_PCE_MASK; /* PCE=1: Enable the clock to Partition #1 */
295 IP_MC_ME->PRTN1_PUPD |= MC_ME_PRTN1_PUPD_PCUD_MASK; /* PCUD=1: Trigger the hardware process */
296 Clock_Ip_McMeEnterKey();
297 /* Wait until SXOSC clock is running */
298 Clock_Ip_StartTimeout(&StartTime, &ElapsedTime, &TimeoutTicks, CLOCK_IP_TIMEOUT_VALUE_US);
299 do
300 {
301 TimeoutOccurred = Clock_Ip_TimeoutExpired(&StartTime, &ElapsedTime, TimeoutTicks);
302 }
303 while((0U == (IP_MC_ME->PRTN1_COFB1_STAT & MC_ME_PRTN1_COFB1_STAT_BLOCK51_MASK)) && (FALSE == TimeoutOccurred));
304 /* timeout notification */
305 if (TRUE == TimeoutOccurred)
306 {
307 /* Report timeout error */
308 Clock_Ip_ReportClockErrors(CLOCK_IP_REPORT_TIMEOUT_ERROR, SXOSC_CLK);
309 }
310 }
311 #endif
312
313 /* CMUs are not powered */
314 if (0U == (IP_MC_ME->PRTN1_COFB1_STAT & MC_ME_PRTN1_COFB1_STAT_BLOCK47_MASK))
315 {
316 /* Power CMU devices */
317 IP_MC_ME->PRTN1_COFB1_CLKEN |= MC_ME_PRTN1_COFB1_CLKEN_REQ47(1U); /* REQ47: Clock monitor unit */
318 IP_MC_ME->PRTN1_PCONF |= MC_ME_PRTN1_PCONF_PCE_MASK; /* PCE=1: Enable the clock to Partition #1 */
319 IP_MC_ME->PRTN1_PUPD |= MC_ME_PRTN1_PUPD_PCUD_MASK; /* PCUD=1: Trigger the hardware process */
320 Clock_Ip_McMeEnterKey();
321 /* Wait until CMU clock is running */
322 Clock_Ip_StartTimeout(&StartTime, &ElapsedTime, &TimeoutTicks, CLOCK_IP_TIMEOUT_VALUE_US);
323 do
324 {
325 TimeoutOccurred = Clock_Ip_TimeoutExpired(&StartTime, &ElapsedTime, TimeoutTicks);
326 }
327 while((0U == (IP_MC_ME->PRTN1_COFB1_STAT & MC_ME_PRTN1_COFB1_STAT_BLOCK47_MASK)) && (FALSE == TimeoutOccurred));
328 /* timeout notification */
329 if (TRUE == TimeoutOccurred)
330 {
331 /* Report timeout error */
332 Clock_Ip_ReportClockErrors(CLOCK_IP_REPORT_TIMEOUT_ERROR, RESERVED_CLK);
333 }
334 }
335
336 /* MSCM is not powered */
337 if (0U == (IP_MC_ME->PRTN1_COFB0_STAT & MC_ME_PRTN1_COFB0_STAT_BLOCK24_MASK))
338 {
339 /* Power MSCM devices */
340 IP_MC_ME->PRTN1_COFB0_CLKEN |= MC_ME_PRTN1_COFB0_CLKEN_REQ24(1U); /* REQ24: MSCM */
341 IP_MC_ME->PRTN1_PCONF |= MC_ME_PRTN1_PCONF_PCE_MASK; /* PCE=1: Enable the clock to Partition #1 */
342 IP_MC_ME->PRTN1_PUPD |= MC_ME_PRTN1_PUPD_PCUD_MASK; /* PCUD=1: Trigger the hardware process */
343 Clock_Ip_McMeEnterKey();
344 /* Wait until MSCM clock is running */
345 Clock_Ip_StartTimeout(&StartTime, &ElapsedTime, &TimeoutTicks, CLOCK_IP_TIMEOUT_VALUE_US);
346 do
347 {
348 TimeoutOccurred = Clock_Ip_TimeoutExpired(&StartTime, &ElapsedTime, TimeoutTicks);
349 }
350 while((0U == (IP_MC_ME->PRTN1_COFB0_STAT & MC_ME_PRTN1_COFB0_STAT_BLOCK24_MASK)) && (FALSE == TimeoutOccurred));
351 /* timeout notification */
352 if (TRUE == TimeoutOccurred)
353 {
354 /* Report timeout error */
355 Clock_Ip_ReportClockErrors(CLOCK_IP_REPORT_TIMEOUT_ERROR, RESERVED_CLK);
356 }
357 }
358
359 }
360 /* Clock stop section code */
361 #define MCU_STOP_SEC_CODE
362 #include "Mcu_MemMap.h"
363
364 #ifdef CLOCK_IP_HAS_FLASH_WAIT_STATES
365
366
367 /* Clock start ram section code */
368 #define MCU_START_SEC_RAMCODE
369
370 #include "Mcu_MemMap.h"
371
372 /* Configuration Flash wait state value base on ControllerRamFrequency */
Clock_Ip_CodeInRamSetFlashWaitStates(void)373 static void Clock_Ip_CodeInRamSetFlashWaitStates(void)
374 {
375 uint32 RegValue;
376 uint32 RwscSetting = 0U;
377 uint32 ConfiguredCoreClock = 0U;
378
379 ConfiguredCoreClock = (*Clock_Ip_pxConfig->ConfiguredFrequencies)[Clock_Ip_FreqIds[CORE_CLK]].ConfiguredFrequencyValue;
380
381 if (ConfiguredCoreClock <= 167000000U)
382 {
383 if (ConfiguredCoreClock <= 66000000U)
384 {
385 RwscSetting = 1U;
386 }
387 else if (ConfiguredCoreClock <= 100000000U)
388 {
389 RwscSetting = 2U;
390 }
391 else if (ConfiguredCoreClock <= 133000000U)
392 {
393 RwscSetting = 3U;
394 }
395 else
396 {
397 RwscSetting = 4U;
398 }
399 }
400 else
401 {
402 if (ConfiguredCoreClock <= 200000000U)
403 {
404 RwscSetting = 5U;
405 }
406 else if (ConfiguredCoreClock <= 233000000U)
407 {
408 RwscSetting = 6U;
409 }
410 else if (ConfiguredCoreClock <= 250000000U)
411 {
412 RwscSetting = 7U;
413 }
414 else
415 {
416 RwscSetting = 7U;
417 }
418 }
419
420 /* Update register value with the new WS value. */
421 RegValue = IP_FLASH->CTL;
422 RegValue &= ~FLASH_CTL_RWSL_MASK;
423 RegValue &= ~FLASH_CTL_RWSC_MASK;
424 RegValue |= FLASH_CTL_RWSC(RwscSetting);
425
426 /* Complete all data memory accesses and instructions. */
427 ASM_KEYWORD("dsb");
428 ASM_KEYWORD("isb");
429
430 /* Unlock register to set flash wait states */
431 IP_FLASH->CTL &= ~FLASH_CTL_RWSL_MASK;
432
433 /* Configure wait states */
434 IP_FLASH->CTL = RegValue;
435 }
436
437 /* Clock stop ram section code */
438 #define MCU_STOP_SEC_RAMCODE
439 #include "Mcu_MemMap.h"
440
441 #endif
442
443 /*==================================================================================================
444 * GLOBAL FUNCTIONS
445 ==================================================================================================*/
446
447 #define MCU_START_SEC_CODE
448 #include "Mcu_MemMap.h"
449
450 #ifdef CLOCK_IP_HAS_RAM_WAIT_STATES
451
452 /* Set Ram wait state */
Clock_Ip_SetRamWaitStates(void)453 void Clock_Ip_SetRamWaitStates(void)
454 {
455 #ifdef CLOCK_IP_ENABLE_USER_MODE_SUPPORT
456 #if (STD_ON == CLOCK_IP_ENABLE_USER_MODE_SUPPORT)
457 OsIf_Trusted_Call(Clock_Ip_PRAMCSetRamIWS);
458 #else
459 Clock_Ip_PRAMCSetRamIWS();
460 #endif
461 #else
462 Clock_Ip_PRAMCSetRamIWS();
463 #endif
464 }
465 #endif
466
467 #ifdef CLOCK_IP_HAS_FLASH_WAIT_STATES
468 void Clock_Ip_FLASH_SetFlashIWS(void);
469
470 /* Set Flash wait state */
Clock_Ip_SetFlashWaitStates(void)471 void Clock_Ip_SetFlashWaitStates(void)
472 {
473 Clock_Ip_FLASH_SetFlashIWS();
474 }
475 #endif
476
Clock_Ip_McMeEnterKey(void)477 void Clock_Ip_McMeEnterKey(void)
478 {
479 IP_MC_ME->CTL_KEY = 0x5AF0U; /* Enter key */
480
481 IP_MC_ME->CTL_KEY = 0xA50FU;
482 }
483
484
485
Clock_Ip_SpecificPlatformInitClock(Clock_Ip_ClockConfigType const * Config)486 static void Clock_Ip_SpecificPlatformInitClock(Clock_Ip_ClockConfigType const * Config)
487 {
488 (void)Config;
489
490 /* Power clock ip modules.
491 * On some platforms clock ip modules cannot be configured,
492 * registers cannot be access until device is powered.
493 * Check and power if it is required clock ip modules.
494 */
495 Clock_Ip_PowerClockIpModules();
496 }
497
498 /* Disable FIRC in Standby mode */
DisableFircInStandbyMode(void)499 void DisableFircInStandbyMode(void)
500 {
501 Clock_Ip_pxFircStdbyClock->Disable(FIRC_CLK);
502 }
503
504 /* Enable Firc in Standby mode */
EnableFircInStandbyMode(void)505 void EnableFircInStandbyMode(void)
506 {
507 Clock_Ip_IrcoscConfigType FircConfig;
508 FircConfig.Enable = TRUE;
509 Clock_Ip_pxFircStdbyClock->Enable(&FircConfig);
510 }
511
512 /* Disable Sirc in Standby mode */
DisableSircInStandbyMode(void)513 void DisableSircInStandbyMode(void)
514 {
515 Clock_Ip_pxSircStdbyClock->Disable(SIRC_CLK);
516 }
517
518 /* Enable Sirc in Standby mode */
EnableSircInStandbyMode(void)519 void EnableSircInStandbyMode(void)
520 {
521 Clock_Ip_IrcoscConfigType SircConfig;
522 SircConfig.Enable = TRUE;
523 Clock_Ip_pxSircStdbyClock->Enable(&SircConfig);
524 }
525
526 /* Initialize objects for clock */
Clock_Ip_ClockInitializeObjects(void)527 static void Clock_Ip_ClockInitializeObjects(void)
528 {
529 if (FALSE == Clock_Ip_bObjectsAreInitialized)
530 {
531 Clock_Ip_bObjectsAreInitialized = TRUE;
532
533 Clock_Ip_pxSircStdbyClock = &Clock_Ip_axIntOscCallbacks[Clock_Ip_au8IrcoscCallbackIndex[CLOCK_IP_SIRCOSC_STDBY]];
534
535 Clock_Ip_pxFircStdbyClock = &Clock_Ip_axIntOscCallbacks[Clock_Ip_au8IrcoscCallbackIndex[CLOCK_IP_FIRCOSC_STDBY]];
536 }
537 }
538
539 #if (defined(CLOCK_IP_ENABLE_USER_MODE_SUPPORT))
540 #if (STD_ON == CLOCK_IP_ENABLE_USER_MODE_SUPPORT)
Clock_Ip_SpecificSetUserAccessAllowed(void)541 void Clock_Ip_SpecificSetUserAccessAllowed(void)
542 {
543 #ifdef CLOCK_IP_ENABLE_USER_MODE_SUPPORT
544 #if (STD_ON == CLOCK_IP_ENABLE_USER_MODE_SUPPORT)
545 OsIf_Trusted_Call(Clock_Ip_PowerClockIpModules);
546 #else
547 Clock_Ip_PowerClockIpModules();
548 #endif
549 #else
550 Clock_Ip_PowerClockIpModules();
551 #endif
552 /* PLLDIG SetUserAccessAllowed */
553 #if ( defined(MCAL_PLLDIG_REG_PROT_AVAILABLE))
554 #if (STD_ON == MCAL_PLLDIG_REG_PROT_AVAILABLE)
555 #if (defined(IP_PLL_BASE))
556 SET_USER_ACCESS_ALLOWED(IP_PLL_BASE, PLLDIG_PROT_MEM_U32);
557 #endif
558 #endif
559 #endif /* MCAL_PLLDIG_REG_PROT_AVAILABLE */
560
561 /* PLLDIG SetUserAccessAllowed */
562 #if ( defined(MCAL_PLLDIG_REG_PROT_AVAILABLE))
563 #if (STD_ON == MCAL_PLLDIG_REG_PROT_AVAILABLE)
564 #if (defined(IP_PLL_AUX_BASE))
565 SET_USER_ACCESS_ALLOWED(IP_PLL_AUX_BASE, PLLDIG_PROT_MEM_U32);
566 #endif
567 #endif
568 #endif /* MCAL_PLLDIG_REG_PROT_AVAILABLE */
569 /* FXOSC SetUserAccessAllowed */
570 #if (defined(MCAL_FXOSC_REG_PROT_AVAILABLE))
571 #if (STD_ON == MCAL_FXOSC_REG_PROT_AVAILABLE)
572 #if (defined(IP_FXOSC_BASE))
573 SET_USER_ACCESS_ALLOWED(IP_FXOSC_BASE, FXOSC_PROT_MEM_U32);
574 #endif
575 #endif
576 #endif /* MCAL_FXOSC_REG_PROT_AVAILABLE */
577
578 /* MC_CGM SetUserAccessAllowed */
579 #if ( defined(MCAL_MC_CGM_REG_PROT_AVAILABLE))
580 #if (STD_ON == MCAL_MC_CGM_REG_PROT_AVAILABLE)
581 #if (defined(IP_MC_CGM_BASE))
582 SET_USER_ACCESS_ALLOWED(IP_MC_CGM_BASE, MC_CGM_PROT_MEM_U32);
583 #endif
584 #endif
585 #endif /* MCAL_MC_CGM_REG_PROT_AVAILABLE */
586
587 /* CMU SetUserAccessAllowed */
588 #if (defined(MCAL_CMU_REG_PROT_AVAILABLE))
589 #if (STD_ON == MCAL_CMU_REG_PROT_AVAILABLE)
590 #if (defined(IP_CMU_0_BASE))
591 /* Check clock status for CMU0 */
592 SET_USER_ACCESS_ALLOWED(IP_CMU_0_BASE, CMU_PROT_MEM_U32);
593 #endif
594 #endif
595 #endif /* MCAL_CMU_REG_PROT_AVAILABLE */
596
597 /* SRAM SetUserAccessAllowed */
598 #if (defined(MCAL_PRAMC_REG_PROT_AVAILABLE))
599 #if (STD_ON == MCAL_PRAMC_REG_PROT_AVAILABLE)
600 #if (defined(IP_PRAMC_0_BASE))
601 SET_USER_ACCESS_ALLOWED(IP_PRAMC_0_BASE, PRAMC_PROT_MEM_U32);
602 #endif
603 #if (defined(IP_PRAMC_1_BASE))
604 SET_USER_ACCESS_ALLOWED(IP_PRAMC_1_BASE, PRAMC_PROT_MEM_U32);
605 #endif
606 #endif
607 #endif /* MCAL_PRAMC_REG_PROT_AVAILABLE */
608
609 /* MC_ME SetUserAccessAllowed */
610 #if (defined(MCAL_MC_ME_REG_PROT_AVAILABLE ))
611 #if (STD_ON == MCAL_MC_ME_REG_PROT_AVAILABLE )
612 #if (defined(IP_MC_ME_BASE))
613 SET_USER_ACCESS_ALLOWED(IP_MC_ME_BASE, MC_ME_PROT_MEM_U32);
614 #endif
615 #endif
616 #endif /* MCAL_MC_ME_REG_PROT_AVAILABLE */
617
618 /* FLASH_C40ASF SetUserAccessAllowed */
619 #if (defined(MCAL_C40ASF_REG_PROT_AVAILABLE ))
620 #if (STD_ON == MCAL_C40ASF_REG_PROT_AVAILABLE )
621 #if (defined(IP_FLASH_BASE))
622 SET_USER_ACCESS_ALLOWED(IP_FLASH_BASE, C40ASF_PROT_MEM_U32);
623 #endif
624 #endif
625 #endif /* MCAL_C40ASF_REG_PROT_AVAILABLE */
626 }
627 #endif
628 #endif /* CLOCK_IP_ENABLE_USER_MODE_SUPPORT */
629
Clock_Ip_Command(Clock_Ip_ClockConfigType const * Config,Clock_Ip_CommandType Command)630 void Clock_Ip_Command(Clock_Ip_ClockConfigType const * Config, Clock_Ip_CommandType Command)
631 {
632 switch(Command)
633 {
634 case CLOCK_IP_INITIALIZE_CLOCK_OBJECTS_COMMAND:
635 Clock_Ip_ClockInitializeObjects();
636 break;
637 case CLOCK_IP_INITIALIZE_PLATFORM_COMMAND:
638 Clock_Ip_SpecificPlatformInitClock(Config);
639 break;
640 #ifdef CLOCK_IP_ENABLE_USER_MODE_SUPPORT
641 #if (STD_ON == CLOCK_IP_ENABLE_USER_MODE_SUPPORT)
642 case CLOCK_IP_SET_USER_ACCESS_ALLOWED_COMMAND:
643 OsIf_Trusted_Call(Clock_Ip_SpecificSetUserAccessAllowed);
644 break;
645 #endif
646 #endif
647 default:
648 /* Command is not implemented on this platform */
649 break;
650 }
651 }
652
653 /* Clock stop section code */
654 #define MCU_STOP_SEC_CODE
655 #include "Mcu_MemMap.h"
656
657
658 #ifdef CLOCK_IP_HAS_FLASH_WAIT_STATES
659
660 /* Clock start section code */
661 #define MCU_START_SEC_CODE
662 #include "Mcu_MemMap.h"
663 /* Set Flash wait state */
Clock_Ip_FLASH_SetFlashIWS(void)664 void Clock_Ip_FLASH_SetFlashIWS(void)
665 {
666 Clock_Ip_SetFlashWaitStatesCallback();
667 }
668
669 /* Clock stop section code */
670 #define MCU_STOP_SEC_CODE
671 #include "Mcu_MemMap.h"
672
673 #endif
674
675 #ifdef CLOCK_IP_HAS_RAM_WAIT_STATES
676
677
678 /* Clock start rom section code */
679 #define MCU_START_SEC_CODE_AC
680
681 #include "Mcu_MemMap.h"
682
Clock_Ip_PRAMCSetRamIWS(void)683 void Clock_Ip_PRAMCSetRamIWS(void)
684 {
685 uint32 ControllerRamFrequency = 0U; /* Frequency at which PRAM controller is working */
686 uint32 ArrayRamFrequency = 0U; /* Frequency at which system ram is working */
687
688 uint32 Pram0RegVal = IP_PRAMC_0->PRCR1;
689 #ifdef IP_PRAMC_1
690 uint32 Pram1RegVal = IP_PRAMC_1->PRCR1;
691 #endif
692
693 #if defined(CLOCK_IP_HAS_CORE_CLK)
694 ControllerRamFrequency = (*Clock_Ip_pxConfig->ConfiguredFrequencies)[Clock_Ip_FreqIds[CORE_CLK]].ConfiguredFrequencyValue;
695 #endif
696
697 #if defined(CLOCK_IP_HAS_AIPS_PLAT_CLK)
698 ArrayRamFrequency = (*Clock_Ip_pxConfig->ConfiguredFrequencies)[Clock_Ip_FreqIds[AIPS_PLAT_CLK]].ConfiguredFrequencyValue;
699 #endif
700
701 /* if controller is working at a higher frequency than array ram (system/physical ram) */
702 if (ControllerRamFrequency > ArrayRamFrequency)
703 {
704 /* Enable RAM WS */
705 Pram0RegVal |= PRAMC_PRCR1_FT_DIS_MASK;
706 #ifdef IP_PRAMC_1
707 Pram1RegVal |= PRAMC_PRCR1_FT_DIS_MASK;
708 #endif
709
710 /* Read bursts are optimized when flow-through is disabled */
711 Pram0RegVal &= ~PRAMC_PRCR1_P0_BO_DIS_MASK;
712 #ifdef IP_PRAMC_1
713 Pram1RegVal &= ~PRAMC_PRCR1_P0_BO_DIS_MASK;
714 #endif
715 }
716 else
717 {
718 /* Disable RAM WS */
719 Pram0RegVal &= ~PRAMC_PRCR1_FT_DIS_MASK;
720 #ifdef IP_PRAMC_1
721 Pram1RegVal &= ~PRAMC_PRCR1_FT_DIS_MASK;
722 #endif
723 }
724
725 IP_PRAMC_0->PRCR1 = Pram0RegVal;
726 #ifdef IP_PRAMC_1
727 IP_PRAMC_1->PRCR1 = Pram1RegVal;
728 #endif
729 }
730
731 /* Clock stop rom section code */
732 #define MCU_STOP_SEC_CODE_AC
733 #include "Mcu_MemMap.h"
734
735 #endif
736
737
738 #ifdef __cplusplus
739 }
740 #endif
741
742 /** @} */
743
744
