1 /*
2 * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
3 * Copyright 2016 NXP
4 * All rights reserved.
5 *
6 *
7 * SPDX-License-Identifier: BSD-3-Clause
8 */
9
10 #include "fsl_common.h"
11 #include "fsl_debug_console.h"
12
13 #ifndef NDEBUG
14 #if (defined(__CC_ARM)) || (defined(__ICCARM__))
__aeabi_assert(const char * failedExpr,const char * file,int line)15 void __aeabi_assert(const char *failedExpr, const char *file, int line)
16 {
17 PRINTF("ASSERT ERROR \" %s \": file \"%s\" Line \"%d\" \n", failedExpr, file, line);
18 for (;;)
19 {
20 __BKPT(0);
21 }
22 }
23 #elif(defined(__GNUC__))
__assert_func(const char * file,int line,const char * func,const char * failedExpr)24 void __assert_func(const char *file, int line, const char *func, const char *failedExpr)
25 {
26 PRINTF("ASSERT ERROR \" %s \": file \"%s\" Line \"%d\" function name \"%s\" \n", failedExpr, file, line, func);
27 for (;;)
28 {
29 __BKPT(0);
30 }
31 }
32 #endif /* (defined(__CC_ARM)) || (defined (__ICCARM__)) */
33 #endif /* NDEBUG */
34
35 #ifndef __GIC_PRIO_BITS
36 #ifndef __riscv
InstallIRQHandler(IRQn_Type irq,uint32_t irqHandler)37 uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler)
38 {
39 /* Addresses for VECTOR_TABLE and VECTOR_RAM come from the linker file */
40 #if defined(__CC_ARM)
41 extern uint32_t Image$$VECTOR_ROM$$Base[];
42 extern uint32_t Image$$VECTOR_RAM$$Base[];
43 extern uint32_t Image$$RW_m_data$$Base[];
44
45 #define __VECTOR_TABLE Image$$VECTOR_ROM$$Base
46 #define __VECTOR_RAM Image$$VECTOR_RAM$$Base
47 #define __RAM_VECTOR_TABLE_SIZE (((uint32_t)Image$$RW_m_data$$Base - (uint32_t)Image$$VECTOR_RAM$$Base))
48 #elif defined(__ICCARM__)
49 extern uint32_t __RAM_VECTOR_TABLE_SIZE[];
50 extern uint32_t __VECTOR_TABLE[];
51 extern uint32_t __VECTOR_RAM[];
52 #elif defined(__GNUC__)
53 extern uint32_t __VECTOR_TABLE[];
54 extern uint32_t __VECTOR_RAM[];
55 extern uint32_t __RAM_VECTOR_TABLE_SIZE_BYTES[];
56 uint32_t __RAM_VECTOR_TABLE_SIZE = (uint32_t)(__RAM_VECTOR_TABLE_SIZE_BYTES);
57 #endif /* defined(__CC_ARM) */
58 uint32_t n;
59 uint32_t ret;
60 uint32_t irqMaskValue;
61
62 irqMaskValue = DisableGlobalIRQ();
63 if (SCB->VTOR != (uint32_t)__VECTOR_RAM)
64 {
65 /* Copy the vector table from ROM to RAM */
66 for (n = 0; n < ((uint32_t)__RAM_VECTOR_TABLE_SIZE) / sizeof(uint32_t); n++)
67 {
68 __VECTOR_RAM[n] = __VECTOR_TABLE[n];
69 }
70 /* Point the VTOR to the position of vector table */
71 SCB->VTOR = (uint32_t)__VECTOR_RAM;
72 }
73
74 ret = __VECTOR_RAM[irq + 16];
75 /* make sure the __VECTOR_RAM is noncachable */
76 __VECTOR_RAM[irq + 16] = irqHandler;
77
78 EnableGlobalIRQ(irqMaskValue);
79
80 return ret;
81 }
82 #endif
83 #endif
84
85 #ifndef QN908XC_SERIES
86 #if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0))
87
EnableDeepSleepIRQ(IRQn_Type interrupt)88 void EnableDeepSleepIRQ(IRQn_Type interrupt)
89 {
90 uint32_t index = 0;
91 uint32_t intNumber = (uint32_t)interrupt;
92 while (intNumber >= 32u)
93 {
94 index++;
95 intNumber -= 32u;
96 }
97
98 SYSCON->STARTERSET[index] = 1u << intNumber;
99 EnableIRQ(interrupt); /* also enable interrupt at NVIC */
100 }
101
DisableDeepSleepIRQ(IRQn_Type interrupt)102 void DisableDeepSleepIRQ(IRQn_Type interrupt)
103 {
104 uint32_t index = 0;
105 uint32_t intNumber = (uint32_t)interrupt;
106 while (intNumber >= 32u)
107 {
108 index++;
109 intNumber -= 32u;
110 }
111
112 DisableIRQ(interrupt); /* also disable interrupt at NVIC */
113 SYSCON->STARTERCLR[index] = 1u << intNumber;
114 }
115 #endif /* FSL_FEATURE_SOC_SYSCON_COUNT */
116
117 #endif /* QN908XC_SERIES */
118
