1 /* 2 * Copyright (c) 2001-2019, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __DX_ID_REGS_H__ 8 #define __DX_ID_REGS_H__ 9 10 // -------------------------------------- 11 // BLOCK: ID_REGISTERS 12 // -------------------------------------- 13 #define DX_PERIPHERAL_ID_4_REG_OFFSET 0x0FD0UL 14 #define DX_PERIPHERAL_ID_4_VALUE_BIT_SHIFT 0x0UL 15 #define DX_PERIPHERAL_ID_4_VALUE_BIT_SIZE 0x4UL 16 #define DX_PIDRESERVED0_REG_OFFSET 0x0FD4UL 17 #define DX_PIDRESERVED1_REG_OFFSET 0x0FD8UL 18 #define DX_PIDRESERVED2_REG_OFFSET 0x0FDCUL 19 #define DX_PERIPHERAL_ID_0_REG_OFFSET 0x0FE0UL 20 #define DX_PERIPHERAL_ID_0_VALUE_BIT_SHIFT 0x0UL 21 #define DX_PERIPHERAL_ID_0_VALUE_BIT_SIZE 0x8UL 22 #define DX_PERIPHERAL_ID_1_REG_OFFSET 0x0FE4UL 23 #define DX_PERIPHERAL_ID_1_PART_1_BIT_SHIFT 0x0UL 24 #define DX_PERIPHERAL_ID_1_PART_1_BIT_SIZE 0x4UL 25 #define DX_PERIPHERAL_ID_1_DES_0_JEP106_BIT_SHIFT 0x4UL 26 #define DX_PERIPHERAL_ID_1_DES_0_JEP106_BIT_SIZE 0x4UL 27 #define DX_PERIPHERAL_ID_2_REG_OFFSET 0x0FE8UL 28 #define DX_PERIPHERAL_ID_2_DES_1_JEP106_BIT_SHIFT 0x0UL 29 #define DX_PERIPHERAL_ID_2_DES_1_JEP106_BIT_SIZE 0x3UL 30 #define DX_PERIPHERAL_ID_2_JEDEC_BIT_SHIFT 0x3UL 31 #define DX_PERIPHERAL_ID_2_JEDEC_BIT_SIZE 0x1UL 32 #define DX_PERIPHERAL_ID_2_REVISION_BIT_SHIFT 0x4UL 33 #define DX_PERIPHERAL_ID_2_REVISION_BIT_SIZE 0x4UL 34 #define DX_PERIPHERAL_ID_3_REG_OFFSET 0x0FECUL 35 #define DX_PERIPHERAL_ID_3_CMOD_BIT_SHIFT 0x0UL 36 #define DX_PERIPHERAL_ID_3_CMOD_BIT_SIZE 0x4UL 37 #define DX_PERIPHERAL_ID_3_REVAND_BIT_SHIFT 0x4UL 38 #define DX_PERIPHERAL_ID_3_REVAND_BIT_SIZE 0x4UL 39 #define DX_COMPONENT_ID_0_REG_OFFSET 0x0FF0UL 40 #define DX_COMPONENT_ID_0_VALUE_BIT_SHIFT 0x0UL 41 #define DX_COMPONENT_ID_0_VALUE_BIT_SIZE 0x8UL 42 #define DX_COMPONENT_ID_1_REG_OFFSET 0x0FF4UL 43 #define DX_COMPONENT_ID_1_PRMBL_1_BIT_SHIFT 0x0UL 44 #define DX_COMPONENT_ID_1_PRMBL_1_BIT_SIZE 0x4UL 45 #define DX_COMPONENT_ID_1_CLASS_BIT_SHIFT 0x4UL 46 #define DX_COMPONENT_ID_1_CLASS_BIT_SIZE 0x4UL 47 #define DX_COMPONENT_ID_2_REG_OFFSET 0x0FF8UL 48 #define DX_COMPONENT_ID_2_VALUE_BIT_SHIFT 0x0UL 49 #define DX_COMPONENT_ID_2_VALUE_BIT_SIZE 0x8UL 50 #define DX_COMPONENT_ID_3_REG_OFFSET 0x0FFCUL 51 #define DX_COMPONENT_ID_3_VALUE_BIT_SHIFT 0x0UL 52 #define DX_COMPONENT_ID_3_VALUE_BIT_SIZE 0x8UL 53 54 #endif //__DX_ID_REGS_H__ 55 56
