1 /* i2c_dw_registers.h - array access for I2C Design Ware registers */ 2 3 /* 4 * Copyright (c) 2015 Intel Corporation 5 * 6 * SPDX-License-Identifier: Apache-2.0 7 */ 8 #ifndef ZEPHYR_DRIVERS_I2C_I2C_DW_REGISTERS_H_ 9 #define ZEPHYR_DRIVERS_I2C_I2C_DW_REGISTERS_H_ 10 11 #ifdef __cplusplus 12 extern "C" { 13 #endif 14 15 /* IC_CON bits */ 16 union ic_con_register { 17 uint32_t raw; 18 struct { 19 uint32_t master_mode : 1 __packed; 20 uint32_t speed : 2 __packed; 21 uint32_t addr_slave_10bit : 1 __packed; 22 uint32_t addr_master_10bit : 1 __packed; 23 uint32_t restart_en : 1 __packed; 24 uint32_t slave_disable : 1 __packed; 25 uint32_t stop_det : 1 __packed; 26 uint32_t tx_empty_ctl : 1 __packed; 27 uint32_t rx_fifo_full : 1 __packed; 28 } bits; 29 }; 30 31 /* IC_DATA_CMD bits */ 32 #define IC_DATA_CMD_DAT_MASK 0xFF 33 #define IC_DATA_CMD_CMD BIT(8) 34 #define IC_DATA_CMD_STOP BIT(9) 35 #define IC_DATA_CMD_RESTART BIT(10) 36 37 /* DesignWare Interrupt bits positions */ 38 #define DW_INTR_STAT_RX_UNDER BIT(0) 39 #define DW_INTR_STAT_RX_OVER BIT(1) 40 #define DW_INTR_STAT_RX_FULL BIT(2) 41 #define DW_INTR_STAT_TX_OVER BIT(3) 42 #define DW_INTR_STAT_TX_EMPTY BIT(4) 43 #define DW_INTR_STAT_RD_REQ BIT(5) 44 #define DW_INTR_STAT_TX_ABRT BIT(6) 45 #define DW_INTR_STAT_RX_DONE BIT(7) 46 #define DW_INTR_STAT_ACTIVITY BIT(8) 47 #define DW_INTR_STAT_STOP_DET BIT(9) 48 #define DW_INTR_STAT_START_DET BIT(10) 49 #define DW_INTR_STAT_GEN_CALL BIT(11) 50 #define DW_INTR_STAT_RESTART_DET BIT(12) 51 #define DW_INTR_STAT_MST_ON_HOLD BIT(13) 52 53 #define DW_INTR_MASK_RX_UNDER BIT(0) 54 #define DW_INTR_MASK_RX_OVER BIT(1) 55 #define DW_INTR_MASK_RX_FULL BIT(2) 56 #define DW_INTR_MASK_TX_OVER BIT(3) 57 #define DW_INTR_MASK_TX_EMPTY BIT(4) 58 #define DW_INTR_MASK_RD_REQ BIT(5) 59 #define DW_INTR_MASK_TX_ABRT BIT(6) 60 #define DW_INTR_MASK_RX_DONE BIT(7) 61 #define DW_INTR_MASK_ACTIVITY BIT(8) 62 #define DW_INTR_MASK_STOP_DET BIT(9) 63 #define DW_INTR_MASK_START_DET BIT(10) 64 #define DW_INTR_MASK_GEN_CALL BIT(11) 65 #define DW_INTR_MASK_RESTART_DET BIT(12) 66 #define DW_INTR_MASK_MST_ON_HOLD BIT(13) 67 #define DW_INTR_MASK_RESET 0x000008ff 68 69 union ic_interrupt_register { 70 uint32_t raw; 71 struct { 72 uint32_t rx_under : 1 __packed; 73 uint32_t rx_over : 1 __packed; 74 uint32_t rx_full : 1 __packed; 75 uint32_t tx_over : 1 __packed; 76 uint32_t tx_empty : 1 __packed; 77 uint32_t rd_req : 1 __packed; 78 uint32_t tx_abrt : 1 __packed; 79 uint32_t rx_done : 1 __packed; 80 uint32_t activity : 1 __packed; 81 uint32_t stop_det : 1 __packed; 82 uint32_t start_det : 1 __packed; 83 uint32_t gen_call : 1 __packed; 84 uint32_t restart_det : 1 __packed; 85 uint32_t mst_on_hold : 1 __packed; 86 uint32_t reserved : 2 __packed; 87 } bits; 88 }; 89 90 /* IC_TAR */ 91 union ic_tar_register { 92 uint32_t raw; 93 struct { 94 uint32_t ic_tar : 10 __packed; 95 uint32_t gc_or_start : 1 __packed; 96 uint32_t special : 1 __packed; 97 uint32_t ic_10bitaddr_master : 1 __packed; 98 uint32_t reserved : 3 __packed; 99 } bits; 100 }; 101 102 /* IC_COMP_PARAM_1 */ 103 union ic_comp_param_1_register { 104 uint32_t raw; 105 struct { 106 uint32_t apb_data_width : 2 __packed; 107 uint32_t max_speed_mode : 2 __packed; 108 uint32_t hc_count_values : 1 __packed; 109 uint32_t intr_io : 1 __packed; 110 uint32_t has_dma : 1 __packed; 111 uint32_t add_encoded_params : 1 __packed; 112 uint32_t rx_buffer_depth : 8 __packed; 113 uint32_t tx_buffer_depth : 8 __packed; 114 uint32_t reserved : 7 __packed; 115 } bits; 116 }; 117 118 #define DW_IC_REG_CON (0x00) 119 #define DW_IC_REG_TAR (0x04) 120 #define DW_IC_REG_SAR (0x08) 121 #define DW_IC_REG_DATA_CMD (0x10) 122 #define DW_IC_REG_SS_SCL_HCNT (0x14) 123 #define DW_IC_REG_SS_SCL_LCNT (0x18) 124 #define DW_IC_REG_FS_SCL_HCNT (0x1C) 125 #define DW_IC_REG_FS_SCL_LCNT (0x20) 126 #define DW_IC_REG_HS_SCL_HCNT (0x24) 127 #define DW_IC_REG_HS_SCL_LCNT (0x28) 128 #define DW_IC_REG_INTR_STAT (0x2C) 129 #define DW_IC_REG_INTR_MASK (0x30) 130 #define DW_IC_REG_RX_TL (0x38) 131 #define DW_IC_REG_TX_TL (0x3C) 132 #define DW_IC_REG_CLR_INTR (0x40) 133 #define DW_IC_REG_CLR_RX_UNDER (0x44) 134 #define DW_IC_REG_CLR_RX_OVER (0x48) 135 #define DW_IC_REG_CLR_TX_OVER (0x4c) 136 #define DW_IC_REG_CLR_RD_REQ (0x50) 137 #define DW_IC_REG_CLR_TX_ABRT (0x54) 138 #define DW_IC_REG_CLR_RX_DONE (0x58) 139 #define DW_IC_REG_CLR_ACTIVITY (0x5c) 140 #define DW_IC_REG_CLR_STOP_DET (0x60) 141 #define DW_IC_REG_CLR_START_DET (0x64) 142 #define DW_IC_REG_CLR_GEN_CALL (0x68) 143 #define DW_IC_REG_ENABLE (0x6C) 144 #define DW_IC_REG_STATUS (0x70) 145 #define DW_IC_REG_TXFLR (0x74) 146 #define DW_IC_REG_RXFLR (0x78) 147 #define DW_IC_REG_DMA_CR (0x88) 148 #define DW_IC_REG_TDLR (0x8C) 149 #define DW_IC_REG_RDLR (0x90) 150 #define DW_IC_REG_FS_SPKLEN (0xA0) 151 #define DW_IC_REG_HS_SPKLEN (0xA4) 152 #define DW_IC_REG_COMP_PARAM_1 (0xF4) 153 #define DW_IC_REG_COMP_TYPE (0xFC) 154 155 #define IDMA_REG_INTR_STS 0xAE8 156 #define IDMA_TX_RX_CHAN_MASK 0x3 157 158 /* CON Bit */ 159 #define DW_IC_CON_MASTER_MODE_BIT (0) 160 161 /* DMA control bits */ 162 #define DW_IC_DMA_RX_ENABLE BIT(0) 163 #define DW_IC_DMA_TX_ENABLE BIT(1) 164 #define DW_IC_DMA_ENABLE (BIT(0) | BIT(1)) 165 166 DEFINE_TEST_BIT_OP(con_master_mode, DW_IC_REG_CON, DW_IC_CON_MASTER_MODE_BIT) 167 DEFINE_MM_REG_WRITE(con, DW_IC_REG_CON, 32) 168 DEFINE_MM_REG_READ(con, DW_IC_REG_CON, 32) 169 170 DEFINE_MM_REG_WRITE(cmd_data, DW_IC_REG_DATA_CMD, 32) 171 DEFINE_MM_REG_READ(cmd_data, DW_IC_REG_DATA_CMD, 32) 172 173 DEFINE_MM_REG_WRITE(ss_scl_hcnt, DW_IC_REG_SS_SCL_HCNT, 32) 174 DEFINE_MM_REG_WRITE(ss_scl_lcnt, DW_IC_REG_SS_SCL_LCNT, 32) 175 176 DEFINE_MM_REG_WRITE(fs_scl_hcnt, DW_IC_REG_FS_SCL_HCNT, 32) 177 DEFINE_MM_REG_WRITE(fs_scl_lcnt, DW_IC_REG_FS_SCL_LCNT, 32) 178 179 DEFINE_MM_REG_WRITE(hs_scl_hcnt, DW_IC_REG_HS_SCL_HCNT, 32) 180 DEFINE_MM_REG_WRITE(hs_scl_lcnt, DW_IC_REG_HS_SCL_LCNT, 32) 181 182 183 184 DEFINE_MM_REG_READ(intr_stat, DW_IC_REG_INTR_STAT, 32) 185 #define DW_IC_INTR_STAT_TX_ABRT_BIT (6) 186 DEFINE_TEST_BIT_OP(intr_stat_tx_abrt, DW_IC_REG_INTR_STAT, DW_IC_INTR_STAT_TX_ABRT_BIT) 187 188 DEFINE_MM_REG_WRITE(intr_mask, DW_IC_REG_INTR_MASK, 32) 189 #define DW_IC_INTR_MASK_TX_EMPTY_BIT (4) 190 DEFINE_CLEAR_BIT_OP(intr_mask_tx_empty, DW_IC_REG_INTR_MASK, DW_IC_INTR_MASK_TX_EMPTY_BIT) 191 DEFINE_SET_BIT_OP(intr_mask_tx_empty, DW_IC_REG_INTR_MASK, DW_IC_INTR_MASK_TX_EMPTY_BIT) 192 193 DEFINE_MM_REG_WRITE(rx_tl, DW_IC_REG_RX_TL, 32) 194 DEFINE_MM_REG_WRITE(tx_tl, DW_IC_REG_TX_TL, 32) 195 196 DEFINE_MM_REG_READ(clr_intr, DW_IC_REG_CLR_INTR, 32) 197 DEFINE_MM_REG_READ(clr_stop_det, DW_IC_REG_CLR_STOP_DET, 32) 198 DEFINE_MM_REG_READ(clr_start_det, DW_IC_REG_CLR_START_DET, 32) 199 DEFINE_MM_REG_READ(clr_gen_call, DW_IC_REG_CLR_GEN_CALL, 32) 200 DEFINE_MM_REG_READ(clr_tx_abrt, DW_IC_REG_CLR_TX_ABRT, 32) 201 DEFINE_MM_REG_READ(clr_rx_under, DW_IC_REG_CLR_RX_UNDER, 32) 202 DEFINE_MM_REG_READ(clr_rx_over, DW_IC_REG_CLR_RX_OVER, 32) 203 DEFINE_MM_REG_READ(clr_tx_over, DW_IC_REG_CLR_TX_OVER, 32) 204 DEFINE_MM_REG_READ(clr_rx_done, DW_IC_REG_CLR_RX_DONE, 32) 205 DEFINE_MM_REG_READ(clr_rd_req, DW_IC_REG_CLR_RD_REQ, 32) 206 DEFINE_MM_REG_READ(clr_activity, DW_IC_REG_CLR_ACTIVITY, 32) 207 208 #define DW_IC_ENABLE_EN_BIT (0) 209 DEFINE_CLEAR_BIT_OP(enable_en, DW_IC_REG_ENABLE, DW_IC_ENABLE_EN_BIT) 210 DEFINE_SET_BIT_OP(enable_en, DW_IC_REG_ENABLE, DW_IC_ENABLE_EN_BIT) 211 212 213 #define DW_IC_STATUS_ACTIVITY_BIT (0) 214 #define DW_IC_STATUS_TFNT_BIT (1) 215 #define DW_IC_STATUS_RFNE_BIT (3) 216 DEFINE_TEST_BIT_OP(status_activity, DW_IC_REG_STATUS, DW_IC_STATUS_ACTIVITY_BIT) 217 DEFINE_TEST_BIT_OP(status_tfnt, DW_IC_REG_STATUS, DW_IC_STATUS_TFNT_BIT) 218 DEFINE_TEST_BIT_OP(status_rfne, DW_IC_REG_STATUS, DW_IC_STATUS_RFNE_BIT) 219 220 DEFINE_MM_REG_READ(txflr, DW_IC_REG_TXFLR, 32) 221 DEFINE_MM_REG_READ(rxflr, DW_IC_REG_RXFLR, 32) 222 223 DEFINE_MM_REG_READ(dma_cr, DW_IC_REG_DMA_CR, 32) 224 DEFINE_MM_REG_WRITE(dma_cr, DW_IC_REG_DMA_CR, 32) 225 226 DEFINE_MM_REG_READ(tdlr, DW_IC_REG_TDLR, 32) 227 DEFINE_MM_REG_WRITE(tdlr, DW_IC_REG_TDLR, 32) 228 DEFINE_MM_REG_READ(rdlr, DW_IC_REG_RDLR, 32) 229 DEFINE_MM_REG_WRITE(rdlr, DW_IC_REG_RDLR, 32) 230 231 DEFINE_MM_REG_READ(fs_spklen, DW_IC_REG_FS_SPKLEN, 32) 232 DEFINE_MM_REG_READ(hs_spklen, DW_IC_REG_HS_SPKLEN, 32) 233 234 DEFINE_MM_REG_READ(comp_param_1, DW_IC_REG_COMP_PARAM_1, 32) 235 DEFINE_MM_REG_READ(comp_type, DW_IC_REG_COMP_TYPE, 32) 236 DEFINE_MM_REG_READ(tar, DW_IC_REG_TAR, 32) 237 DEFINE_MM_REG_WRITE(tar, DW_IC_REG_TAR, 32) 238 DEFINE_MM_REG_WRITE(sar, DW_IC_REG_SAR, 32) 239 240 #ifdef __cplusplus 241 } 242 #endif 243 244 #endif /* ZEPHYR_DRIVERS_I2C_I2C_DW_REGISTERS_H_ */ 245
