1 /***************************************************************************//** 2 * \file cyip_dw.h 3 * 4 * \brief 5 * DW IP definitions 6 * 7 * \note 8 * Generator version: 1.6.0.409 9 * 10 ******************************************************************************** 11 * \copyright 12 * Copyright 2016-2020 Cypress Semiconductor Corporation 13 * SPDX-License-Identifier: Apache-2.0 14 * 15 * Licensed under the Apache License, Version 2.0 (the "License"); 16 * you may not use this file except in compliance with the License. 17 * You may obtain a copy of the License at 18 * 19 * http://www.apache.org/licenses/LICENSE-2.0 20 * 21 * Unless required by applicable law or agreed to in writing, software 22 * distributed under the License is distributed on an "AS IS" BASIS, 23 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 24 * See the License for the specific language governing permissions and 25 * limitations under the License. 26 *******************************************************************************/ 27 28 #ifndef _CYIP_DW_H_ 29 #define _CYIP_DW_H_ 30 31 #include "cyip_headers.h" 32 33 /******************************************************************************* 34 * DW 35 *******************************************************************************/ 36 37 #define DW_CH_STRUCT_SECTION_SIZE 0x00000020UL 38 #define DW_SECTION_SIZE 0x00001000UL 39 40 /** 41 * \brief DW channel structure (DW_CH_STRUCT) 42 */ 43 typedef struct { 44 __IOM uint32_t CH_CTL; /*!< 0x00000000 Channel control */ 45 __IM uint32_t CH_STATUS; /*!< 0x00000004 Channel status */ 46 __IOM uint32_t CH_IDX; /*!< 0x00000008 Channel current indices */ 47 __IOM uint32_t CH_CURR_PTR; /*!< 0x0000000C Channel current descriptor pointer */ 48 __IOM uint32_t INTR; /*!< 0x00000010 Interrupt */ 49 __IOM uint32_t INTR_SET; /*!< 0x00000014 Interrupt set */ 50 __IOM uint32_t INTR_MASK; /*!< 0x00000018 Interrupt mask */ 51 __IM uint32_t INTR_MASKED; /*!< 0x0000001C Interrupt masked */ 52 } DW_CH_STRUCT_V1_Type; /*!< Size = 32 (0x20) */ 53 54 /** 55 * \brief Datawire Controller (DW) 56 */ 57 typedef struct { 58 __IOM uint32_t CTL; /*!< 0x00000000 Control */ 59 __IM uint32_t STATUS; /*!< 0x00000004 Status */ 60 __IM uint32_t PENDING; /*!< 0x00000008 Pending channels */ 61 __IM uint32_t RESERVED; 62 __IM uint32_t STATUS_INTR; /*!< 0x00000010 System interrupt control */ 63 __IM uint32_t STATUS_INTR_MASKED; /*!< 0x00000014 Status of interrupts masked */ 64 __IM uint32_t RESERVED1[2]; 65 __IM uint32_t ACT_DESCR_CTL; /*!< 0x00000020 Active descriptor control */ 66 __IM uint32_t ACT_DESCR_SRC; /*!< 0x00000024 Active descriptor source */ 67 __IM uint32_t ACT_DESCR_DST; /*!< 0x00000028 Active descriptor destination */ 68 __IM uint32_t RESERVED2; 69 __IM uint32_t ACT_DESCR_X_CTL; /*!< 0x00000030 Active descriptor X loop control */ 70 __IM uint32_t ACT_DESCR_Y_CTL; /*!< 0x00000034 Active descriptor Y loop control */ 71 __IM uint32_t ACT_DESCR_NEXT_PTR; /*!< 0x00000038 Active descriptor next pointer */ 72 __IM uint32_t RESERVED3; 73 __IM uint32_t ACT_SRC; /*!< 0x00000040 Active source */ 74 __IM uint32_t ACT_DST; /*!< 0x00000044 Active destination */ 75 __IM uint32_t RESERVED4[494]; 76 DW_CH_STRUCT_V1_Type CH_STRUCT[32]; /*!< 0x00000800 DW channel structure */ 77 } DW_V1_Type; /*!< Size = 3072 (0xC00) */ 78 79 80 /* DW_CH_STRUCT.CH_CTL */ 81 #define DW_CH_STRUCT_CH_CTL_P_Pos 0UL 82 #define DW_CH_STRUCT_CH_CTL_P_Msk 0x1UL 83 #define DW_CH_STRUCT_CH_CTL_NS_Pos 1UL 84 #define DW_CH_STRUCT_CH_CTL_NS_Msk 0x2UL 85 #define DW_CH_STRUCT_CH_CTL_B_Pos 2UL 86 #define DW_CH_STRUCT_CH_CTL_B_Msk 0x4UL 87 #define DW_CH_STRUCT_CH_CTL_PC_Pos 4UL 88 #define DW_CH_STRUCT_CH_CTL_PC_Msk 0xF0UL 89 #define DW_CH_STRUCT_CH_CTL_PRIO_Pos 16UL 90 #define DW_CH_STRUCT_CH_CTL_PRIO_Msk 0x30000UL 91 #define DW_CH_STRUCT_CH_CTL_PREEMPTABLE_Pos 18UL 92 #define DW_CH_STRUCT_CH_CTL_PREEMPTABLE_Msk 0x40000UL 93 #define DW_CH_STRUCT_CH_CTL_ENABLED_Pos 31UL 94 #define DW_CH_STRUCT_CH_CTL_ENABLED_Msk 0x80000000UL 95 /* DW_CH_STRUCT.CH_STATUS */ 96 #define DW_CH_STRUCT_CH_STATUS_INTR_CAUSE_Pos 0UL 97 #define DW_CH_STRUCT_CH_STATUS_INTR_CAUSE_Msk 0xFUL 98 /* DW_CH_STRUCT.CH_IDX */ 99 #define DW_CH_STRUCT_CH_IDX_X_IDX_Pos 0UL 100 #define DW_CH_STRUCT_CH_IDX_X_IDX_Msk 0xFFUL 101 #define DW_CH_STRUCT_CH_IDX_Y_IDX_Pos 8UL 102 #define DW_CH_STRUCT_CH_IDX_Y_IDX_Msk 0xFF00UL 103 /* DW_CH_STRUCT.CH_CURR_PTR */ 104 #define DW_CH_STRUCT_CH_CURR_PTR_ADDR_Pos 2UL 105 #define DW_CH_STRUCT_CH_CURR_PTR_ADDR_Msk 0xFFFFFFFCUL 106 /* DW_CH_STRUCT.INTR */ 107 #define DW_CH_STRUCT_INTR_CH_Pos 0UL 108 #define DW_CH_STRUCT_INTR_CH_Msk 0x1UL 109 /* DW_CH_STRUCT.INTR_SET */ 110 #define DW_CH_STRUCT_INTR_SET_CH_Pos 0UL 111 #define DW_CH_STRUCT_INTR_SET_CH_Msk 0x1UL 112 /* DW_CH_STRUCT.INTR_MASK */ 113 #define DW_CH_STRUCT_INTR_MASK_CH_Pos 0UL 114 #define DW_CH_STRUCT_INTR_MASK_CH_Msk 0x1UL 115 /* DW_CH_STRUCT.INTR_MASKED */ 116 #define DW_CH_STRUCT_INTR_MASKED_CH_Pos 0UL 117 #define DW_CH_STRUCT_INTR_MASKED_CH_Msk 0x1UL 118 119 120 /* DW.CTL */ 121 #define DW_CTL_ENABLED_Pos 31UL 122 #define DW_CTL_ENABLED_Msk 0x80000000UL 123 /* DW.STATUS */ 124 #define DW_STATUS_P_Pos 0UL 125 #define DW_STATUS_P_Msk 0x1UL 126 #define DW_STATUS_NS_Pos 1UL 127 #define DW_STATUS_NS_Msk 0x2UL 128 #define DW_STATUS_B_Pos 2UL 129 #define DW_STATUS_B_Msk 0x4UL 130 #define DW_STATUS_PC_Pos 4UL 131 #define DW_STATUS_PC_Msk 0xF0UL 132 #define DW_STATUS_CH_IDX_Pos 8UL 133 #define DW_STATUS_CH_IDX_Msk 0x1F00UL 134 #define DW_STATUS_PRIO_Pos 16UL 135 #define DW_STATUS_PRIO_Msk 0x30000UL 136 #define DW_STATUS_PREEMPTABLE_Pos 18UL 137 #define DW_STATUS_PREEMPTABLE_Msk 0x40000UL 138 #define DW_STATUS_STATE_Pos 20UL 139 #define DW_STATUS_STATE_Msk 0x700000UL 140 #define DW_STATUS_ACTIVE_Pos 31UL 141 #define DW_STATUS_ACTIVE_Msk 0x80000000UL 142 /* DW.PENDING */ 143 #define DW_PENDING_CH_PENDING_Pos 0UL 144 #define DW_PENDING_CH_PENDING_Msk 0xFFFFFFFFUL 145 /* DW.STATUS_INTR */ 146 #define DW_STATUS_INTR_CH_Pos 0UL 147 #define DW_STATUS_INTR_CH_Msk 0xFFFFFFFFUL 148 /* DW.STATUS_INTR_MASKED */ 149 #define DW_STATUS_INTR_MASKED_CH_Pos 0UL 150 #define DW_STATUS_INTR_MASKED_CH_Msk 0xFFFFFFFFUL 151 /* DW.ACT_DESCR_CTL */ 152 #define DW_ACT_DESCR_CTL_DATA_Pos 0UL 153 #define DW_ACT_DESCR_CTL_DATA_Msk 0xFFFFFFFFUL 154 /* DW.ACT_DESCR_SRC */ 155 #define DW_ACT_DESCR_SRC_DATA_Pos 0UL 156 #define DW_ACT_DESCR_SRC_DATA_Msk 0xFFFFFFFFUL 157 /* DW.ACT_DESCR_DST */ 158 #define DW_ACT_DESCR_DST_DATA_Pos 0UL 159 #define DW_ACT_DESCR_DST_DATA_Msk 0xFFFFFFFFUL 160 /* DW.ACT_DESCR_X_CTL */ 161 #define DW_ACT_DESCR_X_CTL_DATA_Pos 0UL 162 #define DW_ACT_DESCR_X_CTL_DATA_Msk 0xFFFFFFFFUL 163 /* DW.ACT_DESCR_Y_CTL */ 164 #define DW_ACT_DESCR_Y_CTL_DATA_Pos 0UL 165 #define DW_ACT_DESCR_Y_CTL_DATA_Msk 0xFFFFFFFFUL 166 /* DW.ACT_DESCR_NEXT_PTR */ 167 #define DW_ACT_DESCR_NEXT_PTR_ADDR_Pos 2UL 168 #define DW_ACT_DESCR_NEXT_PTR_ADDR_Msk 0xFFFFFFFCUL 169 /* DW.ACT_SRC */ 170 #define DW_ACT_SRC_SRC_ADDR_Pos 0UL 171 #define DW_ACT_SRC_SRC_ADDR_Msk 0xFFFFFFFFUL 172 /* DW.ACT_DST */ 173 #define DW_ACT_DST_DST_ADDR_Pos 0UL 174 #define DW_ACT_DST_DST_ADDR_Msk 0xFFFFFFFFUL 175 176 177 #endif /* _CYIP_DW_H_ */ 178 179 180 /* [] END OF FILE */ 181
