1 /* 2 * Copyright (c) 2015-2023, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <arch.h> 11 #include <drivers/arm/gic_common.h> 12 #include <lib/utils_def.h> 13 #include <plat/common/common_def.h> 14 15 #include "../stm32mp1_def.h" 16 17 /******************************************************************************* 18 * Generic platform constants 19 ******************************************************************************/ 20 21 /* Size of cacheable stacks */ 22 #if defined(IMAGE_BL32) 23 #define PLATFORM_STACK_SIZE 0x600 24 #else 25 #define PLATFORM_STACK_SIZE 0xC00 26 #endif 27 28 #define STM32MP_PRIMARY_CPU U(0x0) 29 #define STM32MP_SECONDARY_CPU U(0x1) 30 31 #define PLATFORM_CLUSTER_COUNT U(1) 32 #define PLATFORM_CLUSTER0_CORE_COUNT U(2) 33 #define PLATFORM_CLUSTER1_CORE_COUNT U(0) 34 #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \ 35 PLATFORM_CLUSTER0_CORE_COUNT) 36 #define PLATFORM_MAX_CPUS_PER_CLUSTER 2 37 38 #define MAX_IO_DEVICES U(4) 39 #define MAX_IO_HANDLES U(4) 40 #define MAX_IO_BLOCK_DEVICES U(1) 41 #define MAX_IO_MTD_DEVICES U(1) 42 43 /******************************************************************************* 44 * BL2 specific defines. 45 ******************************************************************************/ 46 /* 47 * Put BL2 just below BL3-1. BL2_BASE is calculated using the current BL2 debug 48 * size plus a little space for growth. 49 */ 50 #define BL2_BASE STM32MP_BL2_BASE 51 #define BL2_LIMIT (STM32MP_BL2_BASE + \ 52 STM32MP_BL2_SIZE) 53 54 #define BL2_RO_BASE STM32MP_BL2_RO_BASE 55 #define BL2_RO_LIMIT (STM32MP_BL2_RO_BASE + \ 56 STM32MP_BL2_RO_SIZE) 57 58 #define BL2_RW_BASE STM32MP_BL2_RW_BASE 59 #define BL2_RW_LIMIT (STM32MP_BL2_RW_BASE + \ 60 STM32MP_BL2_RW_SIZE) 61 /******************************************************************************* 62 * BL32 specific defines. 63 ******************************************************************************/ 64 #if defined(IMAGE_BL32) 65 #if ENABLE_PIE 66 #define BL32_BASE 0 67 #define BL32_LIMIT STM32MP_BL32_SIZE 68 #else 69 #define BL32_BASE STM32MP_BL32_BASE 70 #define BL32_LIMIT (STM32MP_BL32_BASE + \ 71 STM32MP_BL32_SIZE) 72 #endif 73 #endif /* defined(IMAGE_BL32) */ 74 75 /******************************************************************************* 76 * BL33 specific defines. 77 ******************************************************************************/ 78 #define BL33_BASE STM32MP_BL33_BASE 79 80 /* 81 * Load address of BL33 for this platform port 82 */ 83 #define PLAT_STM32MP_NS_IMAGE_OFFSET BL33_BASE 84 85 /* Needed by STM32CubeProgrammer support */ 86 #define DWL_BUFFER_SIZE U(0x01000000) 87 88 /* 89 * SSBL offset in case it's stored in eMMC boot partition. 90 * We can fix it to 256K because TF-A size can't be bigger than SRAM 91 */ 92 #define PLAT_EMMC_BOOT_SSBL_OFFSET U(0x40000) 93 94 /******************************************************************************* 95 * DTB specific defines. 96 ******************************************************************************/ 97 #define DTB_BASE STM32MP_DTB_BASE 98 #define DTB_LIMIT (STM32MP_DTB_BASE + \ 99 STM32MP_DTB_SIZE) 100 101 /******************************************************************************* 102 * Platform specific page table and MMU setup constants 103 ******************************************************************************/ 104 #define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 32) 105 #define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 32) 106 107 /******************************************************************************* 108 * Declarations and constants to access the mailboxes safely. Each mailbox is 109 * aligned on the biggest cache line size in the platform. This is known only 110 * to the platform as it might have a combination of integrated and external 111 * caches. Such alignment ensures that two maiboxes do not sit on the same cache 112 * line at any cache level. They could belong to different cpus/clusters & 113 * get written while being protected by different locks causing corruption of 114 * a valid mailbox address. 115 ******************************************************************************/ 116 #define CACHE_WRITEBACK_SHIFT 6 117 #define CACHE_WRITEBACK_GRANULE (U(1) << CACHE_WRITEBACK_SHIFT) 118 119 /* 120 * Secure Interrupt: based on the standard ARM mapping 121 */ 122 #define ARM_IRQ_SEC_PHY_TIMER U(29) 123 124 #define ARM_IRQ_SEC_SGI_0 U(8) 125 #define ARM_IRQ_SEC_SGI_1 U(9) 126 #define ARM_IRQ_SEC_SGI_2 U(10) 127 #define ARM_IRQ_SEC_SGI_3 U(11) 128 #define ARM_IRQ_SEC_SGI_4 U(12) 129 #define ARM_IRQ_SEC_SGI_5 U(13) 130 #define ARM_IRQ_SEC_SGI_6 U(14) 131 #define ARM_IRQ_SEC_SGI_7 U(15) 132 133 #define STM32MP1_IRQ_TZC400 U(36) 134 #define STM32MP1_IRQ_TAMPSERRS U(229) 135 #define STM32MP1_IRQ_AXIERRIRQ U(244) 136 137 /* 138 * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 139 * terminology. On a GICv2 system or mode, the lists will be merged and treated 140 * as Group 0 interrupts. 141 */ 142 #define PLATFORM_G1S_PROPS(grp) \ 143 INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, \ 144 GIC_HIGHEST_SEC_PRIORITY, \ 145 grp, GIC_INTR_CFG_LEVEL), \ 146 INTR_PROP_DESC(STM32MP1_IRQ_AXIERRIRQ, \ 147 GIC_HIGHEST_SEC_PRIORITY, \ 148 grp, GIC_INTR_CFG_LEVEL), \ 149 INTR_PROP_DESC(STM32MP1_IRQ_TZC400, \ 150 GIC_HIGHEST_SEC_PRIORITY, \ 151 grp, GIC_INTR_CFG_LEVEL), \ 152 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, \ 153 GIC_HIGHEST_SEC_PRIORITY, \ 154 grp, GIC_INTR_CFG_EDGE), \ 155 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, \ 156 GIC_HIGHEST_SEC_PRIORITY, \ 157 grp, GIC_INTR_CFG_EDGE), \ 158 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, \ 159 GIC_HIGHEST_SEC_PRIORITY, \ 160 grp, GIC_INTR_CFG_EDGE), \ 161 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, \ 162 GIC_HIGHEST_SEC_PRIORITY, \ 163 grp, GIC_INTR_CFG_EDGE), \ 164 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, \ 165 GIC_HIGHEST_SEC_PRIORITY, \ 166 grp, GIC_INTR_CFG_EDGE), \ 167 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, \ 168 GIC_HIGHEST_SEC_PRIORITY, \ 169 grp, GIC_INTR_CFG_EDGE) 170 171 #define PLATFORM_G0_PROPS(grp) \ 172 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, \ 173 GIC_HIGHEST_SEC_PRIORITY, \ 174 grp, GIC_INTR_CFG_EDGE), \ 175 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, \ 176 GIC_HIGHEST_SEC_PRIORITY, \ 177 grp, GIC_INTR_CFG_EDGE) 178 179 /* 180 * Power 181 */ 182 #define PLAT_MAX_PWR_LVL U(1) 183 184 /* Local power state for power domains in Run state. */ 185 #define ARM_LOCAL_STATE_RUN U(0) 186 /* Local power state for retention. Valid only for CPU power domains */ 187 #define ARM_LOCAL_STATE_RET U(1) 188 /* Local power state for power-down. Valid for CPU and cluster power domains */ 189 #define ARM_LOCAL_STATE_OFF U(2) 190 /* 191 * This macro defines the deepest retention state possible. 192 * A higher state id will represent an invalid or a power down state. 193 */ 194 #define PLAT_MAX_RET_STATE ARM_LOCAL_STATE_RET 195 /* 196 * This macro defines the deepest power down states possible. Any state ID 197 * higher than this is invalid. 198 */ 199 #define PLAT_MAX_OFF_STATE ARM_LOCAL_STATE_OFF 200 201 /******************************************************************************* 202 * Size of the per-cpu data in bytes that should be reserved in the generic 203 * per-cpu data structure for the FVP port. 204 ******************************************************************************/ 205 #define PLAT_PCPU_DATA_SIZE 2 206 207 /******************************************************************************* 208 * Number of parallel entry slots in SMT SCMI server entry context. For this 209 * platform, SCMI server is reached through SMC only, hence the number of 210 * entry slots. 211 ******************************************************************************/ 212 #define PLAT_SMT_ENTRY_COUNT PLATFORM_CORE_COUNT 213 214 #endif /* PLATFORM_DEF_H */ 215
