1 /* 2 * Copyright 2019 Broadcom 3 * The term "Broadcom" refers to Broadcom Inc. and/or its subsidiaries. 4 * 5 * SPDX-License-Identifier: Apache-2.0 6 */ 7 8 /* Set below flag to get debug prints */ 9 #define MMU_DEBUG_PRINTS 0 10 11 #if MMU_DEBUG_PRINTS 12 /* To dump page table entries while filling them, set DUMP_PTE macro */ 13 #define DUMP_PTE 0 14 #define MMU_DEBUG(fmt, ...) printk(fmt, ##__VA_ARGS__) 15 #else 16 #define MMU_DEBUG(...) 17 #endif 18 19 /* 20 * 48-bit address with 4KB granule size: 21 * 22 * +------------+------------+------------+------------+-----------+ 23 * | VA [47:39] | VA [38:30] | VA [29:21] | VA [20:12] | VA [11:0] | 24 * +---------------------------------------------------------------+ 25 * | L0 | L1 | L2 | L3 | block off | 26 * +------------+------------+------------+------------+-----------+ 27 */ 28 29 /* Only 4K granule is supported */ 30 #define PAGE_SIZE_SHIFT 12U 31 32 /* 48-bit VA address */ 33 #define VA_SIZE_SHIFT_MAX 48U 34 35 /* Maximum 4 XLAT table levels (L0 - L3) */ 36 #define XLAT_LAST_LEVEL 3U 37 38 /* The VA shift of L3 depends on the granule size */ 39 #define L3_XLAT_VA_SIZE_SHIFT PAGE_SIZE_SHIFT 40 41 /* Number of VA bits to assign to each table (9 bits) */ 42 #define Ln_XLAT_VA_SIZE_SHIFT (PAGE_SIZE_SHIFT - 3) 43 44 /* Starting bit in the VA address for each level */ 45 #define L2_XLAT_VA_SIZE_SHIFT (L3_XLAT_VA_SIZE_SHIFT + Ln_XLAT_VA_SIZE_SHIFT) 46 #define L1_XLAT_VA_SIZE_SHIFT (L2_XLAT_VA_SIZE_SHIFT + Ln_XLAT_VA_SIZE_SHIFT) 47 #define L0_XLAT_VA_SIZE_SHIFT (L1_XLAT_VA_SIZE_SHIFT + Ln_XLAT_VA_SIZE_SHIFT) 48 49 #define LEVEL_TO_VA_SIZE_SHIFT(level) \ 50 (PAGE_SIZE_SHIFT + (Ln_XLAT_VA_SIZE_SHIFT * \ 51 (XLAT_LAST_LEVEL - (level)))) 52 53 /* Number of entries for each table (512) */ 54 #define Ln_XLAT_NUM_ENTRIES ((1U << PAGE_SIZE_SHIFT) / 8U) 55 56 /* Virtual Address Index within a given translation table level */ 57 #define XLAT_TABLE_VA_IDX(va_addr, level) \ 58 ((va_addr >> LEVEL_TO_VA_SIZE_SHIFT(level)) & (Ln_XLAT_NUM_ENTRIES - 1)) 59 60 /* 61 * Calculate the initial translation table level from CONFIG_ARM64_VA_BITS 62 * For a 4 KB page size: 63 * 64 * (va_bits <= 21) - base level 3 65 * (22 <= va_bits <= 30) - base level 2 66 * (31 <= va_bits <= 39) - base level 1 67 * (40 <= va_bits <= 48) - base level 0 68 */ 69 #define GET_BASE_XLAT_LEVEL(va_bits) \ 70 ((va_bits > L0_XLAT_VA_SIZE_SHIFT) ? 0U \ 71 : (va_bits > L1_XLAT_VA_SIZE_SHIFT) ? 1U \ 72 : (va_bits > L2_XLAT_VA_SIZE_SHIFT) ? 2U : 3U) 73 74 /* Level for the base XLAT */ 75 #define BASE_XLAT_LEVEL GET_BASE_XLAT_LEVEL(CONFIG_ARM64_VA_BITS) 76 77 #if (CONFIG_ARM64_PA_BITS == 48) 78 #define TCR_PS_BITS TCR_PS_BITS_256TB 79 #elif (CONFIG_ARM64_PA_BITS == 44) 80 #define TCR_PS_BITS TCR_PS_BITS_16TB 81 #elif (CONFIG_ARM64_PA_BITS == 42) 82 #define TCR_PS_BITS TCR_PS_BITS_4TB 83 #elif (CONFIG_ARM64_PA_BITS == 40) 84 #define TCR_PS_BITS TCR_PS_BITS_1TB 85 #elif (CONFIG_ARM64_PA_BITS == 36) 86 #define TCR_PS_BITS TCR_PS_BITS_64GB 87 #else 88 #define TCR_PS_BITS TCR_PS_BITS_4GB 89 #endif 90 91 /* Upper and lower attributes mask for page/block descriptor */ 92 #define DESC_ATTRS_UPPER_MASK GENMASK(63, 51) 93 #define DESC_ATTRS_LOWER_MASK GENMASK(11, 2) 94 95 #define DESC_ATTRS_MASK (DESC_ATTRS_UPPER_MASK | DESC_ATTRS_LOWER_MASK) 96 97 /* 98 * PTE descriptor can be Block descriptor or Table descriptor 99 * or Page descriptor. 100 */ 101 #define PTE_DESC_TYPE_MASK 3ULL 102 #define PTE_BLOCK_DESC 1ULL 103 #define PTE_TABLE_DESC 3ULL 104 #define PTE_PAGE_DESC 3ULL 105 #define PTE_INVALID_DESC 0ULL 106 107 /* 108 * Block and Page descriptor attributes fields 109 */ 110 #define PTE_BLOCK_DESC_MEMTYPE(x) (x << 2) 111 #define PTE_BLOCK_DESC_NS (1ULL << 5) 112 #define PTE_BLOCK_DESC_AP_ELx (1ULL << 6) 113 #define PTE_BLOCK_DESC_AP_EL_HIGHER (0ULL << 6) 114 #define PTE_BLOCK_DESC_AP_RO (1ULL << 7) 115 #define PTE_BLOCK_DESC_AP_RW (0ULL << 7) 116 #define PTE_BLOCK_DESC_NON_SHARE (0ULL << 8) 117 #define PTE_BLOCK_DESC_OUTER_SHARE (2ULL << 8) 118 #define PTE_BLOCK_DESC_INNER_SHARE (3ULL << 8) 119 #define PTE_BLOCK_DESC_AF (1ULL << 10) 120 #define PTE_BLOCK_DESC_NG (1ULL << 11) 121 #define PTE_BLOCK_DESC_PXN (1ULL << 53) 122 #define PTE_BLOCK_DESC_UXN (1ULL << 54) 123 124 /* 125 * Descriptor physical address field bits 126 */ 127 #define PTE_PHYSADDR_MASK GENMASK64(47, PAGE_SIZE_SHIFT) 128 129 /* 130 * TCR definitions. 131 */ 132 #define TCR_EL1_IPS_SHIFT 32U 133 #define TCR_EL2_PS_SHIFT 16U 134 #define TCR_EL3_PS_SHIFT 16U 135 136 #define TCR_T0SZ_SHIFT 0U 137 #define TCR_T0SZ(x) ((64 - (x)) << TCR_T0SZ_SHIFT) 138 139 #define TCR_IRGN_NC (0ULL << 8) 140 #define TCR_IRGN_WBWA (1ULL << 8) 141 #define TCR_IRGN_WT (2ULL << 8) 142 #define TCR_IRGN_WBNWA (3ULL << 8) 143 #define TCR_IRGN_MASK (3ULL << 8) 144 #define TCR_ORGN_NC (0ULL << 10) 145 #define TCR_ORGN_WBWA (1ULL << 10) 146 #define TCR_ORGN_WT (2ULL << 10) 147 #define TCR_ORGN_WBNWA (3ULL << 10) 148 #define TCR_ORGN_MASK (3ULL << 10) 149 #define TCR_SHARED_NON (0ULL << 12) 150 #define TCR_SHARED_OUTER (2ULL << 12) 151 #define TCR_SHARED_INNER (3ULL << 12) 152 #define TCR_TG0_4K (0ULL << 14) 153 #define TCR_TG0_64K (1ULL << 14) 154 #define TCR_TG0_16K (2ULL << 14) 155 #define TCR_EPD1_DISABLE (1ULL << 23) 156 #define TCR_TG1_16K (1ULL << 30) 157 #define TCR_TG1_4K (2ULL << 30) 158 #define TCR_TG1_64K (3ULL << 30) 159 160 #define TCR_PS_BITS_4GB 0x0ULL 161 #define TCR_PS_BITS_64GB 0x1ULL 162 #define TCR_PS_BITS_1TB 0x2ULL 163 #define TCR_PS_BITS_4TB 0x3ULL 164 #define TCR_PS_BITS_16TB 0x4ULL 165 #define TCR_PS_BITS_256TB 0x5ULL 166 167 /* 168 * ARM guarantees at least 8 ASID bits. 169 * We may have more available, but do not make use of them for the time being. 170 */ 171 #define VM_ASID_BITS 8 172 #define TTBR_ASID_SHIFT 48 173
