1 /* 2 * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 8 * Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 11 * Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the 14 * distribution. 15 * 16 * Neither the name of Texas Instruments Incorporated nor the names of 17 * its contributors may be used to endorse or promote products derived 18 * from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 */ 33 //***************************************************************************** 34 35 #ifndef __HW_DTHE_H__ 36 #define __HW_DTHE_H__ 37 38 //***************************************************************************** 39 // 40 // The following are defines for the DTHE register offsets. 41 // 42 //***************************************************************************** 43 #define DTHE_O_SHA_IM 0x00000810 44 #define DTHE_O_SHA_RIS 0x00000814 45 #define DTHE_O_SHA_MIS 0x00000818 46 #define DTHE_O_SHA_IC 0x0000081C 47 #define DTHE_O_AES_IM 0x00000820 48 #define DTHE_O_AES_RIS 0x00000824 49 #define DTHE_O_AES_MIS 0x00000828 50 #define DTHE_O_AES_IC 0x0000082C 51 #define DTHE_O_DES_IM 0x00000830 52 #define DTHE_O_DES_RIS 0x00000834 53 #define DTHE_O_DES_MIS 0x00000838 54 #define DTHE_O_DES_IC 0x0000083C 55 #define DTHE_O_EIP_CGCFG 0x00000A00 56 #define DTHE_O_EIP_CGREQ 0x00000A04 57 #define DTHE_O_CRC_CTRL 0x00000C00 58 #define DTHE_O_CRC_SEED 0x00000C10 59 #define DTHE_O_CRC_DIN 0x00000C14 60 #define DTHE_O_CRC_RSLT_PP 0x00000C18 61 #define DTHE_O_RAND_KEY0 0x00000F00 62 #define DTHE_O_RAND_KEY1 0x00000F04 63 #define DTHE_O_RAND_KEY2 0x00000F08 64 #define DTHE_O_RAND_KEY3 0x00000F0C 65 66 67 //****************************************************************************** 68 // 69 // The following are defines for the bit fields in the 70 // DTHE_O_SHAMD5_IMST register. 71 // 72 //****************************************************************************** 73 #define DTHE_SHAMD5_IMST_DIN 0x00000004 // Data in: this interrupt is 74 // raised when DMA writes last word 75 // of input data to internal FIFO of 76 // the engine 77 #define DTHE_SHAMD5_IMST_COUT 0x00000002 // Context out: this interrupt is 78 // raised when DMA complets the 79 // output context movement from 80 // internal register 81 #define DTHE_SHAMD5_IMST_CIN 0x00000001 // context in: this interrupt is 82 // raised when DMA complets Context 83 // write to internal register 84 //****************************************************************************** 85 // 86 // The following are defines for the bit fields in the 87 // DTHE_O_SHAMD5_IRIS register. 88 // 89 //****************************************************************************** 90 #define DTHE_SHAMD5_IRIS_DIN 0x00000004 // input Data movement is done 91 #define DTHE_SHAMD5_IRIS_COUT 0x00000002 // Context output is done 92 #define DTHE_SHAMD5_IRIS_CIN 0x00000001 // context input is done 93 //****************************************************************************** 94 // 95 // The following are defines for the bit fields in the 96 // DTHE_O_SHAMD5_IMIS register. 97 // 98 //****************************************************************************** 99 #define DTHE_SHAMD5_IMIS_DIN 0x00000004 // input Data movement is done 100 #define DTHE_SHAMD5_IMIS_COUT 0x00000002 // Context output is done 101 #define DTHE_SHAMD5_IMIS_CIN 0x00000001 // context input is done 102 //****************************************************************************** 103 // 104 // The following are defines for the bit fields in the 105 // DTHE_O_SHAMD5_ICIS register. 106 // 107 //****************************************************************************** 108 #define DTHE_SHAMD5_ICIS_DIN 0x00000004 // Clear “input Data movement done�? 109 // flag 110 #define DTHE_SHAMD5_ICIS_COUT 0x00000002 // Clear “Context output done�? flag 111 #define DTHE_SHAMD5_ICIS_CIN 0x00000001 // Clear “context input done�? flag 112 //****************************************************************************** 113 // 114 // The following are defines for the bit fields in the 115 // DTHE_O_AES_IMST register. 116 // 117 //****************************************************************************** 118 #define DTHE_AES_IMST_DOUT 0x00000008 // Data out: this interrupt is 119 // raised when DMA finishes writing 120 // last word of the process result 121 #define DTHE_AES_IMST_DIN 0x00000004 // Data in: this interrupt is 122 // raised when DMA writes last word 123 // of input data to internal FIFO of 124 // the engine 125 #define DTHE_AES_IMST_COUT 0x00000002 // Context out: this interrupt is 126 // raised when DMA complets the 127 // output context movement from 128 // internal register 129 #define DTHE_AES_IMST_CIN 0x00000001 // context in: this interrupt is 130 // raised when DMA complets Context 131 // write to internal register 132 //****************************************************************************** 133 // 134 // The following are defines for the bit fields in the 135 // DTHE_O_AES_IRIS register. 136 // 137 //****************************************************************************** 138 #define DTHE_AES_IRIS_DOUT 0x00000008 // Output Data movement is done 139 #define DTHE_AES_IRIS_DIN 0x00000004 // input Data movement is done 140 #define DTHE_AES_IRIS_COUT 0x00000002 // Context output is done 141 #define DTHE_AES_IRIS_CIN 0x00000001 // context input is done 142 //****************************************************************************** 143 // 144 // The following are defines for the bit fields in the 145 // DTHE_O_AES_IMIS register. 146 // 147 //****************************************************************************** 148 #define DTHE_AES_IMIS_DOUT 0x00000008 // Output Data movement is done 149 #define DTHE_AES_IMIS_DIN 0x00000004 // input Data movement is done 150 #define DTHE_AES_IMIS_COUT 0x00000002 // Context output is done 151 #define DTHE_AES_IMIS_CIN 0x00000001 // context input is done 152 //****************************************************************************** 153 // 154 // The following are defines for the bit fields in the 155 // DTHE_O_AES_ICIS register. 156 // 157 //****************************************************************************** 158 #define DTHE_AES_ICIS_DOUT 0x00000008 // Clear “output Data movement 159 // done�? flag 160 #define DTHE_AES_ICIS_DIN 0x00000004 // Clear “input Data movement done�? 161 // flag 162 #define DTHE_AES_ICIS_COUT 0x00000002 // Clear “Context output done�? flag 163 #define DTHE_AES_ICIS_CIN 0x00000001 // Clear “context input done�? flag 164 //****************************************************************************** 165 // 166 // The following are defines for the bit fields in the 167 // DTHE_O_DES_IMST register. 168 // 169 //****************************************************************************** 170 #define DTHE_DES_IMST_DOUT 0x00000008 // Data out: this interrupt is 171 // raised when DMA finishes writing 172 // last word of the process result 173 #define DTHE_DES_IMST_DIN 0x00000004 // Data in: this interrupt is 174 // raised when DMA writes last word 175 // of input data to internal FIFO of 176 // the engine 177 #define DTHE_DES_IMST_CIN 0x00000001 // context in: this interrupt is 178 // raised when DMA complets Context 179 // write to internal register 180 //****************************************************************************** 181 // 182 // The following are defines for the bit fields in the 183 // DTHE_O_DES_IRIS register. 184 // 185 //****************************************************************************** 186 #define DTHE_DES_IRIS_DOUT 0x00000008 // Output Data movement is done 187 #define DTHE_DES_IRIS_DIN 0x00000004 // input Data movement is done 188 #define DTHE_DES_IRIS_CIN 0x00000001 // context input is done 189 //****************************************************************************** 190 // 191 // The following are defines for the bit fields in the 192 // DTHE_O_DES_IMIS register. 193 // 194 //****************************************************************************** 195 #define DTHE_DES_IMIS_DOUT 0x00000008 // Output Data movement is done 196 #define DTHE_DES_IMIS_DIN 0x00000004 // input Data movement is done 197 #define DTHE_DES_IMIS_CIN 0x00000001 // context input is done 198 //****************************************************************************** 199 // 200 // The following are defines for the bit fields in the 201 // DTHE_O_DES_ICIS register. 202 // 203 //****************************************************************************** 204 #define DTHE_DES_ICIS_DOUT 0x00000008 // Clear “output Data movement 205 // done�? flag 206 #define DTHE_DES_ICIS_DIN 0x00000004 // Clear “input Data movement done�? 207 // flag 208 #define DTHE_DES_ICIS_CIN 0x00000001 // Clear "context input done�? flag 209 //****************************************************************************** 210 // 211 // The following are defines for the bit fields in the 212 // DTHE_O_EIP_CGCFG register. 213 // 214 //****************************************************************************** 215 #define DTHE_EIP_CGCFG_EIP29_CFG \ 216 0x00000010 // Clock gating protocol setting 217 // for EIP29T. 0 – Follow direct 218 // protocol 1 – Follow idle_req/ack 219 // protocol. 220 221 #define DTHE_EIP_CGCFG_EIP75_CFG \ 222 0x00000008 // Clock gating protocol setting 223 // for EIP75T. 0 – Follow direct 224 // protocol 1 – Follow idle_req/ack 225 // protocol. 226 227 #define DTHE_EIP_CGCFG_EIP16_CFG \ 228 0x00000004 // Clock gating protocol setting 229 // for DES. 0 – Follow direct 230 // protocol 1 – Follow idle_req/ack 231 // protocol. 232 233 #define DTHE_EIP_CGCFG_EIP36_CFG \ 234 0x00000002 // Clock gating protocol setting 235 // for AES. 0 – Follow direct 236 // protocol 1 – Follow idle_req/ack 237 // protocol. 238 239 #define DTHE_EIP_CGCFG_EIP57_CFG \ 240 0x00000001 // Clock gating protocol setting 241 // for SHAMD5. 0 – Follow direct 242 // protocol 1 – Follow idle_req/ack 243 // protocol. 244 245 //****************************************************************************** 246 // 247 // The following are defines for the bit fields in the 248 // DTHE_O_EIP_CGREQ register. 249 // 250 //****************************************************************************** 251 #define DTHE_EIP_CGREQ_Key_M 0xF0000000 // When “0x5�? write “1�? to lower 252 // bits [4:0] will set the bit. 253 // Write “0�? will be ignored When 254 // “0x2�? write “1�? to lower bit 255 // [4:0] will clear the bit. Write 256 // “0�? will be ignored for other key 257 // value, regular read write 258 // operation 259 #define DTHE_EIP_CGREQ_Key_S 28 260 #define DTHE_EIP_CGREQ_EIP29_REQ \ 261 0x00000010 // 0 – request clock gating 1 – 262 // request to un-gate the clock. 263 264 #define DTHE_EIP_CGREQ_EIP75_REQ \ 265 0x00000008 // 0 – request clock gating 1 – 266 // request to un-gate the clock. 267 268 #define DTHE_EIP_CGREQ_EIP16_REQ \ 269 0x00000004 // 0 – request clock gating 1 – 270 // request to un-gate the clock. 271 272 #define DTHE_EIP_CGREQ_EIP36_REQ \ 273 0x00000002 // 0 – request clock gating 1 – 274 // request to un-gate the clock. 275 276 #define DTHE_EIP_CGREQ_EIP57_REQ \ 277 0x00000001 // 0 – request clock gating 1 – 278 // request to un-gate the clock. 279 280 //****************************************************************************** 281 // 282 // The following are defines for the bit fields in the DTHE_O_CRC_CTRL register. 283 // 284 //****************************************************************************** 285 #define DTHE_CRC_CTRL_INIT_M 0x00006000 // Initialize the CRC 00 – use SEED 286 // register context as starting 287 // value 10 – all “zero�? 11 – all 288 // “one�? This is self clearing. With 289 // first write to data register this 290 // value clears to zero and remain 291 // zero for rest of the operation 292 // unless written again 293 #define DTHE_CRC_CTRL_INIT_S 13 294 #define DTHE_CRC_CTRL_SIZE 0x00001000 // Input data size 0 – 32 bit 1 – 8 295 // bit 296 #define DTHE_CRC_CTRL_OINV 0x00000200 // Inverse the bits of result 297 // before storing to CRC_RSLT_PP0 298 #define DTHE_CRC_CTRL_OBR 0x00000100 // Bit reverse the output result 299 // byte before storing to 300 // CRC_RSLT_PP0. applicable for all 301 // bytes in word 302 #define DTHE_CRC_CTRL_IBR 0x00000080 // Bit reverse the input byte. For 303 // all bytes in word 304 #define DTHE_CRC_CTRL_ENDIAN_M \ 305 0x00000030 // Endian control [0] – swap byte 306 // in half-word [1] – swap half word 307 308 #define DTHE_CRC_CTRL_ENDIAN_S 4 309 #define DTHE_CRC_CTRL_TYPE_M 0x0000000F // Type of operation 0000 – 310 // polynomial 0x8005 0001 – 311 // polynomial 0x1021 0010 – 312 // polynomial 0x4C11DB7 0011 – 313 // polynomial 0x1EDC6F41 1000 – TCP 314 // checksum TYPE in DTHE_S_CRC_CTRL 315 // & DTHE_S_CRC_CTRL should be 316 // exclusive 317 #define DTHE_CRC_CTRL_TYPE_S 0 318 //****************************************************************************** 319 // 320 // The following are defines for the bit fields in the DTHE_O_CRC_SEED register. 321 // 322 //****************************************************************************** 323 #define DTHE_CRC_SEED_SEED_M 0xFFFFFFFF // Starting seed of CRC and 324 // checksum operation. Please see 325 // CTRL register for more detail. 326 // This resister also holds the 327 // latest result of CRC or checksum 328 // operation 329 #define DTHE_CRC_SEED_SEED_S 0 330 //****************************************************************************** 331 // 332 // The following are defines for the bit fields in the DTHE_O_CRC_DIN register. 333 // 334 //****************************************************************************** 335 #define DTHE_CRC_DIN_DATA_IN_M \ 336 0xFFFFFFFF // Input data for CRC or checksum 337 // operation 338 339 #define DTHE_CRC_DIN_DATA_IN_S 0 340 //****************************************************************************** 341 // 342 // The following are defines for the bit fields in the 343 // DTHE_O_CRC_RSLT_PP register. 344 // 345 //****************************************************************************** 346 #define DTHE_CRC_RSLT_PP_RSLT_PP_M \ 347 0xFFFFFFFF // Input data for CRC or checksum 348 // operation 349 350 #define DTHE_CRC_RSLT_PP_RSLT_PP_S 0 351 //****************************************************************************** 352 // 353 // The following are defines for the bit fields in the 354 // DTHE_O_RAND_KEY0 register. 355 // 356 //****************************************************************************** 357 #define DTHE_RAND_KEY0_KEY_M 0xFFFFFFFF // Device Specific Randon key 358 // [31:0] 359 #define DTHE_RAND_KEY0_KEY_S 0 360 //****************************************************************************** 361 // 362 // The following are defines for the bit fields in the 363 // DTHE_O_RAND_KEY1 register. 364 // 365 //****************************************************************************** 366 #define DTHE_RAND_KEY1_KEY_M 0xFFFFFFFF // Device Specific Randon key 367 // [63:32] 368 #define DTHE_RAND_KEY1_KEY_S 0 369 //****************************************************************************** 370 // 371 // The following are defines for the bit fields in the 372 // DTHE_O_RAND_KEY2 register. 373 // 374 //****************************************************************************** 375 #define DTHE_RAND_KEY2_KEY_M 0xFFFFFFFF // Device Specific Randon key 376 // [95:34] 377 #define DTHE_RAND_KEY2_KEY_S 0 378 //****************************************************************************** 379 // 380 // The following are defines for the bit fields in the 381 // DTHE_O_RAND_KEY3 register. 382 // 383 //****************************************************************************** 384 #define DTHE_RAND_KEY3_KEY_M 0xFFFFFFFF // Device Specific Randon key 385 // [127:96] 386 #define DTHE_RAND_KEY3_KEY_S 0 387 388 389 390 #endif // __HW_DTHE_H__ 391
