1 /* 2 * Copyright (c) 2019 Intel Corporation 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #ifndef ZEPHYR_SOC_INTEL_ADSP_COMMON_SOC_H_ 7 #define ZEPHYR_SOC_INTEL_ADSP_COMMON_SOC_H_ 8 9 #include <string.h> 10 #include <errno.h> 11 #include <zephyr/linker/sections.h> 12 13 #include <adsp_interrupt.h> 14 15 /* DSP Wall Clock Timers (0 and 1) */ 16 #define DSP_WCT_IRQ(x) \ 17 SOC_AGGREGATE_IRQ((22 + x), CAVS_L2_AGG_INT_LEVEL2) 18 19 #define DSP_WCT_CS_TA(x) BIT(x) 20 #define DSP_WCT_CS_TT(x) BIT(4 + x) 21 22 23 extern void z_soc_mp_asm_entry(void); 24 extern void soc_mp_startup(uint32_t cpu); 25 extern void soc_start_core(int cpu_num); 26 27 extern bool soc_cpus_active[CONFIG_MP_MAX_NUM_CPUS]; 28 29 /** 30 * @brief Halts and offlines a running CPU 31 * 32 * Enables power gating on the specified CPU, which cannot be the 33 * current CPU or CPU 0. The CPU must be idle; no application threads 34 * may be runnable on it when this function is called (or at least the 35 * CPU must be guaranteed to reach idle in finite time without 36 * deadlock). Actual CPU shutdown can only happen in the context of 37 * the idle thread, and synchronization is an application 38 * responsibility. This function will hang if the other CPU fails to 39 * reach idle. 40 * 41 * @note On older cAVS hardware, core power is controlled by the host. 42 * This function must still be called for OS bookkeeping, but it is 43 * insufficient without application coordination (and careful 44 * synchronization!) with the host x86 environment. 45 * 46 * @param id CPU to halt, not current cpu or cpu 0 47 * @return 0 on success, -EINVAL on error 48 */ 49 int soc_adsp_halt_cpu(int id); 50 51 52 z_idelay(int n)53static ALWAYS_INLINE void z_idelay(int n) 54 { 55 while (n--) { 56 __asm__ volatile("nop"); 57 } 58 } 59 60 #endif /* ZEPHYR_SOC_INTEL_ADSP_COMMON_SOC_H_ */ 61
