1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2024 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_DSPI.h 10 * @version 2.3 11 * @date 2024-05-03 12 * @brief Peripheral Access Layer for S32Z2_DSPI 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_DSPI_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_DSPI_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- DSPI Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup DSPI_Peripheral_Access_Layer DSPI Peripheral Access Layer 68 * @{ 69 */ 70 71 /** DSPI - Size of Registers Arrays */ 72 #define DSPI_MODE_CTAR_CTAR_COUNT 6u 73 #define DSPI_TXFR_COUNT 16u 74 #define DSPI_RXFR_COUNT 16u 75 #define DSPI_CTARE_COUNT 6u 76 77 /** DSPI - Register Layout Typedef */ 78 typedef struct { 79 __IO uint32_t MCR; /**< Module Configuration Register, offset: 0x0 */ 80 uint8_t RESERVED_0[4]; 81 __IO uint32_t TCR; /**< Transfer Count Register, offset: 0x8 */ 82 union { /* offset: 0xC */ 83 __IO uint32_t CTAR[DSPI_MODE_CTAR_CTAR_COUNT]; /**< Clock and Transfer Attributes Register (In Master Mode), array offset: 0xC, array step: 0x4 */ 84 } MODE; 85 uint8_t RESERVED_1[8]; 86 __IO uint32_t SR; /**< Status Register, offset: 0x2C */ 87 __IO uint32_t RSER; /**< DMA/Interrupt Request Select and Enable Register, offset: 0x30 */ 88 union { /* offset: 0x34 */ 89 struct DSPI_PUSHR_FIFO { /* offset: 0x34 */ 90 __IO uint16_t TX; /**< DSPI_TX register, offset: 0x34 */ 91 __IO uint16_t CMD; /**< DSPI_CMD register, offset: 0x36 */ 92 } FIFO; 93 __IO uint32_t PUSHR; /**< PUSH TX FIFO Register In Master Mode, offset: 0x34 */ 94 } PUSHR; 95 __I uint32_t POPR; /**< POP RX FIFO Register, offset: 0x38 */ 96 __I uint32_t TXFR[DSPI_TXFR_COUNT]; /**< Transmit FIFO Registers, array offset: 0x3C, array step: 0x4 */ 97 __I uint32_t RXFR[DSPI_RXFR_COUNT]; /**< Receive FIFO Registers, array offset: 0x7C, array step: 0x4 */ 98 __IO uint32_t DSICR0; /**< DSI Configuration Register 0, offset: 0xBC */ 99 __I uint32_t SDR0; /**< DSI Serialization Data Register 0, offset: 0xC0 */ 100 __IO uint32_t ASDR0; /**< DSI Alternate Serialization Data Register 0, offset: 0xC4 */ 101 __I uint32_t COMPR0; /**< DSI Transmit Comparison Register 0, offset: 0xC8 */ 102 __I uint32_t DDR0; /**< DSI Deserialization Data Register 0, offset: 0xCC */ 103 __IO uint32_t DSICR1; /**< DSI Configuration Register 1, offset: 0xD0 */ 104 __IO uint32_t SSR0; /**< DSI Serialization Source Select Register 0, offset: 0xD4 */ 105 uint8_t RESERVED_2[16]; 106 __IO uint32_t DIMR0; /**< DSI Deserialized Data Interrupt Mask Register 0, offset: 0xE8 */ 107 __IO uint32_t DPIR0; /**< DSI Deserialized Data Polarity Interrupt Register 0, offset: 0xEC */ 108 __I uint32_t SDR1; /**< DSI Serialization Data Register 1, offset: 0xF0 */ 109 __IO uint32_t ASDR1; /**< DSI Alternate Serialization Data Register 1, offset: 0xF4 */ 110 __I uint32_t COMPR1; /**< DSI Transmit Comparison Register 1, offset: 0xF8 */ 111 __I uint32_t DDR1; /**< DSI Deserialization Data Register 1, offset: 0xFC */ 112 __IO uint32_t SSR1; /**< DSI Serialization Source Select Register 1, offset: 0x100 */ 113 uint8_t RESERVED_3[16]; 114 __IO uint32_t DIMR1; /**< DSI Deserialized Data Interrupt Mask Register 1, offset: 0x114 */ 115 __IO uint32_t DPIR1; /**< DSI Deserialized Data Polarity Interrupt Register 1, offset: 0x118 */ 116 __IO uint32_t CTARE[DSPI_CTARE_COUNT]; /**< Clock and Transfer Attributes Register Extended, array offset: 0x11C, array step: 0x4 */ 117 uint8_t RESERVED_4[8]; 118 __I uint32_t SREX; /**< Status Register Extended, offset: 0x13C */ 119 uint8_t RESERVED_5[16]; 120 __IO uint32_t TSL; /**< Time Slot Length Register, offset: 0x150 */ 121 __IO uint32_t TS_CONF; /**< Time Slot Configuration Register, offset: 0x154 */ 122 } DSPI_Type, *DSPI_MemMapPtr; 123 124 /** Number of instances of the DSPI module. */ 125 #define DSPI_INSTANCE_COUNT (1u) 126 127 /* DSPI - Peripheral instance base addresses */ 128 /** Peripheral MSC_0_DSPI base address */ 129 #define IP_MSC_0_DSPI_BASE (0x40340000u) 130 /** Peripheral MSC_0_DSPI base pointer */ 131 #define IP_MSC_0_DSPI ((DSPI_Type *)IP_MSC_0_DSPI_BASE) 132 /** Array initializer of DSPI peripheral base addresses */ 133 #define IP_DSPI_BASE_ADDRS { IP_MSC_0_DSPI_BASE } 134 /** Array initializer of DSPI peripheral base pointers */ 135 #define IP_DSPI_BASE_PTRS { IP_MSC_0_DSPI } 136 137 /* ---------------------------------------------------------------------------- 138 -- DSPI Register Masks 139 ---------------------------------------------------------------------------- */ 140 141 /*! 142 * @addtogroup DSPI_Register_Masks DSPI Register Masks 143 * @{ 144 */ 145 146 /*! @name MCR - Module Configuration Register */ 147 /*! @{ */ 148 149 #define DSPI_MCR_HALT_MASK (0x1U) 150 #define DSPI_MCR_HALT_SHIFT (0U) 151 #define DSPI_MCR_HALT_WIDTH (1U) 152 #define DSPI_MCR_HALT(x) (((uint32_t)(((uint32_t)(x)) << DSPI_MCR_HALT_SHIFT)) & DSPI_MCR_HALT_MASK) 153 154 #define DSPI_MCR_PES_MASK (0x2U) 155 #define DSPI_MCR_PES_SHIFT (1U) 156 #define DSPI_MCR_PES_WIDTH (1U) 157 #define DSPI_MCR_PES(x) (((uint32_t)(((uint32_t)(x)) << DSPI_MCR_PES_SHIFT)) & DSPI_MCR_PES_MASK) 158 159 #define DSPI_MCR_FCPCS_MASK (0x4U) 160 #define DSPI_MCR_FCPCS_SHIFT (2U) 161 #define DSPI_MCR_FCPCS_WIDTH (1U) 162 #define DSPI_MCR_FCPCS(x) (((uint32_t)(((uint32_t)(x)) << DSPI_MCR_FCPCS_SHIFT)) & DSPI_MCR_FCPCS_MASK) 163 164 #define DSPI_MCR_XSPI_MASK (0x8U) 165 #define DSPI_MCR_XSPI_SHIFT (3U) 166 #define DSPI_MCR_XSPI_WIDTH (1U) 167 #define DSPI_MCR_XSPI(x) (((uint32_t)(((uint32_t)(x)) << DSPI_MCR_XSPI_SHIFT)) & DSPI_MCR_XSPI_MASK) 168 169 #define DSPI_MCR_SMPL_PT_MASK (0x300U) 170 #define DSPI_MCR_SMPL_PT_SHIFT (8U) 171 #define DSPI_MCR_SMPL_PT_WIDTH (2U) 172 #define DSPI_MCR_SMPL_PT(x) (((uint32_t)(((uint32_t)(x)) << DSPI_MCR_SMPL_PT_SHIFT)) & DSPI_MCR_SMPL_PT_MASK) 173 174 #define DSPI_MCR_CLR_RXF_MASK (0x400U) 175 #define DSPI_MCR_CLR_RXF_SHIFT (10U) 176 #define DSPI_MCR_CLR_RXF_WIDTH (1U) 177 #define DSPI_MCR_CLR_RXF(x) (((uint32_t)(((uint32_t)(x)) << DSPI_MCR_CLR_RXF_SHIFT)) & DSPI_MCR_CLR_RXF_MASK) 178 179 #define DSPI_MCR_CLR_TXF_MASK (0x800U) 180 #define DSPI_MCR_CLR_TXF_SHIFT (11U) 181 #define DSPI_MCR_CLR_TXF_WIDTH (1U) 182 #define DSPI_MCR_CLR_TXF(x) (((uint32_t)(((uint32_t)(x)) << DSPI_MCR_CLR_TXF_SHIFT)) & DSPI_MCR_CLR_TXF_MASK) 183 184 #define DSPI_MCR_DIS_RXF_MASK (0x1000U) 185 #define DSPI_MCR_DIS_RXF_SHIFT (12U) 186 #define DSPI_MCR_DIS_RXF_WIDTH (1U) 187 #define DSPI_MCR_DIS_RXF(x) (((uint32_t)(((uint32_t)(x)) << DSPI_MCR_DIS_RXF_SHIFT)) & DSPI_MCR_DIS_RXF_MASK) 188 189 #define DSPI_MCR_DIS_TXF_MASK (0x2000U) 190 #define DSPI_MCR_DIS_TXF_SHIFT (13U) 191 #define DSPI_MCR_DIS_TXF_WIDTH (1U) 192 #define DSPI_MCR_DIS_TXF(x) (((uint32_t)(((uint32_t)(x)) << DSPI_MCR_DIS_TXF_SHIFT)) & DSPI_MCR_DIS_TXF_MASK) 193 194 #define DSPI_MCR_MDIS_MASK (0x4000U) 195 #define DSPI_MCR_MDIS_SHIFT (14U) 196 #define DSPI_MCR_MDIS_WIDTH (1U) 197 #define DSPI_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << DSPI_MCR_MDIS_SHIFT)) & DSPI_MCR_MDIS_MASK) 198 199 #define DSPI_MCR_PCSIS_MASK (0x70000U) 200 #define DSPI_MCR_PCSIS_SHIFT (16U) 201 #define DSPI_MCR_PCSIS_WIDTH (3U) 202 #define DSPI_MCR_PCSIS(x) (((uint32_t)(((uint32_t)(x)) << DSPI_MCR_PCSIS_SHIFT)) & DSPI_MCR_PCSIS_MASK) 203 204 #define DSPI_MCR_ROOE_MASK (0x1000000U) 205 #define DSPI_MCR_ROOE_SHIFT (24U) 206 #define DSPI_MCR_ROOE_WIDTH (1U) 207 #define DSPI_MCR_ROOE(x) (((uint32_t)(((uint32_t)(x)) << DSPI_MCR_ROOE_SHIFT)) & DSPI_MCR_ROOE_MASK) 208 209 #define DSPI_MCR_MTFE_MASK (0x4000000U) 210 #define DSPI_MCR_MTFE_SHIFT (26U) 211 #define DSPI_MCR_MTFE_WIDTH (1U) 212 #define DSPI_MCR_MTFE(x) (((uint32_t)(((uint32_t)(x)) << DSPI_MCR_MTFE_SHIFT)) & DSPI_MCR_MTFE_MASK) 213 214 #define DSPI_MCR_FRZ_MASK (0x8000000U) 215 #define DSPI_MCR_FRZ_SHIFT (27U) 216 #define DSPI_MCR_FRZ_WIDTH (1U) 217 #define DSPI_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << DSPI_MCR_FRZ_SHIFT)) & DSPI_MCR_FRZ_MASK) 218 219 #define DSPI_MCR_DCONF_MASK (0x30000000U) 220 #define DSPI_MCR_DCONF_SHIFT (28U) 221 #define DSPI_MCR_DCONF_WIDTH (2U) 222 #define DSPI_MCR_DCONF(x) (((uint32_t)(((uint32_t)(x)) << DSPI_MCR_DCONF_SHIFT)) & DSPI_MCR_DCONF_MASK) 223 224 #define DSPI_MCR_CONT_SCKE_MASK (0x40000000U) 225 #define DSPI_MCR_CONT_SCKE_SHIFT (30U) 226 #define DSPI_MCR_CONT_SCKE_WIDTH (1U) 227 #define DSPI_MCR_CONT_SCKE(x) (((uint32_t)(((uint32_t)(x)) << DSPI_MCR_CONT_SCKE_SHIFT)) & DSPI_MCR_CONT_SCKE_MASK) 228 229 #define DSPI_MCR_MSTR_MASK (0x80000000U) 230 #define DSPI_MCR_MSTR_SHIFT (31U) 231 #define DSPI_MCR_MSTR_WIDTH (1U) 232 #define DSPI_MCR_MSTR(x) (((uint32_t)(((uint32_t)(x)) << DSPI_MCR_MSTR_SHIFT)) & DSPI_MCR_MSTR_MASK) 233 /*! @} */ 234 235 /*! @name TCR - Transfer Count Register */ 236 /*! @{ */ 237 238 #define DSPI_TCR_SPI_TCNT_MASK (0xFFFF0000U) 239 #define DSPI_TCR_SPI_TCNT_SHIFT (16U) 240 #define DSPI_TCR_SPI_TCNT_WIDTH (16U) 241 #define DSPI_TCR_SPI_TCNT(x) (((uint32_t)(((uint32_t)(x)) << DSPI_TCR_SPI_TCNT_SHIFT)) & DSPI_TCR_SPI_TCNT_MASK) 242 /*! @} */ 243 244 /*! @name CTAR - Clock and Transfer Attributes Register (In Master Mode) */ 245 /*! @{ */ 246 247 #define DSPI_CTAR_BR_MASK (0xFU) 248 #define DSPI_CTAR_BR_SHIFT (0U) 249 #define DSPI_CTAR_BR_WIDTH (4U) 250 #define DSPI_CTAR_BR(x) (((uint32_t)(((uint32_t)(x)) << DSPI_CTAR_BR_SHIFT)) & DSPI_CTAR_BR_MASK) 251 252 #define DSPI_CTAR_DT_MASK (0xF0U) 253 #define DSPI_CTAR_DT_SHIFT (4U) 254 #define DSPI_CTAR_DT_WIDTH (4U) 255 #define DSPI_CTAR_DT(x) (((uint32_t)(((uint32_t)(x)) << DSPI_CTAR_DT_SHIFT)) & DSPI_CTAR_DT_MASK) 256 257 #define DSPI_CTAR_ASC_MASK (0xF00U) 258 #define DSPI_CTAR_ASC_SHIFT (8U) 259 #define DSPI_CTAR_ASC_WIDTH (4U) 260 #define DSPI_CTAR_ASC(x) (((uint32_t)(((uint32_t)(x)) << DSPI_CTAR_ASC_SHIFT)) & DSPI_CTAR_ASC_MASK) 261 262 #define DSPI_CTAR_CSSCK_MASK (0xF000U) 263 #define DSPI_CTAR_CSSCK_SHIFT (12U) 264 #define DSPI_CTAR_CSSCK_WIDTH (4U) 265 #define DSPI_CTAR_CSSCK(x) (((uint32_t)(((uint32_t)(x)) << DSPI_CTAR_CSSCK_SHIFT)) & DSPI_CTAR_CSSCK_MASK) 266 267 #define DSPI_CTAR_PBR_MASK (0x30000U) 268 #define DSPI_CTAR_PBR_SHIFT (16U) 269 #define DSPI_CTAR_PBR_WIDTH (2U) 270 #define DSPI_CTAR_PBR(x) (((uint32_t)(((uint32_t)(x)) << DSPI_CTAR_PBR_SHIFT)) & DSPI_CTAR_PBR_MASK) 271 272 #define DSPI_CTAR_PDT_MASK (0xC0000U) 273 #define DSPI_CTAR_PDT_SHIFT (18U) 274 #define DSPI_CTAR_PDT_WIDTH (2U) 275 #define DSPI_CTAR_PDT(x) (((uint32_t)(((uint32_t)(x)) << DSPI_CTAR_PDT_SHIFT)) & DSPI_CTAR_PDT_MASK) 276 277 #define DSPI_CTAR_PASC_MASK (0x300000U) 278 #define DSPI_CTAR_PASC_SHIFT (20U) 279 #define DSPI_CTAR_PASC_WIDTH (2U) 280 #define DSPI_CTAR_PASC(x) (((uint32_t)(((uint32_t)(x)) << DSPI_CTAR_PASC_SHIFT)) & DSPI_CTAR_PASC_MASK) 281 282 #define DSPI_CTAR_PCSSCK_MASK (0xC00000U) 283 #define DSPI_CTAR_PCSSCK_SHIFT (22U) 284 #define DSPI_CTAR_PCSSCK_WIDTH (2U) 285 #define DSPI_CTAR_PCSSCK(x) (((uint32_t)(((uint32_t)(x)) << DSPI_CTAR_PCSSCK_SHIFT)) & DSPI_CTAR_PCSSCK_MASK) 286 287 #define DSPI_CTAR_LSBFE_MASK (0x1000000U) 288 #define DSPI_CTAR_LSBFE_SHIFT (24U) 289 #define DSPI_CTAR_LSBFE_WIDTH (1U) 290 #define DSPI_CTAR_LSBFE(x) (((uint32_t)(((uint32_t)(x)) << DSPI_CTAR_LSBFE_SHIFT)) & DSPI_CTAR_LSBFE_MASK) 291 292 #define DSPI_CTAR_CPHA_MASK (0x2000000U) 293 #define DSPI_CTAR_CPHA_SHIFT (25U) 294 #define DSPI_CTAR_CPHA_WIDTH (1U) 295 #define DSPI_CTAR_CPHA(x) (((uint32_t)(((uint32_t)(x)) << DSPI_CTAR_CPHA_SHIFT)) & DSPI_CTAR_CPHA_MASK) 296 297 #define DSPI_CTAR_CPOL_MASK (0x4000000U) 298 #define DSPI_CTAR_CPOL_SHIFT (26U) 299 #define DSPI_CTAR_CPOL_WIDTH (1U) 300 #define DSPI_CTAR_CPOL(x) (((uint32_t)(((uint32_t)(x)) << DSPI_CTAR_CPOL_SHIFT)) & DSPI_CTAR_CPOL_MASK) 301 302 #define DSPI_CTAR_FMSZ_MASK (0x78000000U) 303 #define DSPI_CTAR_FMSZ_SHIFT (27U) 304 #define DSPI_CTAR_FMSZ_WIDTH (4U) 305 #define DSPI_CTAR_FMSZ(x) (((uint32_t)(((uint32_t)(x)) << DSPI_CTAR_FMSZ_SHIFT)) & DSPI_CTAR_FMSZ_MASK) 306 307 #define DSPI_CTAR_DBR_MASK (0x80000000U) 308 #define DSPI_CTAR_DBR_SHIFT (31U) 309 #define DSPI_CTAR_DBR_WIDTH (1U) 310 #define DSPI_CTAR_DBR(x) (((uint32_t)(((uint32_t)(x)) << DSPI_CTAR_DBR_SHIFT)) & DSPI_CTAR_DBR_MASK) 311 /*! @} */ 312 313 /*! @name SR - Status Register */ 314 /*! @{ */ 315 316 #define DSPI_SR_POPNXTPTR_MASK (0xFU) 317 #define DSPI_SR_POPNXTPTR_SHIFT (0U) 318 #define DSPI_SR_POPNXTPTR_WIDTH (4U) 319 #define DSPI_SR_POPNXTPTR(x) (((uint32_t)(((uint32_t)(x)) << DSPI_SR_POPNXTPTR_SHIFT)) & DSPI_SR_POPNXTPTR_MASK) 320 321 #define DSPI_SR_RXCTR_MASK (0xF0U) 322 #define DSPI_SR_RXCTR_SHIFT (4U) 323 #define DSPI_SR_RXCTR_WIDTH (4U) 324 #define DSPI_SR_RXCTR(x) (((uint32_t)(((uint32_t)(x)) << DSPI_SR_RXCTR_SHIFT)) & DSPI_SR_RXCTR_MASK) 325 326 #define DSPI_SR_TXNXTPTR_MASK (0xF00U) 327 #define DSPI_SR_TXNXTPTR_SHIFT (8U) 328 #define DSPI_SR_TXNXTPTR_WIDTH (4U) 329 #define DSPI_SR_TXNXTPTR(x) (((uint32_t)(((uint32_t)(x)) << DSPI_SR_TXNXTPTR_SHIFT)) & DSPI_SR_TXNXTPTR_MASK) 330 331 #define DSPI_SR_TXCTR_MASK (0xF000U) 332 #define DSPI_SR_TXCTR_SHIFT (12U) 333 #define DSPI_SR_TXCTR_WIDTH (4U) 334 #define DSPI_SR_TXCTR(x) (((uint32_t)(((uint32_t)(x)) << DSPI_SR_TXCTR_SHIFT)) & DSPI_SR_TXCTR_MASK) 335 336 #define DSPI_SR_CMDFFF_MASK (0x10000U) 337 #define DSPI_SR_CMDFFF_SHIFT (16U) 338 #define DSPI_SR_CMDFFF_WIDTH (1U) 339 #define DSPI_SR_CMDFFF(x) (((uint32_t)(((uint32_t)(x)) << DSPI_SR_CMDFFF_SHIFT)) & DSPI_SR_CMDFFF_MASK) 340 341 #define DSPI_SR_RFDF_MASK (0x20000U) 342 #define DSPI_SR_RFDF_SHIFT (17U) 343 #define DSPI_SR_RFDF_WIDTH (1U) 344 #define DSPI_SR_RFDF(x) (((uint32_t)(((uint32_t)(x)) << DSPI_SR_RFDF_SHIFT)) & DSPI_SR_RFDF_MASK) 345 346 #define DSPI_SR_TFIWF_MASK (0x40000U) 347 #define DSPI_SR_TFIWF_SHIFT (18U) 348 #define DSPI_SR_TFIWF_WIDTH (1U) 349 #define DSPI_SR_TFIWF(x) (((uint32_t)(((uint32_t)(x)) << DSPI_SR_TFIWF_SHIFT)) & DSPI_SR_TFIWF_MASK) 350 351 #define DSPI_SR_RFOF_MASK (0x80000U) 352 #define DSPI_SR_RFOF_SHIFT (19U) 353 #define DSPI_SR_RFOF_WIDTH (1U) 354 #define DSPI_SR_RFOF(x) (((uint32_t)(((uint32_t)(x)) << DSPI_SR_RFOF_SHIFT)) & DSPI_SR_RFOF_MASK) 355 356 #define DSPI_SR_DDIF_MASK (0x100000U) 357 #define DSPI_SR_DDIF_SHIFT (20U) 358 #define DSPI_SR_DDIF_WIDTH (1U) 359 #define DSPI_SR_DDIF(x) (((uint32_t)(((uint32_t)(x)) << DSPI_SR_DDIF_SHIFT)) & DSPI_SR_DDIF_MASK) 360 361 #define DSPI_SR_SPEF_MASK (0x200000U) 362 #define DSPI_SR_SPEF_SHIFT (21U) 363 #define DSPI_SR_SPEF_WIDTH (1U) 364 #define DSPI_SR_SPEF(x) (((uint32_t)(((uint32_t)(x)) << DSPI_SR_SPEF_SHIFT)) & DSPI_SR_SPEF_MASK) 365 366 #define DSPI_SR_DPEF_MASK (0x400000U) 367 #define DSPI_SR_DPEF_SHIFT (22U) 368 #define DSPI_SR_DPEF_WIDTH (1U) 369 #define DSPI_SR_DPEF(x) (((uint32_t)(((uint32_t)(x)) << DSPI_SR_DPEF_SHIFT)) & DSPI_SR_DPEF_MASK) 370 371 #define DSPI_SR_CMDTCF_MASK (0x800000U) 372 #define DSPI_SR_CMDTCF_SHIFT (23U) 373 #define DSPI_SR_CMDTCF_WIDTH (1U) 374 #define DSPI_SR_CMDTCF(x) (((uint32_t)(((uint32_t)(x)) << DSPI_SR_CMDTCF_SHIFT)) & DSPI_SR_CMDTCF_MASK) 375 376 #define DSPI_SR_BSYF_MASK (0x1000000U) 377 #define DSPI_SR_BSYF_SHIFT (24U) 378 #define DSPI_SR_BSYF_WIDTH (1U) 379 #define DSPI_SR_BSYF(x) (((uint32_t)(((uint32_t)(x)) << DSPI_SR_BSYF_SHIFT)) & DSPI_SR_BSYF_MASK) 380 381 #define DSPI_SR_TFFF_MASK (0x2000000U) 382 #define DSPI_SR_TFFF_SHIFT (25U) 383 #define DSPI_SR_TFFF_WIDTH (1U) 384 #define DSPI_SR_TFFF(x) (((uint32_t)(((uint32_t)(x)) << DSPI_SR_TFFF_SHIFT)) & DSPI_SR_TFFF_MASK) 385 386 #define DSPI_SR_EOQF_MASK (0x10000000U) 387 #define DSPI_SR_EOQF_SHIFT (28U) 388 #define DSPI_SR_EOQF_WIDTH (1U) 389 #define DSPI_SR_EOQF(x) (((uint32_t)(((uint32_t)(x)) << DSPI_SR_EOQF_SHIFT)) & DSPI_SR_EOQF_MASK) 390 391 #define DSPI_SR_SPITCF_MASK (0x20000000U) 392 #define DSPI_SR_SPITCF_SHIFT (29U) 393 #define DSPI_SR_SPITCF_WIDTH (1U) 394 #define DSPI_SR_SPITCF(x) (((uint32_t)(((uint32_t)(x)) << DSPI_SR_SPITCF_SHIFT)) & DSPI_SR_SPITCF_MASK) 395 396 #define DSPI_SR_TXRXS_MASK (0x40000000U) 397 #define DSPI_SR_TXRXS_SHIFT (30U) 398 #define DSPI_SR_TXRXS_WIDTH (1U) 399 #define DSPI_SR_TXRXS(x) (((uint32_t)(((uint32_t)(x)) << DSPI_SR_TXRXS_SHIFT)) & DSPI_SR_TXRXS_MASK) 400 401 #define DSPI_SR_TCF_MASK (0x80000000U) 402 #define DSPI_SR_TCF_SHIFT (31U) 403 #define DSPI_SR_TCF_WIDTH (1U) 404 #define DSPI_SR_TCF(x) (((uint32_t)(((uint32_t)(x)) << DSPI_SR_TCF_SHIFT)) & DSPI_SR_TCF_MASK) 405 /*! @} */ 406 407 /*! @name RSER - DMA/Interrupt Request Select and Enable Register */ 408 /*! @{ */ 409 410 #define DSPI_RSER_DDIF_DIRS_MASK (0x4000U) 411 #define DSPI_RSER_DDIF_DIRS_SHIFT (14U) 412 #define DSPI_RSER_DDIF_DIRS_WIDTH (1U) 413 #define DSPI_RSER_DDIF_DIRS(x) (((uint32_t)(((uint32_t)(x)) << DSPI_RSER_DDIF_DIRS_SHIFT)) & DSPI_RSER_DDIF_DIRS_MASK) 414 415 #define DSPI_RSER_CMDFFF_DIRS_MASK (0x8000U) 416 #define DSPI_RSER_CMDFFF_DIRS_SHIFT (15U) 417 #define DSPI_RSER_CMDFFF_DIRS_WIDTH (1U) 418 #define DSPI_RSER_CMDFFF_DIRS(x) (((uint32_t)(((uint32_t)(x)) << DSPI_RSER_CMDFFF_DIRS_SHIFT)) & DSPI_RSER_CMDFFF_DIRS_MASK) 419 420 #define DSPI_RSER_RFDF_DIRS_MASK (0x10000U) 421 #define DSPI_RSER_RFDF_DIRS_SHIFT (16U) 422 #define DSPI_RSER_RFDF_DIRS_WIDTH (1U) 423 #define DSPI_RSER_RFDF_DIRS(x) (((uint32_t)(((uint32_t)(x)) << DSPI_RSER_RFDF_DIRS_SHIFT)) & DSPI_RSER_RFDF_DIRS_MASK) 424 425 #define DSPI_RSER_RFDF_RE_MASK (0x20000U) 426 #define DSPI_RSER_RFDF_RE_SHIFT (17U) 427 #define DSPI_RSER_RFDF_RE_WIDTH (1U) 428 #define DSPI_RSER_RFDF_RE(x) (((uint32_t)(((uint32_t)(x)) << DSPI_RSER_RFDF_RE_SHIFT)) & DSPI_RSER_RFDF_RE_MASK) 429 430 #define DSPI_RSER_TFIWF_RE_MASK (0x40000U) 431 #define DSPI_RSER_TFIWF_RE_SHIFT (18U) 432 #define DSPI_RSER_TFIWF_RE_WIDTH (1U) 433 #define DSPI_RSER_TFIWF_RE(x) (((uint32_t)(((uint32_t)(x)) << DSPI_RSER_TFIWF_RE_SHIFT)) & DSPI_RSER_TFIWF_RE_MASK) 434 435 #define DSPI_RSER_RFOF_RE_MASK (0x80000U) 436 #define DSPI_RSER_RFOF_RE_SHIFT (19U) 437 #define DSPI_RSER_RFOF_RE_WIDTH (1U) 438 #define DSPI_RSER_RFOF_RE(x) (((uint32_t)(((uint32_t)(x)) << DSPI_RSER_RFOF_RE_SHIFT)) & DSPI_RSER_RFOF_RE_MASK) 439 440 #define DSPI_RSER_DDIF_RE_MASK (0x100000U) 441 #define DSPI_RSER_DDIF_RE_SHIFT (20U) 442 #define DSPI_RSER_DDIF_RE_WIDTH (1U) 443 #define DSPI_RSER_DDIF_RE(x) (((uint32_t)(((uint32_t)(x)) << DSPI_RSER_DDIF_RE_SHIFT)) & DSPI_RSER_DDIF_RE_MASK) 444 445 #define DSPI_RSER_SPEF_RE_MASK (0x200000U) 446 #define DSPI_RSER_SPEF_RE_SHIFT (21U) 447 #define DSPI_RSER_SPEF_RE_WIDTH (1U) 448 #define DSPI_RSER_SPEF_RE(x) (((uint32_t)(((uint32_t)(x)) << DSPI_RSER_SPEF_RE_SHIFT)) & DSPI_RSER_SPEF_RE_MASK) 449 450 #define DSPI_RSER_DPEF_RE_MASK (0x400000U) 451 #define DSPI_RSER_DPEF_RE_SHIFT (22U) 452 #define DSPI_RSER_DPEF_RE_WIDTH (1U) 453 #define DSPI_RSER_DPEF_RE(x) (((uint32_t)(((uint32_t)(x)) << DSPI_RSER_DPEF_RE_SHIFT)) & DSPI_RSER_DPEF_RE_MASK) 454 455 #define DSPI_RSER_CMDTCF_RE_MASK (0x800000U) 456 #define DSPI_RSER_CMDTCF_RE_SHIFT (23U) 457 #define DSPI_RSER_CMDTCF_RE_WIDTH (1U) 458 #define DSPI_RSER_CMDTCF_RE(x) (((uint32_t)(((uint32_t)(x)) << DSPI_RSER_CMDTCF_RE_SHIFT)) & DSPI_RSER_CMDTCF_RE_MASK) 459 460 #define DSPI_RSER_TFFF_DIRS_MASK (0x1000000U) 461 #define DSPI_RSER_TFFF_DIRS_SHIFT (24U) 462 #define DSPI_RSER_TFFF_DIRS_WIDTH (1U) 463 #define DSPI_RSER_TFFF_DIRS(x) (((uint32_t)(((uint32_t)(x)) << DSPI_RSER_TFFF_DIRS_SHIFT)) & DSPI_RSER_TFFF_DIRS_MASK) 464 465 #define DSPI_RSER_TFFF_RE_MASK (0x2000000U) 466 #define DSPI_RSER_TFFF_RE_SHIFT (25U) 467 #define DSPI_RSER_TFFF_RE_WIDTH (1U) 468 #define DSPI_RSER_TFFF_RE(x) (((uint32_t)(((uint32_t)(x)) << DSPI_RSER_TFFF_RE_SHIFT)) & DSPI_RSER_TFFF_RE_MASK) 469 470 #define DSPI_RSER_EOQF_RE_MASK (0x10000000U) 471 #define DSPI_RSER_EOQF_RE_SHIFT (28U) 472 #define DSPI_RSER_EOQF_RE_WIDTH (1U) 473 #define DSPI_RSER_EOQF_RE(x) (((uint32_t)(((uint32_t)(x)) << DSPI_RSER_EOQF_RE_SHIFT)) & DSPI_RSER_EOQF_RE_MASK) 474 475 #define DSPI_RSER_CMDFFF_RE_MASK (0x40000000U) 476 #define DSPI_RSER_CMDFFF_RE_SHIFT (30U) 477 #define DSPI_RSER_CMDFFF_RE_WIDTH (1U) 478 #define DSPI_RSER_CMDFFF_RE(x) (((uint32_t)(((uint32_t)(x)) << DSPI_RSER_CMDFFF_RE_SHIFT)) & DSPI_RSER_CMDFFF_RE_MASK) 479 480 #define DSPI_RSER_TCF_RE_MASK (0x80000000U) 481 #define DSPI_RSER_TCF_RE_SHIFT (31U) 482 #define DSPI_RSER_TCF_RE_WIDTH (1U) 483 #define DSPI_RSER_TCF_RE(x) (((uint32_t)(((uint32_t)(x)) << DSPI_RSER_TCF_RE_SHIFT)) & DSPI_RSER_TCF_RE_MASK) 484 /*! @} */ 485 486 /*! @name TX - DSPI_TX register */ 487 /*! @{ */ 488 489 #define DSPI_TX_TX_MASK (0xFFFFU) 490 #define DSPI_TX_TX_SHIFT (0U) 491 #define DSPI_TX_TX_WIDTH (16U) 492 #define DSPI_TX_TX(x) (((uint16_t)(((uint16_t)(x)) << DSPI_TX_TX_SHIFT)) & DSPI_TX_TX_MASK) 493 /*! @} */ 494 495 /*! @name CMD - DSPI_CMD register */ 496 /*! @{ */ 497 498 #define DSPI_CMD_CMD_MASK (0xFFFFU) 499 #define DSPI_CMD_CMD_SHIFT (0U) 500 #define DSPI_CMD_CMD_WIDTH (16U) 501 #define DSPI_CMD_CMD(x) (((uint16_t)(((uint16_t)(x)) << DSPI_CMD_CMD_SHIFT)) & DSPI_CMD_CMD_MASK) 502 /*! @} */ 503 504 /*! @name PUSHR - PUSH TX FIFO Register In Master Mode */ 505 /*! @{ */ 506 507 #define DSPI_PUSHR_TXDATA_MASK (0xFFFFU) 508 #define DSPI_PUSHR_TXDATA_SHIFT (0U) 509 #define DSPI_PUSHR_TXDATA_WIDTH (16U) 510 #define DSPI_PUSHR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << DSPI_PUSHR_TXDATA_SHIFT)) & DSPI_PUSHR_TXDATA_MASK) 511 512 #define DSPI_PUSHR_PCS_MASK (0x70000U) 513 #define DSPI_PUSHR_PCS_SHIFT (16U) 514 #define DSPI_PUSHR_PCS_WIDTH (3U) 515 #define DSPI_PUSHR_PCS(x) (((uint32_t)(((uint32_t)(x)) << DSPI_PUSHR_PCS_SHIFT)) & DSPI_PUSHR_PCS_MASK) 516 517 #define DSPI_PUSHR_PP_MCSC_MASK (0x1000000U) 518 #define DSPI_PUSHR_PP_MCSC_SHIFT (24U) 519 #define DSPI_PUSHR_PP_MCSC_WIDTH (1U) 520 #define DSPI_PUSHR_PP_MCSC(x) (((uint32_t)(((uint32_t)(x)) << DSPI_PUSHR_PP_MCSC_SHIFT)) & DSPI_PUSHR_PP_MCSC_MASK) 521 522 #define DSPI_PUSHR_PE_MASC_MASK (0x2000000U) 523 #define DSPI_PUSHR_PE_MASC_SHIFT (25U) 524 #define DSPI_PUSHR_PE_MASC_WIDTH (1U) 525 #define DSPI_PUSHR_PE_MASC(x) (((uint32_t)(((uint32_t)(x)) << DSPI_PUSHR_PE_MASC_SHIFT)) & DSPI_PUSHR_PE_MASC_MASK) 526 527 #define DSPI_PUSHR_CTCNT_MASK (0x4000000U) 528 #define DSPI_PUSHR_CTCNT_SHIFT (26U) 529 #define DSPI_PUSHR_CTCNT_WIDTH (1U) 530 #define DSPI_PUSHR_CTCNT(x) (((uint32_t)(((uint32_t)(x)) << DSPI_PUSHR_CTCNT_SHIFT)) & DSPI_PUSHR_CTCNT_MASK) 531 532 #define DSPI_PUSHR_EOQ_MASK (0x8000000U) 533 #define DSPI_PUSHR_EOQ_SHIFT (27U) 534 #define DSPI_PUSHR_EOQ_WIDTH (1U) 535 #define DSPI_PUSHR_EOQ(x) (((uint32_t)(((uint32_t)(x)) << DSPI_PUSHR_EOQ_SHIFT)) & DSPI_PUSHR_EOQ_MASK) 536 537 #define DSPI_PUSHR_CTAS_MASK (0x70000000U) 538 #define DSPI_PUSHR_CTAS_SHIFT (28U) 539 #define DSPI_PUSHR_CTAS_WIDTH (3U) 540 #define DSPI_PUSHR_CTAS(x) (((uint32_t)(((uint32_t)(x)) << DSPI_PUSHR_CTAS_SHIFT)) & DSPI_PUSHR_CTAS_MASK) 541 542 #define DSPI_PUSHR_CONT_MASK (0x80000000U) 543 #define DSPI_PUSHR_CONT_SHIFT (31U) 544 #define DSPI_PUSHR_CONT_WIDTH (1U) 545 #define DSPI_PUSHR_CONT(x) (((uint32_t)(((uint32_t)(x)) << DSPI_PUSHR_CONT_SHIFT)) & DSPI_PUSHR_CONT_MASK) 546 /*! @} */ 547 548 /*! @name POPR - POP RX FIFO Register */ 549 /*! @{ */ 550 551 #define DSPI_POPR_RXDATA_MASK (0xFFFFFFFFU) 552 #define DSPI_POPR_RXDATA_SHIFT (0U) 553 #define DSPI_POPR_RXDATA_WIDTH (32U) 554 #define DSPI_POPR_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << DSPI_POPR_RXDATA_SHIFT)) & DSPI_POPR_RXDATA_MASK) 555 /*! @} */ 556 557 /*! @name TXFR - Transmit FIFO Registers */ 558 /*! @{ */ 559 560 #define DSPI_TXFR_TXDATA_MASK (0xFFFFU) 561 #define DSPI_TXFR_TXDATA_SHIFT (0U) 562 #define DSPI_TXFR_TXDATA_WIDTH (16U) 563 #define DSPI_TXFR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << DSPI_TXFR_TXDATA_SHIFT)) & DSPI_TXFR_TXDATA_MASK) 564 565 #define DSPI_TXFR_TXCMD_TXDATA_MASK (0xFFFF0000U) 566 #define DSPI_TXFR_TXCMD_TXDATA_SHIFT (16U) 567 #define DSPI_TXFR_TXCMD_TXDATA_WIDTH (16U) 568 #define DSPI_TXFR_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << DSPI_TXFR_TXCMD_TXDATA_SHIFT)) & DSPI_TXFR_TXCMD_TXDATA_MASK) 569 /*! @} */ 570 571 /*! @name RXFR - Receive FIFO Registers */ 572 /*! @{ */ 573 574 #define DSPI_RXFR_RXDATA_MASK (0xFFFFFFFFU) 575 #define DSPI_RXFR_RXDATA_SHIFT (0U) 576 #define DSPI_RXFR_RXDATA_WIDTH (32U) 577 #define DSPI_RXFR_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << DSPI_RXFR_RXDATA_SHIFT)) & DSPI_RXFR_RXDATA_MASK) 578 /*! @} */ 579 580 /*! @name DSICR0 - DSI Configuration Register 0 */ 581 /*! @{ */ 582 583 #define DSPI_DSICR0_DPCSx_MASK (0xFFU) 584 #define DSPI_DSICR0_DPCSx_SHIFT (0U) 585 #define DSPI_DSICR0_DPCSx_WIDTH (8U) 586 #define DSPI_DSICR0_DPCSx(x) (((uint32_t)(((uint32_t)(x)) << DSPI_DSICR0_DPCSx_SHIFT)) & DSPI_DSICR0_DPCSx_MASK) 587 588 #define DSPI_DSICR0_PP_MASK (0x100U) 589 #define DSPI_DSICR0_PP_SHIFT (8U) 590 #define DSPI_DSICR0_PP_WIDTH (1U) 591 #define DSPI_DSICR0_PP(x) (((uint32_t)(((uint32_t)(x)) << DSPI_DSICR0_PP_SHIFT)) & DSPI_DSICR0_PP_MASK) 592 593 #define DSPI_DSICR0_PE_MASK (0x200U) 594 #define DSPI_DSICR0_PE_SHIFT (9U) 595 #define DSPI_DSICR0_PE_WIDTH (1U) 596 #define DSPI_DSICR0_PE(x) (((uint32_t)(((uint32_t)(x)) << DSPI_DSICR0_PE_SHIFT)) & DSPI_DSICR0_PE_MASK) 597 598 #define DSPI_DSICR0_PES_MASK (0x400U) 599 #define DSPI_DSICR0_PES_SHIFT (10U) 600 #define DSPI_DSICR0_PES_WIDTH (1U) 601 #define DSPI_DSICR0_PES(x) (((uint32_t)(((uint32_t)(x)) << DSPI_DSICR0_PES_SHIFT)) & DSPI_DSICR0_PES_MASK) 602 603 #define DSPI_DSICR0_DMS_MASK (0x800U) 604 #define DSPI_DSICR0_DMS_SHIFT (11U) 605 #define DSPI_DSICR0_DMS_WIDTH (1U) 606 #define DSPI_DSICR0_DMS(x) (((uint32_t)(((uint32_t)(x)) << DSPI_DSICR0_DMS_SHIFT)) & DSPI_DSICR0_DMS_MASK) 607 608 #define DSPI_DSICR0_DSICTAS_MASK (0x7000U) 609 #define DSPI_DSICR0_DSICTAS_SHIFT (12U) 610 #define DSPI_DSICR0_DSICTAS_WIDTH (3U) 611 #define DSPI_DSICR0_DSICTAS(x) (((uint32_t)(((uint32_t)(x)) << DSPI_DSICR0_DSICTAS_SHIFT)) & DSPI_DSICR0_DSICTAS_MASK) 612 613 #define DSPI_DSICR0_DCONT_MASK (0x8000U) 614 #define DSPI_DSICR0_DCONT_SHIFT (15U) 615 #define DSPI_DSICR0_DCONT_WIDTH (1U) 616 #define DSPI_DSICR0_DCONT(x) (((uint32_t)(((uint32_t)(x)) << DSPI_DSICR0_DCONT_SHIFT)) & DSPI_DSICR0_DCONT_MASK) 617 618 #define DSPI_DSICR0_CID_MASK (0x10000U) 619 #define DSPI_DSICR0_CID_SHIFT (16U) 620 #define DSPI_DSICR0_CID_WIDTH (1U) 621 #define DSPI_DSICR0_CID(x) (((uint32_t)(((uint32_t)(x)) << DSPI_DSICR0_CID_SHIFT)) & DSPI_DSICR0_CID_MASK) 622 623 #define DSPI_DSICR0_TXSS_MASK (0x80000U) 624 #define DSPI_DSICR0_TXSS_SHIFT (19U) 625 #define DSPI_DSICR0_TXSS_WIDTH (1U) 626 #define DSPI_DSICR0_TXSS(x) (((uint32_t)(((uint32_t)(x)) << DSPI_DSICR0_TXSS_SHIFT)) & DSPI_DSICR0_TXSS_MASK) 627 628 #define DSPI_DSICR0_TSBC_MASK (0x100000U) 629 #define DSPI_DSICR0_TSBC_SHIFT (20U) 630 #define DSPI_DSICR0_TSBC_WIDTH (1U) 631 #define DSPI_DSICR0_TSBC(x) (((uint32_t)(((uint32_t)(x)) << DSPI_DSICR0_TSBC_SHIFT)) & DSPI_DSICR0_TSBC_MASK) 632 633 #define DSPI_DSICR0_ITSB_MASK (0x200000U) 634 #define DSPI_DSICR0_ITSB_SHIFT (21U) 635 #define DSPI_DSICR0_ITSB_WIDTH (1U) 636 #define DSPI_DSICR0_ITSB(x) (((uint32_t)(((uint32_t)(x)) << DSPI_DSICR0_ITSB_SHIFT)) & DSPI_DSICR0_ITSB_MASK) 637 638 #define DSPI_DSICR0_FMSZ5_MASK (0x800000U) 639 #define DSPI_DSICR0_FMSZ5_SHIFT (23U) 640 #define DSPI_DSICR0_FMSZ5_WIDTH (1U) 641 #define DSPI_DSICR0_FMSZ5(x) (((uint32_t)(((uint32_t)(x)) << DSPI_DSICR0_FMSZ5_SHIFT)) & DSPI_DSICR0_FMSZ5_MASK) 642 643 #define DSPI_DSICR0_FMSZ4_MASK (0x40000000U) 644 #define DSPI_DSICR0_FMSZ4_SHIFT (30U) 645 #define DSPI_DSICR0_FMSZ4_WIDTH (1U) 646 #define DSPI_DSICR0_FMSZ4(x) (((uint32_t)(((uint32_t)(x)) << DSPI_DSICR0_FMSZ4_SHIFT)) & DSPI_DSICR0_FMSZ4_MASK) 647 /*! @} */ 648 649 /*! @name SDR0 - DSI Serialization Data Register 0 */ 650 /*! @{ */ 651 652 #define DSPI_SDR0_SER_DATA_MASK (0xFFFFFFFFU) 653 #define DSPI_SDR0_SER_DATA_SHIFT (0U) 654 #define DSPI_SDR0_SER_DATA_WIDTH (32U) 655 #define DSPI_SDR0_SER_DATA(x) (((uint32_t)(((uint32_t)(x)) << DSPI_SDR0_SER_DATA_SHIFT)) & DSPI_SDR0_SER_DATA_MASK) 656 /*! @} */ 657 658 /*! @name ASDR0 - DSI Alternate Serialization Data Register 0 */ 659 /*! @{ */ 660 661 #define DSPI_ASDR0_ASER_DATA_MASK (0xFFFFFFFFU) 662 #define DSPI_ASDR0_ASER_DATA_SHIFT (0U) 663 #define DSPI_ASDR0_ASER_DATA_WIDTH (32U) 664 #define DSPI_ASDR0_ASER_DATA(x) (((uint32_t)(((uint32_t)(x)) << DSPI_ASDR0_ASER_DATA_SHIFT)) & DSPI_ASDR0_ASER_DATA_MASK) 665 /*! @} */ 666 667 /*! @name COMPR0 - DSI Transmit Comparison Register 0 */ 668 /*! @{ */ 669 670 #define DSPI_COMPR0_COMP_DATA_MASK (0xFFFFFFFFU) 671 #define DSPI_COMPR0_COMP_DATA_SHIFT (0U) 672 #define DSPI_COMPR0_COMP_DATA_WIDTH (32U) 673 #define DSPI_COMPR0_COMP_DATA(x) (((uint32_t)(((uint32_t)(x)) << DSPI_COMPR0_COMP_DATA_SHIFT)) & DSPI_COMPR0_COMP_DATA_MASK) 674 /*! @} */ 675 676 /*! @name DDR0 - DSI Deserialization Data Register 0 */ 677 /*! @{ */ 678 679 #define DSPI_DDR0_DESER_DATA_MASK (0xFFFFFFFFU) 680 #define DSPI_DDR0_DESER_DATA_SHIFT (0U) 681 #define DSPI_DDR0_DESER_DATA_WIDTH (32U) 682 #define DSPI_DDR0_DESER_DATA(x) (((uint32_t)(((uint32_t)(x)) << DSPI_DDR0_DESER_DATA_SHIFT)) & DSPI_DDR0_DESER_DATA_MASK) 683 /*! @} */ 684 685 /*! @name DSICR1 - DSI Configuration Register 1 */ 686 /*! @{ */ 687 688 #define DSPI_DSICR1_DPCS1_x_MASK (0xFFU) 689 #define DSPI_DSICR1_DPCS1_x_SHIFT (0U) 690 #define DSPI_DSICR1_DPCS1_x_WIDTH (8U) 691 #define DSPI_DSICR1_DPCS1_x(x) (((uint32_t)(((uint32_t)(x)) << DSPI_DSICR1_DPCS1_x_SHIFT)) & DSPI_DSICR1_DPCS1_x_MASK) 692 693 #define DSPI_DSICR1_DSE0_MASK (0x10000U) 694 #define DSPI_DSICR1_DSE0_SHIFT (16U) 695 #define DSPI_DSICR1_DSE0_WIDTH (1U) 696 #define DSPI_DSICR1_DSE0(x) (((uint32_t)(((uint32_t)(x)) << DSPI_DSICR1_DSE0_SHIFT)) & DSPI_DSICR1_DSE0_MASK) 697 698 #define DSPI_DSICR1_DSE1_MASK (0x20000U) 699 #define DSPI_DSICR1_DSE1_SHIFT (17U) 700 #define DSPI_DSICR1_DSE1_WIDTH (1U) 701 #define DSPI_DSICR1_DSE1(x) (((uint32_t)(((uint32_t)(x)) << DSPI_DSICR1_DSE1_SHIFT)) & DSPI_DSICR1_DSE1_MASK) 702 703 #define DSPI_DSICR1_DSI64E_MASK (0x40000U) 704 #define DSPI_DSICR1_DSI64E_SHIFT (18U) 705 #define DSPI_DSICR1_DSI64E_WIDTH (1U) 706 #define DSPI_DSICR1_DSI64E(x) (((uint32_t)(((uint32_t)(x)) << DSPI_DSICR1_DSI64E_SHIFT)) & DSPI_DSICR1_DSI64E_MASK) 707 708 #define DSPI_DSICR1_CSE_MASK (0x80000U) 709 #define DSPI_DSICR1_CSE_SHIFT (19U) 710 #define DSPI_DSICR1_CSE_WIDTH (1U) 711 #define DSPI_DSICR1_CSE(x) (((uint32_t)(((uint32_t)(x)) << DSPI_DSICR1_CSE_SHIFT)) & DSPI_DSICR1_CSE_MASK) 712 713 #define DSPI_DSICR1_TSBCNT_MASK (0x3F000000U) 714 #define DSPI_DSICR1_TSBCNT_SHIFT (24U) 715 #define DSPI_DSICR1_TSBCNT_WIDTH (6U) 716 #define DSPI_DSICR1_TSBCNT(x) (((uint32_t)(((uint32_t)(x)) << DSPI_DSICR1_TSBCNT_SHIFT)) & DSPI_DSICR1_TSBCNT_MASK) 717 /*! @} */ 718 719 /*! @name SSR0 - DSI Serialization Source Select Register 0 */ 720 /*! @{ */ 721 722 #define DSPI_SSR0_SS_MASK (0xFFFFFFFFU) 723 #define DSPI_SSR0_SS_SHIFT (0U) 724 #define DSPI_SSR0_SS_WIDTH (32U) 725 #define DSPI_SSR0_SS(x) (((uint32_t)(((uint32_t)(x)) << DSPI_SSR0_SS_SHIFT)) & DSPI_SSR0_SS_MASK) 726 /*! @} */ 727 728 /*! @name DIMR0 - DSI Deserialized Data Interrupt Mask Register 0 */ 729 /*! @{ */ 730 731 #define DSPI_DIMR0_MASK_MASK (0xFFFFFFFFU) 732 #define DSPI_DIMR0_MASK_SHIFT (0U) 733 #define DSPI_DIMR0_MASK_WIDTH (32U) 734 #define DSPI_DIMR0_MASK(x) (((uint32_t)(((uint32_t)(x)) << DSPI_DIMR0_MASK_SHIFT)) & DSPI_DIMR0_MASK_MASK) 735 /*! @} */ 736 737 /*! @name DPIR0 - DSI Deserialized Data Polarity Interrupt Register 0 */ 738 /*! @{ */ 739 740 #define DSPI_DPIR0_DP_MASK (0xFFFFFFFFU) 741 #define DSPI_DPIR0_DP_SHIFT (0U) 742 #define DSPI_DPIR0_DP_WIDTH (32U) 743 #define DSPI_DPIR0_DP(x) (((uint32_t)(((uint32_t)(x)) << DSPI_DPIR0_DP_SHIFT)) & DSPI_DPIR0_DP_MASK) 744 /*! @} */ 745 746 /*! @name SDR1 - DSI Serialization Data Register 1 */ 747 /*! @{ */ 748 749 #define DSPI_SDR1_SER_DATA_MASK (0xFFFFFFFFU) 750 #define DSPI_SDR1_SER_DATA_SHIFT (0U) 751 #define DSPI_SDR1_SER_DATA_WIDTH (32U) 752 #define DSPI_SDR1_SER_DATA(x) (((uint32_t)(((uint32_t)(x)) << DSPI_SDR1_SER_DATA_SHIFT)) & DSPI_SDR1_SER_DATA_MASK) 753 /*! @} */ 754 755 /*! @name ASDR1 - DSI Alternate Serialization Data Register 1 */ 756 /*! @{ */ 757 758 #define DSPI_ASDR1_ASER_DATA_MASK (0xFFFFFFFFU) 759 #define DSPI_ASDR1_ASER_DATA_SHIFT (0U) 760 #define DSPI_ASDR1_ASER_DATA_WIDTH (32U) 761 #define DSPI_ASDR1_ASER_DATA(x) (((uint32_t)(((uint32_t)(x)) << DSPI_ASDR1_ASER_DATA_SHIFT)) & DSPI_ASDR1_ASER_DATA_MASK) 762 /*! @} */ 763 764 /*! @name COMPR1 - DSI Transmit Comparison Register 1 */ 765 /*! @{ */ 766 767 #define DSPI_COMPR1_COMP_DATA_MASK (0xFFFFFFFFU) 768 #define DSPI_COMPR1_COMP_DATA_SHIFT (0U) 769 #define DSPI_COMPR1_COMP_DATA_WIDTH (32U) 770 #define DSPI_COMPR1_COMP_DATA(x) (((uint32_t)(((uint32_t)(x)) << DSPI_COMPR1_COMP_DATA_SHIFT)) & DSPI_COMPR1_COMP_DATA_MASK) 771 /*! @} */ 772 773 /*! @name DDR1 - DSI Deserialization Data Register 1 */ 774 /*! @{ */ 775 776 #define DSPI_DDR1_DESER_DATA_MASK (0xFFFFFFFFU) 777 #define DSPI_DDR1_DESER_DATA_SHIFT (0U) 778 #define DSPI_DDR1_DESER_DATA_WIDTH (32U) 779 #define DSPI_DDR1_DESER_DATA(x) (((uint32_t)(((uint32_t)(x)) << DSPI_DDR1_DESER_DATA_SHIFT)) & DSPI_DDR1_DESER_DATA_MASK) 780 /*! @} */ 781 782 /*! @name SSR1 - DSI Serialization Source Select Register 1 */ 783 /*! @{ */ 784 785 #define DSPI_SSR1_SS_MASK (0xFFFFFFFFU) 786 #define DSPI_SSR1_SS_SHIFT (0U) 787 #define DSPI_SSR1_SS_WIDTH (32U) 788 #define DSPI_SSR1_SS(x) (((uint32_t)(((uint32_t)(x)) << DSPI_SSR1_SS_SHIFT)) & DSPI_SSR1_SS_MASK) 789 /*! @} */ 790 791 /*! @name DIMR1 - DSI Deserialized Data Interrupt Mask Register 1 */ 792 /*! @{ */ 793 794 #define DSPI_DIMR1_MASK_MASK (0xFFFFFFFFU) 795 #define DSPI_DIMR1_MASK_SHIFT (0U) 796 #define DSPI_DIMR1_MASK_WIDTH (32U) 797 #define DSPI_DIMR1_MASK(x) (((uint32_t)(((uint32_t)(x)) << DSPI_DIMR1_MASK_SHIFT)) & DSPI_DIMR1_MASK_MASK) 798 /*! @} */ 799 800 /*! @name DPIR1 - DSI Deserialized Data Polarity Interrupt Register 1 */ 801 /*! @{ */ 802 803 #define DSPI_DPIR1_DP_MASK (0xFFFFFFFFU) 804 #define DSPI_DPIR1_DP_SHIFT (0U) 805 #define DSPI_DPIR1_DP_WIDTH (32U) 806 #define DSPI_DPIR1_DP(x) (((uint32_t)(((uint32_t)(x)) << DSPI_DPIR1_DP_SHIFT)) & DSPI_DPIR1_DP_MASK) 807 /*! @} */ 808 809 /*! @name CTARE - Clock and Transfer Attributes Register Extended */ 810 /*! @{ */ 811 812 #define DSPI_CTARE_DTCP_MASK (0x7FFU) 813 #define DSPI_CTARE_DTCP_SHIFT (0U) 814 #define DSPI_CTARE_DTCP_WIDTH (11U) 815 #define DSPI_CTARE_DTCP(x) (((uint32_t)(((uint32_t)(x)) << DSPI_CTARE_DTCP_SHIFT)) & DSPI_CTARE_DTCP_MASK) 816 817 #define DSPI_CTARE_FMSZE_MASK (0x10000U) 818 #define DSPI_CTARE_FMSZE_SHIFT (16U) 819 #define DSPI_CTARE_FMSZE_WIDTH (1U) 820 #define DSPI_CTARE_FMSZE(x) (((uint32_t)(((uint32_t)(x)) << DSPI_CTARE_FMSZE_SHIFT)) & DSPI_CTARE_FMSZE_MASK) 821 /*! @} */ 822 823 /*! @name SREX - Status Register Extended */ 824 /*! @{ */ 825 826 #define DSPI_SREX_CMDNXTPTR_MASK (0xFU) 827 #define DSPI_SREX_CMDNXTPTR_SHIFT (0U) 828 #define DSPI_SREX_CMDNXTPTR_WIDTH (4U) 829 #define DSPI_SREX_CMDNXTPTR(x) (((uint32_t)(((uint32_t)(x)) << DSPI_SREX_CMDNXTPTR_SHIFT)) & DSPI_SREX_CMDNXTPTR_MASK) 830 831 #define DSPI_SREX_CMDCTR_MASK (0x1F0U) 832 #define DSPI_SREX_CMDCTR_SHIFT (4U) 833 #define DSPI_SREX_CMDCTR_WIDTH (5U) 834 #define DSPI_SREX_CMDCTR(x) (((uint32_t)(((uint32_t)(x)) << DSPI_SREX_CMDCTR_SHIFT)) & DSPI_SREX_CMDCTR_MASK) 835 836 #define DSPI_SREX_RXCTR4_MASK (0x800U) 837 #define DSPI_SREX_RXCTR4_SHIFT (11U) 838 #define DSPI_SREX_RXCTR4_WIDTH (1U) 839 #define DSPI_SREX_RXCTR4(x) (((uint32_t)(((uint32_t)(x)) << DSPI_SREX_RXCTR4_SHIFT)) & DSPI_SREX_RXCTR4_MASK) 840 841 #define DSPI_SREX_TXCTR4_MASK (0x4000U) 842 #define DSPI_SREX_TXCTR4_SHIFT (14U) 843 #define DSPI_SREX_TXCTR4_WIDTH (1U) 844 #define DSPI_SREX_TXCTR4(x) (((uint32_t)(((uint32_t)(x)) << DSPI_SREX_TXCTR4_SHIFT)) & DSPI_SREX_TXCTR4_MASK) 845 /*! @} */ 846 847 /*! @name TSL - Time Slot Length Register */ 848 /*! @{ */ 849 850 #define DSPI_TSL_TS0_LEN_MASK (0x7FU) 851 #define DSPI_TSL_TS0_LEN_SHIFT (0U) 852 #define DSPI_TSL_TS0_LEN_WIDTH (7U) 853 #define DSPI_TSL_TS0_LEN(x) (((uint32_t)(((uint32_t)(x)) << DSPI_TSL_TS0_LEN_SHIFT)) & DSPI_TSL_TS0_LEN_MASK) 854 855 #define DSPI_TSL_TS1_LEN_MASK (0x7F00U) 856 #define DSPI_TSL_TS1_LEN_SHIFT (8U) 857 #define DSPI_TSL_TS1_LEN_WIDTH (7U) 858 #define DSPI_TSL_TS1_LEN(x) (((uint32_t)(((uint32_t)(x)) << DSPI_TSL_TS1_LEN_SHIFT)) & DSPI_TSL_TS1_LEN_MASK) 859 860 #define DSPI_TSL_TS2_LEN_MASK (0x7F0000U) 861 #define DSPI_TSL_TS2_LEN_SHIFT (16U) 862 #define DSPI_TSL_TS2_LEN_WIDTH (7U) 863 #define DSPI_TSL_TS2_LEN(x) (((uint32_t)(((uint32_t)(x)) << DSPI_TSL_TS2_LEN_SHIFT)) & DSPI_TSL_TS2_LEN_MASK) 864 865 #define DSPI_TSL_TS3_LEN_MASK (0x7F000000U) 866 #define DSPI_TSL_TS3_LEN_SHIFT (24U) 867 #define DSPI_TSL_TS3_LEN_WIDTH (7U) 868 #define DSPI_TSL_TS3_LEN(x) (((uint32_t)(((uint32_t)(x)) << DSPI_TSL_TS3_LEN_SHIFT)) & DSPI_TSL_TS3_LEN_MASK) 869 /*! @} */ 870 871 /*! @name TS_CONF - Time Slot Configuration Register */ 872 /*! @{ */ 873 874 #define DSPI_TS_CONF_TS0_MASK (0xFU) 875 #define DSPI_TS_CONF_TS0_SHIFT (0U) 876 #define DSPI_TS_CONF_TS0_WIDTH (4U) 877 #define DSPI_TS_CONF_TS0(x) (((uint32_t)(((uint32_t)(x)) << DSPI_TS_CONF_TS0_SHIFT)) & DSPI_TS_CONF_TS0_MASK) 878 879 #define DSPI_TS_CONF_TS1_MASK (0xF0U) 880 #define DSPI_TS_CONF_TS1_SHIFT (4U) 881 #define DSPI_TS_CONF_TS1_WIDTH (4U) 882 #define DSPI_TS_CONF_TS1(x) (((uint32_t)(((uint32_t)(x)) << DSPI_TS_CONF_TS1_SHIFT)) & DSPI_TS_CONF_TS1_MASK) 883 884 #define DSPI_TS_CONF_TS2_MASK (0xF00U) 885 #define DSPI_TS_CONF_TS2_SHIFT (8U) 886 #define DSPI_TS_CONF_TS2_WIDTH (4U) 887 #define DSPI_TS_CONF_TS2(x) (((uint32_t)(((uint32_t)(x)) << DSPI_TS_CONF_TS2_SHIFT)) & DSPI_TS_CONF_TS2_MASK) 888 889 #define DSPI_TS_CONF_TS3_MASK (0xF000U) 890 #define DSPI_TS_CONF_TS3_SHIFT (12U) 891 #define DSPI_TS_CONF_TS3_WIDTH (4U) 892 #define DSPI_TS_CONF_TS3(x) (((uint32_t)(((uint32_t)(x)) << DSPI_TS_CONF_TS3_SHIFT)) & DSPI_TS_CONF_TS3_MASK) 893 /*! @} */ 894 895 /*! 896 * @} 897 */ /* end of group DSPI_Register_Masks */ 898 899 /*! 900 * @} 901 */ /* end of group DSPI_Peripheral_Access_Layer */ 902 903 #endif /* #if !defined(S32Z2_DSPI_H_) */ 904
