1 /** 2 ****************************************************************************** 3 * @file stm32l4xx_hal_dsi.h 4 * @author MCD Application Team 5 * @brief Header file of DSI HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> 10 * 11 * Redistribution and use in source and binary forms, with or without modification, 12 * are permitted provided that the following conditions are met: 13 * 1. Redistributions of source code must retain the above copyright notice, 14 * this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright notice, 16 * this list of conditions and the following disclaimer in the documentation 17 * and/or other materials provided with the distribution. 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 ****************************************************************************** 34 */ 35 36 /* Define to prevent recursive inclusion -------------------------------------*/ 37 #ifndef STM32L4xx_HAL_DSI_H 38 #define STM32L4xx_HAL_DSI_H 39 40 #ifdef __cplusplus 41 extern "C" { 42 #endif 43 44 #if defined(DSI) 45 /* Includes ------------------------------------------------------------------*/ 46 #include "stm32l4xx_hal_def.h" 47 48 /** @addtogroup STM32L4xx_HAL_Driver 49 * @{ 50 */ 51 52 /** @defgroup DSI DSI 53 * @brief DSI HAL module driver 54 * @{ 55 */ 56 57 /* Exported types ------------------------------------------------------------*/ 58 /** 59 * @brief DSI Init Structure definition 60 */ 61 typedef struct 62 { 63 uint32_t AutomaticClockLaneControl; /*!< Automatic clock lane control 64 This parameter can be any value of @ref DSI_Automatic_Clk_Lane_Control */ 65 66 uint32_t TXEscapeCkdiv; /*!< TX Escape clock division 67 The values 0 and 1 stop the TX_ESC clock generation */ 68 69 uint32_t NumberOfLanes; /*!< Number of lanes 70 This parameter can be any value of @ref DSI_Number_Of_Lanes */ 71 72 }DSI_InitTypeDef; 73 74 /** 75 * @brief DSI PLL Clock structure definition 76 */ 77 typedef struct 78 { 79 uint32_t PLLNDIV; /*!< PLL Loop Division Factor 80 This parameter must be a value between 10 and 125 */ 81 82 uint32_t PLLIDF; /*!< PLL Input Division Factor 83 This parameter can be any value of @ref DSI_PLL_IDF */ 84 85 uint32_t PLLODF; /*!< PLL Output Division Factor 86 This parameter can be any value of @ref DSI_PLL_ODF */ 87 88 }DSI_PLLInitTypeDef; 89 90 /** 91 * @brief DSI Video mode configuration 92 */ 93 typedef struct 94 { 95 uint32_t VirtualChannelID; /*!< Virtual channel ID */ 96 97 uint32_t ColorCoding; /*!< Color coding for LTDC interface 98 This parameter can be any value of @ref DSI_Color_Coding */ 99 100 uint32_t LooselyPacked; /*!< Enable or disable loosely packed stream (needed only when using 101 18-bit configuration). 102 This parameter can be any value of @ref DSI_LooselyPacked */ 103 104 uint32_t Mode; /*!< Video mode type 105 This parameter can be any value of @ref DSI_Video_Mode_Type */ 106 107 uint32_t PacketSize; /*!< Video packet size */ 108 109 uint32_t NumberOfChunks; /*!< Number of chunks */ 110 111 uint32_t NullPacketSize; /*!< Null packet size */ 112 113 uint32_t HSPolarity; /*!< HSYNC pin polarity 114 This parameter can be any value of @ref DSI_HSYNC_Polarity */ 115 116 uint32_t VSPolarity; /*!< VSYNC pin polarity 117 This parameter can be any value of @ref DSI_VSYNC_Active_Polarity */ 118 119 uint32_t DEPolarity; /*!< Data Enable pin polarity 120 This parameter can be any value of @ref DSI_DATA_ENABLE_Polarity */ 121 122 uint32_t HorizontalSyncActive; /*!< Horizontal synchronism active duration (in lane byte clock cycles) */ 123 124 uint32_t HorizontalBackPorch; /*!< Horizontal back-porch duration (in lane byte clock cycles) */ 125 126 uint32_t HorizontalLine; /*!< Horizontal line duration (in lane byte clock cycles) */ 127 128 uint32_t VerticalSyncActive; /*!< Vertical synchronism active duration */ 129 130 uint32_t VerticalBackPorch; /*!< Vertical back-porch duration */ 131 132 uint32_t VerticalFrontPorch; /*!< Vertical front-porch duration */ 133 134 uint32_t VerticalActive; /*!< Vertical active duration */ 135 136 uint32_t LPCommandEnable; /*!< Low-power command enable 137 This parameter can be any value of @ref DSI_LP_Command */ 138 139 uint32_t LPLargestPacketSize; /*!< The size, in bytes, of the low power largest packet that 140 can fit in a line during VSA, VBP and VFP regions */ 141 142 uint32_t LPVACTLargestPacketSize; /*!< The size, in bytes, of the low power largest packet that 143 can fit in a line during VACT region */ 144 145 uint32_t LPHorizontalFrontPorchEnable; /*!< Low-power horizontal front-porch enable 146 This parameter can be any value of @ref DSI_LP_HFP */ 147 148 uint32_t LPHorizontalBackPorchEnable; /*!< Low-power horizontal back-porch enable 149 This parameter can be any value of @ref DSI_LP_HBP */ 150 151 uint32_t LPVerticalActiveEnable; /*!< Low-power vertical active enable 152 This parameter can be any value of @ref DSI_LP_VACT */ 153 154 uint32_t LPVerticalFrontPorchEnable; /*!< Low-power vertical front-porch enable 155 This parameter can be any value of @ref DSI_LP_VFP */ 156 157 uint32_t LPVerticalBackPorchEnable; /*!< Low-power vertical back-porch enable 158 This parameter can be any value of @ref DSI_LP_VBP */ 159 160 uint32_t LPVerticalSyncActiveEnable; /*!< Low-power vertical sync active enable 161 This parameter can be any value of @ref DSI_LP_VSYNC */ 162 163 uint32_t FrameBTAAcknowledgeEnable; /*!< Frame bus-turn-around acknowledge enable 164 This parameter can be any value of @ref DSI_FBTA_acknowledge */ 165 166 }DSI_VidCfgTypeDef; 167 168 /** 169 * @brief DSI Adapted command mode configuration 170 */ 171 typedef struct 172 { 173 uint32_t VirtualChannelID; /*!< Virtual channel ID */ 174 175 uint32_t ColorCoding; /*!< Color coding for LTDC interface 176 This parameter can be any value of @ref DSI_Color_Coding */ 177 178 uint32_t CommandSize; /*!< Maximum allowed size for an LTDC write memory command, measured in 179 pixels. This parameter can be any value between 0x00 and 0xFFFFU */ 180 181 uint32_t TearingEffectSource; /*!< Tearing effect source 182 This parameter can be any value of @ref DSI_TearingEffectSource */ 183 184 uint32_t TearingEffectPolarity; /*!< Tearing effect pin polarity 185 This parameter can be any value of @ref DSI_TearingEffectPolarity */ 186 187 uint32_t HSPolarity; /*!< HSYNC pin polarity 188 This parameter can be any value of @ref DSI_HSYNC_Polarity */ 189 190 uint32_t VSPolarity; /*!< VSYNC pin polarity 191 This parameter can be any value of @ref DSI_VSYNC_Active_Polarity */ 192 193 uint32_t DEPolarity; /*!< Data Enable pin polarity 194 This parameter can be any value of @ref DSI_DATA_ENABLE_Polarity */ 195 196 uint32_t VSyncPol; /*!< VSync edge on which the LTDC is halted 197 This parameter can be any value of @ref DSI_Vsync_Polarity */ 198 199 uint32_t AutomaticRefresh; /*!< Automatic refresh mode 200 This parameter can be any value of @ref DSI_AutomaticRefresh */ 201 202 uint32_t TEAcknowledgeRequest; /*!< Tearing Effect Acknowledge Request Enable 203 This parameter can be any value of @ref DSI_TE_AcknowledgeRequest */ 204 205 }DSI_CmdCfgTypeDef; 206 207 /** 208 * @brief DSI command transmission mode configuration 209 */ 210 typedef struct 211 { 212 uint32_t LPGenShortWriteNoP; /*!< Generic Short Write Zero parameters Transmission 213 This parameter can be any value of @ref DSI_LP_LPGenShortWriteNoP */ 214 215 uint32_t LPGenShortWriteOneP; /*!< Generic Short Write One parameter Transmission 216 This parameter can be any value of @ref DSI_LP_LPGenShortWriteOneP */ 217 218 uint32_t LPGenShortWriteTwoP; /*!< Generic Short Write Two parameters Transmission 219 This parameter can be any value of @ref DSI_LP_LPGenShortWriteTwoP */ 220 221 uint32_t LPGenShortReadNoP; /*!< Generic Short Read Zero parameters Transmission 222 This parameter can be any value of @ref DSI_LP_LPGenShortReadNoP */ 223 224 uint32_t LPGenShortReadOneP; /*!< Generic Short Read One parameter Transmission 225 This parameter can be any value of @ref DSI_LP_LPGenShortReadOneP */ 226 227 uint32_t LPGenShortReadTwoP; /*!< Generic Short Read Two parameters Transmission 228 This parameter can be any value of @ref DSI_LP_LPGenShortReadTwoP */ 229 230 uint32_t LPGenLongWrite; /*!< Generic Long Write Transmission 231 This parameter can be any value of @ref DSI_LP_LPGenLongWrite */ 232 233 uint32_t LPDcsShortWriteNoP; /*!< DCS Short Write Zero parameters Transmission 234 This parameter can be any value of @ref DSI_LP_LPDcsShortWriteNoP */ 235 236 uint32_t LPDcsShortWriteOneP; /*!< DCS Short Write One parameter Transmission 237 This parameter can be any value of @ref DSI_LP_LPDcsShortWriteOneP */ 238 239 uint32_t LPDcsShortReadNoP; /*!< DCS Short Read Zero parameters Transmission 240 This parameter can be any value of @ref DSI_LP_LPDcsShortReadNoP */ 241 242 uint32_t LPDcsLongWrite; /*!< DCS Long Write Transmission 243 This parameter can be any value of @ref DSI_LP_LPDcsLongWrite */ 244 245 uint32_t LPMaxReadPacket; /*!< Maximum Read Packet Size Transmission 246 This parameter can be any value of @ref DSI_LP_LPMaxReadPacket */ 247 248 uint32_t AcknowledgeRequest; /*!< Acknowledge Request Enable 249 This parameter can be any value of @ref DSI_AcknowledgeRequest */ 250 251 }DSI_LPCmdTypeDef; 252 253 /** 254 * @brief DSI PHY Timings definition 255 */ 256 typedef struct 257 { 258 uint32_t ClockLaneHS2LPTime; /*!< The maximum time that the D-PHY clock lane takes to go from high-speed 259 to low-power transmission */ 260 261 uint32_t ClockLaneLP2HSTime; /*!< The maximum time that the D-PHY clock lane takes to go from low-power 262 to high-speed transmission */ 263 264 uint32_t DataLaneHS2LPTime; /*!< The maximum time that the D-PHY data lanes takes to go from high-speed 265 to low-power transmission */ 266 267 uint32_t DataLaneLP2HSTime; /*!< The maximum time that the D-PHY data lanes takes to go from low-power 268 to high-speed transmission */ 269 270 uint32_t DataLaneMaxReadTime; /*!< The maximum time required to perform a read command */ 271 272 uint32_t StopWaitTime; /*!< The minimum wait period to request a High-Speed transmission after the 273 Stop state */ 274 275 }DSI_PHY_TimerTypeDef; 276 277 /** 278 * @brief DSI HOST Timeouts definition 279 */ 280 typedef struct 281 { 282 uint32_t TimeoutCkdiv; /*!< Time-out clock division */ 283 284 uint32_t HighSpeedTransmissionTimeout; /*!< High-speed transmission time-out */ 285 286 uint32_t LowPowerReceptionTimeout; /*!< Low-power reception time-out */ 287 288 uint32_t HighSpeedReadTimeout; /*!< High-speed read time-out */ 289 290 uint32_t LowPowerReadTimeout; /*!< Low-power read time-out */ 291 292 uint32_t HighSpeedWriteTimeout; /*!< High-speed write time-out */ 293 294 uint32_t HighSpeedWritePrespMode; /*!< High-speed write presp mode 295 This parameter can be any value of @ref DSI_HS_PrespMode */ 296 297 uint32_t LowPowerWriteTimeout; /*!< Low-speed write time-out */ 298 299 uint32_t BTATimeout; /*!< BTA time-out */ 300 301 }DSI_HOST_TimeoutTypeDef; 302 303 /** 304 * @brief DSI States Structure definition 305 */ 306 typedef enum 307 { 308 HAL_DSI_STATE_RESET = 0x00U, 309 HAL_DSI_STATE_READY = 0x01U, 310 HAL_DSI_STATE_ERROR = 0x02U, 311 HAL_DSI_STATE_BUSY = 0x03U, 312 HAL_DSI_STATE_TIMEOUT = 0x04U 313 }HAL_DSI_StateTypeDef; 314 315 /** 316 * @brief DSI Handle Structure definition 317 */ 318 typedef struct __DSI_HandleTypeDef 319 { 320 DSI_TypeDef *Instance; /*!< Register base address */ 321 DSI_InitTypeDef Init; /*!< DSI required parameters */ 322 HAL_LockTypeDef Lock; /*!< DSI peripheral status */ 323 __IO HAL_DSI_StateTypeDef State; /*!< DSI communication state */ 324 __IO uint32_t ErrorCode; /*!< DSI Error code */ 325 uint32_t ErrorMsk; /*!< DSI Error monitoring mask */ 326 327 #if (USE_HAL_DSI_REGISTER_CALLBACKS == 1) 328 void (* TearingEffectCallback)(struct __DSI_HandleTypeDef *hdsi); /*!< DSI Tearing Effect Callback */ 329 void (* EndOfRefreshCallback) (struct __DSI_HandleTypeDef *hdsi); /*!< DSI End Of Refresh Callback */ 330 void (* ErrorCallback) (struct __DSI_HandleTypeDef *hdsi); /*!< DSI Error Callback */ 331 332 void (* MspInitCallback) (struct __DSI_HandleTypeDef *hdsi); /*!< DSI Msp Init callback */ 333 void (* MspDeInitCallback) (struct __DSI_HandleTypeDef *hdsi); /*!< DSI Msp DeInit callback */ 334 335 #endif /* USE_HAL_DSI_REGISTER_CALLBACKS */ 336 337 }DSI_HandleTypeDef; 338 339 #if (USE_HAL_DSI_REGISTER_CALLBACKS == 1) 340 /** 341 * @brief HAL DSI Callback ID enumeration definition 342 */ 343 typedef enum 344 { 345 HAL_DSI_MSPINIT_CB_ID = 0x00U, /*!< DSI MspInit callback ID */ 346 HAL_DSI_MSPDEINIT_CB_ID = 0x01U, /*!< DSI MspDeInit callback ID */ 347 348 HAL_DSI_TEARING_EFFECT_CB_ID = 0x02U, /*!< DSI Tearing Effect Callback ID */ 349 HAL_DSI_ENDOF_REFRESH_CB_ID = 0x03U, /*!< DSI End Of Refresh Callback ID */ 350 HAL_DSI_ERROR_CB_ID = 0x04U /*!< DSI Error Callback ID */ 351 352 }HAL_DSI_CallbackIDTypeDef; 353 354 /** 355 * @brief HAL DSI Callback pointer definition 356 */ 357 typedef void (*pDSI_CallbackTypeDef)(DSI_HandleTypeDef * hdsi); /*!< pointer to an DSI callback function */ 358 359 #endif /* USE_HAL_DSI_REGISTER_CALLBACKS */ 360 361 /* Exported constants --------------------------------------------------------*/ 362 /** @defgroup DSI_DCS_Command DSI DCS Command 363 * @{ 364 */ 365 #define DSI_ENTER_IDLE_MODE 0x39U 366 #define DSI_ENTER_INVERT_MODE 0x21U 367 #define DSI_ENTER_NORMAL_MODE 0x13U 368 #define DSI_ENTER_PARTIAL_MODE 0x12U 369 #define DSI_ENTER_SLEEP_MODE 0x10U 370 #define DSI_EXIT_IDLE_MODE 0x38U 371 #define DSI_EXIT_INVERT_MODE 0x20U 372 #define DSI_EXIT_SLEEP_MODE 0x11U 373 #define DSI_GET_3D_CONTROL 0x3FU 374 #define DSI_GET_ADDRESS_MODE 0x0BU 375 #define DSI_GET_BLUE_CHANNEL 0x08U 376 #define DSI_GET_DIAGNOSTIC_RESULT 0x0FU 377 #define DSI_GET_DISPLAY_MODE 0x0DU 378 #define DSI_GET_GREEN_CHANNEL 0x07U 379 #define DSI_GET_PIXEL_FORMAT 0x0CU 380 #define DSI_GET_POWER_MODE 0x0AU 381 #define DSI_GET_RED_CHANNEL 0x06U 382 #define DSI_GET_SCANLINE 0x45U 383 #define DSI_GET_SIGNAL_MODE 0x0EU 384 #define DSI_NOP 0x00U 385 #define DSI_READ_DDB_CONTINUE 0xA8U 386 #define DSI_READ_DDB_START 0xA1U 387 #define DSI_READ_MEMORY_CONTINUE 0x3EU 388 #define DSI_READ_MEMORY_START 0x2EU 389 #define DSI_SET_3D_CONTROL 0x3DU 390 #define DSI_SET_ADDRESS_MODE 0x36U 391 #define DSI_SET_COLUMN_ADDRESS 0x2AU 392 #define DSI_SET_DISPLAY_OFF 0x28U 393 #define DSI_SET_DISPLAY_ON 0x29U 394 #define DSI_SET_GAMMA_CURVE 0x26U 395 #define DSI_SET_PAGE_ADDRESS 0x2BU 396 #define DSI_SET_PARTIAL_COLUMNS 0x31U 397 #define DSI_SET_PARTIAL_ROWS 0x30U 398 #define DSI_SET_PIXEL_FORMAT 0x3AU 399 #define DSI_SET_SCROLL_AREA 0x33U 400 #define DSI_SET_SCROLL_START 0x37U 401 #define DSI_SET_TEAR_OFF 0x34U 402 #define DSI_SET_TEAR_ON 0x35U 403 #define DSI_SET_TEAR_SCANLINE 0x44U 404 #define DSI_SET_VSYNC_TIMING 0x40U 405 #define DSI_SOFT_RESET 0x01U 406 #define DSI_WRITE_LUT 0x2DU 407 #define DSI_WRITE_MEMORY_CONTINUE 0x3CU 408 #define DSI_WRITE_MEMORY_START 0x2CU 409 /** 410 * @} 411 */ 412 413 /** @defgroup DSI_Video_Mode_Type DSI Video Mode Type 414 * @{ 415 */ 416 #define DSI_VID_MODE_NB_PULSES 0U 417 #define DSI_VID_MODE_NB_EVENTS 1U 418 #define DSI_VID_MODE_BURST 2U 419 /** 420 * @} 421 */ 422 423 /** @defgroup DSI_Color_Mode DSI Color Mode 424 * @{ 425 */ 426 #define DSI_COLOR_MODE_FULL 0x00000000U 427 #define DSI_COLOR_MODE_EIGHT DSI_WCR_COLM 428 /** 429 * @} 430 */ 431 432 /** @defgroup DSI_ShutDown DSI ShutDown 433 * @{ 434 */ 435 #define DSI_DISPLAY_ON 0x00000000U 436 #define DSI_DISPLAY_OFF DSI_WCR_SHTDN 437 /** 438 * @} 439 */ 440 441 /** @defgroup DSI_LP_Command DSI LP Command 442 * @{ 443 */ 444 #define DSI_LP_COMMAND_DISABLE 0x00000000U 445 #define DSI_LP_COMMAND_ENABLE DSI_VMCR_LPCE 446 /** 447 * @} 448 */ 449 450 /** @defgroup DSI_LP_HFP DSI LP HFP 451 * @{ 452 */ 453 #define DSI_LP_HFP_DISABLE 0x00000000U 454 #define DSI_LP_HFP_ENABLE DSI_VMCR_LPHFPE 455 /** 456 * @} 457 */ 458 459 /** @defgroup DSI_LP_HBP DSI LP HBP 460 * @{ 461 */ 462 #define DSI_LP_HBP_DISABLE 0x00000000U 463 #define DSI_LP_HBP_ENABLE DSI_VMCR_LPHBPE 464 /** 465 * @} 466 */ 467 468 /** @defgroup DSI_LP_VACT DSI LP VACT 469 * @{ 470 */ 471 #define DSI_LP_VACT_DISABLE 0x00000000U 472 #define DSI_LP_VACT_ENABLE DSI_VMCR_LPVAE 473 /** 474 * @} 475 */ 476 477 /** @defgroup DSI_LP_VFP DSI LP VFP 478 * @{ 479 */ 480 #define DSI_LP_VFP_DISABLE 0x00000000U 481 #define DSI_LP_VFP_ENABLE DSI_VMCR_LPVFPE 482 /** 483 * @} 484 */ 485 486 /** @defgroup DSI_LP_VBP DSI LP VBP 487 * @{ 488 */ 489 #define DSI_LP_VBP_DISABLE 0x00000000U 490 #define DSI_LP_VBP_ENABLE DSI_VMCR_LPVBPE 491 /** 492 * @} 493 */ 494 495 /** @defgroup DSI_LP_VSYNC DSI LP VSYNC 496 * @{ 497 */ 498 #define DSI_LP_VSYNC_DISABLE 0x00000000U 499 #define DSI_LP_VSYNC_ENABLE DSI_VMCR_LPVSAE 500 /** 501 * @} 502 */ 503 504 /** @defgroup DSI_FBTA_acknowledge DSI FBTA Acknowledge 505 * @{ 506 */ 507 #define DSI_FBTAA_DISABLE 0x00000000U 508 #define DSI_FBTAA_ENABLE DSI_VMCR_FBTAAE 509 /** 510 * @} 511 */ 512 513 /** @defgroup DSI_TearingEffectSource DSI Tearing Effect Source 514 * @{ 515 */ 516 #define DSI_TE_DSILINK 0x00000000U 517 #define DSI_TE_EXTERNAL DSI_WCFGR_TESRC 518 /** 519 * @} 520 */ 521 522 /** @defgroup DSI_TearingEffectPolarity DSI Tearing Effect Polarity 523 * @{ 524 */ 525 #define DSI_TE_RISING_EDGE 0x00000000U 526 #define DSI_TE_FALLING_EDGE DSI_WCFGR_TEPOL 527 /** 528 * @} 529 */ 530 531 /** @defgroup DSI_Vsync_Polarity DSI Vsync Polarity 532 * @{ 533 */ 534 #define DSI_VSYNC_FALLING 0x00000000U 535 #define DSI_VSYNC_RISING DSI_WCFGR_VSPOL 536 /** 537 * @} 538 */ 539 540 /** @defgroup DSI_AutomaticRefresh DSI Automatic Refresh 541 * @{ 542 */ 543 #define DSI_AR_DISABLE 0x00000000U 544 #define DSI_AR_ENABLE DSI_WCFGR_AR 545 /** 546 * @} 547 */ 548 549 /** @defgroup DSI_TE_AcknowledgeRequest DSI TE Acknowledge Request 550 * @{ 551 */ 552 #define DSI_TE_ACKNOWLEDGE_DISABLE 0x00000000U 553 #define DSI_TE_ACKNOWLEDGE_ENABLE DSI_CMCR_TEARE 554 /** 555 * @} 556 */ 557 558 /** @defgroup DSI_AcknowledgeRequest DSI Acknowledge Request 559 * @{ 560 */ 561 #define DSI_ACKNOWLEDGE_DISABLE 0x00000000U 562 #define DSI_ACKNOWLEDGE_ENABLE DSI_CMCR_ARE 563 /** 564 * @} 565 */ 566 567 /** @defgroup DSI_LP_LPGenShortWriteNoP DSI LP LPGen Short Write NoP 568 * @{ 569 */ 570 #define DSI_LP_GSW0P_DISABLE 0x00000000U 571 #define DSI_LP_GSW0P_ENABLE DSI_CMCR_GSW0TX 572 /** 573 * @} 574 */ 575 576 /** @defgroup DSI_LP_LPGenShortWriteOneP DSI LP LPGen Short Write OneP 577 * @{ 578 */ 579 #define DSI_LP_GSW1P_DISABLE 0x00000000U 580 #define DSI_LP_GSW1P_ENABLE DSI_CMCR_GSW1TX 581 /** 582 * @} 583 */ 584 585 /** @defgroup DSI_LP_LPGenShortWriteTwoP DSI LP LPGen Short Write TwoP 586 * @{ 587 */ 588 #define DSI_LP_GSW2P_DISABLE 0x00000000U 589 #define DSI_LP_GSW2P_ENABLE DSI_CMCR_GSW2TX 590 /** 591 * @} 592 */ 593 594 /** @defgroup DSI_LP_LPGenShortReadNoP DSI LP LPGen Short Read NoP 595 * @{ 596 */ 597 #define DSI_LP_GSR0P_DISABLE 0x00000000U 598 #define DSI_LP_GSR0P_ENABLE DSI_CMCR_GSR0TX 599 /** 600 * @} 601 */ 602 603 /** @defgroup DSI_LP_LPGenShortReadOneP DSI LP LPGen Short Read OneP 604 * @{ 605 */ 606 #define DSI_LP_GSR1P_DISABLE 0x00000000U 607 #define DSI_LP_GSR1P_ENABLE DSI_CMCR_GSR1TX 608 /** 609 * @} 610 */ 611 612 /** @defgroup DSI_LP_LPGenShortReadTwoP DSI LP LPGen Short Read TwoP 613 * @{ 614 */ 615 #define DSI_LP_GSR2P_DISABLE 0x00000000U 616 #define DSI_LP_GSR2P_ENABLE DSI_CMCR_GSR2TX 617 /** 618 * @} 619 */ 620 621 /** @defgroup DSI_LP_LPGenLongWrite DSI LP LPGen LongWrite 622 * @{ 623 */ 624 #define DSI_LP_GLW_DISABLE 0x00000000U 625 #define DSI_LP_GLW_ENABLE DSI_CMCR_GLWTX 626 /** 627 * @} 628 */ 629 630 /** @defgroup DSI_LP_LPDcsShortWriteNoP DSI LP LPDcs Short Write NoP 631 * @{ 632 */ 633 #define DSI_LP_DSW0P_DISABLE 0x00000000U 634 #define DSI_LP_DSW0P_ENABLE DSI_CMCR_DSW0TX 635 /** 636 * @} 637 */ 638 639 /** @defgroup DSI_LP_LPDcsShortWriteOneP DSI LP LPDcs Short Write OneP 640 * @{ 641 */ 642 #define DSI_LP_DSW1P_DISABLE 0x00000000U 643 #define DSI_LP_DSW1P_ENABLE DSI_CMCR_DSW1TX 644 /** 645 * @} 646 */ 647 648 /** @defgroup DSI_LP_LPDcsShortReadNoP DSI LP LPDcs Short Read NoP 649 * @{ 650 */ 651 #define DSI_LP_DSR0P_DISABLE 0x00000000U 652 #define DSI_LP_DSR0P_ENABLE DSI_CMCR_DSR0TX 653 /** 654 * @} 655 */ 656 657 /** @defgroup DSI_LP_LPDcsLongWrite DSI LP LPDcs Long Write 658 * @{ 659 */ 660 #define DSI_LP_DLW_DISABLE 0x00000000U 661 #define DSI_LP_DLW_ENABLE DSI_CMCR_DLWTX 662 /** 663 * @} 664 */ 665 666 /** @defgroup DSI_LP_LPMaxReadPacket DSI LP LPMax Read Packet 667 * @{ 668 */ 669 #define DSI_LP_MRDP_DISABLE 0x00000000U 670 #define DSI_LP_MRDP_ENABLE DSI_CMCR_MRDPS 671 /** 672 * @} 673 */ 674 675 /** @defgroup DSI_HS_PrespMode DSI HS Presp Mode 676 * @{ 677 */ 678 #define DSI_HS_PM_DISABLE 0x00000000U 679 #define DSI_HS_PM_ENABLE DSI_TCCR3_PM 680 /** 681 * @} 682 */ 683 684 685 /** @defgroup DSI_Automatic_Clk_Lane_Control DSI Automatic Clk Lane Control 686 * @{ 687 */ 688 #define DSI_AUTO_CLK_LANE_CTRL_DISABLE 0x00000000U 689 #define DSI_AUTO_CLK_LANE_CTRL_ENABLE DSI_CLCR_ACR 690 /** 691 * @} 692 */ 693 694 /** @defgroup DSI_Number_Of_Lanes DSI Number Of Lanes 695 * @{ 696 */ 697 #define DSI_ONE_DATA_LANE 0U 698 #define DSI_TWO_DATA_LANES 1U 699 /** 700 * @} 701 */ 702 703 /** @defgroup DSI_FlowControl DSI Flow Control 704 * @{ 705 */ 706 #define DSI_FLOW_CONTROL_CRC_RX DSI_PCR_CRCRXE 707 #define DSI_FLOW_CONTROL_ECC_RX DSI_PCR_ECCRXE 708 #define DSI_FLOW_CONTROL_BTA DSI_PCR_BTAE 709 #define DSI_FLOW_CONTROL_EOTP_RX DSI_PCR_ETRXE 710 #define DSI_FLOW_CONTROL_EOTP_TX DSI_PCR_ETTXE 711 #define DSI_FLOW_CONTROL_ALL (DSI_FLOW_CONTROL_CRC_RX | DSI_FLOW_CONTROL_ECC_RX | \ 712 DSI_FLOW_CONTROL_BTA | DSI_FLOW_CONTROL_EOTP_RX | \ 713 DSI_FLOW_CONTROL_EOTP_TX) 714 /** 715 * @} 716 */ 717 718 /** @defgroup DSI_Color_Coding DSI Color Coding 719 * @{ 720 */ 721 #define DSI_RGB565 0x00000000U /*!< The values 0x00000001 and 0x00000002 can also be used for the RGB565 color mode configuration */ 722 #define DSI_RGB666 0x00000003U /*!< The value 0x00000004 can also be used for the RGB666 color mode configuration */ 723 #define DSI_RGB888 0x00000005U 724 /** 725 * @} 726 */ 727 728 /** @defgroup DSI_LooselyPacked DSI Loosely Packed 729 * @{ 730 */ 731 #define DSI_LOOSELY_PACKED_ENABLE DSI_LCOLCR_LPE 732 #define DSI_LOOSELY_PACKED_DISABLE 0x00000000U 733 /** 734 * @} 735 */ 736 737 /** @defgroup DSI_HSYNC_Polarity DSI HSYNC Polarity 738 * @{ 739 */ 740 #define DSI_HSYNC_ACTIVE_HIGH 0x00000000U 741 #define DSI_HSYNC_ACTIVE_LOW DSI_LPCR_HSP 742 /** 743 * @} 744 */ 745 746 /** @defgroup DSI_VSYNC_Active_Polarity DSI VSYNC Active Polarity 747 * @{ 748 */ 749 #define DSI_VSYNC_ACTIVE_HIGH 0x00000000U 750 #define DSI_VSYNC_ACTIVE_LOW DSI_LPCR_VSP 751 /** 752 * @} 753 */ 754 755 /** @defgroup DSI_DATA_ENABLE_Polarity DSI DATA ENABLE Polarity 756 * @{ 757 */ 758 #define DSI_DATA_ENABLE_ACTIVE_HIGH 0x00000000U 759 #define DSI_DATA_ENABLE_ACTIVE_LOW DSI_LPCR_DEP 760 /** 761 * @} 762 */ 763 764 /** @defgroup DSI_PLL_IDF DSI PLL IDF 765 * @{ 766 */ 767 #define DSI_PLL_IN_DIV1 0x00000001U 768 #define DSI_PLL_IN_DIV2 0x00000002U 769 #define DSI_PLL_IN_DIV3 0x00000003U 770 #define DSI_PLL_IN_DIV4 0x00000004U 771 #define DSI_PLL_IN_DIV5 0x00000005U 772 #define DSI_PLL_IN_DIV6 0x00000006U 773 #define DSI_PLL_IN_DIV7 0x00000007U 774 /** 775 * @} 776 */ 777 778 /** @defgroup DSI_PLL_ODF DSI PLL ODF 779 * @{ 780 */ 781 #define DSI_PLL_OUT_DIV1 0x00000000U 782 #define DSI_PLL_OUT_DIV2 0x00000001U 783 #define DSI_PLL_OUT_DIV4 0x00000002U 784 #define DSI_PLL_OUT_DIV8 0x00000003U 785 /** 786 * @} 787 */ 788 789 /** @defgroup DSI_Flags DSI Flags 790 * @{ 791 */ 792 #define DSI_FLAG_TE DSI_WISR_TEIF 793 #define DSI_FLAG_ER DSI_WISR_ERIF 794 #define DSI_FLAG_BUSY DSI_WISR_BUSY 795 #define DSI_FLAG_PLLLS DSI_WISR_PLLLS 796 #define DSI_FLAG_PLLL DSI_WISR_PLLLIF 797 #define DSI_FLAG_PLLU DSI_WISR_PLLUIF 798 #define DSI_FLAG_RRS DSI_WISR_RRS 799 #define DSI_FLAG_RR DSI_WISR_RRIF 800 /** 801 * @} 802 */ 803 804 /** @defgroup DSI_Interrupts DSI Interrupts 805 * @{ 806 */ 807 #define DSI_IT_TE DSI_WIER_TEIE 808 #define DSI_IT_ER DSI_WIER_ERIE 809 #define DSI_IT_PLLL DSI_WIER_PLLLIE 810 #define DSI_IT_PLLU DSI_WIER_PLLUIE 811 #define DSI_IT_RR DSI_WIER_RRIE 812 /** 813 * @} 814 */ 815 816 /** @defgroup DSI_SHORT_WRITE_PKT_Data_Type DSI SHORT WRITE PKT Data Type 817 * @{ 818 */ 819 #define DSI_DCS_SHORT_PKT_WRITE_P0 0x00000005U /*!< DCS short write, no parameters */ 820 #define DSI_DCS_SHORT_PKT_WRITE_P1 0x00000015U /*!< DCS short write, one parameter */ 821 #define DSI_GEN_SHORT_PKT_WRITE_P0 0x00000003U /*!< Generic short write, no parameters */ 822 #define DSI_GEN_SHORT_PKT_WRITE_P1 0x00000013U /*!< Generic short write, one parameter */ 823 #define DSI_GEN_SHORT_PKT_WRITE_P2 0x00000023U /*!< Generic short write, two parameters */ 824 /** 825 * @} 826 */ 827 828 /** @defgroup DSI_LONG_WRITE_PKT_Data_Type DSI LONG WRITE PKT Data Type 829 * @{ 830 */ 831 #define DSI_DCS_LONG_PKT_WRITE 0x00000039U /*!< DCS long write */ 832 #define DSI_GEN_LONG_PKT_WRITE 0x00000029U /*!< Generic long write */ 833 /** 834 * @} 835 */ 836 837 /** @defgroup DSI_SHORT_READ_PKT_Data_Type DSI SHORT READ PKT Data Type 838 * @{ 839 */ 840 #define DSI_DCS_SHORT_PKT_READ 0x00000006U /*!< DCS short read */ 841 #define DSI_GEN_SHORT_PKT_READ_P0 0x00000004U /*!< Generic short read, no parameters */ 842 #define DSI_GEN_SHORT_PKT_READ_P1 0x00000014U /*!< Generic short read, one parameter */ 843 #define DSI_GEN_SHORT_PKT_READ_P2 0x00000024U /*!< Generic short read, two parameters */ 844 /** 845 * @} 846 */ 847 848 /** @defgroup DSI_Error_Data_Type DSI Error Data Type 849 * @{ 850 */ 851 #define HAL_DSI_ERROR_NONE 0U 852 #define HAL_DSI_ERROR_ACK 0x00000001U /*!< acknowledge errors */ 853 #define HAL_DSI_ERROR_PHY 0x00000002U /*!< PHY related errors */ 854 #define HAL_DSI_ERROR_TX 0x00000004U /*!< transmission error */ 855 #define HAL_DSI_ERROR_RX 0x00000008U /*!< reception error */ 856 #define HAL_DSI_ERROR_ECC 0x00000010U /*!< ECC errors */ 857 #define HAL_DSI_ERROR_CRC 0x00000020U /*!< CRC error */ 858 #define HAL_DSI_ERROR_PSE 0x00000040U /*!< Packet Size error */ 859 #define HAL_DSI_ERROR_EOT 0x00000080U /*!< End Of Transmission error */ 860 #define HAL_DSI_ERROR_OVF 0x00000100U /*!< FIFO overflow error */ 861 #define HAL_DSI_ERROR_GEN 0x00000200U /*!< Generic FIFO related errors */ 862 #if (USE_HAL_DSI_REGISTER_CALLBACKS == 1) 863 #define HAL_DSI_ERROR_INVALID_CALLBACK 0x00000400U /*!< DSI Invalid Callback error */ 864 #endif /* USE_HAL_DSI_REGISTER_CALLBACKS */ 865 /** 866 * @} 867 */ 868 869 /** @defgroup DSI_Lane_Group DSI Lane Group 870 * @{ 871 */ 872 #define DSI_CLOCK_LANE 0x00000000U 873 #define DSI_DATA_LANES 0x00000001U 874 /** 875 * @} 876 */ 877 878 /** @defgroup DSI_Communication_Delay DSI Communication Delay 879 * @{ 880 */ 881 #define DSI_SLEW_RATE_HSTX 0x00000000U 882 #define DSI_SLEW_RATE_LPTX 0x00000001U 883 #define DSI_HS_DELAY 0x00000002U 884 /** 885 * @} 886 */ 887 888 /** @defgroup DSI_CustomLane DSI CustomLane 889 * @{ 890 */ 891 #define DSI_SWAP_LANE_PINS 0x00000000U 892 #define DSI_INVERT_HS_SIGNAL 0x00000001U 893 /** 894 * @} 895 */ 896 897 /** @defgroup DSI_Lane_Select DSI Lane Select 898 * @{ 899 */ 900 #define DSI_CLK_LANE 0x00000000U 901 #define DSI_DATA_LANE0 0x00000001U 902 #define DSI_DATA_LANE1 0x00000002U 903 /** 904 * @} 905 */ 906 907 /** @defgroup DSI_PHY_Timing DSI PHY Timing 908 * @{ 909 */ 910 #define DSI_TCLK_POST 0x00000000U 911 #define DSI_TLPX_CLK 0x00000001U 912 #define DSI_THS_EXIT 0x00000002U 913 #define DSI_TLPX_DATA 0x00000003U 914 #define DSI_THS_ZERO 0x00000004U 915 #define DSI_THS_TRAIL 0x00000005U 916 #define DSI_THS_PREPARE 0x00000006U 917 #define DSI_TCLK_ZERO 0x00000007U 918 #define DSI_TCLK_PREPARE 0x00000008U 919 /** 920 * @} 921 */ 922 923 /* Exported macros -----------------------------------------------------------*/ 924 /** 925 * @brief Reset DSI handle state. 926 * @param __HANDLE__: DSI handle 927 * @retval None 928 */ 929 #if (USE_HAL_DSI_REGISTER_CALLBACKS == 1) 930 #define __HAL_DSI_RESET_HANDLE_STATE(__HANDLE__) do{ \ 931 (__HANDLE__)->State = HAL_DSI_STATE_RESET; \ 932 (__HANDLE__)->MspInitCallback = NULL; \ 933 (__HANDLE__)->MspDeInitCallback = NULL; \ 934 } while(0) 935 #else 936 #define __HAL_DSI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DSI_STATE_RESET) 937 #endif /*USE_HAL_DSI_REGISTER_CALLBACKS */ 938 939 /** 940 * @brief Enables the DSI host. 941 * @param __HANDLE__ DSI handle 942 * @retval None. 943 */ 944 #define __HAL_DSI_ENABLE(__HANDLE__) do { \ 945 __IO uint32_t tmpreg = 0x00U; \ 946 SET_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\ 947 /* Delay after an DSI Host enabling */ \ 948 tmpreg = READ_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\ 949 UNUSED(tmpreg); \ 950 }while(0U) 951 952 /** 953 * @brief Disables the DSI host. 954 * @param __HANDLE__ DSI handle 955 * @retval None. 956 */ 957 #define __HAL_DSI_DISABLE(__HANDLE__) do { \ 958 __IO uint32_t tmpreg = 0x00U; \ 959 CLEAR_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\ 960 /* Delay after an DSI Host disabling */ \ 961 tmpreg = READ_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\ 962 UNUSED(tmpreg); \ 963 }while(0U) 964 965 /** 966 * @brief Enables the DSI wrapper. 967 * @param __HANDLE__ DSI handle 968 * @retval None. 969 */ 970 #define __HAL_DSI_WRAPPER_ENABLE(__HANDLE__) do { \ 971 __IO uint32_t tmpreg = 0x00U; \ 972 SET_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\ 973 /* Delay after an DSI warpper enabling */ \ 974 tmpreg = READ_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\ 975 UNUSED(tmpreg); \ 976 }while(0U) 977 978 /** 979 * @brief Disable the DSI wrapper. 980 * @param __HANDLE__ DSI handle 981 * @retval None. 982 */ 983 #define __HAL_DSI_WRAPPER_DISABLE(__HANDLE__) do { \ 984 __IO uint32_t tmpreg = 0x00U; \ 985 CLEAR_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\ 986 /* Delay after an DSI warpper disabling*/ \ 987 tmpreg = READ_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\ 988 UNUSED(tmpreg); \ 989 }while(0U) 990 991 /** 992 * @brief Enables the DSI PLL. 993 * @param __HANDLE__ DSI handle 994 * @retval None. 995 */ 996 #define __HAL_DSI_PLL_ENABLE(__HANDLE__) do { \ 997 __IO uint32_t tmpreg = 0x00U; \ 998 SET_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\ 999 /* Delay after an DSI PLL enabling */ \ 1000 tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\ 1001 UNUSED(tmpreg); \ 1002 }while(0U) 1003 1004 /** 1005 * @brief Disables the DSI PLL. 1006 * @param __HANDLE__ DSI handle 1007 * @retval None. 1008 */ 1009 #define __HAL_DSI_PLL_DISABLE(__HANDLE__) do { \ 1010 __IO uint32_t tmpreg = 0x00U; \ 1011 CLEAR_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\ 1012 /* Delay after an DSI PLL disabling */ \ 1013 tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\ 1014 UNUSED(tmpreg); \ 1015 }while(0U) 1016 1017 /** 1018 * @brief Enables the DSI regulator. 1019 * @param __HANDLE__ DSI handle 1020 * @retval None. 1021 */ 1022 #define __HAL_DSI_REG_ENABLE(__HANDLE__) do { \ 1023 __IO uint32_t tmpreg = 0x00U; \ 1024 SET_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\ 1025 /* Delay after an DSI regulator enabling */ \ 1026 tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\ 1027 UNUSED(tmpreg); \ 1028 }while(0U) 1029 1030 /** 1031 * @brief Disables the DSI regulator. 1032 * @param __HANDLE__ DSI handle 1033 * @retval None. 1034 */ 1035 #define __HAL_DSI_REG_DISABLE(__HANDLE__) do { \ 1036 __IO uint32_t tmpreg = 0x00U; \ 1037 CLEAR_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\ 1038 /* Delay after an DSI regulator disabling */ \ 1039 tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\ 1040 UNUSED(tmpreg); \ 1041 }while(0U) 1042 1043 /** 1044 * @brief Get the DSI pending flags. 1045 * @param __HANDLE__ DSI handle. 1046 * @param __FLAG__ Get the specified flag. 1047 * This parameter can be any combination of the following values: 1048 * @arg DSI_FLAG_TE : Tearing Effect Interrupt Flag 1049 * @arg DSI_FLAG_ER : End of Refresh Interrupt Flag 1050 * @arg DSI_FLAG_BUSY : Busy Flag 1051 * @arg DSI_FLAG_PLLLS: PLL Lock Status 1052 * @arg DSI_FLAG_PLLL : PLL Lock Interrupt Flag 1053 * @arg DSI_FLAG_PLLU : PLL Unlock Interrupt Flag 1054 * @arg DSI_FLAG_RRS : Regulator Ready Flag 1055 * @arg DSI_FLAG_RR : Regulator Ready Interrupt Flag 1056 * @retval The state of FLAG (SET or RESET). 1057 */ 1058 #define __HAL_DSI_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->WISR & (__FLAG__)) 1059 1060 /** 1061 * @brief Clears the DSI pending flags. 1062 * @param __HANDLE__ DSI handle. 1063 * @param __FLAG__ specifies the flag to clear. 1064 * This parameter can be any combination of the following values: 1065 * @arg DSI_FLAG_TE : Tearing Effect Interrupt Flag 1066 * @arg DSI_FLAG_ER : End of Refresh Interrupt Flag 1067 * @arg DSI_FLAG_PLLL : PLL Lock Interrupt Flag 1068 * @arg DSI_FLAG_PLLU : PLL Unlock Interrupt Flag 1069 * @arg DSI_FLAG_RR : Regulator Ready Interrupt Flag 1070 * @retval None 1071 */ 1072 #define __HAL_DSI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->WIFCR = (__FLAG__)) 1073 1074 /** 1075 * @brief Enables the specified DSI interrupts. 1076 * @param __HANDLE__ DSI handle. 1077 * @param __INTERRUPT__ specifies the DSI interrupt sources to be enabled. 1078 * This parameter can be any combination of the following values: 1079 * @arg DSI_IT_TE : Tearing Effect Interrupt 1080 * @arg DSI_IT_ER : End of Refresh Interrupt 1081 * @arg DSI_IT_PLLL: PLL Lock Interrupt 1082 * @arg DSI_IT_PLLU: PLL Unlock Interrupt 1083 * @arg DSI_IT_RR : Regulator Ready Interrupt 1084 * @retval None 1085 */ 1086 #define __HAL_DSI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->WIER |= (__INTERRUPT__)) 1087 1088 /** 1089 * @brief Disables the specified DSI interrupts. 1090 * @param __HANDLE__ DSI handle 1091 * @param __INTERRUPT__ specifies the DSI interrupt sources to be disabled. 1092 * This parameter can be any combination of the following values: 1093 * @arg DSI_IT_TE : Tearing Effect Interrupt 1094 * @arg DSI_IT_ER : End of Refresh Interrupt 1095 * @arg DSI_IT_PLLL: PLL Lock Interrupt 1096 * @arg DSI_IT_PLLU: PLL Unlock Interrupt 1097 * @arg DSI_IT_RR : Regulator Ready Interrupt 1098 * @retval None 1099 */ 1100 #define __HAL_DSI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->WIER &= ~(__INTERRUPT__)) 1101 1102 /** 1103 * @brief Checks whether the specified DSI interrupt source is enabled or not. 1104 * @param __HANDLE__ DSI handle 1105 * @param __INTERRUPT__ specifies the DSI interrupt source to check. 1106 * This parameter can be one of the following values: 1107 * @arg DSI_IT_TE : Tearing Effect Interrupt 1108 * @arg DSI_IT_ER : End of Refresh Interrupt 1109 * @arg DSI_IT_PLLL: PLL Lock Interrupt 1110 * @arg DSI_IT_PLLU: PLL Unlock Interrupt 1111 * @arg DSI_IT_RR : Regulator Ready Interrupt 1112 * @retval The state of INTERRUPT (SET or RESET). 1113 */ 1114 #define __HAL_DSI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->WIER & (__INTERRUPT__)) 1115 1116 /* Exported functions --------------------------------------------------------*/ 1117 /** @defgroup DSI_Exported_Functions DSI Exported Functions 1118 * @{ 1119 */ 1120 HAL_StatusTypeDef HAL_DSI_Init(DSI_HandleTypeDef *hdsi, DSI_PLLInitTypeDef *PLLInit); 1121 HAL_StatusTypeDef HAL_DSI_DeInit(DSI_HandleTypeDef *hdsi); 1122 void HAL_DSI_MspInit(DSI_HandleTypeDef *hdsi); 1123 void HAL_DSI_MspDeInit(DSI_HandleTypeDef *hdsi); 1124 1125 void HAL_DSI_IRQHandler(DSI_HandleTypeDef *hdsi); 1126 void HAL_DSI_TearingEffectCallback(DSI_HandleTypeDef *hdsi); 1127 void HAL_DSI_EndOfRefreshCallback(DSI_HandleTypeDef *hdsi); 1128 void HAL_DSI_ErrorCallback(DSI_HandleTypeDef *hdsi); 1129 1130 /* Callbacks Register/UnRegister functions ***********************************/ 1131 #if (USE_HAL_DSI_REGISTER_CALLBACKS == 1) 1132 HAL_StatusTypeDef HAL_DSI_RegisterCallback(DSI_HandleTypeDef *hdsi, HAL_DSI_CallbackIDTypeDef CallbackID, pDSI_CallbackTypeDef pCallback); 1133 HAL_StatusTypeDef HAL_DSI_UnRegisterCallback(DSI_HandleTypeDef *hdsi, HAL_DSI_CallbackIDTypeDef CallbackID); 1134 #endif /* USE_HAL_DSI_REGISTER_CALLBACKS */ 1135 1136 HAL_StatusTypeDef HAL_DSI_SetGenericVCID(DSI_HandleTypeDef *hdsi, uint32_t VirtualChannelID); 1137 HAL_StatusTypeDef HAL_DSI_ConfigVideoMode(DSI_HandleTypeDef *hdsi, DSI_VidCfgTypeDef *VidCfg); 1138 HAL_StatusTypeDef HAL_DSI_ConfigAdaptedCommandMode(DSI_HandleTypeDef *hdsi, DSI_CmdCfgTypeDef *CmdCfg); 1139 HAL_StatusTypeDef HAL_DSI_ConfigCommand(DSI_HandleTypeDef *hdsi, DSI_LPCmdTypeDef *LPCmd); 1140 HAL_StatusTypeDef HAL_DSI_ConfigFlowControl(DSI_HandleTypeDef *hdsi, uint32_t FlowControl); 1141 HAL_StatusTypeDef HAL_DSI_ConfigPhyTimer(DSI_HandleTypeDef *hdsi, DSI_PHY_TimerTypeDef *PhyTimers); 1142 HAL_StatusTypeDef HAL_DSI_ConfigHostTimeouts(DSI_HandleTypeDef *hdsi, DSI_HOST_TimeoutTypeDef *HostTimeouts); 1143 HAL_StatusTypeDef HAL_DSI_Start(DSI_HandleTypeDef *hdsi); 1144 HAL_StatusTypeDef HAL_DSI_Stop(DSI_HandleTypeDef *hdsi); 1145 HAL_StatusTypeDef HAL_DSI_Refresh(DSI_HandleTypeDef *hdsi); 1146 HAL_StatusTypeDef HAL_DSI_ColorMode(DSI_HandleTypeDef *hdsi, uint32_t ColorMode); 1147 HAL_StatusTypeDef HAL_DSI_Shutdown(DSI_HandleTypeDef *hdsi, uint32_t Shutdown); 1148 HAL_StatusTypeDef HAL_DSI_ShortWrite(DSI_HandleTypeDef *hdsi, 1149 uint32_t ChannelID, 1150 uint32_t Mode, 1151 uint32_t Param1, 1152 uint32_t Param2); 1153 HAL_StatusTypeDef HAL_DSI_LongWrite(DSI_HandleTypeDef *hdsi, 1154 uint32_t ChannelID, 1155 uint32_t Mode, 1156 uint32_t NbParams, 1157 uint32_t Param1, 1158 uint8_t* ParametersTable); 1159 HAL_StatusTypeDef HAL_DSI_Read(DSI_HandleTypeDef *hdsi, 1160 uint32_t ChannelNbr, 1161 uint8_t* Array, 1162 uint32_t Size, 1163 uint32_t Mode, 1164 uint32_t DCSCmd, 1165 uint8_t* ParametersTable); 1166 HAL_StatusTypeDef HAL_DSI_EnterULPMData(DSI_HandleTypeDef *hdsi); 1167 HAL_StatusTypeDef HAL_DSI_ExitULPMData(DSI_HandleTypeDef *hdsi); 1168 HAL_StatusTypeDef HAL_DSI_EnterULPM(DSI_HandleTypeDef *hdsi); 1169 HAL_StatusTypeDef HAL_DSI_ExitULPM(DSI_HandleTypeDef *hdsi); 1170 1171 HAL_StatusTypeDef HAL_DSI_PatternGeneratorStart(DSI_HandleTypeDef *hdsi, uint32_t Mode, uint32_t Orientation); 1172 HAL_StatusTypeDef HAL_DSI_PatternGeneratorStop(DSI_HandleTypeDef *hdsi); 1173 1174 HAL_StatusTypeDef HAL_DSI_SetSlewRateAndDelayTuning(DSI_HandleTypeDef *hdsi, uint32_t CommDelay, uint32_t Lane, uint32_t Value); 1175 HAL_StatusTypeDef HAL_DSI_SetLowPowerRXFilter(DSI_HandleTypeDef *hdsi, uint32_t Frequency); 1176 HAL_StatusTypeDef HAL_DSI_SetSDD(DSI_HandleTypeDef *hdsi, FunctionalState State); 1177 HAL_StatusTypeDef HAL_DSI_SetLanePinsConfiguration(DSI_HandleTypeDef *hdsi, uint32_t CustomLane, uint32_t Lane, FunctionalState State); 1178 HAL_StatusTypeDef HAL_DSI_SetPHYTimings(DSI_HandleTypeDef *hdsi, uint32_t Timing, FunctionalState State, uint32_t Value); 1179 HAL_StatusTypeDef HAL_DSI_ForceTXStopMode(DSI_HandleTypeDef *hdsi, uint32_t Lane, FunctionalState State); 1180 HAL_StatusTypeDef HAL_DSI_ForceRXLowPower(DSI_HandleTypeDef *hdsi, FunctionalState State); 1181 HAL_StatusTypeDef HAL_DSI_ForceDataLanesInRX(DSI_HandleTypeDef *hdsi, FunctionalState State); 1182 HAL_StatusTypeDef HAL_DSI_SetPullDown(DSI_HandleTypeDef *hdsi, FunctionalState State); 1183 HAL_StatusTypeDef HAL_DSI_SetContentionDetectionOff(DSI_HandleTypeDef *hdsi, FunctionalState State); 1184 1185 uint32_t HAL_DSI_GetError(DSI_HandleTypeDef *hdsi); 1186 HAL_StatusTypeDef HAL_DSI_ConfigErrorMonitor(DSI_HandleTypeDef *hdsi, uint32_t ActiveErrors); 1187 HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi); 1188 /** 1189 * @} 1190 */ 1191 1192 /* Private types -------------------------------------------------------------*/ 1193 /** @defgroup DSI_Private_Types DSI Private Types 1194 * @{ 1195 */ 1196 1197 /** 1198 * @} 1199 */ 1200 1201 /* Private defines -----------------------------------------------------------*/ 1202 /** @defgroup DSI_Private_Defines DSI Private Defines 1203 * @{ 1204 */ 1205 1206 /** 1207 * @} 1208 */ 1209 1210 /* Private variables ---------------------------------------------------------*/ 1211 /** @defgroup DSI_Private_Variables DSI Private Variables 1212 * @{ 1213 */ 1214 1215 /** 1216 * @} 1217 */ 1218 1219 /* Private constants ---------------------------------------------------------*/ 1220 /** @defgroup DSI_Private_Constants DSI Private Constants 1221 * @{ 1222 */ 1223 #define DSI_MAX_RETURN_PKT_SIZE (0x00000037U) /*!< Maximum return packet configuration */ 1224 /** 1225 * @} 1226 */ 1227 1228 /* Private macros ------------------------------------------------------------*/ 1229 /** @defgroup DSI_Private_Macros DSI Private Macros 1230 * @{ 1231 */ 1232 #define IS_DSI_PLL_NDIV(NDIV) ((10U <= (NDIV)) && ((NDIV) <= 125U)) 1233 #define IS_DSI_PLL_IDF(IDF) (((IDF) == DSI_PLL_IN_DIV1) || \ 1234 ((IDF) == DSI_PLL_IN_DIV2) || \ 1235 ((IDF) == DSI_PLL_IN_DIV3) || \ 1236 ((IDF) == DSI_PLL_IN_DIV4) || \ 1237 ((IDF) == DSI_PLL_IN_DIV5) || \ 1238 ((IDF) == DSI_PLL_IN_DIV6) || \ 1239 ((IDF) == DSI_PLL_IN_DIV7)) 1240 #define IS_DSI_PLL_ODF(ODF) (((ODF) == DSI_PLL_OUT_DIV1) || \ 1241 ((ODF) == DSI_PLL_OUT_DIV2) || \ 1242 ((ODF) == DSI_PLL_OUT_DIV4) || \ 1243 ((ODF) == DSI_PLL_OUT_DIV8)) 1244 #define IS_DSI_AUTO_CLKLANE_CONTROL(AutoClkLane) (((AutoClkLane) == DSI_AUTO_CLK_LANE_CTRL_DISABLE) || ((AutoClkLane) == DSI_AUTO_CLK_LANE_CTRL_ENABLE)) 1245 #define IS_DSI_NUMBER_OF_LANES(NumberOfLanes) (((NumberOfLanes) == DSI_ONE_DATA_LANE) || ((NumberOfLanes) == DSI_TWO_DATA_LANES)) 1246 #define IS_DSI_FLOW_CONTROL(FlowControl) (((FlowControl) | DSI_FLOW_CONTROL_ALL) == DSI_FLOW_CONTROL_ALL) 1247 #define IS_DSI_COLOR_CODING(ColorCoding) ((ColorCoding) <= 5U) 1248 #define IS_DSI_LOOSELY_PACKED(LooselyPacked) (((LooselyPacked) == DSI_LOOSELY_PACKED_ENABLE) || ((LooselyPacked) == DSI_LOOSELY_PACKED_DISABLE)) 1249 #define IS_DSI_DE_POLARITY(DataEnable) (((DataEnable) == DSI_DATA_ENABLE_ACTIVE_HIGH) || ((DataEnable) == DSI_DATA_ENABLE_ACTIVE_LOW)) 1250 #define IS_DSI_VSYNC_POLARITY(VSYNC) (((VSYNC) == DSI_VSYNC_ACTIVE_HIGH) || ((VSYNC) == DSI_VSYNC_ACTIVE_LOW)) 1251 #define IS_DSI_HSYNC_POLARITY(HSYNC) (((HSYNC) == DSI_HSYNC_ACTIVE_HIGH) || ((HSYNC) == DSI_HSYNC_ACTIVE_LOW)) 1252 #define IS_DSI_VIDEO_MODE_TYPE(VideoModeType) (((VideoModeType) == DSI_VID_MODE_NB_PULSES) || \ 1253 ((VideoModeType) == DSI_VID_MODE_NB_EVENTS) || \ 1254 ((VideoModeType) == DSI_VID_MODE_BURST)) 1255 #define IS_DSI_COLOR_MODE(ColorMode) (((ColorMode) == DSI_COLOR_MODE_FULL) || ((ColorMode) == DSI_COLOR_MODE_EIGHT)) 1256 #define IS_DSI_SHUT_DOWN(ShutDown) (((ShutDown) == DSI_DISPLAY_ON) || ((ShutDown) == DSI_DISPLAY_OFF)) 1257 #define IS_DSI_LP_COMMAND(LPCommand) (((LPCommand) == DSI_LP_COMMAND_DISABLE) || ((LPCommand) == DSI_LP_COMMAND_ENABLE)) 1258 #define IS_DSI_LP_HFP(LPHFP) (((LPHFP) == DSI_LP_HFP_DISABLE) || ((LPHFP) == DSI_LP_HFP_ENABLE)) 1259 #define IS_DSI_LP_HBP(LPHBP) (((LPHBP) == DSI_LP_HBP_DISABLE) || ((LPHBP) == DSI_LP_HBP_ENABLE)) 1260 #define IS_DSI_LP_VACTIVE(LPVActive) (((LPVActive) == DSI_LP_VACT_DISABLE) || ((LPVActive) == DSI_LP_VACT_ENABLE)) 1261 #define IS_DSI_LP_VFP(LPVFP) (((LPVFP) == DSI_LP_VFP_DISABLE) || ((LPVFP) == DSI_LP_VFP_ENABLE)) 1262 #define IS_DSI_LP_VBP(LPVBP) (((LPVBP) == DSI_LP_VBP_DISABLE) || ((LPVBP) == DSI_LP_VBP_ENABLE)) 1263 #define IS_DSI_LP_VSYNC(LPVSYNC) (((LPVSYNC) == DSI_LP_VSYNC_DISABLE) || ((LPVSYNC) == DSI_LP_VSYNC_ENABLE)) 1264 #define IS_DSI_FBTAA(FrameBTAAcknowledge) (((FrameBTAAcknowledge) == DSI_FBTAA_DISABLE) || ((FrameBTAAcknowledge) == DSI_FBTAA_ENABLE)) 1265 #define IS_DSI_TE_SOURCE(TESource) (((TESource) == DSI_TE_DSILINK) || ((TESource) == DSI_TE_EXTERNAL)) 1266 #define IS_DSI_TE_POLARITY(TEPolarity) (((TEPolarity) == DSI_TE_RISING_EDGE) || ((TEPolarity) == DSI_TE_FALLING_EDGE)) 1267 #define IS_DSI_AUTOMATIC_REFRESH(AutomaticRefresh) (((AutomaticRefresh) == DSI_AR_DISABLE) || ((AutomaticRefresh) == DSI_AR_ENABLE)) 1268 #define IS_DSI_VS_POLARITY(VSPolarity) (((VSPolarity) == DSI_VSYNC_FALLING) || ((VSPolarity) == DSI_VSYNC_RISING)) 1269 #define IS_DSI_TE_ACK_REQUEST(TEAcknowledgeRequest) (((TEAcknowledgeRequest) == DSI_TE_ACKNOWLEDGE_DISABLE) || ((TEAcknowledgeRequest) == DSI_TE_ACKNOWLEDGE_ENABLE)) 1270 #define IS_DSI_ACK_REQUEST(AcknowledgeRequest) (((AcknowledgeRequest) == DSI_ACKNOWLEDGE_DISABLE) || ((AcknowledgeRequest) == DSI_ACKNOWLEDGE_ENABLE)) 1271 #define IS_DSI_LP_GSW0P(LP_GSW0P) (((LP_GSW0P) == DSI_LP_GSW0P_DISABLE) || ((LP_GSW0P) == DSI_LP_GSW0P_ENABLE)) 1272 #define IS_DSI_LP_GSW1P(LP_GSW1P) (((LP_GSW1P) == DSI_LP_GSW1P_DISABLE) || ((LP_GSW1P) == DSI_LP_GSW1P_ENABLE)) 1273 #define IS_DSI_LP_GSW2P(LP_GSW2P) (((LP_GSW2P) == DSI_LP_GSW2P_DISABLE) || ((LP_GSW2P) == DSI_LP_GSW2P_ENABLE)) 1274 #define IS_DSI_LP_GSR0P(LP_GSR0P) (((LP_GSR0P) == DSI_LP_GSR0P_DISABLE) || ((LP_GSR0P) == DSI_LP_GSR0P_ENABLE)) 1275 #define IS_DSI_LP_GSR1P(LP_GSR1P) (((LP_GSR1P) == DSI_LP_GSR1P_DISABLE) || ((LP_GSR1P) == DSI_LP_GSR1P_ENABLE)) 1276 #define IS_DSI_LP_GSR2P(LP_GSR2P) (((LP_GSR2P) == DSI_LP_GSR2P_DISABLE) || ((LP_GSR2P) == DSI_LP_GSR2P_ENABLE)) 1277 #define IS_DSI_LP_GLW(LP_GLW) (((LP_GLW) == DSI_LP_GLW_DISABLE) || ((LP_GLW) == DSI_LP_GLW_ENABLE)) 1278 #define IS_DSI_LP_DSW0P(LP_DSW0P) (((LP_DSW0P) == DSI_LP_DSW0P_DISABLE) || ((LP_DSW0P) == DSI_LP_DSW0P_ENABLE)) 1279 #define IS_DSI_LP_DSW1P(LP_DSW1P) (((LP_DSW1P) == DSI_LP_DSW1P_DISABLE) || ((LP_DSW1P) == DSI_LP_DSW1P_ENABLE)) 1280 #define IS_DSI_LP_DSR0P(LP_DSR0P) (((LP_DSR0P) == DSI_LP_DSR0P_DISABLE) || ((LP_DSR0P) == DSI_LP_DSR0P_ENABLE)) 1281 #define IS_DSI_LP_DLW(LP_DLW) (((LP_DLW) == DSI_LP_DLW_DISABLE) || ((LP_DLW) == DSI_LP_DLW_ENABLE)) 1282 #define IS_DSI_LP_MRDP(LP_MRDP) (((LP_MRDP) == DSI_LP_MRDP_DISABLE) || ((LP_MRDP) == DSI_LP_MRDP_ENABLE)) 1283 #define IS_DSI_SHORT_WRITE_PACKET_TYPE(MODE) (((MODE) == DSI_DCS_SHORT_PKT_WRITE_P0) || \ 1284 ((MODE) == DSI_DCS_SHORT_PKT_WRITE_P1) || \ 1285 ((MODE) == DSI_GEN_SHORT_PKT_WRITE_P0) || \ 1286 ((MODE) == DSI_GEN_SHORT_PKT_WRITE_P1) || \ 1287 ((MODE) == DSI_GEN_SHORT_PKT_WRITE_P2)) 1288 #define IS_DSI_LONG_WRITE_PACKET_TYPE(MODE) (((MODE) == DSI_DCS_LONG_PKT_WRITE) || \ 1289 ((MODE) == DSI_GEN_LONG_PKT_WRITE)) 1290 #define IS_DSI_READ_PACKET_TYPE(MODE) (((MODE) == DSI_DCS_SHORT_PKT_READ) || \ 1291 ((MODE) == DSI_GEN_SHORT_PKT_READ_P0) || \ 1292 ((MODE) == DSI_GEN_SHORT_PKT_READ_P1) || \ 1293 ((MODE) == DSI_GEN_SHORT_PKT_READ_P2)) 1294 #define IS_DSI_COMMUNICATION_DELAY(CommDelay) (((CommDelay) == DSI_SLEW_RATE_HSTX) || ((CommDelay) == DSI_SLEW_RATE_LPTX) || ((CommDelay) == DSI_HS_DELAY)) 1295 #define IS_DSI_LANE_GROUP(Lane) (((Lane) == DSI_CLOCK_LANE) || ((Lane) == DSI_DATA_LANES)) 1296 #define IS_DSI_CUSTOM_LANE(CustomLane) (((CustomLane) == DSI_SWAP_LANE_PINS) || ((CustomLane) == DSI_INVERT_HS_SIGNAL)) 1297 #define IS_DSI_LANE(Lane) (((Lane) == DSI_CLOCK_LANE) || ((Lane) == DSI_DATA_LANE0) || ((Lane) == DSI_DATA_LANE1)) 1298 #define IS_DSI_PHY_TIMING(Timing) (((Timing) == DSI_TCLK_POST ) || \ 1299 ((Timing) == DSI_TLPX_CLK ) || \ 1300 ((Timing) == DSI_THS_EXIT ) || \ 1301 ((Timing) == DSI_TLPX_DATA ) || \ 1302 ((Timing) == DSI_THS_ZERO ) || \ 1303 ((Timing) == DSI_THS_TRAIL ) || \ 1304 ((Timing) == DSI_THS_PREPARE ) || \ 1305 ((Timing) == DSI_TCLK_ZERO ) || \ 1306 ((Timing) == DSI_TCLK_PREPARE)) 1307 1308 /** 1309 * @} 1310 */ 1311 1312 /* Private functions prototypes ----------------------------------------------*/ 1313 /** @defgroup DSI_Private_Functions_Prototypes DSI Private Functions Prototypes 1314 * @{ 1315 */ 1316 1317 /** 1318 * @} 1319 */ 1320 1321 /* Private functions ---------------------------------------------------------*/ 1322 /** @defgroup DSI_Private_Functions DSI Private Functions 1323 * @{ 1324 */ 1325 1326 /** 1327 * @} 1328 */ 1329 1330 /** 1331 * @} 1332 */ 1333 1334 /** 1335 * @} 1336 */ 1337 #endif /* DSI */ 1338 1339 #ifdef __cplusplus 1340 } 1341 #endif 1342 1343 #endif /* STM32L4xx_HAL_DSI_H */ 1344 1345 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 1346
