1 /* 2 * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #define DR_REG_UART_BASE 0x60000000 7 #define DR_REG_SPI1_BASE 0x60002000 8 #define DR_REG_SPI0_BASE 0x60003000 9 #define DR_REG_GPIO_BASE 0x60004000 10 #define DR_REG_GPIO_SD_BASE 0x60004f00 11 #define DR_REG_FE2_BASE 0x60005000 12 #define DR_REG_FE_BASE 0x60006000 13 #define DR_REG_EFUSE_BASE 0x60007000 14 #define DR_REG_RTCCNTL_BASE 0x60008000 15 #define DR_REG_RTCIO_BASE 0x60008400 16 #define DR_REG_SENS_BASE 0x60008800 17 #define DR_REG_RTC_I2C_BASE 0x60008C00 18 #define DR_REG_IO_MUX_BASE 0x60009000 19 #define DR_REG_HINF_BASE 0x6000B000 20 #define DR_REG_UHCI1_BASE 0x6000C000 21 #define DR_REG_I2S_BASE 0x6000F000 22 #define DR_REG_UART1_BASE 0x60010000 23 #define DR_REG_BT_BASE 0x60011000 24 #define DR_REG_I2C_EXT_BASE 0x60013000 25 #define DR_REG_UHCI0_BASE 0x60014000 26 #define DR_REG_SLCHOST_BASE 0x60015000 27 #define DR_REG_RMT_BASE 0x60016000 28 #define DR_REG_PCNT_BASE 0x60017000 29 #define DR_REG_SLC_BASE 0x60018000 30 #define DR_REG_LEDC_BASE 0x60019000 31 #define DR_REG_NRX_BASE 0x6001CC00 32 #define DR_REG_BB_BASE 0x6001D000 33 #define DR_REG_PWM0_BASE 0x6001E000 34 #define DR_REG_TIMERGROUP0_BASE 0x6001F000 35 #define DR_REG_TIMERGROUP1_BASE 0x60020000 36 #define DR_REG_RTC_SLOWMEM_BASE 0x60021000 37 #define DR_REG_SYSTIMER_BASE 0x60023000 38 #define DR_REG_SPI2_BASE 0x60024000 39 #define DR_REG_SPI3_BASE 0x60025000 40 #define DR_REG_SYSCON_BASE 0x60026000 41 #define DR_REG_APB_CTRL_BASE 0x60026000 /* Old name for SYSCON, to be removed */ 42 #define DR_REG_I2C1_EXT_BASE 0x60027000 43 #define DR_REG_SDMMC_BASE 0x60028000 44 #define DR_REG_PERI_BACKUP_BASE 0x6002A000 45 #define DR_REG_TWAI_BASE 0x6002B000 46 #define DR_REG_PWM1_BASE 0x6002C000 47 #define DR_REG_I2S1_BASE 0x6002D000 48 #define DR_REG_UART2_BASE 0x6002E000 49 #define DR_REG_USB_SERIAL_JTAG_BASE 0x60038000 50 #define DR_REG_USB_WRAP_BASE 0x60039000 51 #define DR_REG_AES_BASE 0x6003A000 52 #define DR_REG_SHA_BASE 0x6003B000 53 #define DR_REG_RSA_BASE 0x6003C000 54 #define DR_REG_HMAC_BASE 0x6003E000 55 #define DR_REG_DIGITAL_SIGNATURE_BASE 0x6003D000 56 #define DR_REG_GDMA_BASE 0x6003F000 57 #define DR_REG_APB_SARADC_BASE 0x60040000 58 #define DR_REG_LCD_CAM_BASE 0x60041000 59 #define DR_REG_SYSTEM_BASE 0x600C0000 60 #define DR_REG_SENSITIVE_BASE 0x600C1000 61 #define DR_REG_INTERRUPT_BASE 0x600C2000 62 #define DR_REG_EXTMEM_BASE 0x600C4000 63 #define DR_REG_ASSIST_DEBUG_BASE 0x600CE000 64 #define DR_REG_WCL_BASE 0x600D0000 65
