1 // Copyright 2010-2019 Espressif Systems (Shanghai) PTE LTD 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 // 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 15 #pragma once 16 17 #ifndef __ASSEMBLER__ 18 #include <stdint.h> 19 #include "esp_assert.h" 20 #endif 21 22 #include <esp_bit_defs.h> 23 24 #define PRO_CPU_NUM (0) 25 #define APP_CPU_NUM (1) 26 27 28 #define SOC_MAX_CONTIGUOUS_RAM_SIZE 0x400000 ///< Largest span of contiguous memory (DRAM or IRAM) in the address space 29 30 31 #define DR_REG_DPORT_BASE 0x3ff00000 32 #define DR_REG_AES_BASE 0x3ff01000 33 #define DR_REG_RSA_BASE 0x3ff02000 34 #define DR_REG_SHA_BASE 0x3ff03000 35 #define DR_REG_FLASH_MMU_TABLE_PRO 0x3ff10000 36 #define DR_REG_FLASH_MMU_TABLE_APP 0x3ff12000 37 #define DR_REG_DPORT_END 0x3ff13FFC 38 #define DR_REG_UART_BASE 0x3ff40000 39 #define DR_REG_SPI1_BASE 0x3ff42000 40 #define DR_REG_SPI0_BASE 0x3ff43000 41 #define DR_REG_GPIO_BASE 0x3ff44000 42 #define DR_REG_GPIO_SD_BASE 0x3ff44f00 43 #define DR_REG_FE2_BASE 0x3ff45000 44 #define DR_REG_FE_BASE 0x3ff46000 45 #define DR_REG_FRC_TIMER_BASE 0x3ff47000 46 #define DR_REG_RTCCNTL_BASE 0x3ff48000 47 #define DR_REG_RTCIO_BASE 0x3ff48400 48 #define DR_REG_SENS_BASE 0x3ff48800 49 #define DR_REG_RTC_I2C_BASE 0x3ff48C00 50 #define DR_REG_IO_MUX_BASE 0x3ff49000 51 #define DR_REG_HINF_BASE 0x3ff4B000 52 #define DR_REG_UHCI1_BASE 0x3ff4C000 53 #define DR_REG_I2S_BASE 0x3ff4F000 54 #define DR_REG_UART1_BASE 0x3ff50000 55 #define DR_REG_BT_BASE 0x3ff51000 56 #define DR_REG_I2C_EXT_BASE 0x3ff53000 57 #define DR_REG_UHCI0_BASE 0x3ff54000 58 #define DR_REG_SLCHOST_BASE 0x3ff55000 59 #define DR_REG_RMT_BASE 0x3ff56000 60 #define DR_REG_PCNT_BASE 0x3ff57000 61 #define DR_REG_SLC_BASE 0x3ff58000 62 #define DR_REG_LEDC_BASE 0x3ff59000 63 #define DR_REG_EFUSE_BASE 0x3ff5A000 64 #define DR_REG_SPI_ENCRYPT_BASE 0x3ff5B000 65 #define DR_REG_NRX_BASE 0x3ff5CC00 66 #define DR_REG_BB_BASE 0x3ff5D000 67 #define DR_REG_PWM_BASE 0x3ff5E000 68 #define DR_REG_TIMERGROUP0_BASE 0x3ff5F000 69 #define DR_REG_TIMERGROUP1_BASE 0x3ff60000 70 #define DR_REG_RTCMEM0_BASE 0x3ff61000 71 #define DR_REG_RTCMEM1_BASE 0x3ff62000 72 #define DR_REG_RTCMEM2_BASE 0x3ff63000 73 #define DR_REG_SPI2_BASE 0x3ff64000 74 #define DR_REG_SPI3_BASE 0x3ff65000 75 #define DR_REG_SYSCON_BASE 0x3ff66000 76 #define DR_REG_APB_CTRL_BASE 0x3ff66000 /* Old name for SYSCON, to be removed */ 77 #define DR_REG_I2C1_EXT_BASE 0x3ff67000 78 #define DR_REG_SDMMC_BASE 0x3ff68000 79 #define DR_REG_EMAC_BASE 0x3ff69000 80 #define DR_REG_CAN_BASE 0x3ff6B000 81 #define DR_REG_PWM1_BASE 0x3ff6C000 82 #define DR_REG_I2S1_BASE 0x3ff6D000 83 #define DR_REG_UART2_BASE 0x3ff6E000 84 #define DR_REG_PWM2_BASE 0x3ff6F000 85 #define DR_REG_PWM3_BASE 0x3ff70000 86 #define PERIPHS_SPI_ENCRYPT_BASEADDR DR_REG_SPI_ENCRYPT_BASE 87 88 //Registers Operation {{ 89 #define ETS_UNCACHED_ADDR(addr) (addr) 90 #define ETS_CACHED_ADDR(addr) (addr) 91 92 93 #ifndef __ASSEMBLER__ 94 95 #define IS_DPORT_REG(_r) (((_r) >= DR_REG_DPORT_BASE) && (_r) <= DR_REG_DPORT_END) 96 97 #if !defined( BOOTLOADER_BUILD ) && defined( CONFIG_ESP32_DPORT_WORKAROUND ) && defined( ESP_PLATFORM ) 98 #define ASSERT_IF_DPORT_REG(_r, OP) TRY_STATIC_ASSERT(!IS_DPORT_REG(_r), (Cannot use OP for DPORT registers use DPORT_##OP)); 99 #else 100 #define ASSERT_IF_DPORT_REG(_r, OP) 101 #endif 102 103 //write value to register 104 #define REG_WRITE(_r, _v) ({ \ 105 ASSERT_IF_DPORT_REG((_r), REG_WRITE); \ 106 (*(volatile uint32_t *)(_r)) = (_v); \ 107 }) 108 109 //read value from register 110 #define REG_READ(_r) ({ \ 111 ASSERT_IF_DPORT_REG((_r), REG_READ); \ 112 (*(volatile uint32_t *)(_r)); \ 113 }) 114 115 //get bit or get bits from register 116 #define REG_GET_BIT(_r, _b) ({ \ 117 ASSERT_IF_DPORT_REG((_r), REG_GET_BIT); \ 118 (*(volatile uint32_t*)(_r) & (_b)); \ 119 }) 120 121 //set bit or set bits to register 122 #define REG_SET_BIT(_r, _b) ({ \ 123 ASSERT_IF_DPORT_REG((_r), REG_SET_BIT); \ 124 (*(volatile uint32_t*)(_r) |= (_b)); \ 125 }) 126 127 //clear bit or clear bits of register 128 #define REG_CLR_BIT(_r, _b) ({ \ 129 ASSERT_IF_DPORT_REG((_r), REG_CLR_BIT); \ 130 (*(volatile uint32_t*)(_r) &= ~(_b)); \ 131 }) 132 133 //set bits of register controlled by mask 134 #define REG_SET_BITS(_r, _b, _m) ({ \ 135 ASSERT_IF_DPORT_REG((_r), REG_SET_BITS); \ 136 (*(volatile uint32_t*)(_r) = (*(volatile uint32_t*)(_r) & ~(_m)) | ((_b) & (_m))); \ 137 }) 138 139 //get field from register, uses field _S & _V to determine mask 140 #define REG_GET_FIELD(_r, _f) ({ \ 141 ASSERT_IF_DPORT_REG((_r), REG_GET_FIELD); \ 142 ((REG_READ(_r) >> (_f##_S)) & (_f##_V)); \ 143 }) 144 145 //set field of a register from variable, uses field _S & _V to determine mask 146 #define REG_SET_FIELD(_r, _f, _v) ({ \ 147 ASSERT_IF_DPORT_REG((_r), REG_SET_FIELD); \ 148 (REG_WRITE((_r),((REG_READ(_r) & ~((_f##_V) << (_f##_S)))|(((_v) & (_f##_V))<<(_f##_S))))); \ 149 }) 150 151 //get field value from a variable, used when _f is not left shifted by _f##_S 152 #define VALUE_GET_FIELD(_r, _f) (((_r) >> (_f##_S)) & (_f)) 153 154 //get field value from a variable, used when _f is left shifted by _f##_S 155 #define VALUE_GET_FIELD2(_r, _f) (((_r) & (_f))>> (_f##_S)) 156 157 //set field value to a variable, used when _f is not left shifted by _f##_S 158 #define VALUE_SET_FIELD(_r, _f, _v) ((_r)=(((_r) & ~((_f) << (_f##_S)))|((_v)<<(_f##_S)))) 159 160 //set field value to a variable, used when _f is left shifted by _f##_S 161 #define VALUE_SET_FIELD2(_r, _f, _v) ((_r)=(((_r) & ~(_f))|((_v)<<(_f##_S)))) 162 163 //generate a value from a field value, used when _f is not left shifted by _f##_S 164 #define FIELD_TO_VALUE(_f, _v) (((_v)&(_f))<<_f##_S) 165 166 //generate a value from a field value, used when _f is left shifted by _f##_S 167 #define FIELD_TO_VALUE2(_f, _v) (((_v)<<_f##_S) & (_f)) 168 169 //read value from register 170 #define READ_PERI_REG(addr) ({ \ 171 ASSERT_IF_DPORT_REG((addr), READ_PERI_REG); \ 172 (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))); \ 173 }) 174 175 //write value to register 176 #define WRITE_PERI_REG(addr, val) ({ \ 177 ASSERT_IF_DPORT_REG((addr), WRITE_PERI_REG); \ 178 (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))) = (uint32_t)(val); \ 179 }) 180 181 //clear bits of register controlled by mask 182 #define CLEAR_PERI_REG_MASK(reg, mask) ({ \ 183 ASSERT_IF_DPORT_REG((reg), CLEAR_PERI_REG_MASK); \ 184 WRITE_PERI_REG((reg), (READ_PERI_REG(reg)&(~(mask)))); \ 185 }) 186 187 //set bits of register controlled by mask 188 #define SET_PERI_REG_MASK(reg, mask) ({ \ 189 ASSERT_IF_DPORT_REG((reg), SET_PERI_REG_MASK); \ 190 WRITE_PERI_REG((reg), (READ_PERI_REG(reg)|(mask))); \ 191 }) 192 193 //get bits of register controlled by mask 194 #define GET_PERI_REG_MASK(reg, mask) ({ \ 195 ASSERT_IF_DPORT_REG((reg), GET_PERI_REG_MASK); \ 196 (READ_PERI_REG(reg) & (mask)); \ 197 }) 198 199 //get bits of register controlled by highest bit and lowest bit 200 #define GET_PERI_REG_BITS(reg, hipos,lowpos) ({ \ 201 ASSERT_IF_DPORT_REG((reg), GET_PERI_REG_BITS); \ 202 ((READ_PERI_REG(reg)>>(lowpos))&((1<<((hipos)-(lowpos)+1))-1)); \ 203 }) 204 205 //set bits of register controlled by mask and shift 206 #define SET_PERI_REG_BITS(reg,bit_map,value,shift) ({ \ 207 ASSERT_IF_DPORT_REG((reg), SET_PERI_REG_BITS); \ 208 (WRITE_PERI_REG((reg),(READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & bit_map)<<(shift)) )); \ 209 }) 210 211 //get field of register 212 #define GET_PERI_REG_BITS2(reg, mask,shift) ({ \ 213 ASSERT_IF_DPORT_REG((reg), GET_PERI_REG_BITS2); \ 214 ((READ_PERI_REG(reg)>>(shift))&(mask)); \ 215 }) 216 217 #endif /* !__ASSEMBLER__ */ 218 //}} 219 220 //Periheral Clock {{ 221 #define APB_CLK_FREQ_ROM ( 26*1000000 ) 222 #define CPU_CLK_FREQ_ROM APB_CLK_FREQ_ROM 223 #define CPU_CLK_FREQ APB_CLK_FREQ //this may be incorrect, please refer to ESP32_DEFAULT_CPU_FREQ_MHZ 224 #define APB_CLK_FREQ ( 80*1000000 ) //unit: Hz 225 #define REF_CLK_FREQ ( 1000000 ) 226 #define UART_CLK_FREQ APB_CLK_FREQ 227 #define WDT_CLK_FREQ APB_CLK_FREQ 228 #define TIMER_CLK_FREQ (80000000>>4) //80MHz divided by 16 229 #define SPI_CLK_DIV 4 230 #define TICKS_PER_US_ROM 26 // CPU is 80MHz 231 #define GPIO_MATRIX_DELAY_NS 25 232 //}} 233 234 /* Overall memory map */ 235 #define SOC_DROM_LOW 0x3F400000 236 #define SOC_DROM_HIGH 0x3F800000 237 #define SOC_DRAM_LOW 0x3FFAE000 238 #define SOC_DRAM_HIGH 0x40000000 239 #define SOC_IROM_LOW 0x400D0000 240 #define SOC_IROM_HIGH 0x40400000 241 #define SOC_IROM_MASK_LOW 0x40000000 242 #define SOC_IROM_MASK_HIGH 0x40064F00 243 #define SOC_CACHE_PRO_LOW 0x40070000 244 #define SOC_CACHE_PRO_HIGH 0x40078000 245 #define SOC_CACHE_APP_LOW 0x40078000 246 #define SOC_CACHE_APP_HIGH 0x40080000 247 #define SOC_IRAM_LOW 0x40080000 248 #define SOC_IRAM_HIGH 0x400A0000 249 #define SOC_RTC_IRAM_LOW 0x400C0000 250 #define SOC_RTC_IRAM_HIGH 0x400C2000 251 #define SOC_RTC_DRAM_LOW 0x3FF80000 252 #define SOC_RTC_DRAM_HIGH 0x3FF82000 253 #define SOC_RTC_DATA_LOW 0x50000000 254 #define SOC_RTC_DATA_HIGH 0x50002000 255 #define SOC_EXTRAM_DATA_LOW 0x3F800000 256 #define SOC_EXTRAM_DATA_HIGH 0x3FC00000 257 258 #define SOC_EXTRAM_DATA_SIZE (SOC_EXTRAM_DATA_HIGH - SOC_EXTRAM_DATA_LOW) 259 260 //First and last words of the D/IRAM region, for both the DRAM address as well as the IRAM alias. 261 #define SOC_DIRAM_IRAM_LOW 0x400A0000 262 #define SOC_DIRAM_IRAM_HIGH 0x400C0000 263 #define SOC_DIRAM_DRAM_LOW 0x3FFE0000 264 #define SOC_DIRAM_DRAM_HIGH 0x40000000 265 // Byte order of D/IRAM regions is reversed between accessing as DRAM or IRAM 266 #define SOC_DIRAM_INVERTED 1 267 268 // Region of memory accessible via DMA. See esp_ptr_dma_capable(). 269 #define SOC_DMA_LOW 0x3FFAE000 270 #define SOC_DMA_HIGH 0x40000000 271 272 // Region of memory that is byte-accessible. See esp_ptr_byte_accessible(). 273 #define SOC_BYTE_ACCESSIBLE_LOW 0x3FF90000 274 #define SOC_BYTE_ACCESSIBLE_HIGH 0x40000000 275 276 //Region of memory that is internal, as in on the same silicon die as the ESP32 CPUs 277 //(excluding RTC data region, that's checked separately.) See esp_ptr_internal(). 278 #define SOC_MEM_INTERNAL_LOW 0x3FF90000 279 #define SOC_MEM_INTERNAL_HIGH 0x400C2000 280 281 // Start (highest address) of ROM boot stack, only relevant during early boot 282 #define SOC_ROM_STACK_START 0x3ffe3f20 283 284 //Interrupt hardware source table 285 //This table is decided by hardware, don't touch this. 286 #define ETS_WIFI_MAC_INTR_SOURCE 0/**< interrupt of WiFi MAC, level*/ 287 #define ETS_WIFI_MAC_NMI_SOURCE 1/**< interrupt of WiFi MAC, NMI, use if MAC have bug to fix in NMI*/ 288 #define ETS_WIFI_BB_INTR_SOURCE 2/**< interrupt of WiFi BB, level, we can do some calibartion*/ 289 #define ETS_BT_MAC_INTR_SOURCE 3/**< will be cancelled*/ 290 #define ETS_BT_BB_INTR_SOURCE 4/**< interrupt of BT BB, level*/ 291 #define ETS_BT_BB_NMI_SOURCE 5/**< interrupt of BT BB, NMI, use if BB have bug to fix in NMI*/ 292 #define ETS_RWBT_INTR_SOURCE 6/**< interrupt of RWBT, level*/ 293 #define ETS_RWBLE_INTR_SOURCE 7/**< interrupt of RWBLE, level*/ 294 #define ETS_RWBT_NMI_SOURCE 8/**< interrupt of RWBT, NMI, use if RWBT have bug to fix in NMI*/ 295 #define ETS_RWBLE_NMI_SOURCE 9/**< interrupt of RWBLE, NMI, use if RWBT have bug to fix in NMI*/ 296 #define ETS_SLC0_INTR_SOURCE 10/**< interrupt of SLC0, level*/ 297 #define ETS_SLC1_INTR_SOURCE 11/**< interrupt of SLC1, level*/ 298 #define ETS_UHCI0_INTR_SOURCE 12/**< interrupt of UHCI0, level*/ 299 #define ETS_UHCI1_INTR_SOURCE 13/**< interrupt of UHCI1, level*/ 300 #define ETS_TG0_T0_LEVEL_INTR_SOURCE 14/**< interrupt of TIMER_GROUP0, TIMER0, level, we would like use EDGE for timer if permission*/ 301 #define ETS_TG0_T1_LEVEL_INTR_SOURCE 15/**< interrupt of TIMER_GROUP0, TIMER1, level, we would like use EDGE for timer if permission*/ 302 #define ETS_TG0_WDT_LEVEL_INTR_SOURCE 16/**< interrupt of TIMER_GROUP0, WATCHDOG, level*/ 303 #define ETS_TG0_LACT_LEVEL_INTR_SOURCE 17/**< interrupt of TIMER_GROUP0, LACT, level*/ 304 #define ETS_TG1_T0_LEVEL_INTR_SOURCE 18/**< interrupt of TIMER_GROUP1, TIMER0, level, we would like use EDGE for timer if permission*/ 305 #define ETS_TG1_T1_LEVEL_INTR_SOURCE 19/**< interrupt of TIMER_GROUP1, TIMER1, level, we would like use EDGE for timer if permission*/ 306 #define ETS_TG1_WDT_LEVEL_INTR_SOURCE 20/**< interrupt of TIMER_GROUP1, WATCHDOG, level*/ 307 #define ETS_TG1_LACT_LEVEL_INTR_SOURCE 21/**< interrupt of TIMER_GROUP1, LACT, level*/ 308 #define ETS_GPIO_INTR_SOURCE 22/**< interrupt of GPIO, level*/ 309 #define ETS_GPIO_NMI_SOURCE 23/**< interrupt of GPIO, NMI*/ 310 #define ETS_FROM_CPU_INTR0_SOURCE 24/**< interrupt0 generated from a CPU, level*/ /* Used for FreeRTOS */ 311 #define ETS_FROM_CPU_INTR1_SOURCE 25/**< interrupt1 generated from a CPU, level*/ /* Used for FreeRTOS */ 312 #define ETS_FROM_CPU_INTR2_SOURCE 26/**< interrupt2 generated from a CPU, level*/ /* Used for DPORT Access */ 313 #define ETS_FROM_CPU_INTR3_SOURCE 27/**< interrupt3 generated from a CPU, level*/ /* Used for DPORT Access */ 314 #define ETS_SPI0_INTR_SOURCE 28/**< interrupt of SPI0, level, SPI0 is for Cache Access, do not use this*/ 315 #define ETS_SPI1_INTR_SOURCE 29/**< interrupt of SPI1, level, SPI1 is for flash read/write, do not use this*/ 316 #define ETS_SPI2_INTR_SOURCE 30/**< interrupt of SPI2, level*/ 317 #define ETS_SPI3_INTR_SOURCE 31/**< interrupt of SPI3, level*/ 318 #define ETS_I2S0_INTR_SOURCE 32/**< interrupt of I2S0, level*/ 319 #define ETS_I2S1_INTR_SOURCE 33/**< interrupt of I2S1, level*/ 320 #define ETS_UART0_INTR_SOURCE 34/**< interrupt of UART0, level*/ 321 #define ETS_UART1_INTR_SOURCE 35/**< interrupt of UART1, level*/ 322 #define ETS_UART2_INTR_SOURCE 36/**< interrupt of UART2, level*/ 323 #define ETS_SDIO_HOST_INTR_SOURCE 37/**< interrupt of SD/SDIO/MMC HOST, level*/ 324 #define ETS_ETH_MAC_INTR_SOURCE 38/**< interrupt of ethernet mac, level*/ 325 #define ETS_PWM0_INTR_SOURCE 39/**< interrupt of PWM0, level, Reserved*/ 326 #define ETS_PWM1_INTR_SOURCE 40/**< interrupt of PWM1, level, Reserved*/ 327 #define ETS_PWM2_INTR_SOURCE 41/**< interrupt of PWM2, level*/ 328 #define ETS_PWM3_INTR_SOURCE 42/**< interruot of PWM3, level*/ 329 #define ETS_LEDC_INTR_SOURCE 43/**< interrupt of LED PWM, level*/ 330 #define ETS_EFUSE_INTR_SOURCE 44/**< interrupt of efuse, level, not likely to use*/ 331 #define ETS_TWAI_INTR_SOURCE 45/**< interrupt of twai, level*/ 332 #define ETS_CAN_INTR_SOURCE ETS_TWAI_INTR_SOURCE 333 #define ETS_RTC_CORE_INTR_SOURCE 46/**< interrupt of rtc core, level, include rtc watchdog*/ 334 #define ETS_RMT_INTR_SOURCE 47/**< interrupt of remote controller, level*/ 335 #define ETS_PCNT_INTR_SOURCE 48/**< interrupt of pluse count, level*/ 336 #define ETS_I2C_EXT0_INTR_SOURCE 49/**< interrupt of I2C controller1, level*/ 337 #define ETS_I2C_EXT1_INTR_SOURCE 50/**< interrupt of I2C controller0, level*/ 338 #define ETS_RSA_INTR_SOURCE 51/**< interrupt of RSA accelerator, level*/ 339 #define ETS_SPI1_DMA_INTR_SOURCE 52/**< interrupt of SPI1 DMA, SPI1 is for flash read/write, do not use this*/ 340 #define ETS_SPI2_DMA_INTR_SOURCE 53/**< interrupt of SPI2 DMA, level*/ 341 #define ETS_SPI3_DMA_INTR_SOURCE 54/**< interrupt of SPI3 DMA, level*/ 342 #define ETS_WDT_INTR_SOURCE 55/**< will be cancelled*/ 343 #define ETS_TIMER1_INTR_SOURCE 56/**< will be cancelled*/ 344 #define ETS_TIMER2_INTR_SOURCE 57/**< will be cancelled*/ 345 #define ETS_TG0_T0_EDGE_INTR_SOURCE 58/**< interrupt of TIMER_GROUP0, TIMER0, EDGE*/ 346 #define ETS_TG0_T1_EDGE_INTR_SOURCE 59/**< interrupt of TIMER_GROUP0, TIMER1, EDGE*/ 347 #define ETS_TG0_WDT_EDGE_INTR_SOURCE 60/**< interrupt of TIMER_GROUP0, WATCH DOG, EDGE*/ 348 #define ETS_TG0_LACT_EDGE_INTR_SOURCE 61/**< interrupt of TIMER_GROUP0, LACT, EDGE*/ 349 #define ETS_TG1_T0_EDGE_INTR_SOURCE 62/**< interrupt of TIMER_GROUP1, TIMER0, EDGE*/ 350 #define ETS_TG1_T1_EDGE_INTR_SOURCE 63/**< interrupt of TIMER_GROUP1, TIMER1, EDGE*/ 351 #define ETS_TG1_WDT_EDGE_INTR_SOURCE 64/**< interrupt of TIMER_GROUP1, WATCHDOG, EDGE*/ 352 #define ETS_TG1_LACT_EDGE_INTR_SOURCE 65/**< interrupt of TIMER_GROUP0, LACT, EDGE*/ 353 #define ETS_MMU_IA_INTR_SOURCE 66/**< interrupt of MMU Invalid Access, LEVEL*/ 354 #define ETS_MPU_IA_INTR_SOURCE 67/**< interrupt of MPU Invalid Access, LEVEL*/ 355 #define ETS_CACHE_IA_INTR_SOURCE 68/**< interrupt of Cache Invalied Access, LEVEL*/ 356 #define ETS_MAX_INTR_SOURCE 69/**< total number of interrupt sources*/ 357 358 //interrupt cpu using table, Please see the core-isa.h 359 /************************************************************************************************************* 360 * Intr num Level Type PRO CPU usage APP CPU uasge 361 * 0 1 extern level WMAC Reserved 362 * 1 1 extern level BT/BLE Host HCI DMA BT/BLE Host HCI DMA 363 * 2 1 extern level 364 * 3 1 extern level 365 * 4 1 extern level WBB 366 * 5 1 extern level BT/BLE Controller BT/BLE Controller 367 * 6 1 timer FreeRTOS Tick(L1) FreeRTOS Tick(L1) 368 * 7 1 software BT/BLE VHCI BT/BLE VHCI 369 * 8 1 extern level BT/BLE BB(RX/TX) BT/BLE BB(RX/TX) 370 * 9 1 extern level 371 * 10 1 extern edge 372 * 11 3 profiling 373 * 12 1 extern level 374 * 13 1 extern level 375 * 14 7 nmi Reserved Reserved 376 * 15 3 timer FreeRTOS Tick(L3) FreeRTOS Tick(L3) 377 * 16 5 timer 378 * 17 1 extern level 379 * 18 1 extern level 380 * 19 2 extern level 381 * 20 2 extern level 382 * 21 2 extern level 383 * 22 3 extern edge 384 * 23 3 extern level 385 * 24 4 extern level TG1_WDT 386 * 25 4 extern level CACHEERR 387 * 26 5 extern level 388 * 27 3 extern level Reserved Reserved 389 * 28 4 extern edge DPORT ACCESS DPORT ACCESS 390 * 29 3 software Reserved Reserved 391 * 30 4 extern edge Reserved Reserved 392 * 31 5 extern level 393 ************************************************************************************************************* 394 */ 395 396 //CPU0 Interrupt number reserved, not touch this. 397 #define ETS_WMAC_INUM 0 398 #define ETS_BT_HOST_INUM 1 399 #define ETS_WBB_INUM 4 400 #define ETS_TG0_T1_INUM 10 /**< use edge interrupt*/ 401 #define ETS_FRC1_INUM 22 402 #define ETS_T1_WDT_INUM 24 403 #define ETS_MEMACCESS_ERR_INUM 25 404 /* backwards compatibility only, use ETS_MEMACCESS_ERR_INUM instead*/ 405 #define ETS_CACHEERR_INUM ETS_MEMACCESS_ERR_INUM 406 #define ETS_DPORT_INUM 28 407 408 //CPU0 Interrupt number used in ROM, should be cancelled in SDK 409 #define ETS_SLC_INUM 1 410 #define ETS_UART0_INUM 5 411 #define ETS_UART1_INUM 5 412 //Other interrupt number should be managed by the user 413 414 //Invalid interrupt for number interrupt matrix 415 #define ETS_INVALID_INUM 6 416
