1 /* 2 * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #define DR_REG_DPORT_BASE 0x3ff00000 7 #define DR_REG_AES_BASE 0x3ff01000 8 #define DR_REG_RSA_BASE 0x3ff02000 9 #define DR_REG_SHA_BASE 0x3ff03000 10 #define DR_REG_FLASH_MMU_TABLE_PRO 0x3ff10000 11 #define DR_REG_FLASH_MMU_TABLE_APP 0x3ff12000 12 #define DR_REG_DPORT_END 0x3ff13FFC 13 #define DR_REG_UART_BASE 0x3ff40000 14 #define DR_REG_SPI1_BASE 0x3ff42000 15 #define DR_REG_SPI0_BASE 0x3ff43000 16 #define DR_REG_GPIO_BASE 0x3ff44000 17 #define DR_REG_GPIO_SD_BASE 0x3ff44f00 18 #define DR_REG_FE2_BASE 0x3ff45000 19 #define DR_REG_FE_BASE 0x3ff46000 20 #define DR_REG_FRC_TIMER_BASE 0x3ff47000 21 #define DR_REG_RTCCNTL_BASE 0x3ff48000 22 #define DR_REG_RTCIO_BASE 0x3ff48400 23 #define DR_REG_SENS_BASE 0x3ff48800 24 #define DR_REG_RTC_I2C_BASE 0x3ff48C00 25 #define DR_REG_IO_MUX_BASE 0x3ff49000 26 #define DR_REG_HINF_BASE 0x3ff4B000 27 #define DR_REG_UHCI1_BASE 0x3ff4C000 28 #define DR_REG_I2S_BASE 0x3ff4F000 29 #define DR_REG_UART1_BASE 0x3ff50000 30 #define DR_REG_BT_BASE 0x3ff51000 31 #define DR_REG_I2C_EXT_BASE 0x3ff53000 32 #define DR_REG_UHCI0_BASE 0x3ff54000 33 #define DR_REG_SLCHOST_BASE 0x3ff55000 34 #define DR_REG_RMT_BASE 0x3ff56000 35 #define DR_REG_PCNT_BASE 0x3ff57000 36 #define DR_REG_SLC_BASE 0x3ff58000 37 #define DR_REG_LEDC_BASE 0x3ff59000 38 #define DR_REG_EFUSE_BASE 0x3ff5A000 39 #define DR_REG_SPI_ENCRYPT_BASE 0x3ff5B000 40 #define DR_REG_NRX_BASE 0x3ff5CC00 41 #define DR_REG_BB_BASE 0x3ff5D000 42 #define DR_REG_PWM0_BASE 0x3ff5E000 43 #define DR_REG_TIMERGROUP0_BASE 0x3ff5F000 44 #define DR_REG_TIMERGROUP1_BASE 0x3ff60000 45 #define DR_REG_RTCMEM0_BASE 0x3ff61000 46 #define DR_REG_RTCMEM1_BASE 0x3ff62000 47 #define DR_REG_RTCMEM2_BASE 0x3ff63000 48 #define DR_REG_SPI2_BASE 0x3ff64000 49 #define DR_REG_SPI3_BASE 0x3ff65000 50 #define DR_REG_SYSCON_BASE 0x3ff66000 51 #define DR_REG_APB_CTRL_BASE 0x3ff66000 /* Old name for SYSCON, to be removed */ 52 #define DR_REG_I2C1_EXT_BASE 0x3ff67000 53 #define DR_REG_SDMMC_BASE 0x3ff68000 54 #define DR_REG_EMAC_BASE 0x3ff69000 55 #define DR_REG_CAN_BASE 0x3ff6B000 56 #define DR_REG_PWM1_BASE 0x3ff6C000 57 #define DR_REG_I2S1_BASE 0x3ff6D000 58 #define DR_REG_UART2_BASE 0x3ff6E000 59 #define PERIPHS_SPI_ENCRYPT_BASEADDR DR_REG_SPI_ENCRYPT_BASE 60
