1 /* 2 * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #ifndef _CACHE_MEMORY_H_ 7 #define _CACHE_MEMORY_H_ 8 9 #include "esp_bit_defs.h" 10 11 12 #ifdef __cplusplus 13 extern "C" { 14 #endif 15 16 #define IRAM0_CACHE_ADDRESS_LOW 0x400D0000 17 #define IRAM0_CACHE_ADDRESS_HIGH 0x40400000 18 19 #define IRAM1_CACHE_ADDRESS_LOW 0x40400000 20 #define IRAM1_CACHE_ADDRESS_HIGH 0x40800000 21 22 #define IROM0_CACHE_ADDRESS_LOW 0x40800000 23 #define IROM0_CACHE_ADDRESS_HIGH 0x40C00000 24 25 #define DRAM1_CACHE_ADDRESS_LOW 0x3F800000 26 #define DRAM1_CACHE_ADDRESS_HIGH 0x3FC00000 27 28 #define DROM0_CACHE_ADDRESS_LOW 0x3F400000 29 #define DROM0_CACHE_ADDRESS_HIGH 0x3F800000 30 31 32 #define BUS_SIZE(bus_name) (bus_name##_ADDRESS_HIGH - bus_name##_ADDRESS_LOW) 33 #define ADDRESS_IN_BUS(bus_name, vaddr) ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) < bus_name##_ADDRESS_HIGH) 34 #define ADDRESS_IN_IRAM0_CACHE(vaddr) ADDRESS_IN_BUS(IRAM0_CACHE, vaddr) 35 #define ADDRESS_IN_IRAM1_CACHE(vaddr) ADDRESS_IN_BUS(IRAM1_CACHE, vaddr) 36 #define ADDRESS_IN_IROM0_CACHE(vaddr) ADDRESS_IN_BUS(IROM0_CACHE, vaddr) 37 #define ADDRESS_IN_DRAM1_CACHE(vaddr) ADDRESS_IN_BUS(DRAM1_CACHE, vaddr) 38 #define ADDRESS_IN_DROM0_CACHE(vaddr) ADDRESS_IN_BUS(DROM0_CACHE, vaddr) 39 40 #define MMU_INVALID BIT(8) 41 42 /** 43 * Max MMU available paddr page num. 44 * `MMU_MAX_PADDR_PAGE_NUM * SOC_MMU_PAGE_SIZE` means the max paddr address supported by the MMU. e.g.: 45 * 256 * 64KB, means MMU can support 16MB paddr at most 46 */ 47 #define MMU_MAX_PADDR_PAGE_NUM 256 48 /** 49 * This is the mask used for mapping. e.g.: 50 * 0x4008_0000 & MMU_VADDR_MASK 51 */ 52 #define MMU_VADDR_MASK 0x3FFFFF 53 //MMU entry num, 384 entries that are used in IDF for Flash 54 #define MMU_ENTRY_NUM 384 55 56 57 #define SOC_MMU_DBUS_VADDR_BASE 0x3E000000 58 #define SOC_MMU_IBUS_VADDR_BASE 0x40000000 59 60 /*------------------------------------------------------------------------------ 61 * MMU Linear Address 62 *----------------------------------------------------------------------------*/ 63 /** 64 * - 64KB MMU page size: the last 0xFFFF, which is the offset 65 * - 384 MMU entries, needs 0x1FF to hold it. 66 * 67 * Therefore, 0x1FF,FFFF 68 */ 69 #define SOC_MMU_LINEAR_ADDR_MASK 0x1FFFFFF 70 71 #define SOC_MMU_IRAM0_LINEAR_ADDRESS_LOW (IRAM0_CACHE_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK) 72 #define SOC_MMU_IRAM0_LINEAR_ADDRESS_HIGH (IRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK) 73 74 #define SOC_MMU_IRAM1_LINEAR_ADDRESS_LOW (IRAM1_CACHE_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK) 75 #define SOC_MMU_IRAM1_LINEAR_ADDRESS_HIGH (IRAM1_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK) 76 77 #define SOC_MMU_IROM0_LINEAR_ADDRESS_LOW (IROM0_CACHE_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK) 78 #define SOC_MMU_IROM0_LINEAR_ADDRESS_HIGH (IROM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK) 79 80 #define SOC_MMU_DROM0_LINEAR_ADDRESS_LOW (DROM0_CACHE_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK) 81 #define SOC_MMU_DROM0_LINEAR_ADDRESS_HIGH (DROM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK) 82 83 #define SOC_MMU_DRAM1_LINEAR_ADDRESS_LOW (DRAM1_CACHE_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK) 84 #define SOC_MMU_DRAM1_LINEAR_ADDRESS_HIGH (DRAM1_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK) 85 86 87 88 89 #ifdef __cplusplus 90 } 91 #endif 92 93 #endif /*_CACHE_MEMORY_H_ */ 94
